diff --git a/tcl/target/lpc1751.cfg b/tcl/target/lpc1751.cfg new file mode 100644 index 0000000000000000000000000000000000000000..28edddbb02eaba33fae01390c88e3409b6083dd9 --- /dev/null +++ b/tcl/target/lpc1751.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1751 Cortex-M3 with 32kB Flash and 8kB Local On-Chip SRAM, +set CHIPNAME lpc1751 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x2000 +set CPUROMSIZE 0x8000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1752.cfg b/tcl/target/lpc1752.cfg new file mode 100644 index 0000000000000000000000000000000000000000..3aae38f1b6ca130f7be10441ffb9e654cfb1186b --- /dev/null +++ b/tcl/target/lpc1752.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1752 Cortex-M3 with 64kB Flash and 16kB Local On-Chip SRAM, +set CHIPNAME lpc1752 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x4000 +set CPUROMSIZE 0x10000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1754.cfg b/tcl/target/lpc1754.cfg new file mode 100644 index 0000000000000000000000000000000000000000..ae2ad50f8461c2d8c40c6f4fad07dc2cc942338e --- /dev/null +++ b/tcl/target/lpc1754.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1754 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM, +set CHIPNAME lpc1754 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x4000 +set CPUROMSIZE 0x20000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1756.cfg b/tcl/target/lpc1756.cfg new file mode 100644 index 0000000000000000000000000000000000000000..8110727ffc35f572757169ffa2775e6ae7bdfa87 --- /dev/null +++ b/tcl/target/lpc1756.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1756 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM, +set CHIPNAME lpc1756 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x40000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1758.cfg b/tcl/target/lpc1758.cfg new file mode 100644 index 0000000000000000000000000000000000000000..79f6624272f7082e780e89a87f026ed53da05048 --- /dev/null +++ b/tcl/target/lpc1758.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1758 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +set CHIPNAME lpc1758 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x80000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1759.cfg b/tcl/target/lpc1759.cfg new file mode 100644 index 0000000000000000000000000000000000000000..3560e97a762bf732a07aa59d31cb1eb49176036c --- /dev/null +++ b/tcl/target/lpc1759.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1759 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +set CHIPNAME lpc1759 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x80000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1763.cfg b/tcl/target/lpc1763.cfg new file mode 100644 index 0000000000000000000000000000000000000000..08a2be3f77a7805f0b3dc289b43599a24f84caac --- /dev/null +++ b/tcl/target/lpc1763.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1763 Cortex-M3 with 256kB Flash and 32kB+32kB Local On-Chip SRAM, +set CHIPNAME lpc1763 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x40000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1764.cfg b/tcl/target/lpc1764.cfg new file mode 100644 index 0000000000000000000000000000000000000000..df7ab936336ad618e4b04dc34efce74f2e4a89c7 --- /dev/null +++ b/tcl/target/lpc1764.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1764 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM, +set CHIPNAME lpc1764 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x4000 +set CPUROMSIZE 0x20000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1765.cfg b/tcl/target/lpc1765.cfg new file mode 100644 index 0000000000000000000000000000000000000000..6d8e8ea5cc70a857116a6e7022bf862e4916b76f --- /dev/null +++ b/tcl/target/lpc1765.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1765 Cortex-M3 with 256kB Flash and 32kB+1632kB Local On-Chip SRAM, +set CHIPNAME lpc1765 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x40000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1766.cfg b/tcl/target/lpc1766.cfg new file mode 100644 index 0000000000000000000000000000000000000000..8956c0609a08b11cce10a1ef99889e1bea6adf15 --- /dev/null +++ b/tcl/target/lpc1766.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1766 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM, +set CHIPNAME lpc1766 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x40000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1767.cfg b/tcl/target/lpc1767.cfg new file mode 100644 index 0000000000000000000000000000000000000000..825dbebc679b7ce40708dfc63fb4317d9d0e9552 --- /dev/null +++ b/tcl/target/lpc1767.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1767 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +set CHIPNAME lpc1767 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x80000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1769.cfg b/tcl/target/lpc1769.cfg new file mode 100644 index 0000000000000000000000000000000000000000..61ab3ee882de2ba7583eb4622b17c305e95e4f66 --- /dev/null +++ b/tcl/target/lpc1769.cfg @@ -0,0 +1,17 @@ +# NXP LPC1769 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +set CHIPNAME lpc1769 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x80000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg];