From ee8df96b2b064fd666e9a3aa8b8f03eb0f2bd75f Mon Sep 17 00:00:00 2001 From: Vandra Akos <axos88@gmail.com> Date: Sun, 27 May 2012 12:50:04 +0200 Subject: [PATCH] added target configs for the lpc17xx devices lpc1751, lpc1752, lpc1754, lpc1756, lpc1758, lpc1759 lpc1763, lpc1764, lpc1765, lpc1766, lpc1767, lpc1768, lpc1769 Change-Id: I740b66930cd379c9390f3c1031cdbada747a6ce4 Signed-off-by: Vandra Akos <axos88@gmail.com> Reviewed-on: http://openocd.zylin.com/676 Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Tested-by: jenkins --- tcl/target/lpc1751.cfg | 21 +++++++++++++++++++++ tcl/target/lpc1752.cfg | 21 +++++++++++++++++++++ tcl/target/lpc1754.cfg | 21 +++++++++++++++++++++ tcl/target/lpc1756.cfg | 21 +++++++++++++++++++++ tcl/target/lpc1758.cfg | 21 +++++++++++++++++++++ tcl/target/lpc1759.cfg | 21 +++++++++++++++++++++ tcl/target/lpc1763.cfg | 21 +++++++++++++++++++++ tcl/target/lpc1764.cfg | 21 +++++++++++++++++++++ tcl/target/lpc1765.cfg | 21 +++++++++++++++++++++ tcl/target/lpc1766.cfg | 21 +++++++++++++++++++++ tcl/target/lpc1767.cfg | 21 +++++++++++++++++++++ tcl/target/lpc1769.cfg | 17 +++++++++++++++++ 12 files changed, 248 insertions(+) create mode 100644 tcl/target/lpc1751.cfg create mode 100644 tcl/target/lpc1752.cfg create mode 100644 tcl/target/lpc1754.cfg create mode 100644 tcl/target/lpc1756.cfg create mode 100644 tcl/target/lpc1758.cfg create mode 100644 tcl/target/lpc1759.cfg create mode 100644 tcl/target/lpc1763.cfg create mode 100644 tcl/target/lpc1764.cfg create mode 100644 tcl/target/lpc1765.cfg create mode 100644 tcl/target/lpc1766.cfg create mode 100644 tcl/target/lpc1767.cfg create mode 100644 tcl/target/lpc1769.cfg diff --git a/tcl/target/lpc1751.cfg b/tcl/target/lpc1751.cfg new file mode 100644 index 000000000..28edddbb0 --- /dev/null +++ b/tcl/target/lpc1751.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1751 Cortex-M3 with 32kB Flash and 8kB Local On-Chip SRAM, +set CHIPNAME lpc1751 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x2000 +set CPUROMSIZE 0x8000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1752.cfg b/tcl/target/lpc1752.cfg new file mode 100644 index 000000000..3aae38f1b --- /dev/null +++ b/tcl/target/lpc1752.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1752 Cortex-M3 with 64kB Flash and 16kB Local On-Chip SRAM, +set CHIPNAME lpc1752 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x4000 +set CPUROMSIZE 0x10000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1754.cfg b/tcl/target/lpc1754.cfg new file mode 100644 index 000000000..ae2ad50f8 --- /dev/null +++ b/tcl/target/lpc1754.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1754 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM, +set CHIPNAME lpc1754 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x4000 +set CPUROMSIZE 0x20000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1756.cfg b/tcl/target/lpc1756.cfg new file mode 100644 index 000000000..8110727ff --- /dev/null +++ b/tcl/target/lpc1756.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1756 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM, +set CHIPNAME lpc1756 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x40000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1758.cfg b/tcl/target/lpc1758.cfg new file mode 100644 index 000000000..79f662427 --- /dev/null +++ b/tcl/target/lpc1758.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1758 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +set CHIPNAME lpc1758 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x80000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1759.cfg b/tcl/target/lpc1759.cfg new file mode 100644 index 000000000..3560e97a7 --- /dev/null +++ b/tcl/target/lpc1759.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1759 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +set CHIPNAME lpc1759 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x80000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1763.cfg b/tcl/target/lpc1763.cfg new file mode 100644 index 000000000..08a2be3f7 --- /dev/null +++ b/tcl/target/lpc1763.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1763 Cortex-M3 with 256kB Flash and 32kB+32kB Local On-Chip SRAM, +set CHIPNAME lpc1763 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x40000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1764.cfg b/tcl/target/lpc1764.cfg new file mode 100644 index 000000000..df7ab9363 --- /dev/null +++ b/tcl/target/lpc1764.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1764 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM, +set CHIPNAME lpc1764 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x4000 +set CPUROMSIZE 0x20000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1765.cfg b/tcl/target/lpc1765.cfg new file mode 100644 index 000000000..6d8e8ea5c --- /dev/null +++ b/tcl/target/lpc1765.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1765 Cortex-M3 with 256kB Flash and 32kB+1632kB Local On-Chip SRAM, +set CHIPNAME lpc1765 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x40000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1766.cfg b/tcl/target/lpc1766.cfg new file mode 100644 index 000000000..8956c0609 --- /dev/null +++ b/tcl/target/lpc1766.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1766 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM, +set CHIPNAME lpc1766 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x40000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1767.cfg b/tcl/target/lpc1767.cfg new file mode 100644 index 000000000..825dbebc6 --- /dev/null +++ b/tcl/target/lpc1767.cfg @@ -0,0 +1,21 @@ +# !!!!!!!!!!!! +# ! UNTESTED ! +# !!!!!!!!!!!! + +# NXP LPC1767 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +set CHIPNAME lpc1767 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x80000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; diff --git a/tcl/target/lpc1769.cfg b/tcl/target/lpc1769.cfg new file mode 100644 index 000000000..61ab3ee88 --- /dev/null +++ b/tcl/target/lpc1769.cfg @@ -0,0 +1,17 @@ +# NXP LPC1769 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, +set CHIPNAME lpc1769 +set CPUTAPID 0x4ba00477 +set CPURAMSIZE 0x8000 +set CPUROMSIZE 0x80000 + +# After reset the chip is clocked by the ~4MHz internal RC oscillator. +# When board-specific code (reset-init handler or device firmware) +# configures another oscillator and/or PLL0, set CCLK to match; if +# you don't, then flash erase and write operations may misbehave. +# (The ROM code doing those updates cares about core clock speed...) +# +# CCLK is the core clock frequency in KHz +set CCLK 4000 + +#Include the main configuration file. +source [find target/lpc17xx.cfg]; -- GitLab