From a3ad0066db3315cd1b89528d197d4c47549be42f Mon Sep 17 00:00:00 2001
From: Jake <jake.read@cba.mit.edu>
Date: Sat, 9 Dec 2017 19:08:03 -0500
Subject: [PATCH] remove ASF folders
---
.gitignore | 2 +
.../src/ASF/common/boards/board.h | 448 -
.../src/ASF/common/boards/user_board/init.c | 21 -
.../ASF/common/boards/user_board/user_board.h | 40 -
.../src/ASF/common/services/clock/genclk.h | 199 -
.../src/ASF/common/services/clock/osc.h | 185 -
.../src/ASF/common/services/clock/pll.h | 341 -
.../ASF/common/services/clock/sams70/genclk.h | 269 -
.../ASF/common/services/clock/sams70/osc.h | 247 -
.../ASF/common/services/clock/sams70/pll.h | 269 -
.../ASF/common/services/clock/sams70/sysclk.c | 261 -
.../ASF/common/services/clock/sams70/sysclk.h | 473 --
.../src/ASF/common/services/clock/sysclk.h | 194 -
.../src/ASF/common/services/delay/delay.h | 139 -
.../common/services/delay/sam/cycle_counter.c | 61 -
.../common/services/delay/sam/cycle_counter.h | 126 -
.../src/ASF/common/utils/interrupt.h | 142 -
.../utils/interrupt/interrupt_sam_nvic.c | 86 -
.../utils/interrupt/interrupt_sam_nvic.h | 189 -
.../src/ASF/common/utils/parts.h | 1585 ----
.../src/ASF/sam/drivers/pmc/pmc.c | 1657 ----
.../src/ASF/sam/drivers/pmc/pmc.h | 550 --
.../src/ASF/sam/drivers/pmc/sleep.c | 391 -
.../src/ASF/sam/drivers/pmc/sleep.h | 127 -
.../cmsis/sams70/include/component/acc.h | 143 -
.../cmsis/sams70/include/component/aes.h | 187 -
.../cmsis/sams70/include/component/afec.h | 498 --
.../cmsis/sams70/include/component/chipid.h | 138 -
.../cmsis/sams70/include/component/dacc.h | 217 -
.../cmsis/sams70/include/component/efc.h | 133 -
.../cmsis/sams70/include/component/gpbr.h | 68 -
.../cmsis/sams70/include/component/hsmci.h | 350 -
.../cmsis/sams70/include/component/icm.h | 207 -
.../cmsis/sams70/include/component/isi.h | 295 -
.../cmsis/sams70/include/component/matrix.h | 476 --
.../cmsis/sams70/include/component/pio.h | 1629 ----
.../cmsis/sams70/include/component/pmc.h | 736 --
.../cmsis/sams70/include/component/pwm.h | 715 --
.../cmsis/sams70/include/component/qspi.h | 238 -
.../cmsis/sams70/include/component/rstc.h | 94 -
.../cmsis/sams70/include/component/rswdt.h | 87 -
.../cmsis/sams70/include/component/rtc.h | 241 -
.../cmsis/sams70/include/component/rtt.h | 86 -
.../cmsis/sams70/include/component/sdramc.h | 188 -
.../cmsis/sams70/include/component/smc.h | 159 -
.../cmsis/sams70/include/component/spi.h | 176 -
.../cmsis/sams70/include/component/ssc.h | 295 -
.../cmsis/sams70/include/component/supc.h | 310 -
.../utils/cmsis/sams70/include/component/tc.h | 361 -
.../cmsis/sams70/include/component/trng.h | 88 -
.../cmsis/sams70/include/component/twihs.h | 265 -
.../cmsis/sams70/include/component/uart.h | 166 -
.../cmsis/sams70/include/component/usart.h | 432 -
.../cmsis/sams70/include/component/usbhs.h | 975 ---
.../cmsis/sams70/include/component/utmi.h | 78 -
.../cmsis/sams70/include/component/wdt.h | 87 -
.../cmsis/sams70/include/component/xdmac.h | 634 --
.../utils/cmsis/sams70/include/instance/acc.h | 71 -
.../utils/cmsis/sams70/include/instance/aes.h | 85 -
.../cmsis/sams70/include/instance/afec0.h | 111 -
.../cmsis/sams70/include/instance/afec1.h | 111 -
.../cmsis/sams70/include/instance/chipid.h | 57 -
.../cmsis/sams70/include/instance/dacc.h | 81 -
.../utils/cmsis/sams70/include/instance/efc.h | 65 -
.../cmsis/sams70/include/instance/gpbr.h | 55 -
.../cmsis/sams70/include/instance/hsmci.h | 93 -
.../utils/cmsis/sams70/include/instance/icm.h | 75 -
.../utils/cmsis/sams70/include/instance/isi.h | 103 -
.../cmsis/sams70/include/instance/matrix.h | 117 -
.../cmsis/sams70/include/instance/pioa.h | 179 -
.../cmsis/sams70/include/instance/piob.h | 179 -
.../cmsis/sams70/include/instance/pioc.h | 179 -
.../cmsis/sams70/include/instance/piod.h | 179 -
.../cmsis/sams70/include/instance/pioe.h | 179 -
.../utils/cmsis/sams70/include/instance/pmc.h | 125 -
.../cmsis/sams70/include/instance/pwm0.h | 275 -
.../cmsis/sams70/include/instance/pwm1.h | 275 -
.../cmsis/sams70/include/instance/qspi.h | 85 -
.../cmsis/sams70/include/instance/rstc.h | 59 -
.../cmsis/sams70/include/instance/rswdt.h | 59 -
.../utils/cmsis/sams70/include/instance/rtc.h | 77 -
.../utils/cmsis/sams70/include/instance/rtt.h | 61 -
.../cmsis/sams70/include/instance/sdramc.h | 79 -
.../utils/cmsis/sams70/include/instance/smc.h | 95 -
.../cmsis/sams70/include/instance/spi0.h | 75 -
.../cmsis/sams70/include/instance/spi1.h | 75 -
.../utils/cmsis/sams70/include/instance/ssc.h | 89 -
.../cmsis/sams70/include/instance/supc.h | 65 -
.../utils/cmsis/sams70/include/instance/tc0.h | 147 -
.../utils/cmsis/sams70/include/instance/tc1.h | 147 -
.../utils/cmsis/sams70/include/instance/tc2.h | 147 -
.../utils/cmsis/sams70/include/instance/tc3.h | 147 -
.../cmsis/sams70/include/instance/trng.h | 65 -
.../cmsis/sams70/include/instance/twihs0.h | 85 -
.../cmsis/sams70/include/instance/twihs1.h | 85 -
.../cmsis/sams70/include/instance/twihs2.h | 85 -
.../cmsis/sams70/include/instance/uart0.h | 75 -
.../cmsis/sams70/include/instance/uart1.h | 75 -
.../cmsis/sams70/include/instance/uart2.h | 75 -
.../cmsis/sams70/include/instance/uart3.h | 75 -
.../cmsis/sams70/include/instance/uart4.h | 75 -
.../cmsis/sams70/include/instance/usart0.h | 109 -
.../cmsis/sams70/include/instance/usart1.h | 109 -
.../cmsis/sams70/include/instance/usart2.h | 109 -
.../cmsis/sams70/include/instance/usbhs.h | 255 -
.../cmsis/sams70/include/instance/utmi.h | 57 -
.../utils/cmsis/sams70/include/instance/wdt.h | 59 -
.../cmsis/sams70/include/instance/xdmac.h | 759 --
.../cmsis/sams70/include/pio/sams70j19.h | 418 -
.../cmsis/sams70/include/pio/sams70j20.h | 422 -
.../cmsis/sams70/include/pio/sams70j21.h | 422 -
.../cmsis/sams70/include/pio/sams70n19.h | 479 --
.../cmsis/sams70/include/pio/sams70n20.h | 475 --
.../cmsis/sams70/include/pio/sams70n21.h | 475 --
.../cmsis/sams70/include/pio/sams70q19.h | 652 --
.../cmsis/sams70/include/pio/sams70q20.h | 652 --
.../cmsis/sams70/include/pio/sams70q21.h | 652 --
.../sam/utils/cmsis/sams70/include/sams70.h | 69 -
.../utils/cmsis/sams70/include/sams70j19.h | 618 --
.../utils/cmsis/sams70/include/sams70j20.h | 625 --
.../utils/cmsis/sams70/include/sams70j21.h | 625 --
.../utils/cmsis/sams70/include/sams70n19.h | 631 --
.../utils/cmsis/sams70/include/sams70n20.h | 624 --
.../utils/cmsis/sams70/include/sams70n21.h | 624 --
.../utils/cmsis/sams70/include/sams70q19.h | 679 --
.../utils/cmsis/sams70/include/sams70q20.h | 679 --
.../utils/cmsis/sams70/include/sams70q21.h | 679 --
.../source/templates/gcc/startup_sams70.c | 334 -
.../sams70/source/templates/system_sams70.c | 265 -
.../sams70/source/templates/system_sams70.h | 85 -
.../src/ASF/sam/utils/compiler.h | 1199 ---
.../src/ASF/sam/utils/fpu/fpu.h | 94 -
.../src/ASF/sam/utils/header_files/io.h | 157 -
.../sams70/sams70n20/gcc/flash.ld | 174 -
.../src/ASF/sam/utils/make/Makefile.sam.in | 496 --
.../src/ASF/sam/utils/preprocessor/mrepeat.h | 339 -
.../ASF/sam/utils/preprocessor/preprocessor.h | 55 -
.../src/ASF/sam/utils/preprocessor/stringz.h | 85 -
.../src/ASF/sam/utils/preprocessor/tpaste.h | 105 -
.../src/ASF/sam/utils/status_codes.h | 113 -
.../src/ASF/sam/utils/syscalls/gcc/syscalls.c | 144 -
.../ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt | 20 -
.../CMSIS_END_USER_LICENCE_AGREEMENT.pdf | Bin 172641 -> 0 bytes
.../CMSIS/Include/arm_common_tables.h | 136 -
.../CMSIS/Include/arm_const_structs.h | 79 -
.../ASF/thirdparty/CMSIS/Include/arm_math.h | 7538 -----------------
.../ASF/thirdparty/CMSIS/Include/core_cm7.h | 2221 -----
.../thirdparty/CMSIS/Include/core_cmFunc.h | 637 --
.../thirdparty/CMSIS/Include/core_cmInstr.h | 880 --
.../thirdparty/CMSIS/Include/core_cmSimd.h | 697 --
.../CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a | Bin 3199620 -> 0 bytes
.../Lib/GCC/libarm_cortexM7lfsp_math_softfp.a | Bin 3199824 -> 0 bytes
.../src/ASF/thirdparty/CMSIS/Lib/license.txt | 28 -
.../src/ASF/thirdparty/CMSIS/README.txt | 42 -
.../src/ASF/common/boards/board.h | 448 -
.../src/ASF/common/boards/user_board/init.c | 21 -
.../ASF/common/boards/user_board/user_board.h | 40 -
.../src/ASF/common/services/clock/genclk.h | 199 -
.../src/ASF/common/services/clock/osc.h | 185 -
.../src/ASF/common/services/clock/pll.h | 341 -
.../ASF/common/services/clock/sams70/genclk.h | 269 -
.../ASF/common/services/clock/sams70/osc.h | 247 -
.../ASF/common/services/clock/sams70/pll.h | 269 -
.../ASF/common/services/clock/sams70/sysclk.c | 261 -
.../ASF/common/services/clock/sams70/sysclk.h | 473 --
.../src/ASF/common/services/clock/sysclk.h | 194 -
.../src/ASF/common/services/delay/delay.h | 139 -
.../common/services/delay/sam/cycle_counter.c | 61 -
.../common/services/delay/sam/cycle_counter.h | 126 -
.../src/ASF/common/utils/interrupt.h | 142 -
.../utils/interrupt/interrupt_sam_nvic.c | 86 -
.../utils/interrupt/interrupt_sam_nvic.h | 189 -
.../src/ASF/common/utils/parts.h | 1594 ----
.../src/ASF/sam/drivers/pmc/pmc.c | 1657 ----
.../src/ASF/sam/drivers/pmc/pmc.h | 550 --
.../src/ASF/sam/drivers/pmc/sleep.c | 391 -
.../src/ASF/sam/drivers/pmc/sleep.h | 127 -
.../cmsis/sams70/include/component/acc.h | 143 -
.../cmsis/sams70/include/component/aes.h | 187 -
.../cmsis/sams70/include/component/afec.h | 498 --
.../cmsis/sams70/include/component/chipid.h | 138 -
.../cmsis/sams70/include/component/dacc.h | 217 -
.../cmsis/sams70/include/component/efc.h | 133 -
.../cmsis/sams70/include/component/gpbr.h | 68 -
.../cmsis/sams70/include/component/hsmci.h | 350 -
.../cmsis/sams70/include/component/icm.h | 207 -
.../cmsis/sams70/include/component/isi.h | 295 -
.../cmsis/sams70/include/component/matrix.h | 476 --
.../cmsis/sams70/include/component/pio.h | 1629 ----
.../cmsis/sams70/include/component/pmc.h | 736 --
.../cmsis/sams70/include/component/pwm.h | 715 --
.../cmsis/sams70/include/component/qspi.h | 238 -
.../cmsis/sams70/include/component/rstc.h | 94 -
.../cmsis/sams70/include/component/rswdt.h | 87 -
.../cmsis/sams70/include/component/rtc.h | 241 -
.../cmsis/sams70/include/component/rtt.h | 86 -
.../cmsis/sams70/include/component/sdramc.h | 188 -
.../cmsis/sams70/include/component/smc.h | 159 -
.../cmsis/sams70/include/component/spi.h | 176 -
.../cmsis/sams70/include/component/ssc.h | 295 -
.../cmsis/sams70/include/component/supc.h | 310 -
.../utils/cmsis/sams70/include/component/tc.h | 361 -
.../cmsis/sams70/include/component/trng.h | 88 -
.../cmsis/sams70/include/component/twihs.h | 265 -
.../cmsis/sams70/include/component/uart.h | 166 -
.../cmsis/sams70/include/component/usart.h | 432 -
.../cmsis/sams70/include/component/usbhs.h | 975 ---
.../cmsis/sams70/include/component/utmi.h | 78 -
.../cmsis/sams70/include/component/wdt.h | 87 -
.../cmsis/sams70/include/component/xdmac.h | 634 --
.../utils/cmsis/sams70/include/instance/acc.h | 71 -
.../utils/cmsis/sams70/include/instance/aes.h | 85 -
.../cmsis/sams70/include/instance/afec0.h | 111 -
.../cmsis/sams70/include/instance/afec1.h | 111 -
.../cmsis/sams70/include/instance/chipid.h | 57 -
.../cmsis/sams70/include/instance/dacc.h | 81 -
.../utils/cmsis/sams70/include/instance/efc.h | 65 -
.../cmsis/sams70/include/instance/gpbr.h | 55 -
.../cmsis/sams70/include/instance/hsmci.h | 93 -
.../utils/cmsis/sams70/include/instance/icm.h | 75 -
.../utils/cmsis/sams70/include/instance/isi.h | 103 -
.../cmsis/sams70/include/instance/matrix.h | 117 -
.../cmsis/sams70/include/instance/pioa.h | 179 -
.../cmsis/sams70/include/instance/piob.h | 179 -
.../cmsis/sams70/include/instance/pioc.h | 179 -
.../cmsis/sams70/include/instance/piod.h | 179 -
.../cmsis/sams70/include/instance/pioe.h | 179 -
.../utils/cmsis/sams70/include/instance/pmc.h | 125 -
.../cmsis/sams70/include/instance/pwm0.h | 275 -
.../cmsis/sams70/include/instance/pwm1.h | 275 -
.../cmsis/sams70/include/instance/qspi.h | 85 -
.../cmsis/sams70/include/instance/rstc.h | 59 -
.../cmsis/sams70/include/instance/rswdt.h | 59 -
.../utils/cmsis/sams70/include/instance/rtc.h | 77 -
.../utils/cmsis/sams70/include/instance/rtt.h | 61 -
.../cmsis/sams70/include/instance/sdramc.h | 79 -
.../utils/cmsis/sams70/include/instance/smc.h | 95 -
.../cmsis/sams70/include/instance/spi0.h | 75 -
.../cmsis/sams70/include/instance/spi1.h | 75 -
.../utils/cmsis/sams70/include/instance/ssc.h | 89 -
.../cmsis/sams70/include/instance/supc.h | 65 -
.../utils/cmsis/sams70/include/instance/tc0.h | 147 -
.../utils/cmsis/sams70/include/instance/tc1.h | 147 -
.../utils/cmsis/sams70/include/instance/tc2.h | 147 -
.../utils/cmsis/sams70/include/instance/tc3.h | 147 -
.../cmsis/sams70/include/instance/trng.h | 65 -
.../cmsis/sams70/include/instance/twihs0.h | 85 -
.../cmsis/sams70/include/instance/twihs1.h | 85 -
.../cmsis/sams70/include/instance/twihs2.h | 85 -
.../cmsis/sams70/include/instance/uart0.h | 75 -
.../cmsis/sams70/include/instance/uart1.h | 75 -
.../cmsis/sams70/include/instance/uart2.h | 75 -
.../cmsis/sams70/include/instance/uart3.h | 75 -
.../cmsis/sams70/include/instance/uart4.h | 75 -
.../cmsis/sams70/include/instance/usart0.h | 109 -
.../cmsis/sams70/include/instance/usart1.h | 109 -
.../cmsis/sams70/include/instance/usart2.h | 109 -
.../cmsis/sams70/include/instance/usbhs.h | 255 -
.../cmsis/sams70/include/instance/utmi.h | 57 -
.../utils/cmsis/sams70/include/instance/wdt.h | 59 -
.../cmsis/sams70/include/instance/xdmac.h | 759 --
.../cmsis/sams70/include/pio/sams70j19.h | 418 -
.../cmsis/sams70/include/pio/sams70j20.h | 422 -
.../cmsis/sams70/include/pio/sams70j21.h | 422 -
.../cmsis/sams70/include/pio/sams70n19.h | 479 --
.../cmsis/sams70/include/pio/sams70n20.h | 475 --
.../cmsis/sams70/include/pio/sams70n21.h | 475 --
.../cmsis/sams70/include/pio/sams70q19.h | 652 --
.../cmsis/sams70/include/pio/sams70q20.h | 652 --
.../cmsis/sams70/include/pio/sams70q21.h | 652 --
.../sam/utils/cmsis/sams70/include/sams70.h | 69 -
.../utils/cmsis/sams70/include/sams70j19.h | 618 --
.../utils/cmsis/sams70/include/sams70j20.h | 625 --
.../utils/cmsis/sams70/include/sams70j21.h | 625 --
.../utils/cmsis/sams70/include/sams70n19.h | 631 --
.../utils/cmsis/sams70/include/sams70n20.h | 624 --
.../utils/cmsis/sams70/include/sams70n21.h | 624 --
.../utils/cmsis/sams70/include/sams70q19.h | 679 --
.../utils/cmsis/sams70/include/sams70q20.h | 679 --
.../utils/cmsis/sams70/include/sams70q21.h | 679 --
.../source/templates/gcc/startup_sams70.c | 334 -
.../sams70/source/templates/system_sams70.c | 265 -
.../sams70/source/templates/system_sams70.h | 85 -
.../src/ASF/sam/utils/compiler.h | 1199 ---
.../src/ASF/sam/utils/fpu/fpu.h | 94 -
.../src/ASF/sam/utils/header_files/io.h | 157 -
.../sams70/sams70n20/gcc/flash.ld | 174 -
.../src/ASF/sam/utils/make/Makefile.sam.in | 496 --
.../src/ASF/sam/utils/preprocessor/mrepeat.h | 339 -
.../ASF/sam/utils/preprocessor/preprocessor.h | 55 -
.../src/ASF/sam/utils/preprocessor/stringz.h | 85 -
.../src/ASF/sam/utils/preprocessor/tpaste.h | 105 -
.../src/ASF/sam/utils/status_codes.h | 113 -
.../src/ASF/sam/utils/syscalls/gcc/syscalls.c | 144 -
.../ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt | 20 -
.../CMSIS_END_USER_LICENCE_AGREEMENT.pdf | Bin 172641 -> 0 bytes
.../CMSIS/Include/arm_common_tables.h | 136 -
.../CMSIS/Include/arm_const_structs.h | 79 -
.../ASF/thirdparty/CMSIS/Include/arm_math.h | 7538 -----------------
.../ASF/thirdparty/CMSIS/Include/core_cm7.h | 2221 -----
.../thirdparty/CMSIS/Include/core_cmFunc.h | 637 --
.../thirdparty/CMSIS/Include/core_cmInstr.h | 880 --
.../thirdparty/CMSIS/Include/core_cmSimd.h | 697 --
.../CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a | Bin 3199620 -> 0 bytes
.../Lib/GCC/libarm_cortexM7lfsp_math_softfp.a | Bin 3199824 -> 0 bytes
.../src/ASF/thirdparty/CMSIS/Lib/license.txt | 28 -
.../src/ASF/thirdparty/CMSIS/README.txt | 42 -
307 files changed, 2 insertions(+), 102665 deletions(-)
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/boards/board.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/boards/user_board/init.c
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/boards/user_board/user_board.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/genclk.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/osc.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/pll.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/genclk.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/osc.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/pll.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/sysclk.c
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/sysclk.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sysclk.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/delay/delay.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/delay/sam/cycle_counter.c
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/delay/sam/cycle_counter.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/interrupt.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/parts.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/pmc.c
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/pmc.h
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/sleep.c
delete mode 100644 embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/sleep.h
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diff --git a/.gitignore b/.gitignore
index 61f56c7..a6d2fcc 100644
--- a/.gitignore
+++ b/.gitignore
@@ -11,6 +11,8 @@ jake/
**.b#*
**.s#*
+**/ASF/
+
js/node_modules/
sim/js_code.txt
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/boards/board.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/boards/board.h
deleted file mode 100644
index 0dc09cd..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/boards/board.h
+++ /dev/null
@@ -1,448 +0,0 @@
-/**
- * \file
- *
- * \brief Standard board header file.
- *
- * This file includes the appropriate board header file according to the
- * defined board (parameter BOARD).
- *
- * Copyright (c) 2009-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/**
- * \defgroup group_common_boards Generic board support
- *
- * The generic board support module includes board-specific definitions
- * and function prototypes, such as the board initialization function.
- *
- * \{
- */
-
-#include "compiler.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/*! \name Base Boards
- */
-//! @{
-#define EVK1100 1 //!< AT32UC3A EVK1100 board.
-#define EVK1101 2 //!< AT32UC3B EVK1101 board.
-#define UC3C_EK 3 //!< AT32UC3C UC3C-EK board.
-#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.
-#define EVK1105 5 //!< AT32UC3A EVK1105 board.
-#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board.
-#define UC3L_EK 7 //!< AT32UC3L-EK board.
-#define XPLAIN 8 //!< ATxmega128A1 Xplain board.
-#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board.
-#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board.
-#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board.
-#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board.
-#define STK600_RCUC3D 16 //!< STK600 RCUC3D board.
-#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board.
-#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board.
-#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board.
-#define XMEGA_A1U_XPLAINED_PRO 20 //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
-#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board.
-#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board.
-#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board.
-#define STK600_RC044X 24 //!< STK600 with RC044X routing card board.
-#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board.
-#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board.
-#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board.
-#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board.
-#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board.
-#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards.
-#define RZ600 31 //!< AT32UC3A RZ600 MCU board.
-#define SAM3S_EK 32 //!< SAM3S-EK board.
-#define SAM3U_EK 33 //!< SAM3U-EK board.
-#define SAM3X_EK 34 //!< SAM3X-EK board.
-#define SAM3N_EK 35 //!< SAM3N-EK board.
-#define SAM3S_EK2 36 //!< SAM3S-EK2 board.
-#define SAM4S_EK 37 //!< SAM4S-EK board.
-#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board.
-#define STK600_MEGA 39 //!< STK600 MEGA board.
-#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board.
-#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board.
-#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board.
-#define ARDUINO_DUE_X 43 //!< Arduino Due/X board.
-#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board.
-#define SAM4L_EK 45 //!< SAM4L-EK board.
-#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board.
-#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board.
-#define STK600_RC032X 48 //!< STK600 with RC032X routing card board.
-#define SAM4S_EK2 49 //!< SAM4S-EK2 board.
-#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board.
-#define SAM4E_EK 51 //!< SAM4E-EK board.
-#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board.
-#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board.
-#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board.
-#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit.
-#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 Zigbit.
-#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B Zigbit.
-#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board.
-#define SAMD20_XPLAINED_PRO 59 //!< SAM D20 Xplained Pro board.
-#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board.
-#define SAM4N_XPLAINED_PRO 61 //!< SAM4N Xplained Pro board.
-#define XMEGA_A3_REB_CBB 62 //!< XMEGA REB Controller Base board.
-#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB.
-#define SAM4C_EK 64 //!< SAM4C-EK board.
-#define RCB256RFR2_XPRO 65 //!< RFR2 RCB Xplained Pro board.
-#define SAMG53_XPLAINED_PRO 66 //!< SAMG53 Xplained Pro board.
-#define SAM4CP16BMB 67 //!< SAM4CP16BMB board.
-#define SAM4E_XPLAINED_PRO 68 //!< SAM4E Xplained Pro board.
-#define SAMD21_XPLAINED_PRO 69 //!< SAM D21 Xplained Pro board.
-#define SAMR21_XPLAINED_PRO 70 //!< SAM R21 Xplained Pro board.
-#define SAM4CMP_DB 71 //!< SAM4CMP demo board.
-#define SAM4CMS_DB 72 //!< SAM4CMS demo board.
-#define ATPL230AMB 73 //!< ATPL230AMB board.
-#define SAMD11_XPLAINED_PRO 74 //!< SAM D11 Xplained Pro board.
-#define SAMG55_XPLAINED_PRO 75 //!< SAMG55 Xplained Pro board.
-#define SAML21_XPLAINED_PRO 76 //!< SAM L21 Xplained Pro board.
-#define SAMD10_XPLAINED_MINI 77 //!< SAM D10 Xplained Mini board.
-#define SAMDA1_XPLAINED_PRO 78 //!< SAM DA1 Xplained Pro board.
-#define SAMW25_XPLAINED_PRO 79 //!< SAMW25 Xplained Pro board.
-#define SAMC21_XPLAINED_PRO 80 //!< SAM C21 Xplained Pro board.
-#define SAMV71_XPLAINED_ULTRA 81 //!< SAMV71 Xplained Ultra board.
-#define ATMEGA328P_XPLAINED_MINI 82 //!< ATMEGA328P Xplained MINI board.
-#define ATMEGA328PB_XPLAINED_MINI 83 //!< ATMEGA328PB Xplained MINI board.
-#define SAMB11_XPLAINED_PRO 84 //!< SAM B11 Xplained Pro board.
-#define SAME70_XPLAINED 85 //!< SAME70 Xplained board.
-#define SAML22_XPLAINED_PRO 86 //!< SAM L22 Xplained Pro board.
-#define SAML22_XPLAINED_PRO_B 87 //!< SAM L22 Xplained Pro board.
-#define SAMR21ZLL_EK 88 //!< SAMR21ZLL-EK board.
-#define ATMEGA168PB_XPLAINED_MINI 89 //!< ATMEGA168PB Xplained MINI board.
-#define ATMEGA324PB_XPLAINED_PRO 90 //!< ATMEGA324PB Xplained Pro board.
-#define SAMB11CSP_XPLAINED_PRO 91 //!< SAM B11 CSP Xplained Pro board.
-#define SAMB11ZR_XPLAINED_PRO 92 //!< SAM B11 ZR Xplained Pro board.
-#define SAMR30_XPLAINED_PRO 93 //!< SAM R30 Xplained Pro board.
-#define SAMHA1G16A_XPLAINED_PRO 94 //!< SAM HA1G16A Xplained Pro board.
-#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices.
-#define AVR_SIMULATOR_UC3 98 //!< Simulator for the AVR UC3 device family.
-#define USER_BOARD 99 //!< User-reserved board (if any).
-#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader).
-//! @}
-
-/*! \name Extension Boards
- */
-//! @{
-#define EXT1102 1 //!< AT32UC3B EXT1102 board
-#define MC300 2 //!< AT32UC3 MC300 board
-#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1
-#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2
-#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board
-#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board
-#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A"
-#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600
-#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600
-#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600
-#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard
-#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board
-#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).
-//! @}
-
-#if BOARD == EVK1100
-# include "evk1100/evk1100.h"
-#elif BOARD == EVK1101
-# include "evk1101/evk1101.h"
-#elif BOARD == UC3C_EK
-# include "uc3c_ek/uc3c_ek.h"
-#elif BOARD == EVK1104
-# include "evk1104/evk1104.h"
-#elif BOARD == EVK1105
-# include "evk1105/evk1105.h"
-#elif BOARD == STK600_RCUC3L0
-# include "stk600/rcuc3l0/stk600_rcuc3l0.h"
-#elif BOARD == UC3L_EK
-# include "uc3l_ek/uc3l_ek.h"
-#elif BOARD == STK600_RCUC3L4
-# include "stk600/rcuc3l4/stk600_rcuc3l4.h"
-#elif BOARD == XPLAIN
-# include "xplain/xplain.h"
-#elif BOARD == STK600_MEGA
- /*No header-file to include*/
-#elif BOARD == STK600_MEGA_RF
-# include "stk600.h"
-#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO
-# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"
-#elif BOARD == ATMEGA256RFR2_ZIGBIT
-# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"
-#elif BOARD == STK600_RC032X
-# include "stk600/rc032x/stk600_rc032x.h"
-#elif BOARD == STK600_RC044X
-# include "stk600/rc044x/stk600_rc044x.h"
-#elif BOARD == STK600_RC064X
-# include "stk600/rc064x/stk600_rc064x.h"
-#elif BOARD == STK600_RC100X
-# include "stk600/rc100x/stk600_rc100x.h"
-#elif BOARD == UC3_A3_XPLAINED
-# include "uc3_a3_xplained/uc3_a3_xplained.h"
-#elif BOARD == UC3_L0_XPLAINED
-# include "uc3_l0_xplained/uc3_l0_xplained.h"
-#elif BOARD == STK600_RCUC3B0
-# include "stk600/rcuc3b0/stk600_rcuc3b0.h"
-#elif BOARD == STK600_RCUC3D
-# include "stk600/rcuc3d/stk600_rcuc3d.h"
-#elif BOARD == STK600_RCUC3C0
-# include "stk600/rcuc3c0/stk600_rcuc3c0.h"
-#elif BOARD == SAMG53_XPLAINED_PRO
-# include "samg53_xplained_pro/samg53_xplained_pro.h"
-#elif BOARD == SAMG55_XPLAINED_PRO
-# include "samg55_xplained_pro/samg55_xplained_pro.h"
-#elif BOARD == XMEGA_B1_XPLAINED
-# include "xmega_b1_xplained/xmega_b1_xplained.h"
-#elif BOARD == STK600_RC064X_LCDX
-# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"
-#elif BOARD == STK600_RC100X_LCDX
-# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"
-#elif BOARD == XMEGA_A1_XPLAINED
-# include "xmega_a1_xplained/xmega_a1_xplained.h"
-#elif BOARD == XMEGA_A1U_XPLAINED_PRO
-# include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h"
-#elif BOARD == UC3_L0_XPLAINED_BC
-# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"
-#elif BOARD == SAM3S_EK
-# include "sam3s_ek/sam3s_ek.h"
-# include "system_sam3s.h"
-#elif BOARD == SAM3S_EK2
-# include "sam3s_ek2/sam3s_ek2.h"
-# include "system_sam3sd8.h"
-#elif BOARD == SAM3U_EK
-# include "sam3u_ek/sam3u_ek.h"
-# include "system_sam3u.h"
-#elif BOARD == SAM3X_EK
-# include "sam3x_ek/sam3x_ek.h"
-# include "system_sam3x.h"
-#elif BOARD == SAM3N_EK
-# include "sam3n_ek/sam3n_ek.h"
-# include "system_sam3n.h"
-#elif BOARD == SAM4S_EK
-# include "sam4s_ek/sam4s_ek.h"
-# include "system_sam4s.h"
-#elif BOARD == SAM4S_WPIR_RD
-# include "sam4s_wpir_rd/sam4s_wpir_rd.h"
-# include "system_sam4s.h"
-#elif BOARD == SAM4S_XPLAINED
-# include "sam4s_xplained/sam4s_xplained.h"
-# include "system_sam4s.h"
-#elif BOARD == SAM4S_EK2
-# include "sam4s_ek2/sam4s_ek2.h"
-# include "system_sam4s.h"
-#elif BOARD == MEGA_1284P_XPLAINED
- /*No header-file to include*/
-#elif BOARD == ARDUINO_DUE_X
-# include "arduino_due_x/arduino_due_x.h"
-# include "system_sam3x.h"
-#elif BOARD == SAM4L_EK
-# include "sam4l_ek/sam4l_ek.h"
-#elif BOARD == SAM4E_EK
-# include "sam4e_ek/sam4e_ek.h"
-#elif BOARD == SAMD20_XPLAINED_PRO
-# include "samd20_xplained_pro/samd20_xplained_pro.h"
-#elif BOARD == SAMD21_XPLAINED_PRO
-# include "samd21_xplained_pro/samd21_xplained_pro.h"
-#elif BOARD == SAMR21_XPLAINED_PRO
-# include "samr21_xplained_pro/samr21_xplained_pro.h"
-#elif BOARD == SAMR30_XPLAINED_PRO
-# include "samr30_xplained_pro/samr30_xplained_pro.h"
-#elif BOARD == SAMR21ZLL_EK
-# include "samr21zll_ek/samr21zll_ek.h"
-#elif BOARD == SAMD11_XPLAINED_PRO
-# include "samd11_xplained_pro/samd11_xplained_pro.h"
-#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__)
-# include "saml21_xplained_pro/saml21_xplained_pro.h"
-#elif BOARD == SAML22_XPLAINED_PRO
-# include "saml22_xplained_pro/saml22_xplained_pro.h"
-#elif BOARD == SAML22_XPLAINED_PRO_B
-# include "saml22_xplained_pro_b/saml22_xplained_pro_b.h"
-#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__)
-# include "saml21_xplained_pro_b/saml21_xplained_pro.h"
-#elif BOARD == SAMD10_XPLAINED_MINI
-# include "samd10_xplained_mini/samd10_xplained_mini.h"
-#elif BOARD == SAMDA1_XPLAINED_PRO
-# include "samda1_xplained_pro/samda1_xplained_pro.h"
-#elif BOARD == SAMHA1G16A_XPLAINED_PRO
-# include "samha1g16a_xplained_pro/samha1g16a_xplained_pro.h"
-#elif BOARD == SAMC21_XPLAINED_PRO
-# include "samc21_xplained_pro/samc21_xplained_pro.h"
-#elif BOARD == SAM4N_XPLAINED_PRO
-# include "sam4n_xplained_pro/sam4n_xplained_pro.h"
-#elif BOARD == SAMW25_XPLAINED_PRO
-# include "samw25_xplained_pro/samw25_xplained_pro.h"
-#elif BOARD == SAMV71_XPLAINED_ULTRA
-# include "samv71_xplained_ultra/samv71_xplained_ultra.h"
-#elif BOARD == MEGA1284P_XPLAINED_BC
-# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"
-#elif BOARD == UC3_L0_QT600
-# include "uc3_l0_qt600/uc3_l0_qt600.h"
-#elif BOARD == XMEGA_A3BU_XPLAINED
-# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"
-#elif BOARD == XMEGA_E5_XPLAINED
-# include "xmega_e5_xplained/xmega_e5_xplained.h"
-#elif BOARD == UC3B_BOARD_CONTROLLER
-# include "uc3b_board_controller/uc3b_board_controller.h"
-#elif BOARD == RZ600
-# include "rz600/rz600.h"
-#elif BOARD == STK600_RCUC3A0
-# include "stk600/rcuc3a0/stk600_rcuc3a0.h"
-#elif BOARD == ATXMEGA128A1_QT600
-# include "atxmega128a1_qt600/atxmega128a1_qt600.h"
-#elif BOARD == STK600_RCUC3L3
-# include "stk600/rcuc3l3/stk600_rcuc3l3.h"
-#elif BOARD == SAM4S_XPLAINED_PRO
-# include "sam4s_xplained_pro/sam4s_xplained_pro.h"
-#elif BOARD == SAM4L_XPLAINED_PRO
-# include "sam4l_xplained_pro/sam4l_xplained_pro.h"
-#elif BOARD == SAM4L8_XPLAINED_PRO
-# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"
-#elif BOARD == SAM4C_EK
-# include "sam4c_ek/sam4c_ek.h"
-#elif BOARD == SAM4CMP_DB
-# include "sam4cmp_db/sam4cmp_db.h"
-#elif BOARD == SAM4CMS_DB
-# include "sam4cms_db/sam4cms_db.h"
-#elif BOARD == SAM4CP16BMB
-# include "sam4cp16bmb/sam4cp16bmb.h"
-#elif BOARD == ATPL230AMB
-# include "atpl230amb/atpl230amb.h"
-#elif BOARD == XMEGA_C3_XPLAINED
-# include "xmega_c3_xplained/xmega_c3_xplained.h"
-#elif BOARD == XMEGA_RF233_ZIGBIT
-# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"
-#elif BOARD == XMEGA_A3_REB_CBB
-# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"
-#elif BOARD == ATMEGARFX_RCB
-# include "atmegarfx_rcb/atmegarfx_rcb.h"
-#elif BOARD == RCB256RFR2_XPRO
-# include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h"
-#elif BOARD == XMEGA_RF212B_ZIGBIT
-# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"
-#elif BOARD == SAM4E_XPLAINED_PRO
-# include "sam4e_xplained_pro/sam4e_xplained_pro.h"
-#elif BOARD == ATMEGA328P_XPLAINED_MINI
-# include "atmega328p_xplained_mini/atmega328p_xplained_mini.h"
-#elif BOARD == ATMEGA328PB_XPLAINED_MINI
-# include "atmega328pb_xplained_mini/atmega328pb_xplained_mini.h"
-#elif BOARD == SAMB11_XPLAINED_PRO
-# include "samb11_xplained_pro/samb11_xplained_pro.h"
-#elif BOARD == SAME70_XPLAINED
-# include "same70_xplained/same70_xplained.h"
-#elif BOARD == ATMEGA168PB_XPLAINED_MINI
-# include "atmega168pb_xplained_mini/atmega168pb_xplained_mini.h"
-#elif BOARD == ATMEGA324PB_XPLAINED_PRO
-# include "atmega324pb_xplained_pro/atmega324pb_xplained_pro.h"
-#elif BOARD == SAMB11CSP_XPLAINED_PRO
-# include "samb11csp_xplained_pro/samb11csp_xplained_pro.h"
-#elif BOARD == SAMB11ZR_XPLAINED_PRO
-# include "samb11zr_xplained_pro/samb11zr_xplained_pro.h"
-#elif BOARD == SIMULATOR_XMEGA_A1
-# include "simulator/xmega_a1/simulator_xmega_a1.h"
-#elif BOARD == AVR_SIMULATOR_UC3
-# include "avr_simulator_uc3/avr_simulator_uc3.h"
-#elif BOARD == USER_BOARD
- // User-reserved area: #include the header file of your board here (if any).
-# include "user_board.h"
-#elif BOARD == DUMMY_BOARD
-# include "dummy/dummy_board.h"
-#else
-# error No known Atmel board defined
-#endif
-
-#if (defined EXT_BOARD)
-# if EXT_BOARD == MC300
-# include "mc300/mc300.h"
-# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \
- (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \
- (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \
- (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \
- (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \
- (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
-# include "sensors_xplained/sensors_xplained.h"
-# elif EXT_BOARD == RZ600_AT86RF231
-# include "at86rf231/at86rf231.h"
-# elif EXT_BOARD == RZ600_AT86RF230B
-# include "at86rf230b/at86rf230b.h"
-# elif EXT_BOARD == RZ600_AT86RF212
-# include "at86rf212/at86rf212.h"
-# elif EXT_BOARD == SECURITY_XPLAINED
-# include "security_xplained.h"
-# elif EXT_BOARD == USER_EXT_BOARD
- // User-reserved area: #include the header file of your extension board here
- // (if any).
-# endif
-#endif
-
-
-#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
-#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
-
-/*! \brief This function initializes the board target resources
- *
- * This function should be called to ensure proper initialization of the target
- * board hardware connected to the part.
- */
-extern void board_init(void);
-
-#endif // #ifdef __AVR32_ABI_COMPILER__
-#else
-/*! \brief This function initializes the board target resources
- *
- * This function should be called to ensure proper initialization of the target
- * board hardware connected to the part.
- */
-extern void board_init(void);
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * \}
- */
-
-#endif // _BOARD_H_
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/boards/user_board/init.c b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/boards/user_board/init.c
deleted file mode 100644
index 32fba36..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/boards/user_board/init.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/**
- * \file
- *
- * \brief User board initialization template
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include <asf.h>
-#include <board.h>
-#include <conf_board.h>
-
-void board_init(void)
-{
- /* This function is meant to contain board-specific initialization code
- * for, e.g., the I/O pins. The initialization can rely on application-
- * specific board configuration, found in conf_board.h.
- */
-}
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/boards/user_board/user_board.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/boards/user_board/user_board.h
deleted file mode 100644
index 39980a7..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/boards/user_board/user_board.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/**
- * \file
- *
- * \brief User board definition template
- *
- */
-
- /* This file is intended to contain definitions and configuration details for
- * features and devices that are available on the board, e.g., frequency and
- * startup time for an external crystal, external memory devices, LED and USART
- * pins.
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef USER_BOARD_H
-#define USER_BOARD_H
-
-#include <conf_board.h>
-
-// External oscillator settings.
-// Uncomment and set correct values if external oscillator is used.
-
-// External oscillator frequency
-//#define BOARD_XOSC_HZ 8000000
-
-// External oscillator type.
-//!< External clock signal
-//#define BOARD_XOSC_TYPE XOSC_TYPE_EXTERNAL
-//!< 32.768 kHz resonator on TOSC
-//#define BOARD_XOSC_TYPE XOSC_TYPE_32KHZ
-//!< 0.4 to 16 MHz resonator on XTALS
-//#define BOARD_XOSC_TYPE XOSC_TYPE_XTAL
-
-// External oscillator startup time
-//#define BOARD_XOSC_STARTUP_US 500000
-
-
-#endif // USER_BOARD_H
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/genclk.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/genclk.h
deleted file mode 100644
index 503a50a..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/genclk.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/**
- * \file
- *
- * \brief Generic clock management
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef CLK_GENCLK_H_INCLUDED
-#define CLK_GENCLK_H_INCLUDED
-
-#include "parts.h"
-
-#if SAM3S
-# include "sam3s/genclk.h"
-#elif SAM3U
-# include "sam3u/genclk.h"
-#elif SAM3N
-# include "sam3n/genclk.h"
-#elif SAM3XA
-# include "sam3x/genclk.h"
-#elif SAM4S
-# include "sam4s/genclk.h"
-#elif SAM4L
-# include "sam4l/genclk.h"
-#elif SAM4E
-# include "sam4e/genclk.h"
-#elif SAM4N
-# include "sam4n/genclk.h"
-#elif SAM4C
-# include "sam4c/genclk.h"
-#elif SAM4CM
-# include "sam4cm/genclk.h"
-#elif SAM4CP
-# include "sam4cp/genclk.h"
-#elif SAMG
-# include "samg/genclk.h"
-#elif SAMV71
-# include "samv71/genclk.h"
-#elif SAMV70
-# include "samv70/genclk.h"
-#elif SAME70
-# include "same70/genclk.h"
-#elif SAMS70
-# include "sams70/genclk.h"
-#elif (UC3A0 || UC3A1)
-# include "uc3a0_a1/genclk.h"
-#elif UC3A3
-# include "uc3a3_a4/genclk.h"
-#elif UC3B
-# include "uc3b0_b1/genclk.h"
-#elif UC3C
-# include "uc3c/genclk.h"
-#elif UC3D
-# include "uc3d/genclk.h"
-#elif UC3L
-# include "uc3l/genclk.h"
-#else
-# error Unsupported chip type
-#endif
-
-/**
- * \ingroup clk_group
- * \defgroup genclk_group Generic Clock Management
- *
- * Generic clocks are configurable clocks which run outside the system
- * clock domain. They are often connected to peripherals which have an
- * asynchronous component running independently of the bus clock, e.g.
- * USB controllers, low-power timers and RTCs, etc.
- *
- * Note that not all platforms have support for generic clocks; on such
- * platforms, this API will not be available.
- *
- * @{
- */
-
-/**
- * \def GENCLK_DIV_MAX
- * \brief Maximum divider supported by the generic clock implementation
- */
-/**
- * \enum genclk_source
- * \brief Generic clock source ID
- *
- * Each generic clock may be generated from a different clock source.
- * These are the available alternatives provided by the chip.
- */
-
-//! \name Generic clock configuration
-//@{
-/**
- * \struct genclk_config
- * \brief Hardware representation of a set of generic clock parameters
- */
-/**
- * \fn void genclk_config_defaults(struct genclk_config *cfg,
- * unsigned int id)
- * \brief Initialize \a cfg to the default configuration for the clock
- * identified by \a id.
- */
-/**
- * \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id)
- * \brief Read the currently active configuration of the clock
- * identified by \a id into \a cfg.
- */
-/**
- * \fn void genclk_config_write(const struct genclk_config *cfg,
- * unsigned int id)
- * \brief Activate the configuration \a cfg on the clock identified by
- * \a id.
- */
-/**
- * \fn void genclk_config_set_source(struct genclk_config *cfg,
- * enum genclk_source src)
- * \brief Select a new source clock \a src in configuration \a cfg.
- */
-/**
- * \fn void genclk_config_set_divider(struct genclk_config *cfg,
- * unsigned int divider)
- * \brief Set a new \a divider in configuration \a cfg.
- */
-/**
- * \fn void genclk_enable_source(enum genclk_source src)
- * \brief Enable the source clock \a src used by a generic clock.
- */
- //@}
-
-//! \name Enabling and disabling Generic Clocks
-//@{
-/**
- * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id)
- * \brief Activate the configuration \a cfg on the clock identified by
- * \a id and enable it.
- */
-/**
- * \fn void genclk_disable(unsigned int id)
- * \brief Disable the generic clock identified by \a id.
- */
-//@}
-
-/**
- * \brief Enable the configuration defined by \a src and \a divider
- * for the generic clock identified by \a id.
- *
- * \param id The ID of the generic clock.
- * \param src The source clock of the generic clock.
- * \param divider The divider used to generate the generic clock.
- */
-static inline void genclk_enable_config(unsigned int id, enum genclk_source src, unsigned int divider)
-{
- struct genclk_config gcfg;
-
- genclk_config_defaults(&gcfg, id);
- genclk_enable_source(src);
- genclk_config_set_source(&gcfg, src);
- genclk_config_set_divider(&gcfg, divider);
- genclk_enable(&gcfg, id);
-}
-
-//! @}
-
-#endif /* CLK_GENCLK_H_INCLUDED */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/osc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/osc.h
deleted file mode 100644
index e67f01f..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/osc.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/**
- * \file
- *
- * \brief Oscillator management
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef OSC_H_INCLUDED
-#define OSC_H_INCLUDED
-
-#include "parts.h"
-#include "conf_clock.h"
-
-#if SAM3S
-# include "sam3s/osc.h"
-#elif SAM3XA
-# include "sam3x/osc.h"
-#elif SAM3U
-# include "sam3u/osc.h"
-#elif SAM3N
-# include "sam3n/osc.h"
-#elif SAM4S
-# include "sam4s/osc.h"
-#elif SAM4E
-# include "sam4e/osc.h"
-#elif SAM4C
-# include "sam4c/osc.h"
-#elif SAM4CM
-# include "sam4cm/osc.h"
-#elif SAM4CP
-# include "sam4cp/osc.h"
-#elif SAM4L
-# include "sam4l/osc.h"
-#elif SAM4N
-# include "sam4n/osc.h"
-#elif SAMG
-# include "samg/osc.h"
-#elif SAMV71
-# include "samv71/osc.h"
-#elif SAMV70
-# include "samv70/osc.h"
-#elif SAME70
-# include "same70/osc.h"
-#elif SAMS70
-# include "sams70/osc.h"
-#elif (UC3A0 || UC3A1)
-# include "uc3a0_a1/osc.h"
-#elif UC3A3
-# include "uc3a3_a4/osc.h"
-#elif UC3B
-# include "uc3b0_b1/osc.h"
-#elif UC3C
-# include "uc3c/osc.h"
-#elif UC3D
-# include "uc3d/osc.h"
-#elif UC3L
-# include "uc3l/osc.h"
-#elif XMEGA
-# include "xmega/osc.h"
-#else
-# error Unsupported chip type
-#endif
-
-/**
- * \ingroup clk_group
- * \defgroup osc_group Oscillator Management
- *
- * This group contains functions and definitions related to configuring
- * and enabling/disabling on-chip oscillators. Internal RC-oscillators,
- * external crystal oscillators and external clock generators are
- * supported by this module. What all of these have in common is that
- * they swing at a fixed, nominal frequency which is normally not
- * adjustable.
- *
- * \par Example: Enabling an oscillator
- *
- * The following example demonstrates how to enable the external
- * oscillator on XMEGA A and wait for it to be ready to use. The
- * oscillator identifiers are platform-specific, so while the same
- * procedure is used on all platforms, the parameter to osc_enable()
- * will be different from device to device.
- * \code
- osc_enable(OSC_ID_XOSC);
- osc_wait_ready(OSC_ID_XOSC); \endcode
- *
- * \section osc_group_board Board-specific Definitions
- * If external oscillators are used, the board code must provide the
- * following definitions for each of those:
- * - \b BOARD_<osc name>_HZ: The nominal frequency of the oscillator.
- * - \b BOARD_<osc name>_STARTUP_US: The startup time of the
- * oscillator in microseconds.
- * - \b BOARD_<osc name>_TYPE: The type of oscillator connected, i.e.
- * whether it's a crystal or external clock, and sometimes what kind
- * of crystal it is. The meaning of this value is platform-specific.
- *
- * @{
- */
-
-//! \name Oscillator Management
-//@{
-/**
- * \fn void osc_enable(uint8_t id)
- * \brief Enable oscillator \a id
- *
- * The startup time and mode value is automatically determined based on
- * definitions in the board code.
- */
-/**
- * \fn void osc_disable(uint8_t id)
- * \brief Disable oscillator \a id
- */
-/**
- * \fn osc_is_ready(uint8_t id)
- * \brief Determine whether oscillator \a id is ready.
- * \retval true Oscillator \a id is running and ready to use as a clock
- * source.
- * \retval false Oscillator \a id is not running.
- */
-/**
- * \fn uint32_t osc_get_rate(uint8_t id)
- * \brief Return the frequency of oscillator \a id in Hz
- */
-
-#ifndef __ASSEMBLY__
-
-/**
- * \brief Wait until the oscillator identified by \a id is ready
- *
- * This function will busy-wait for the oscillator identified by \a id
- * to become stable and ready to use as a clock source.
- *
- * \param id A number identifying the oscillator to wait for.
- */
-static inline void osc_wait_ready(uint8_t id)
-{
- while (!osc_is_ready(id)) {
- /* Do nothing */
- }
-}
-
-#endif /* __ASSEMBLY__ */
-
-//@}
-
-//! @}
-
-#endif /* OSC_H_INCLUDED */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/pll.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/pll.h
deleted file mode 100644
index 23e930c..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/pll.h
+++ /dev/null
@@ -1,341 +0,0 @@
-/**
- * \file
- *
- * \brief PLL management
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef CLK_PLL_H_INCLUDED
-#define CLK_PLL_H_INCLUDED
-
-#include "parts.h"
-#include "conf_clock.h"
-
-#if SAM3S
-# include "sam3s/pll.h"
-#elif SAM3XA
-# include "sam3x/pll.h"
-#elif SAM3U
-# include "sam3u/pll.h"
-#elif SAM3N
-# include "sam3n/pll.h"
-#elif SAM4S
-# include "sam4s/pll.h"
-#elif SAM4E
-# include "sam4e/pll.h"
-#elif SAM4C
-# include "sam4c/pll.h"
-#elif SAM4CM
-# include "sam4cm/pll.h"
-#elif SAM4CP
-# include "sam4cp/pll.h"
-#elif SAM4L
-# include "sam4l/pll.h"
-#elif SAM4N
-# include "sam4n/pll.h"
-#elif SAMG
-# include "samg/pll.h"
-#elif SAMV71
-# include "samv71/pll.h"
-#elif SAMV70
-# include "samv70/pll.h"
-#elif SAME70
-# include "same70/pll.h"
-#elif SAMS70
-# include "sams70/pll.h"
-#elif (UC3A0 || UC3A1)
-# include "uc3a0_a1/pll.h"
-#elif UC3A3
-# include "uc3a3_a4/pll.h"
-#elif UC3B
-# include "uc3b0_b1/pll.h"
-#elif UC3C
-# include "uc3c/pll.h"
-#elif UC3D
-# include "uc3d/pll.h"
-#elif (UC3L0128 || UC3L0256 || UC3L3_L4)
-# include "uc3l/pll.h"
-#elif XMEGA
-# include "xmega/pll.h"
-#else
-# error Unsupported chip type
-#endif
-
-/**
- * \ingroup clk_group
- * \defgroup pll_group PLL Management
- *
- * This group contains functions and definitions related to configuring
- * and enabling/disabling on-chip PLLs. A PLL will take an input signal
- * (the \em source), optionally divide the frequency by a configurable
- * \em divider, and then multiply the frequency by a configurable \em
- * multiplier.
- *
- * Some devices don't support input dividers; specifying any other
- * divisor than 1 on these devices will result in an assertion failure.
- * Other devices may have various restrictions to the frequency range of
- * the input and output signals.
- *
- * \par Example: Setting up PLL0 with default parameters
- *
- * The following example shows how to configure and enable PLL0 using
- * the default parameters specified using the configuration symbols
- * listed above.
- * \code
- pll_enable_config_defaults(0); \endcode
- *
- * To configure, enable PLL0 using the default parameters and to disable
- * a specific feature like Wide Bandwidth Mode (a UC3A3-specific
- * PLL option.), you can use this initialization process.
- * \code
- struct pll_config pllcfg;
- if (pll_is_locked(pll_id)) {
- return; // Pll already running
- }
- pll_enable_source(CONFIG_PLL0_SOURCE);
- pll_config_defaults(&pllcfg, 0);
- pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);
- pll_enable(&pllcfg, 0);
- pll_wait_for_lock(0); \endcode
- *
- * When the last function call returns, PLL0 is ready to be used as the
- * main system clock source.
- *
- * \section pll_group_config Configuration Symbols
- *
- * Each PLL has a set of default parameters determined by the following
- * configuration symbols in the application's configuration file:
- * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the
- * input of PLL \a n. Must be one of the values defined by the
- * #pll_source enum.
- * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL
- * \a n.
- * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n.
- *
- * These configuration symbols determine the result of calling
- * pll_config_defaults() and pll_get_default_rate().
- *
- * @{
- */
-
-//! \name Chip-specific PLL characteristics
-//@{
-/**
- * \def PLL_MAX_STARTUP_CYCLES
- * \brief Maximum PLL startup time in number of slow clock cycles
- */
-/**
- * \def NR_PLLS
- * \brief Number of on-chip PLLs
- */
-
-/**
- * \def PLL_MIN_HZ
- * \brief Minimum frequency that the PLL can generate
- */
-/**
- * \def PLL_MAX_HZ
- * \brief Maximum frequency that the PLL can generate
- */
-/**
- * \def PLL_NR_OPTIONS
- * \brief Number of PLL option bits
- */
-//@}
-
-/**
- * \enum pll_source
- * \brief PLL clock source
- */
-
-//! \name PLL configuration
-//@{
-
-/**
- * \struct pll_config
- * \brief Hardware-specific representation of PLL configuration.
- *
- * This structure contains one or more device-specific values
- * representing the current PLL configuration. The contents of this
- * structure is typically different from platform to platform, and the
- * user should not access any fields except through the PLL
- * configuration API.
- */
-
-/**
- * \fn void pll_config_init(struct pll_config *cfg,
- * enum pll_source src, unsigned int div, unsigned int mul)
- * \brief Initialize PLL configuration from standard parameters.
- *
- * \note This function may be defined inline because it is assumed to be
- * called very few times, and usually with constant parameters. Inlining
- * it will in such cases reduce the code size significantly.
- *
- * \param cfg The PLL configuration to be initialized.
- * \param src The oscillator to be used as input to the PLL.
- * \param div PLL input divider.
- * \param mul PLL loop divider (i.e. multiplier).
- *
- * \return A configuration which will make the PLL run at
- * (\a mul / \a div) times the frequency of \a src
- */
-/**
- * \def pll_config_defaults(cfg, pll_id)
- * \brief Initialize PLL configuration using default parameters.
- *
- * After this function returns, \a cfg will contain a configuration
- * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV)
- * times the frequency of CONFIG_PLLx_SOURCE.
- *
- * \param cfg The PLL configuration to be initialized.
- * \param pll_id Use defaults for this PLL.
- */
-/**
- * \def pll_get_default_rate(pll_id)
- * \brief Get the default rate in Hz of \a pll_id
- */
-/**
- * \fn void pll_config_set_option(struct pll_config *cfg,
- * unsigned int option)
- * \brief Set the PLL option bit \a option in the configuration \a cfg.
- *
- * \param cfg The PLL configuration to be changed.
- * \param option The PLL option bit to be set.
- */
-/**
- * \fn void pll_config_clear_option(struct pll_config *cfg,
- * unsigned int option)
- * \brief Clear the PLL option bit \a option in the configuration \a cfg.
- *
- * \param cfg The PLL configuration to be changed.
- * \param option The PLL option bit to be cleared.
- */
-/**
- * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id)
- * \brief Read the currently active configuration of \a pll_id.
- *
- * \param cfg The configuration object into which to store the currently
- * active configuration.
- * \param pll_id The ID of the PLL to be accessed.
- */
-/**
- * \fn void pll_config_write(const struct pll_config *cfg,
- * unsigned int pll_id)
- * \brief Activate the configuration \a cfg on \a pll_id
- *
- * \param cfg The configuration object representing the PLL
- * configuration to be activated.
- * \param pll_id The ID of the PLL to be updated.
- */
-
-//@}
-
-//! \name Interaction with the PLL hardware
-//@{
-/**
- * \fn void pll_enable(const struct pll_config *cfg,
- * unsigned int pll_id)
- * \brief Activate the configuration \a cfg and enable PLL \a pll_id.
- *
- * \param cfg The PLL configuration to be activated.
- * \param pll_id The ID of the PLL to be enabled.
- */
-/**
- * \fn void pll_disable(unsigned int pll_id)
- * \brief Disable the PLL identified by \a pll_id.
- *
- * After this function is called, the PLL identified by \a pll_id will
- * be disabled. The PLL configuration stored in hardware may be affected
- * by this, so if the caller needs to restore the same configuration
- * later, it should either do a pll_config_read() before disabling the
- * PLL, or remember the last configuration written to the PLL.
- *
- * \param pll_id The ID of the PLL to be disabled.
- */
-/**
- * \fn bool pll_is_locked(unsigned int pll_id)
- * \brief Determine whether the PLL is locked or not.
- *
- * \param pll_id The ID of the PLL to check.
- *
- * \retval true The PLL is locked and ready to use as a clock source
- * \retval false The PLL is not yet locked, or has not been enabled.
- */
-/**
- * \fn void pll_enable_source(enum pll_source src)
- * \brief Enable the source of the pll.
- * The source is enabled, if the source is not already running.
- *
- * \param src The ID of the PLL source to enable.
- */
-/**
- * \fn void pll_enable_config_defaults(unsigned int pll_id)
- * \brief Enable the pll with the default configuration.
- * PLL is enabled, if the PLL is not already locked.
- *
- * \param pll_id The ID of the PLL to enable.
- */
-
-/**
- * \brief Wait for PLL \a pll_id to become locked
- *
- * \todo Use a timeout to avoid waiting forever and hanging the system
- *
- * \param pll_id The ID of the PLL to wait for.
- *
- * \retval STATUS_OK The PLL is now locked.
- * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked.
- */
-static inline int pll_wait_for_lock(unsigned int pll_id)
-{
- Assert(pll_id < NR_PLLS);
-
- while (!pll_is_locked(pll_id)) {
- /* Do nothing */
- }
-
- return 0;
-}
-
-//@}
-//! @}
-
-#endif /* CLK_PLL_H_INCLUDED */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/genclk.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/genclk.h
deleted file mode 100644
index fbb069a..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/genclk.h
+++ /dev/null
@@ -1,269 +0,0 @@
-/**
- * \file
- *
- * \brief Chip-specific generic clock management.
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef CHIP_GENCLK_H_INCLUDED
-#define CHIP_GENCLK_H_INCLUDED
-
-#include <osc.h>
-#include <pll.h>
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-/**
- * \weakgroup genclk_group
- * @{
- */
-
-//! \name Programmable Clock Identifiers (PCK)
-//@{
-#define GENCLK_PCK_0 0 //!< PCK0 ID
-#define GENCLK_PCK_1 1 //!< PCK1 ID
-#define GENCLK_PCK_2 2 //!< PCK2 ID
-//@}
-
-//! \name Programmable Clock Sources (PCK)
-//@{
-
-enum genclk_source {
- GENCLK_PCK_SRC_SLCK_RC = 0,//!< Internal 32kHz RC oscillator as PCK source clock
- GENCLK_PCK_SRC_SLCK_XTAL = 1,//!< External 32kHz crystal oscillator as PCK source clock
- GENCLK_PCK_SRC_SLCK_BYPASS = 2,//!< External 32kHz bypass oscillator as PCK source clock
- GENCLK_PCK_SRC_MAINCK_4M_RC = 3,//!< Internal 4MHz RC oscillator as PCK source clock
- GENCLK_PCK_SRC_MAINCK_8M_RC = 4,//!< Internal 8MHz RC oscillator as PCK source clock
- GENCLK_PCK_SRC_MAINCK_12M_RC = 5,//!< Internal 12MHz RC oscillator as PCK source clock
- GENCLK_PCK_SRC_MAINCK_XTAL = 6,//!< External crystal oscillator as PCK source clock
- GENCLK_PCK_SRC_MAINCK_BYPASS = 7,//!< External bypass oscillator as PCK source clock
- GENCLK_PCK_SRC_PLLACK = 8,//!< Use PLLACK as PCK source clock
- GENCLK_PCK_SRC_MCK = 9,//!< Use Master Clk as PCK source clock
-};
-
-//@}
-
-//! \name Programmable Clock Prescalers (PCK)
-//@{
-
-enum genclk_divider {
- GENCLK_PCK_PRES_1 = PMC_PCK_PRES(0), //!< Set PCK clock prescaler to 1
- GENCLK_PCK_PRES_2 = PMC_PCK_PRES(1), //!< Set PCK clock prescaler to 2
- GENCLK_PCK_PRES_4 = PMC_PCK_PRES(2), //!< Set PCK clock prescaler to 4
- GENCLK_PCK_PRES_8 = PMC_PCK_PRES(3), //!< Set PCK clock prescaler to 8
- GENCLK_PCK_PRES_16 = PMC_PCK_PRES(4), //!< Set PCK clock prescaler to 16
- GENCLK_PCK_PRES_32 = PMC_PCK_PRES(5), //!< Set PCK clock prescaler to 32
- GENCLK_PCK_PRES_64 = PMC_PCK_PRES(6), //!< Set PCK clock prescaler to 64
-};
-
-//@}
-
-struct genclk_config {
- uint32_t ctrl;
-};
-
-static inline void genclk_config_defaults(struct genclk_config *p_cfg,
- uint32_t ul_id)
-{
- ul_id = ul_id;
- p_cfg->ctrl = 0;
-}
-
-static inline void genclk_config_read(struct genclk_config *p_cfg,
- uint32_t ul_id)
-{
- p_cfg->ctrl = PMC->PMC_PCK[ul_id];
-}
-
-static inline void genclk_config_write(const struct genclk_config *p_cfg,
- uint32_t ul_id)
-{
- PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
-}
-
-//! \name Programmable Clock Source and Prescaler configuration
-//@{
-
-static inline void genclk_config_set_source(struct genclk_config *p_cfg,
- enum genclk_source e_src)
-{
- p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);
-
- switch (e_src) {
- case GENCLK_PCK_SRC_SLCK_RC:
- case GENCLK_PCK_SRC_SLCK_XTAL:
- case GENCLK_PCK_SRC_SLCK_BYPASS:
- p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK);
- break;
-
- case GENCLK_PCK_SRC_MAINCK_4M_RC:
- case GENCLK_PCK_SRC_MAINCK_8M_RC:
- case GENCLK_PCK_SRC_MAINCK_12M_RC:
- case GENCLK_PCK_SRC_MAINCK_XTAL:
- case GENCLK_PCK_SRC_MAINCK_BYPASS:
- p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK);
- break;
-
- case GENCLK_PCK_SRC_PLLACK:
- p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK);
- break;
-
- case GENCLK_PCK_SRC_MCK:
- p_cfg->ctrl |= (PMC_PCK_CSS_MCK);
- break;
-
- default:
- break;
- }
-}
-
-static inline void genclk_config_set_divider(struct genclk_config *p_cfg,
- uint32_t e_divider)
-{
- p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;
- p_cfg->ctrl |= e_divider;
-}
-
-//@}
-
-static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id)
-{
- PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
- pmc_enable_pck(ul_id);
-}
-
-static inline void genclk_disable(uint32_t ul_id)
-{
- pmc_disable_pck(ul_id);
-}
-
-static inline void genclk_enable_source(enum genclk_source e_src)
-{
- switch (e_src) {
- case GENCLK_PCK_SRC_SLCK_RC:
- if (!osc_is_ready(OSC_SLCK_32K_RC)) {
- osc_enable(OSC_SLCK_32K_RC);
- osc_wait_ready(OSC_SLCK_32K_RC);
- }
- break;
-
- case GENCLK_PCK_SRC_SLCK_XTAL:
- if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {
- osc_enable(OSC_SLCK_32K_XTAL);
- osc_wait_ready(OSC_SLCK_32K_XTAL);
- }
- break;
-
- case GENCLK_PCK_SRC_SLCK_BYPASS:
- if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {
- osc_enable(OSC_SLCK_32K_BYPASS);
- osc_wait_ready(OSC_SLCK_32K_BYPASS);
- }
- break;
-
- case GENCLK_PCK_SRC_MAINCK_4M_RC:
- if (!osc_is_ready(OSC_MAINCK_4M_RC)) {
- osc_enable(OSC_MAINCK_4M_RC);
- osc_wait_ready(OSC_MAINCK_4M_RC);
- }
- break;
-
- case GENCLK_PCK_SRC_MAINCK_8M_RC:
- if (!osc_is_ready(OSC_MAINCK_8M_RC)) {
- osc_enable(OSC_MAINCK_8M_RC);
- osc_wait_ready(OSC_MAINCK_8M_RC);
- }
- break;
-
- case GENCLK_PCK_SRC_MAINCK_12M_RC:
- if (!osc_is_ready(OSC_MAINCK_12M_RC)) {
- osc_enable(OSC_MAINCK_12M_RC);
- osc_wait_ready(OSC_MAINCK_12M_RC);
- }
- break;
-
- case GENCLK_PCK_SRC_MAINCK_XTAL:
- if (!osc_is_ready(OSC_MAINCK_XTAL)) {
- osc_enable(OSC_MAINCK_XTAL);
- osc_wait_ready(OSC_MAINCK_XTAL);
- }
- break;
-
- case GENCLK_PCK_SRC_MAINCK_BYPASS:
- if (!osc_is_ready(OSC_MAINCK_BYPASS)) {
- osc_enable(OSC_MAINCK_BYPASS);
- osc_wait_ready(OSC_MAINCK_BYPASS);
- }
- break;
-
-#ifdef CONFIG_PLL0_SOURCE
- case GENCLK_PCK_SRC_PLLACK:
- pll_enable_config_defaults(0);
- break;
-#endif
-
- case GENCLK_PCK_SRC_MCK:
- break;
-
- default:
- Assert(false);
- break;
- }
-}
-
-//! @}
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-#endif /* CHIP_GENCLK_H_INCLUDED */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/osc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/osc.h
deleted file mode 100644
index 191c4ed..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/osc.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/**
- * \file
- *
- * \brief Chip-specific oscillator management functions.
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef CHIP_OSC_H_INCLUDED
-#define CHIP_OSC_H_INCLUDED
-
-#include "board.h"
-#include "pmc.h"
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-/*
- * Below BOARD_XXX macros are related to the specific board, and
- * should be defined by the board code, otherwise default value are used.
- */
-#if !defined(BOARD_FREQ_SLCK_XTAL)
-# warning The board slow clock xtal frequency has not been defined.
-# define BOARD_FREQ_SLCK_XTAL (32768UL)
-#endif
-
-#if !defined(BOARD_FREQ_SLCK_BYPASS)
-# warning The board slow clock bypass frequency has not been defined.
-# define BOARD_FREQ_SLCK_BYPASS (32768UL)
-#endif
-
-#if !defined(BOARD_FREQ_MAINCK_XTAL)
-# warning The board main clock xtal frequency has not been defined.
-# define BOARD_FREQ_MAINCK_XTAL (12000000UL)
-#endif
-
-#if !defined(BOARD_FREQ_MAINCK_BYPASS)
-# warning The board main clock bypass frequency has not been defined.
-# define BOARD_FREQ_MAINCK_BYPASS (12000000UL)
-#endif
-
-#if !defined(BOARD_OSC_STARTUP_US)
-# warning The board main clock xtal startup time has not been defined.
-# define BOARD_OSC_STARTUP_US (15625UL)
-#endif
-
-/**
- * \weakgroup osc_group
- * @{
- */
-
-//! \name Oscillator identifiers
-//@{
-#define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator.
-#define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator.
-#define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator.
-#define OSC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator.
-#define OSC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator.
-#define OSC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator.
-#define OSC_MAINCK_XTAL 6 //!< External crystal oscillator.
-#define OSC_MAINCK_BYPASS 7 //!< External bypass oscillator.
-//@}
-
-//! \name Oscillator clock speed in hertz
-//@{
-#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator.
-#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator.
-#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator.
-#define OSC_MAINCK_4M_RC_HZ CHIP_FREQ_MAINCK_RC_4MHZ //!< Internal 4MHz RC oscillator.
-#define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator.
-#define OSC_MAINCK_12M_RC_HZ CHIP_FREQ_MAINCK_RC_12MHZ //!< Internal 12MHz RC oscillator.
-#define OSC_MAINCK_XTAL_HZ BOARD_FREQ_MAINCK_XTAL //!< External crystal oscillator.
-#define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator.
-//@}
-
-static inline void osc_enable(uint32_t ul_id)
-{
- switch (ul_id) {
- case OSC_SLCK_32K_RC:
- break;
-
- case OSC_SLCK_32K_XTAL:
- pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);
- break;
-
- case OSC_SLCK_32K_BYPASS:
- pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS);
- break;
-
-
- case OSC_MAINCK_4M_RC:
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);
- break;
-
- case OSC_MAINCK_8M_RC:
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);
- break;
-
- case OSC_MAINCK_12M_RC:
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);
- break;
-
-
- case OSC_MAINCK_XTAL:
- pmc_switch_mainck_to_xtal(PMC_OSC_XTAL,
- pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US,
- OSC_SLCK_32K_RC_HZ));
- break;
-
- case OSC_MAINCK_BYPASS:
- pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS,
- pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US,
- OSC_SLCK_32K_RC_HZ));
- break;
- }
-}
-
-static inline void osc_disable(uint32_t ul_id)
-{
- switch (ul_id) {
- case OSC_SLCK_32K_RC:
- case OSC_SLCK_32K_XTAL:
- case OSC_SLCK_32K_BYPASS:
- break;
-
- case OSC_MAINCK_4M_RC:
- case OSC_MAINCK_8M_RC:
- case OSC_MAINCK_12M_RC:
- pmc_osc_disable_fastrc();
- break;
-
- case OSC_MAINCK_XTAL:
- pmc_osc_disable_xtal(PMC_OSC_XTAL);
- break;
-
- case OSC_MAINCK_BYPASS:
- pmc_osc_disable_xtal(PMC_OSC_BYPASS);
- break;
- }
-}
-
-static inline bool osc_is_ready(uint32_t ul_id)
-{
- switch (ul_id) {
- case OSC_SLCK_32K_RC:
- return 1;
-
- case OSC_SLCK_32K_XTAL:
- case OSC_SLCK_32K_BYPASS:
- return pmc_osc_is_ready_32kxtal();
-
- case OSC_MAINCK_4M_RC:
- case OSC_MAINCK_8M_RC:
- case OSC_MAINCK_12M_RC:
- case OSC_MAINCK_XTAL:
- case OSC_MAINCK_BYPASS:
- return pmc_osc_is_ready_mainck();
- }
-
- return 0;
-}
-
-static inline uint32_t osc_get_rate(uint32_t ul_id)
-{
- switch (ul_id) {
- case OSC_SLCK_32K_RC:
- return OSC_SLCK_32K_RC_HZ;
-
- case OSC_SLCK_32K_XTAL:
- return BOARD_FREQ_SLCK_XTAL;
-
- case OSC_SLCK_32K_BYPASS:
- return BOARD_FREQ_SLCK_BYPASS;
-
- case OSC_MAINCK_4M_RC:
- return OSC_MAINCK_4M_RC_HZ;
-
- case OSC_MAINCK_8M_RC:
- return OSC_MAINCK_8M_RC_HZ;
-
- case OSC_MAINCK_12M_RC:
- return OSC_MAINCK_12M_RC_HZ;
-
- case OSC_MAINCK_XTAL:
- return BOARD_FREQ_MAINCK_XTAL;
-
- case OSC_MAINCK_BYPASS:
- return BOARD_FREQ_MAINCK_BYPASS;
- }
-
- return 0;
-}
-
-//! @}
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-#endif /* CHIP_OSC_H_INCLUDED */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/pll.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/pll.h
deleted file mode 100644
index 5006ebb..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/pll.h
+++ /dev/null
@@ -1,269 +0,0 @@
-/**
- * \file
- *
- * \brief Chip-specific PLL definitions.
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef CHIP_PLL_H_INCLUDED
-#define CHIP_PLL_H_INCLUDED
-
-#include <osc.h>
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-/**
- * \weakgroup pll_group
- * @{
- */
-
-#define PLL_OUTPUT_MIN_HZ 160000000
-#define PLL_OUTPUT_MAX_HZ 500000000
-
-#define PLL_INPUT_MIN_HZ 3000000
-#define PLL_INPUT_MAX_HZ 32000000
-
-#define NR_PLLS 2
-#define PLLA_ID 0
-#define UPLL_ID 1 //!< USB UTMI PLL.
-
-#define PLL_UPLL_HZ 480000000
-
-#define PLL_COUNT 0x3fU
-
-enum pll_source {
- PLL_SRC_MAINCK_4M_RC = OSC_MAINCK_4M_RC, //!< Internal 4MHz RC oscillator.
- PLL_SRC_MAINCK_8M_RC = OSC_MAINCK_8M_RC, //!< Internal 8MHz RC oscillator.
- PLL_SRC_MAINCK_12M_RC = OSC_MAINCK_12M_RC, //!< Internal 12MHz RC oscillator.
- PLL_SRC_MAINCK_XTAL = OSC_MAINCK_XTAL, //!< External crystal oscillator.
- PLL_SRC_MAINCK_BYPASS = OSC_MAINCK_BYPASS, //!< External bypass oscillator.
- PLL_NR_SOURCES, //!< Number of PLL sources.
-};
-
-struct pll_config {
- uint32_t ctrl;
-};
-
-#define pll_get_default_rate(pll_id) \
- ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \
- * CONFIG_PLL##pll_id##_MUL) \
- / CONFIG_PLL##pll_id##_DIV)
-
-/* Force UTMI PLL parameters (Hardware defined) */
-#ifdef CONFIG_PLL1_SOURCE
-# undef CONFIG_PLL1_SOURCE
-#endif
-#ifdef CONFIG_PLL1_MUL
-# undef CONFIG_PLL1_MUL
-#endif
-#ifdef CONFIG_PLL1_DIV
-# undef CONFIG_PLL1_DIV
-#endif
-#define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL
-#define CONFIG_PLL1_MUL 0
-#define CONFIG_PLL1_DIV 0
-
-/**
- * \note The SAMV71 PLL hardware interprets mul as mul+1. For readability the
- * hardware mul+1 is hidden in this implementation. Use mul as mul effective
- * value.
- */
-static inline void pll_config_init(struct pll_config *p_cfg,
- enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)
-{
- uint32_t vco_hz;
-
- Assert(e_src < PLL_NR_SOURCES);
-
- if (ul_div == 0 && ul_mul == 0) { /* Must only be true for UTMI PLL */
- p_cfg->ctrl = CKGR_UCKR_UPLLCOUNT(PLL_COUNT);
- } else { /* PLLA */
- /* Calculate internal VCO frequency */
- vco_hz = osc_get_rate(e_src) / ul_div;
- Assert(vco_hz >= PLL_INPUT_MIN_HZ);
- Assert(vco_hz <= PLL_INPUT_MAX_HZ);
-
- vco_hz *= ul_mul;
- Assert(vco_hz >= PLL_OUTPUT_MIN_HZ);
- Assert(vco_hz <= PLL_OUTPUT_MAX_HZ);
-
- /* PMC hardware will automatically make it mul+1 */
- p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) | CKGR_PLLAR_DIVA(ul_div) \
- | CKGR_PLLAR_PLLACOUNT(PLL_COUNT);
- }
-}
-
-#define pll_config_defaults(cfg, pll_id) \
- pll_config_init(cfg, \
- CONFIG_PLL##pll_id##_SOURCE, \
- CONFIG_PLL##pll_id##_DIV, \
- CONFIG_PLL##pll_id##_MUL)
-
-static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id)
-{
- Assert(ul_pll_id < NR_PLLS);
-
- if (ul_pll_id == PLLA_ID) {
- p_cfg->ctrl = PMC->CKGR_PLLAR;
- } else {
- p_cfg->ctrl = PMC->CKGR_UCKR;
- }
-}
-
-static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id)
-{
- Assert(ul_pll_id < NR_PLLS);
-
- if (ul_pll_id == PLLA_ID) {
- pmc_disable_pllack(); // Always stop PLL first!
- PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;
- } else {
- PMC->CKGR_UCKR = p_cfg->ctrl;
- }
-}
-
-static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id)
-{
- Assert(ul_pll_id < NR_PLLS);
-
- if (ul_pll_id == PLLA_ID) {
- pmc_disable_pllack(); // Always stop PLL first!
- PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;
- } else {
- PMC->CKGR_UCKR = p_cfg->ctrl | CKGR_UCKR_UPLLEN;
- }
-}
-
-/**
- * \note This will only disable the selected PLL, not the underlying oscillator (mainck).
- */
-static inline void pll_disable(uint32_t ul_pll_id)
-{
- Assert(ul_pll_id < NR_PLLS);
-
- if (ul_pll_id == PLLA_ID) {
- pmc_disable_pllack();
- } else {
- PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
- }
-}
-
-static inline uint32_t pll_is_locked(uint32_t ul_pll_id)
-{
- Assert(ul_pll_id < NR_PLLS);
-
- if (ul_pll_id == PLLA_ID) {
- return pmc_is_locked_pllack();
- } else {
- return pmc_is_locked_upll();
- }
-}
-
-static inline void pll_enable_source(enum pll_source e_src)
-{
- switch (e_src) {
- case PLL_SRC_MAINCK_4M_RC:
- case PLL_SRC_MAINCK_8M_RC:
- case PLL_SRC_MAINCK_12M_RC:
- case PLL_SRC_MAINCK_XTAL:
- case PLL_SRC_MAINCK_BYPASS:
- osc_enable(e_src);
- osc_wait_ready(e_src);
- break;
-
- default:
- Assert(false);
- break;
- }
-}
-
-static inline void pll_enable_config_defaults(unsigned int ul_pll_id)
-{
- struct pll_config pllcfg;
-
- if (pll_is_locked(ul_pll_id)) {
- return; // Pll already running
- }
- switch (ul_pll_id) {
-#ifdef CONFIG_PLL0_SOURCE
- case 0:
- pll_enable_source(CONFIG_PLL0_SOURCE);
- pll_config_init(&pllcfg,
- CONFIG_PLL0_SOURCE,
- CONFIG_PLL0_DIV,
- CONFIG_PLL0_MUL);
- break;
-#endif
-#ifdef CONFIG_PLL1_SOURCE
- case 1:
- pll_enable_source(CONFIG_PLL1_SOURCE);
- pll_config_init(&pllcfg,
- CONFIG_PLL1_SOURCE,
- CONFIG_PLL1_DIV,
- CONFIG_PLL1_MUL);
- break;
-#endif
- default:
- Assert(false);
- break;
- }
- pll_enable(&pllcfg, ul_pll_id);
- while (!pll_is_locked(ul_pll_id));
-}
-
-//! @}
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-#endif /* CHIP_PLL_H_INCLUDED */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/sysclk.c b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/sysclk.c
deleted file mode 100644
index 8e21e83..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/sysclk.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/**
- * \file
- *
- * \brief Chip-specific system clock management functions.
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include <sysclk.h>
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-/**
- * \weakgroup sysclk_group
- * @{
- */
-
-#if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
-/**
- * \brief boolean signalling that the sysclk_init is done.
- */
-uint32_t sysclk_initialized = 0;
-#endif
-
-/**
- * \brief Set system clock prescaler configuration
- *
- * This function will change the system clock prescaler configuration to
- * match the parameters.
- *
- * \note The parameters to this function are device-specific.
- *
- * \param ul_pres The CPU clock will be divided by \f$2^{mck\_pres}\f$
- */
-void sysclk_set_prescalers(uint32_t ul_pres)
-{
- pmc_mck_set_prescaler(ul_pres);
- SystemCoreClockUpdate();
-}
-
-/**
- * \brief Change the source of the main system clock.
- *
- * \param ul_src The new system clock source. Must be one of the constants
- * from the <em>System Clock Sources</em> section.
- */
-void sysclk_set_source(uint32_t ul_src)
-{
- switch (ul_src) {
- case SYSCLK_SRC_SLCK_RC:
- case SYSCLK_SRC_SLCK_XTAL:
- case SYSCLK_SRC_SLCK_BYPASS:
- pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK);
- break;
-
- case SYSCLK_SRC_MAINCK_4M_RC:
- case SYSCLK_SRC_MAINCK_8M_RC:
- case SYSCLK_SRC_MAINCK_12M_RC:
- case SYSCLK_SRC_MAINCK_XTAL:
- case SYSCLK_SRC_MAINCK_BYPASS:
- pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK);
- break;
-
- case SYSCLK_SRC_PLLACK:
- pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK);
- break;
-
- case SYSCLK_SRC_UPLLCK:
- pmc_mck_set_source(PMC_MCKR_CSS_UPLL_CLK);
- break;
- }
-
- SystemCoreClockUpdate();
-}
-
-#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__)
-/**
- * \brief Enable USB clock.
- *
- * \note The SAMV71 UDP hardware interprets div as div+1. For readability the hardware div+1
- * is hidden in this implementation. Use div as div effective value.
- *
- * \param pll_id Source of the USB clock.
- * \param div Actual clock divisor. Must be superior to 0.
- */
-void sysclk_enable_usb(void)
-{
- Assert(CONFIG_USBCLK_DIV > 0);
-
-#ifdef CONFIG_PLL0_SOURCE
- if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL0) {
- struct pll_config pllcfg;
-
- pll_enable_source(CONFIG_PLL0_SOURCE);
- pll_config_defaults(&pllcfg, 0);
- pll_enable(&pllcfg, 0);
- pll_wait_for_lock(0);
- pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1);
- pmc_enable_udpck();
- return;
- }
-#endif
-
- if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_UPLL) {
-
- pmc_enable_upll_clock();
- pmc_switch_udpck_to_upllck(CONFIG_USBCLK_DIV - 1);
- pmc_enable_udpck();
- return;
- }
-}
-
-/**
- * \brief Disable the USB clock.
- *
- * \note This implementation does not switch off the PLL, it just turns off the USB clock.
- */
-void sysclk_disable_usb(void)
-{
- pmc_disable_udpck();
-}
-#endif // CONFIG_USBCLK_SOURCE
-
-void sysclk_init(void)
-{
- struct pll_config pllcfg;
-
- /* Set flash wait state to max in case the below clock switching. */
- system_init_flash(CHIP_FREQ_CPU_MAX);
-
- /* Config system clock setting */
- if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) {
- osc_enable(OSC_SLCK_32K_RC);
- osc_wait_ready(OSC_SLCK_32K_RC);
- pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
- }
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) {
- osc_enable(OSC_SLCK_32K_XTAL);
- osc_wait_ready(OSC_SLCK_32K_XTAL);
- pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
- }
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) {
- osc_enable(OSC_SLCK_32K_BYPASS);
- osc_wait_ready(OSC_SLCK_32K_BYPASS);
- pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
- }
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) {
- /* Already running from SYSCLK_SRC_MAINCK_4M_RC */
- }
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) {
- osc_enable(OSC_MAINCK_8M_RC);
- osc_wait_ready(OSC_MAINCK_8M_RC);
- pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
- }
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) {
- osc_enable(OSC_MAINCK_12M_RC);
- osc_wait_ready(OSC_MAINCK_12M_RC);
- pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
- }
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) {
- osc_enable(OSC_MAINCK_XTAL);
- osc_wait_ready(OSC_MAINCK_XTAL);
- pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
- }
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) {
- osc_enable(OSC_MAINCK_BYPASS);
- osc_wait_ready(OSC_MAINCK_BYPASS);
- pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
- }
-
-#ifdef CONFIG_PLL0_SOURCE
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) {
- pll_enable_source(CONFIG_PLL0_SOURCE);
- pll_config_defaults(&pllcfg, 0);
- pll_enable(&pllcfg, 0);
- pll_wait_for_lock(0);
- pmc_mck_set_division(CONFIG_SYSCLK_DIV);
- pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES);
- }
-#endif
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_UPLLCK) {
- pll_enable_source(CONFIG_PLL1_SOURCE);
- pll_config_defaults(&pllcfg, 1);
- pll_enable(&pllcfg, 1);
- pll_wait_for_lock(1);
- pmc_mck_set_division(CONFIG_SYSCLK_DIV);
- pmc_switch_mck_to_upllck(CONFIG_SYSCLK_PRES);
- }
- /* Update the SystemFrequency variable */
- SystemCoreClockUpdate();
-
- /* Set a flash wait state depending on the new cpu frequency */
- system_init_flash(sysclk_get_cpu_hz());
-
-#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
- /* Signal that the internal frequencies are setup */
- sysclk_initialized = 1;
-#endif
-}
-
-//! @}
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/sysclk.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/sysclk.h
deleted file mode 100644
index 4a2826a..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sams70/sysclk.h
+++ /dev/null
@@ -1,473 +0,0 @@
-/**
- * \file
- *
- * \brief Chip-specific system clock management functions.
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef CHIP_SYSCLK_H_INCLUDED
-#define CHIP_SYSCLK_H_INCLUDED
-
-#include <osc.h>
-#include <pll.h>
-
-/**
- * \page sysclk_quickstart Quick Start Guide for the System Clock Management
- * service (SAMV71)
- *
- * This is the quick start guide for the \ref sysclk_group "System Clock
- * Management" service, with step-by-step instructions on how to configure and
- * use the service for specific use cases.
- *
- * \section sysclk_quickstart_usecases System Clock Management use cases
- * - \ref sysclk_quickstart_basic
- * - \ref sysclk_quickstart_use_case_2
- *
- * \section sysclk_quickstart_basic Basic usage of the System Clock Management
- * service
- * This section will present a basic use case for the System Clock Management
- * service. This use case will configure the main system clock to 120MHz,
- * using an internal PLL module to multiply the frequency of a crystal attached
- * to the microcontroller.
- *
- * \subsection sysclk_quickstart_use_case_1_prereq Prerequisites
- * - None
- *
- * \subsection sysclk_quickstart_use_case_1_setup_steps Initialization code
- * Add to the application initialization code:
- * \code
- sysclk_init();
-\endcode
- *
- * \subsection sysclk_quickstart_use_case_1_setup_steps_workflow Workflow
- * -# Configure the system clocks according to the settings in conf_clock.h:
- * \code sysclk_init(); \endcode
- *
- * \subsection sysclk_quickstart_use_case_1_example_code Example code
- * Add or uncomment the following in your conf_clock.h header file,
- * commenting out all other definitions of the same symbol(s):
- * \code
- #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
-
- // Fpll0 = (Fclk * PLL_mul) / PLL_div
- #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
- #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL)
- #define CONFIG_PLL0_DIV 1
-
- // Fbus = Fsys / BUS_div
- #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
-\endcode
- *
- * \subsection sysclk_quickstart_use_case_1_example_workflow Workflow
- * -# Configure the main system clock to use the output of the PLL module as
- * its source:
- * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode
- * -# Configure the PLL module to use the fast external fast crystal
- * oscillator as its source:
- * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode
- * -# Configure the PLL module to multiply the external fast crystal
- * oscillator frequency up to 120MHz:
- * \code
- #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL)
- #define CONFIG_PLL0_DIV 1
-\endcode
- * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the
- * board \c conf_board.h configuration
- * file as the frequency of the fast crystal attached to the microcontroller.
- * -# Configure the main clock to run at the full 120MHz, disable scaling of
- * the main system clock speed:
- * \code
- #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
-\endcode
- * \note Some dividers are powers of two, while others are integer division
- * factors. Refer to the formulas in the conf_clock.h template commented
- * above each division define.
- */
-
-/**
- * \page sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus Clock
- * Management (SAMV71)
- *
- * \section sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus
- * Clock Management
- * This section will present a more advanced use case for the System Clock
- * Management service. This use case will configure the main system clock to
- * 96MHz, using an internal PLL module to multiply the frequency of a crystal
- * attached to the microcontroller. The USB clock will be configured via the
- * same PLL module.
- *
- * \subsection sysclk_quickstart_use_case_2_prereq Prerequisites
- * - None
- *
- * \subsection sysclk_quickstart_use_case_2_setup_steps Initialization code
- * Add to the application initialization code:
- * \code
- sysclk_init();
-\endcode
- *
- * \subsection sysclk_quickstart_use_case_2_setup_steps_workflow Workflow
- * -# Configure the system clocks according to the settings in conf_clock.h:
- * \code sysclk_init(); \endcode
- *
- * \subsection sysclk_quickstart_use_case_2_example_code Example code
- * Add or uncomment the following in your conf_clock.h header file,
- * commenting out all other definitions of the same symbol(s):
- * \code
- #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
-
- // Fpll0 = (Fclk * PLL_mul) / PLL_div
- #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
- #define CONFIG_PLL0_MUL (96000000UL / BOARD_FREQ_MAINCK_XTAL)
- #define CONFIG_PLL0_DIV 1
-
- // Fbus = Fsys / BUS_div
- #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
-
- // Fusb = Fsys / USB_div
- #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0
- #define CONFIG_USBCLK_DIV 2
-\endcode
- *
- * \subsection sysclk_quickstart_use_case_2_example_workflow Workflow
- * -# Configure the main system clock to use the output of the PLL0 module as
- * its source:
- * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode
- * -# Configure the PLL0 module to use the fast external fast crystal
- * oscillator as its source:
- * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode
- * -# Configure the PLL0 module to multiply the external fast crystal
- * oscillator frequency up to 96MHz:
- * \code
- #define CONFIG_PLL0_MUL (96000000UL / BOARD_FREQ_MAINCK_XTAL)
- #define CONFIG_PLL0_DIV 1
-\endcode
- * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the
- * board \c conf_board.h configuration file as the frequency of the fast
- * crystal attached to the microcontroller.
- * -# Configure the main clock to run at the full 96MHz, disable scaling of
- * the main system clock speed:
- * \code
- #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
-\endcode
- * \note Some dividers are powers of two, while others are integer division
- * factors. Refer to the formulas in the conf_clock.h template commented
- * above each division define.
- * -# Configure the USB module clock to use the output of the PLL0 module as
- * its source with division 2:
- * \code
- #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0
- #define CONFIG_USBCLK_DIV 2
-\endcode
- */
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-/**
- * \weakgroup sysclk_group
- * @{
- */
-
-//! \name Configuration Symbols
-//@{
-/**
- * \def CONFIG_SYSCLK_SOURCE
- * \brief Initial/static main system clock source
- *
- * The main system clock will be configured to use this clock during
- * initialization.
- */
-#ifndef CONFIG_SYSCLK_SOURCE
-# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
-#endif
-/**
- * \def CONFIG_SYSCLK_PRES
- * \brief Initial CPU clock divider (mck)
- *
- * The MCK will run at
- * \f[
- * f_{MCK} = \frac{f_{sys}}{\mathrm{CONFIG\_SYSCLK\_PRES}}\,\mbox{Hz}
- * \f]
- * after initialization.
- */
-#ifndef CONFIG_SYSCLK_PRES
-# define CONFIG_SYSCLK_PRES 0
-#endif
-
-//@}
-
-//! \name Master Clock Sources (MCK)
-//@{
-#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock
-#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock
-#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock
-#define SYSCLK_SRC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator as master source clock
-#define SYSCLK_SRC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator as master source clock
-#define SYSCLK_SRC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator as master source clock
-#define SYSCLK_SRC_MAINCK_XTAL 6 //!< External crystal oscillator as master source clock
-#define SYSCLK_SRC_MAINCK_BYPASS 7 //!< External bypass oscillator as master source clock
-#define SYSCLK_SRC_PLLACK 8 //!< Use PLLACK as master source clock
-#define SYSCLK_SRC_UPLLCK 9 //!< Use UPLLCK as master source clock
-//@}
-
-//! \name Master Clock Prescalers (MCK)
-//@{
-#define SYSCLK_PRES_1 PMC_MCKR_PRES_CLK_1 //!< Set master clock prescaler to 1
-#define SYSCLK_PRES_2 PMC_MCKR_PRES_CLK_2 //!< Set master clock prescaler to 2
-#define SYSCLK_PRES_4 PMC_MCKR_PRES_CLK_4 //!< Set master clock prescaler to 4
-#define SYSCLK_PRES_8 PMC_MCKR_PRES_CLK_8 //!< Set master clock prescaler to 8
-#define SYSCLK_PRES_16 PMC_MCKR_PRES_CLK_16 //!< Set master clock prescaler to 16
-#define SYSCLK_PRES_32 PMC_MCKR_PRES_CLK_32 //!< Set master clock prescaler to 32
-#define SYSCLK_PRES_64 PMC_MCKR_PRES_CLK_64 //!< Set master clock prescaler to 64
-#define SYSCLK_PRES_3 PMC_MCKR_PRES_CLK_3 //!< Set master clock prescaler to 3
-//@}
-
-//! \name Master Clock Division (MCK)
-//@{
-#define SYSCLK_DIV_1 PMC_MCKR_MDIV_EQ_PCK //!< Set master clock division to 1
-#define SYSCLK_DIV_2 PMC_MCKR_MDIV_PCK_DIV2 //!< Set master clock division to 2
-#define SYSCLK_DIV_4 PMC_MCKR_MDIV_PCK_DIV4 //!< Set master clock division to 4
-#define SYSCLK_DIV_3 PMC_MCKR_MDIV_PCK_DIV3 //!< Set master clock division to 3
-//@}
-
-//! \name USB Clock Sources
-//@{
-#define USBCLK_SRC_PLL0 0 //!< Use PLLA
-#define USBCLK_SRC_UPLL 1 //!< Use UPLL
-//@}
-
-/**
- * \def CONFIG_USBCLK_SOURCE
- * \brief Configuration symbol for the USB generic clock source
- *
- * Sets the clock source to use for the USB. The source must also be properly
- * configured.
- *
- * Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if
- * USB is not required.
- */
-#ifdef __DOXYGEN__
-# define CONFIG_USBCLK_SOURCE
-#endif
-
-/**
- * \def CONFIG_USBCLK_DIV
- * \brief Configuration symbol for the USB generic clock divider setting
- *
- * Sets the clock division for the USB generic clock. If a USB clock source is
- * selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be
- * defined.
- */
-#ifdef __DOXYGEN__
-# define CONFIG_USBCLK_DIV
-#endif
-
-/**
- * \name Querying the system clock
- *
- * The following functions may be used to query the current frequency of
- * the system clock and the CPU and bus clocks derived from it.
- * sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be
- * available on all platforms, although some platforms may define
- * additional accessors for various chip-internal bus clocks. These are
- * usually not intended to be queried directly by generic code.
- */
-//@{
-
-/**
- * \brief Return the current rate in Hz of the main system clock
- *
- * \todo This function assumes that the main clock source never changes
- * once it's been set up, and that PLL0 always runs at the compile-time
- * configured default rate. While this is probably the most common
- * configuration, which we want to support as a special case for
- * performance reasons, we will at some point need to support more
- * dynamic setups as well.
- */
-#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
-extern uint32_t sysclk_initialized;
-#endif
-static inline uint32_t sysclk_get_main_hz(void)
-{
-#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
- if (!sysclk_initialized ) {
- return OSC_MAINCK_4M_RC_HZ;
- }
-#endif
-
- /* Config system clock setting */
- if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) {
- return OSC_SLCK_32K_RC_HZ;
- } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) {
- return OSC_SLCK_32K_XTAL_HZ;
- } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) {
- return OSC_SLCK_32K_BYPASS_HZ;
- } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) {
- return OSC_MAINCK_4M_RC_HZ;
- } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) {
- return OSC_MAINCK_8M_RC_HZ;
- } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) {
- return OSC_MAINCK_12M_RC_HZ;
- } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) {
- return OSC_MAINCK_XTAL_HZ;
- } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) {
- return OSC_MAINCK_BYPASS_HZ;
- }
-#ifdef CONFIG_PLL0_SOURCE
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) {
- return pll_get_default_rate(0);
- }
-#endif
-
-#ifdef CONFIG_PLL1_SOURCE
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_UPLLCK) {
- return PLL_UPLL_HZ;
- }
-#endif
- else {
- /* unhandled_case(CONFIG_SYSCLK_SOURCE); */
- return 0;
- }
-}
-
-/**
- * \brief Return the current rate in Hz of the CPU clock
- *
- * \todo This function assumes that the CPU always runs at the system
- * clock frequency. We want to support at least two more scenarios:
- * Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus
- * clock dividers (which may change at run time). Ditto for all the bus
- * clocks.
- *
- * \return Frequency of the CPU clock, in Hz.
- */
-static inline uint32_t sysclk_get_cpu_hz(void)
-{
- /* CONFIG_SYSCLK_PRES is the register value for setting the expected */
- /* prescaler, not an immediate value. */
- return sysclk_get_main_hz() /
- ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 :
- (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos)));
-}
-
-/**
- * \brief Retrieves the current rate in Hz of the peripheral clocks.
- *
- * \return Frequency of the peripheral clocks, in Hz.
- */
-static inline uint32_t sysclk_get_peripheral_hz(void)
-{
- /* CONFIG_SYSCLK_PRES is the register value for setting the expected */
- /* prescaler, not an immediate value. */
- return sysclk_get_main_hz() /
- (((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 : (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos))) * CONFIG_SYSCLK_DIV);
-}
-
-/**
- * \brief Retrieves the current rate in Hz of the Peripheral Bus clock attached
- * to the specified peripheral.
- *
- * \param module Pointer to the module's base address.
- *
- * \return Frequency of the bus attached to the specified peripheral, in Hz.
- */
-static inline uint32_t sysclk_get_peripheral_bus_hz(const volatile void *module)
-{
- UNUSED(module);
- return sysclk_get_peripheral_hz();
-}
-//@}
-
-//! \name Enabling and disabling synchronous clocks
-//@{
-
-/**
- * \brief Enable a peripheral's clock.
- *
- * \param ul_id Id (number) of the peripheral clock.
- */
-static inline void sysclk_enable_peripheral_clock(uint32_t ul_id)
-{
- pmc_enable_periph_clk(ul_id);
-}
-
-/**
- * \brief Disable a peripheral's clock.
- *
- * \param ul_id Id (number) of the peripheral clock.
- */
-static inline void sysclk_disable_peripheral_clock(uint32_t ul_id)
-{
- pmc_disable_periph_clk(ul_id);
-}
-
-//@}
-
-//! \name System Clock Source and Prescaler configuration
-//@{
-
-extern void sysclk_set_prescalers(uint32_t ul_pres);
-extern void sysclk_set_source(uint32_t ul_src);
-
-//@}
-
-extern void sysclk_enable_usb(void);
-extern void sysclk_disable_usb(void);
-
-extern void sysclk_init(void);
-
-//! @}
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-#endif /* CHIP_SYSCLK_H_INCLUDED */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sysclk.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sysclk.h
deleted file mode 100644
index 86e4bf7..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/clock/sysclk.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/**
- * \file
- *
- * \brief System clock management
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef SYSCLK_H_INCLUDED
-#define SYSCLK_H_INCLUDED
-
-#include "parts.h"
-#include "conf_clock.h"
-
-#if SAM3S
-# include "sam3s/sysclk.h"
-#elif SAM3U
-# include "sam3u/sysclk.h"
-#elif SAM3N
-# include "sam3n/sysclk.h"
-#elif SAM3XA
-# include "sam3x/sysclk.h"
-#elif SAM4S
-# include "sam4s/sysclk.h"
-#elif SAM4E
-# include "sam4e/sysclk.h"
-#elif SAM4C
-# include "sam4c/sysclk.h"
-#elif SAM4CM
-# include "sam4cm/sysclk.h"
-#elif SAM4CP
-# include "sam4cp/sysclk.h"
-#elif SAM4L
-# include "sam4l/sysclk.h"
-#elif SAM4N
-# include "sam4n/sysclk.h"
-#elif SAMG
-# include "samg/sysclk.h"
-#elif SAMV71
-# include "samv71/sysclk.h"
-#elif SAMV70
-# include "samv70/sysclk.h"
-#elif SAME70
-# include "same70/sysclk.h"
-#elif SAMS70
-# include "sams70/sysclk.h"
-#elif (UC3A0 || UC3A1)
-# include "uc3a0_a1/sysclk.h"
-#elif UC3A3
-# include "uc3a3_a4/sysclk.h"
-#elif UC3B
-# include "uc3b0_b1/sysclk.h"
-#elif UC3C
-# include "uc3c/sysclk.h"
-#elif UC3D
-# include "uc3d/sysclk.h"
-#elif UC3L
-# include "uc3l/sysclk.h"
-#elif XMEGA
-# include "xmega/sysclk.h"
-#elif MEGA
-# include "mega/sysclk.h"
-#else
-# error Unsupported chip type
-#endif
-
-/**
- * \defgroup clk_group Clock Management
- */
-
-/**
- * \ingroup clk_group
- * \defgroup sysclk_group System Clock Management
- *
- * See \ref sysclk_quickstart.
- *
- * The <em>sysclk</em> API covers the <em>system clock</em> and all
- * clocks derived from it. The system clock is a chip-internal clock on
- * which all <em>synchronous clocks</em>, i.e. CPU and bus/peripheral
- * clocks, are based. The system clock is typically generated from one
- * of a variety of sources, which may include crystal and RC oscillators
- * as well as PLLs. The clocks derived from the system clock are
- * sometimes also known as <em>synchronous clocks</em>, since they
- * always run synchronously with respect to each other, as opposed to
- * <em>generic clocks</em> which may run from different oscillators or
- * PLLs.
- *
- * Most applications should simply call sysclk_init() to initialize
- * everything related to the system clock and its source (oscillator,
- * PLL or DFLL), and leave it at that. More advanced applications, and
- * platform-specific drivers, may require additional services from the
- * clock system, some of which may be platform-specific.
- *
- * \section sysclk_group_platform Platform Dependencies
- *
- * The sysclk API is partially chip- or platform-specific. While all
- * platforms provide mostly the same functionality, there are some
- * variations around how different bus types and clock tree structures
- * are handled.
- *
- * The following functions are available on all platforms with the same
- * parameters and functionality. These functions may be called freely by
- * portable applications, drivers and services:
- * - sysclk_init()
- * - sysclk_set_source()
- * - sysclk_get_main_hz()
- * - sysclk_get_cpu_hz()
- * - sysclk_get_peripheral_bus_hz()
- *
- * The following functions are available on all platforms, but there may
- * be variations in the function signature (i.e. parameters) and
- * behavior. These functions are typically called by platform-specific
- * parts of drivers, and applications that aren't intended to be
- * portable:
- * - sysclk_enable_peripheral_clock()
- * - sysclk_disable_peripheral_clock()
- * - sysclk_enable_module()
- * - sysclk_disable_module()
- * - sysclk_module_is_enabled()
- * - sysclk_set_prescalers()
- *
- * All other functions should be considered platform-specific.
- * Enabling/disabling clocks to specific peripherals as well as
- * determining the speed of these clocks should be done by calling
- * functions provided by the driver for that peripheral.
- *
- * @{
- */
-
-//! \name System Clock Initialization
-//@{
-/**
- * \fn void sysclk_init(void)
- * \brief Initialize the synchronous clock system.
- *
- * This function will initialize the system clock and its source. This
- * includes:
- * - Mask all synchronous clocks except for any clocks which are
- * essential for normal operation (for example internal memory
- * clocks).
- * - Set up the system clock prescalers as specified by the
- * application's configuration file.
- * - Enable the clock source specified by the application's
- * configuration file (oscillator or PLL) and wait for it to become
- * stable.
- * - Set the main system clock source to the clock specified by the
- * application's configuration file.
- *
- * Since all non-essential peripheral clocks are initially disabled, it
- * is the responsibility of the peripheral driver to re-enable any
- * clocks that are needed for normal operation.
- */
-//@}
-
-//! @}
-
-#endif /* SYSCLK_H_INCLUDED */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/delay/delay.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/delay/delay.h
deleted file mode 100644
index cab97f5..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/delay/delay.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/**
- * \file
- *
- * \brief Common Delay Service
- *
- * Copyright (c) 2014-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef _DELAY_H_
-#define _DELAY_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <sysclk.h>
-
-#if UC3
-# include <cycle_counter.h>
-#elif XMEGA
-# include "xmega/cycle_counter.h"
-#elif MEGA
-# include "mega/cycle_counter.h"
-#elif SAM
-# include "sam/cycle_counter.h"
-#endif
-
-/**
- * @defgroup group_common_services_delay Busy-Wait Delay Routines
- *
- * This module provides simple loop-based delay routines for those
- * applications requiring a brief wait during execution. Common API
- * for UC3, XMEGA, and AVR MEGA.
- *
- * @{
- */
-
-/**
- * @def F_CPU
- * @brief MCU Clock Frequency (Hertz)
- *
- * @deprecated
- * The \ref F_CPU configuration constant is used for compatibility with the
- * \ref group_common_services_delay routines. The common loop-based delay
- * routines are designed to use the \ref clk_group modules while anticipating
- * support for legacy applications assuming a statically defined clock
- * frequency. Applications using a statically configured MCU clock frequency
- * can define \ref F_CPU (Hertz), in which case the common delay routines will
- * use this value rather than calling sysclk_get_cpu_hz() to get the current
- * MCU clock frequency.
- */
-#ifndef F_CPU
-# define F_CPU sysclk_get_cpu_hz()
-#endif
-
-/**
- * @def delay_init
- *
- * @brief Initialize the delay driver.
- * @param fcpu_hz CPU frequency in Hz
- *
- * @deprecated
- * This function is provided for compatibility with ASF applications that
- * may not have been updated to configure the system clock via the common
- * clock service; e.g. sysclk_init() and a configuration header file are
- * used to configure clocks.
- *
- * The functions in this module call \ref sysclk_get_cpu_hz() function to
- * obtain the system clock frequency.
- */
-#define delay_init(fcpu_hz)
-
-/**
- * @def delay_s
- * @brief Delay in seconds.
- * @param delay Delay in seconds
- */
-#define delay_s(delay) ((delay) ? cpu_delay_ms(1000 * delay, F_CPU) : cpu_delay_us(1, F_CPU))
-
-/**
- * @def delay_ms
- * @brief Delay in milliseconds.
- * @param delay Delay in milliseconds
- */
-#define delay_ms(delay) ((delay) ? cpu_delay_ms(delay, F_CPU) : cpu_delay_us(1, F_CPU))
-
-/**
- * @def delay_us
- * @brief Delay in microseconds.
- * @param delay Delay in microseconds
- */
-#define delay_us(delay) ((delay) ? cpu_delay_us(delay, F_CPU) : cpu_delay_us(1, F_CPU))
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @}
- */
-
-#endif /* _DELAY_H_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/delay/sam/cycle_counter.c b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/delay/sam/cycle_counter.c
deleted file mode 100644
index 96669ef..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/delay/sam/cycle_counter.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/**
- * \file
- *
- * \brief ARM functions for busy-wait delay loops
- *
- * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include "cycle_counter.h"
-
-// Delay loop is put to SRAM so that FWS will not affect delay time
-OPTIMIZE_HIGH
-RAMFUNC
-void portable_delay_cycles(unsigned long n)
-{
- UNUSED(n);
-
- __asm (
- "loop: DMB \n"
- "SUBS R0, R0, #1 \n"
- "BNE.N loop "
- );
-}
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/delay/sam/cycle_counter.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/delay/sam/cycle_counter.h
deleted file mode 100644
index 4ac1c6b..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/services/delay/sam/cycle_counter.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/**
- * \file
- *
- * \brief ARM functions for busy-wait delay loops
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef _cycle_counter_h_
-#define _cycle_counter_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#include <compiler.h>
-
-/**
- * @name Convenience functions for busy-wait delay loops
- *
- * @def delay_cycles
- * @brief Delay program execution for a specified number of CPU cycles.
- * @param n number of CPU cycles to wait
- *
- * @def cpu_delay_ms
- * @brief Delay program execution for a specified number of milliseconds.
- * @param delay number of milliseconds to wait
- * @param f_cpu CPU frequency in Hertz
- *
- * @def cpu_delay_us
- * @brief Delay program execution for a specified number of microseconds.
- * @param delay number of microseconds to wait
- * @param f_cpu CPU frequency in Hertz
- *
- * @def cpu_ms_2_cy
- * @brief Convert milli-seconds into CPU cycles.
- * @param ms number of milliseconds
- * @param f_cpu CPU frequency in Hertz
- * @return the converted number of CPU cycles
- *
- * @def cpu_us_2_cy
- * @brief Convert micro-seconds into CPU cycles.
- * @param ms number of microseconds
- * @param f_cpu CPU frequency in Hertz
- * @return the converted number of CPU cycles
- *
- * @{
- */
-
-/**
- * \brief Delay loop to delay n number of cycles
- *
- * \note The function runs in internal RAM so that flash wait states
- * will not affect the delay time.
- *
- * \param n Number of cycles
- */
-void portable_delay_cycles(unsigned long n);
-
-/* Cortex-M7 is faster than Cortex-M3/M4/M0+ */
-#ifdef __CM7_REV
-
-# define cpu_ms_2_cy(ms, f_cpu) \
- (((uint64_t)(ms) * (f_cpu) + (uint64_t)(5.932e3 - 1ul)) / (uint64_t)5.932e3)
-# define cpu_us_2_cy(us, f_cpu) \
- (((uint64_t)(us) * (f_cpu) + (uint64_t)(5.932e6 - 1ul)) / (uint64_t)5.932e6)
-
-#else
-
-# define cpu_ms_2_cy(ms, f_cpu) \
- (((uint64_t)(ms) * (f_cpu) + (uint64_t)(14e3 - 1ul)) / (uint64_t)14e3)
-# define cpu_us_2_cy(us, f_cpu) \
- (((uint64_t)(us) * (f_cpu) + (uint64_t)(14e6 - 1ul)) / (uint64_t)14e6)
-
-#endif
-
-#define delay_cycles portable_delay_cycles
-
-#define cpu_delay_ms(delay, f_cpu) delay_cycles(cpu_ms_2_cy(delay, f_cpu))
-#define cpu_delay_us(delay, f_cpu) delay_cycles(cpu_us_2_cy(delay, f_cpu))
-//! @}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _cycle_counter_h_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/interrupt.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/interrupt.h
deleted file mode 100644
index a88c6f0..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/interrupt.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/**
- * \file
- *
- * \brief Global interrupt management for 8- and 32-bit AVR
- *
- * Copyright (c) 2010-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef UTILS_INTERRUPT_H
-#define UTILS_INTERRUPT_H
-
-#include <parts.h>
-
-#if XMEGA || MEGA
-# include "interrupt/interrupt_avr8.h"
-#elif UC3
-# include "interrupt/interrupt_avr32.h"
-#elif SAM || SAMB
-# include "interrupt/interrupt_sam_nvic.h"
-#else
-# error Unsupported device.
-#endif
-
-/**
- * \defgroup interrupt_group Global interrupt management
- *
- * This is a driver for global enabling and disabling of interrupts.
- *
- * @{
- */
-
-#if defined(__DOXYGEN__)
-/**
- * \def CONFIG_INTERRUPT_FORCE_INTC
- * \brief Force usage of the ASF INTC driver
- *
- * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.
- * This is useful to ensure compatibility across compilers and shall be used only when required
- * by the application needs.
- */
-# define CONFIG_INTERRUPT_FORCE_INTC
-#endif
-
-//! \name Global interrupt flags
-//@{
-/**
- * \typedef irqflags_t
- * \brief Type used for holding state of interrupt flag
- */
-
-/**
- * \def cpu_irq_enable
- * \brief Enable interrupts globally
- */
-
-/**
- * \def cpu_irq_disable
- * \brief Disable interrupts globally
- */
-
-/**
- * \fn irqflags_t cpu_irq_save(void)
- * \brief Get and clear the global interrupt flags
- *
- * Use in conjunction with \ref cpu_irq_restore.
- *
- * \return Current state of interrupt flags.
- *
- * \note This function leaves interrupts disabled.
- */
-
-/**
- * \fn void cpu_irq_restore(irqflags_t flags)
- * \brief Restore global interrupt flags
- *
- * Use in conjunction with \ref cpu_irq_save.
- *
- * \param flags State to set interrupt flag to.
- */
-
-/**
- * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)
- * \brief Check if interrupts are globally enabled in supplied flags
- *
- * \param flags Currents state of interrupt flags.
- *
- * \return True if interrupts are enabled.
- */
-
-/**
- * \def cpu_irq_is_enabled
- * \brief Check if interrupts are globally enabled
- *
- * \return True if interrupts are enabled.
- */
-//@}
-
-//! @}
-
-/**
- * \ingroup interrupt_group
- * \defgroup interrupt_deprecated_group Deprecated interrupt definitions
- */
-
-#endif /* UTILS_INTERRUPT_H */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
deleted file mode 100644
index 26dcc91..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/**
- * \file
- *
- * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
- *
- * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include "interrupt_sam_nvic.h"
-
-#if !defined(__DOXYGEN__)
-/* Deprecated - global flag to determine the global interrupt state. Required by
- * QTouch library, however new applications should use cpu_irq_is_enabled()
- * which probes the true global interrupt state from the CPU special registers.
- */
-volatile bool g_interrupt_enabled = true;
-#endif
-
-void cpu_irq_enter_critical(void)
-{
- if (cpu_irq_critical_section_counter == 0) {
- if (cpu_irq_is_enabled()) {
- cpu_irq_disable();
- cpu_irq_prev_interrupt_state = true;
- } else {
- /* Make sure the to save the prev state as false */
- cpu_irq_prev_interrupt_state = false;
- }
-
- }
-
- cpu_irq_critical_section_counter++;
-}
-
-void cpu_irq_leave_critical(void)
-{
- /* Check if the user is trying to leave a critical section when not in a critical section */
- Assert(cpu_irq_critical_section_counter > 0);
-
- cpu_irq_critical_section_counter--;
-
- /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
- was enabled when entering critical state */
- if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
- cpu_irq_enable();
- }
-}
-
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
deleted file mode 100644
index 419ad20..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/**
- * \file
- *
- * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
- *
- * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef UTILS_INTERRUPT_INTERRUPT_H
-#define UTILS_INTERRUPT_INTERRUPT_H
-
-#include <compiler.h>
-#include <parts.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \weakgroup interrupt_group
- *
- * @{
- */
-
-/**
- * \name Interrupt Service Routine definition
- *
- * @{
- */
-
-/**
- * \brief Define service routine
- *
- * \note For NVIC devices the interrupt service routines are predefined to
- * add to vector table in binary generation, so there is no service
- * register at run time. The routine collections are in exceptions.h.
- *
- * Usage:
- * \code
- ISR(foo_irq_handler)
- {
- // Function definition
- ...
- }
-\endcode
- *
- * \param func Name for the function.
- */
-# define ISR(func) \
- void func (void)
-
-/**
- * \brief Initialize interrupt vectors
- *
- * For NVIC the interrupt vectors are put in vector table. So nothing
- * to do to initialize them, except defined the vector function with
- * right name.
- *
- * This must be called prior to \ref irq_register_handler.
- */
-# define irq_initialize_vectors() \
- do { \
- } while(0)
-
-/**
- * \brief Register handler for interrupt
- *
- * For NVIC the interrupt vectors are put in vector table. So nothing
- * to do to register them, except defined the vector function with
- * right name.
- *
- * Usage:
- * \code
- irq_initialize_vectors();
- irq_register_handler(foo_irq_handler);
-\endcode
- *
- * \note The function \a func must be defined with the \ref ISR macro.
- * \note The functions prototypes can be found in the device exception header
- * files (exceptions.h).
- */
-# define irq_register_handler(int_num, int_prio) \
- NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \
- NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \
- NVIC_EnableIRQ( (IRQn_Type)int_num); \
-
-//@}
-
-# define cpu_irq_enable() \
- do { \
- g_interrupt_enabled = true; \
- __DMB(); \
- __enable_irq(); \
- } while (0)
-# define cpu_irq_disable() \
- do { \
- __disable_irq(); \
- __DMB(); \
- g_interrupt_enabled = false; \
- } while (0)
-
-typedef uint32_t irqflags_t;
-
-#if !defined(__DOXYGEN__)
-extern volatile bool g_interrupt_enabled;
-#endif
-
-#define cpu_irq_is_enabled() (__get_PRIMASK() == 0)
-
-static volatile uint32_t cpu_irq_critical_section_counter;
-static volatile bool cpu_irq_prev_interrupt_state;
-
-static inline irqflags_t cpu_irq_save(void)
-{
- volatile irqflags_t flags = cpu_irq_is_enabled();
- cpu_irq_disable();
- return flags;
-}
-
-static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
-{
- return (flags);
-}
-
-static inline void cpu_irq_restore(irqflags_t flags)
-{
- if (cpu_irq_is_enabled_flags(flags))
- cpu_irq_enable();
-}
-
-void cpu_irq_enter_critical(void);
-void cpu_irq_leave_critical(void);
-
-/**
- * \weakgroup interrupt_deprecated_group
- * @{
- */
-
-#define Enable_global_interrupt() cpu_irq_enable()
-#define Disable_global_interrupt() cpu_irq_disable()
-#define Is_global_interrupt_enabled() cpu_irq_is_enabled()
-
-//@}
-
-//@}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* UTILS_INTERRUPT_INTERRUPT_H */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/parts.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/parts.h
deleted file mode 100644
index 46170c9..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/common/utils/parts.h
+++ /dev/null
@@ -1,1585 +0,0 @@
-/**
- * \file
- *
- * \brief Atmel part identification macros
- *
- * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef ATMEL_PARTS_H
-#define ATMEL_PARTS_H
-
-/**
- * \defgroup part_macros_group Atmel part identification macros
- *
- * This collection of macros identify which series and families that the various
- * Atmel parts belong to. These can be used to select part-dependent sections of
- * code at compile time.
- *
- * @{
- */
-
-/**
- * \name Convenience macros for part checking
- * @{
- */
-/* ! Check GCC and IAR part definition for 8-bit AVR */
-#define AVR8_PART_IS_DEFINED(part) \
- (defined(__ ## part ## __) || defined(__AVR_ ## part ## __))
-
-/* ! Check GCC and IAR part definition for 32-bit AVR */
-#define AVR32_PART_IS_DEFINED(part) \
- (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __))
-
-/* ! Check GCC and IAR part definition for SAM */
-#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __))
-/** @} */
-
-/**
- * \defgroup uc3_part_macros_group AVR UC3 parts
- * @{
- */
-
-/**
- * \name AVR UC3 A series
- * @{
- */
-#define UC3A0 ( \
- AVR32_PART_IS_DEFINED(UC3A0128) || \
- AVR32_PART_IS_DEFINED(UC3A0256) || \
- AVR32_PART_IS_DEFINED(UC3A0512) \
- )
-
-#define UC3A1 ( \
- AVR32_PART_IS_DEFINED(UC3A1128) || \
- AVR32_PART_IS_DEFINED(UC3A1256) || \
- AVR32_PART_IS_DEFINED(UC3A1512) \
- )
-
-#define UC3A3 ( \
- AVR32_PART_IS_DEFINED(UC3A364) || \
- AVR32_PART_IS_DEFINED(UC3A364S) || \
- AVR32_PART_IS_DEFINED(UC3A3128) || \
- AVR32_PART_IS_DEFINED(UC3A3128S) || \
- AVR32_PART_IS_DEFINED(UC3A3256) || \
- AVR32_PART_IS_DEFINED(UC3A3256S) \
- )
-
-#define UC3A4 ( \
- AVR32_PART_IS_DEFINED(UC3A464) || \
- AVR32_PART_IS_DEFINED(UC3A464S) || \
- AVR32_PART_IS_DEFINED(UC3A4128) || \
- AVR32_PART_IS_DEFINED(UC3A4128S) || \
- AVR32_PART_IS_DEFINED(UC3A4256) || \
- AVR32_PART_IS_DEFINED(UC3A4256S) \
- )
-/** @} */
-
-/**
- * \name AVR UC3 B series
- * @{
- */
-#define UC3B0 ( \
- AVR32_PART_IS_DEFINED(UC3B064) || \
- AVR32_PART_IS_DEFINED(UC3B0128) || \
- AVR32_PART_IS_DEFINED(UC3B0256) || \
- AVR32_PART_IS_DEFINED(UC3B0512) \
- )
-
-#define UC3B1 ( \
- AVR32_PART_IS_DEFINED(UC3B164) || \
- AVR32_PART_IS_DEFINED(UC3B1128) || \
- AVR32_PART_IS_DEFINED(UC3B1256) || \
- AVR32_PART_IS_DEFINED(UC3B1512) \
- )
-/** @} */
-
-/**
- * \name AVR UC3 C series
- * @{
- */
-#define UC3C0 ( \
- AVR32_PART_IS_DEFINED(UC3C064C) || \
- AVR32_PART_IS_DEFINED(UC3C0128C) || \
- AVR32_PART_IS_DEFINED(UC3C0256C) || \
- AVR32_PART_IS_DEFINED(UC3C0512C) \
- )
-
-#define UC3C1 ( \
- AVR32_PART_IS_DEFINED(UC3C164C) || \
- AVR32_PART_IS_DEFINED(UC3C1128C) || \
- AVR32_PART_IS_DEFINED(UC3C1256C) || \
- AVR32_PART_IS_DEFINED(UC3C1512C) \
- )
-
-#define UC3C2 ( \
- AVR32_PART_IS_DEFINED(UC3C264C) || \
- AVR32_PART_IS_DEFINED(UC3C2128C) || \
- AVR32_PART_IS_DEFINED(UC3C2256C) || \
- AVR32_PART_IS_DEFINED(UC3C2512C) \
- )
-/** @} */
-
-/**
- * \name AVR UC3 D series
- * @{
- */
-#define UC3D3 ( \
- AVR32_PART_IS_DEFINED(UC64D3) || \
- AVR32_PART_IS_DEFINED(UC128D3) \
- )
-
-#define UC3D4 ( \
- AVR32_PART_IS_DEFINED(UC64D4) || \
- AVR32_PART_IS_DEFINED(UC128D4) \
- )
-/** @} */
-
-/**
- * \name AVR UC3 L series
- * @{
- */
-#define UC3L0 ( \
- AVR32_PART_IS_DEFINED(UC3L016) || \
- AVR32_PART_IS_DEFINED(UC3L032) || \
- AVR32_PART_IS_DEFINED(UC3L064) \
- )
-
-#define UC3L0128 ( \
- AVR32_PART_IS_DEFINED(UC3L0128) \
- )
-
-#define UC3L0256 ( \
- AVR32_PART_IS_DEFINED(UC3L0256) \
- )
-
-#define UC3L3 ( \
- AVR32_PART_IS_DEFINED(UC64L3U) || \
- AVR32_PART_IS_DEFINED(UC128L3U) || \
- AVR32_PART_IS_DEFINED(UC256L3U) \
- )
-
-#define UC3L4 ( \
- AVR32_PART_IS_DEFINED(UC64L4U) || \
- AVR32_PART_IS_DEFINED(UC128L4U) || \
- AVR32_PART_IS_DEFINED(UC256L4U) \
- )
-
-#define UC3L3_L4 (UC3L3 || UC3L4)
-/** @} */
-
-/**
- * \name AVR UC3 families
- * @{
- */
-/** AVR UC3 A family */
-#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4)
-
-/** AVR UC3 B family */
-#define UC3B (UC3B0 || UC3B1)
-
-/** AVR UC3 C family */
-#define UC3C (UC3C0 || UC3C1 || UC3C2)
-
-/** AVR UC3 D family */
-#define UC3D (UC3D3 || UC3D4)
-
-/** AVR UC3 L family */
-#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4)
-/** @} */
-
-/** AVR UC3 product line */
-#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L)
-
-/** @} */
-
-/**
- * \defgroup xmega_part_macros_group AVR XMEGA parts
- * @{
- */
-
-/**
- * \name AVR XMEGA A series
- * @{
- */
-#define XMEGA_A1 ( \
- AVR8_PART_IS_DEFINED(ATxmega64A1) || \
- AVR8_PART_IS_DEFINED(ATxmega128A1) \
- )
-
-#define XMEGA_A3 ( \
- AVR8_PART_IS_DEFINED(ATxmega64A3) || \
- AVR8_PART_IS_DEFINED(ATxmega128A3) || \
- AVR8_PART_IS_DEFINED(ATxmega192A3) || \
- AVR8_PART_IS_DEFINED(ATxmega256A3) \
- )
-
-#define XMEGA_A3B ( \
- AVR8_PART_IS_DEFINED(ATxmega256A3B) \
- )
-
-#define XMEGA_A4 ( \
- AVR8_PART_IS_DEFINED(ATxmega16A4) || \
- AVR8_PART_IS_DEFINED(ATxmega32A4) \
- )
-/** @} */
-
-/**
- * \name AVR XMEGA AU series
- * @{
- */
-#define XMEGA_A1U ( \
- AVR8_PART_IS_DEFINED(ATxmega64A1U) || \
- AVR8_PART_IS_DEFINED(ATxmega128A1U) \
- )
-
-#define XMEGA_A3U ( \
- AVR8_PART_IS_DEFINED(ATxmega64A3U) || \
- AVR8_PART_IS_DEFINED(ATxmega128A3U) || \
- AVR8_PART_IS_DEFINED(ATxmega192A3U) || \
- AVR8_PART_IS_DEFINED(ATxmega256A3U) \
- )
-
-#define XMEGA_A3BU ( \
- AVR8_PART_IS_DEFINED(ATxmega256A3BU) \
- )
-
-#define XMEGA_A4U ( \
- AVR8_PART_IS_DEFINED(ATxmega16A4U) || \
- AVR8_PART_IS_DEFINED(ATxmega32A4U) || \
- AVR8_PART_IS_DEFINED(ATxmega64A4U) || \
- AVR8_PART_IS_DEFINED(ATxmega128A4U) \
- )
-/** @} */
-
-/**
- * \name AVR XMEGA B series
- * @{
- */
-#define XMEGA_B1 ( \
- AVR8_PART_IS_DEFINED(ATxmega64B1) || \
- AVR8_PART_IS_DEFINED(ATxmega128B1) \
- )
-
-#define XMEGA_B3 ( \
- AVR8_PART_IS_DEFINED(ATxmega64B3) || \
- AVR8_PART_IS_DEFINED(ATxmega128B3) \
- )
-/** @} */
-
-/**
- * \name AVR XMEGA C series
- * @{
- */
-#define XMEGA_C3 ( \
- AVR8_PART_IS_DEFINED(ATxmega384C3) || \
- AVR8_PART_IS_DEFINED(ATxmega256C3) || \
- AVR8_PART_IS_DEFINED(ATxmega192C3) || \
- AVR8_PART_IS_DEFINED(ATxmega128C3) || \
- AVR8_PART_IS_DEFINED(ATxmega64C3) || \
- AVR8_PART_IS_DEFINED(ATxmega32C3) \
- )
-
-#define XMEGA_C4 ( \
- AVR8_PART_IS_DEFINED(ATxmega32C4) || \
- AVR8_PART_IS_DEFINED(ATxmega16C4) \
- )
-/** @} */
-
-/**
- * \name AVR XMEGA D series
- * @{
- */
-#define XMEGA_D3 ( \
- AVR8_PART_IS_DEFINED(ATxmega32D3) || \
- AVR8_PART_IS_DEFINED(ATxmega64D3) || \
- AVR8_PART_IS_DEFINED(ATxmega128D3) || \
- AVR8_PART_IS_DEFINED(ATxmega192D3) || \
- AVR8_PART_IS_DEFINED(ATxmega256D3) || \
- AVR8_PART_IS_DEFINED(ATxmega384D3) \
- )
-
-#define XMEGA_D4 ( \
- AVR8_PART_IS_DEFINED(ATxmega16D4) || \
- AVR8_PART_IS_DEFINED(ATxmega32D4) || \
- AVR8_PART_IS_DEFINED(ATxmega64D4) || \
- AVR8_PART_IS_DEFINED(ATxmega128D4) \
- )
-/** @} */
-
-/**
- * \name AVR XMEGA E series
- * @{
- */
-#define XMEGA_E5 ( \
- AVR8_PART_IS_DEFINED(ATxmega8E5) || \
- AVR8_PART_IS_DEFINED(ATxmega16E5) || \
- AVR8_PART_IS_DEFINED(ATxmega32E5) \
- )
-/** @} */
-
-
-/**
- * \name AVR XMEGA families
- * @{
- */
-/** AVR XMEGA A family */
-#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4)
-
-/** AVR XMEGA AU family */
-#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U)
-
-/** AVR XMEGA B family */
-#define XMEGA_B (XMEGA_B1 || XMEGA_B3)
-
-/** AVR XMEGA C family */
-#define XMEGA_C (XMEGA_C3 || XMEGA_C4)
-
-/** AVR XMEGA D family */
-#define XMEGA_D (XMEGA_D3 || XMEGA_D4)
-
-/** AVR XMEGA E family */
-#define XMEGA_E (XMEGA_E5)
-/** @} */
-
-
-/** AVR XMEGA product line */
-#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E)
-
-/** @} */
-
-/**
- * \defgroup mega_part_macros_group megaAVR parts
- *
- * \note These megaAVR groupings are based on the groups in AVR Libc for the
- * part header files. They are not names of official megaAVR device series or
- * families.
- *
- * @{
- */
-
-/**
- * \name ATmegaxx0/xx1 subgroups
- * @{
- */
-#define MEGA_XX0 ( \
- AVR8_PART_IS_DEFINED(ATmega640) || \
- AVR8_PART_IS_DEFINED(ATmega1280) || \
- AVR8_PART_IS_DEFINED(ATmega2560) \
- )
-
-#define MEGA_XX1 ( \
- AVR8_PART_IS_DEFINED(ATmega1281) || \
- AVR8_PART_IS_DEFINED(ATmega2561) \
- )
-/** @} */
-
-/**
- * \name megaAVR groups
- * @{
- */
-/** ATmegaxx0/xx1 group */
-#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1)
-
-/** ATmegaxx4 group */
-#define MEGA_XX4 ( \
- AVR8_PART_IS_DEFINED(ATmega164A) || \
- AVR8_PART_IS_DEFINED(ATmega164PA) || \
- AVR8_PART_IS_DEFINED(ATmega324A) || \
- AVR8_PART_IS_DEFINED(ATmega324PA) || \
- AVR8_PART_IS_DEFINED(ATmega324PB) || \
- AVR8_PART_IS_DEFINED(ATmega644) || \
- AVR8_PART_IS_DEFINED(ATmega644A) || \
- AVR8_PART_IS_DEFINED(ATmega644PA) || \
- AVR8_PART_IS_DEFINED(ATmega1284P) || \
- AVR8_PART_IS_DEFINED(ATmega128RFA1) \
- )
-
-/** ATmegaxx4 group */
-#define MEGA_XX4_A ( \
- AVR8_PART_IS_DEFINED(ATmega164A) || \
- AVR8_PART_IS_DEFINED(ATmega164PA) || \
- AVR8_PART_IS_DEFINED(ATmega324A) || \
- AVR8_PART_IS_DEFINED(ATmega324PA) || \
- AVR8_PART_IS_DEFINED(ATmega644A) || \
- AVR8_PART_IS_DEFINED(ATmega644PA) || \
- AVR8_PART_IS_DEFINED(ATmega1284P) \
- )
-
-/** ATmegaxx8 group */
-#define MEGA_XX8 ( \
- AVR8_PART_IS_DEFINED(ATmega48) || \
- AVR8_PART_IS_DEFINED(ATmega48A) || \
- AVR8_PART_IS_DEFINED(ATmega48PA) || \
- AVR8_PART_IS_DEFINED(ATmega48PB) || \
- AVR8_PART_IS_DEFINED(ATmega88) || \
- AVR8_PART_IS_DEFINED(ATmega88A) || \
- AVR8_PART_IS_DEFINED(ATmega88PA) || \
- AVR8_PART_IS_DEFINED(ATmega88PB) || \
- AVR8_PART_IS_DEFINED(ATmega168) || \
- AVR8_PART_IS_DEFINED(ATmega168A) || \
- AVR8_PART_IS_DEFINED(ATmega168PA) || \
- AVR8_PART_IS_DEFINED(ATmega168PB) || \
- AVR8_PART_IS_DEFINED(ATmega328) || \
- AVR8_PART_IS_DEFINED(ATmega328P) || \
- AVR8_PART_IS_DEFINED(ATmega328PB) \
- )
-
-/** ATmegaxx8A/P/PA group */
-#define MEGA_XX8_A ( \
- AVR8_PART_IS_DEFINED(ATmega48A) || \
- AVR8_PART_IS_DEFINED(ATmega48PA) || \
- AVR8_PART_IS_DEFINED(ATmega88A) || \
- AVR8_PART_IS_DEFINED(ATmega88PA) || \
- AVR8_PART_IS_DEFINED(ATmega168A) || \
- AVR8_PART_IS_DEFINED(ATmega168PA) || \
- AVR8_PART_IS_DEFINED(ATmega328P) \
- )
-
-/** ATmegaxx group */
-#define MEGA_XX ( \
- AVR8_PART_IS_DEFINED(ATmega16) || \
- AVR8_PART_IS_DEFINED(ATmega16A) || \
- AVR8_PART_IS_DEFINED(ATmega32) || \
- AVR8_PART_IS_DEFINED(ATmega32A) || \
- AVR8_PART_IS_DEFINED(ATmega64) || \
- AVR8_PART_IS_DEFINED(ATmega64A) || \
- AVR8_PART_IS_DEFINED(ATmega128) || \
- AVR8_PART_IS_DEFINED(ATmega128A) \
- )
-
-/** ATmegaxxA/P/PA group */
-#define MEGA_XX_A ( \
- AVR8_PART_IS_DEFINED(ATmega16A) || \
- AVR8_PART_IS_DEFINED(ATmega32A) || \
- AVR8_PART_IS_DEFINED(ATmega64A) || \
- AVR8_PART_IS_DEFINED(ATmega128A) \
- )
-/** ATmegaxxRFA1 group */
-#define MEGA_RFA1 ( \
- AVR8_PART_IS_DEFINED(ATmega128RFA1) \
- )
-
-/** ATmegaxxRFR2 group */
-#define MEGA_RFR2 ( \
- AVR8_PART_IS_DEFINED(ATmega64RFR2) || \
- AVR8_PART_IS_DEFINED(ATmega128RFR2) || \
- AVR8_PART_IS_DEFINED(ATmega256RFR2) || \
- AVR8_PART_IS_DEFINED(ATmega644RFR2) || \
- AVR8_PART_IS_DEFINED(ATmega1284RFR2) || \
- AVR8_PART_IS_DEFINED(ATmega2564RFR2) \
- )
-
-
-/** ATmegaxxRFxx group */
-#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2)
-
-/**
- * \name ATmegaxx_un0/un1/un2 subgroups
- * @{
- */
-#define MEGA_XX_UN0 ( \
- AVR8_PART_IS_DEFINED(ATmega16) || \
- AVR8_PART_IS_DEFINED(ATmega16A) || \
- AVR8_PART_IS_DEFINED(ATmega32) || \
- AVR8_PART_IS_DEFINED(ATmega32A) \
- )
-
-/** ATmegaxx group without power reduction and
- * And interrupt sense register.
- */
-#define MEGA_XX_UN1 ( \
- AVR8_PART_IS_DEFINED(ATmega64) || \
- AVR8_PART_IS_DEFINED(ATmega64A) || \
- AVR8_PART_IS_DEFINED(ATmega128) || \
- AVR8_PART_IS_DEFINED(ATmega128A) \
- )
-
-/** ATmegaxx group without power reduction and
- * And interrupt sense register.
- */
-#define MEGA_XX_UN2 ( \
- AVR8_PART_IS_DEFINED(ATmega169P) || \
- AVR8_PART_IS_DEFINED(ATmega169PA) || \
- AVR8_PART_IS_DEFINED(ATmega329P) || \
- AVR8_PART_IS_DEFINED(ATmega329PA) \
- )
-
-/** Devices added to complete megaAVR offering.
- * Please do not use this group symbol as it is not intended
- * to be permanent: the devices should be regrouped.
- */
-#define MEGA_UNCATEGORIZED ( \
- AVR8_PART_IS_DEFINED(AT90CAN128) || \
- AVR8_PART_IS_DEFINED(AT90CAN32) || \
- AVR8_PART_IS_DEFINED(AT90CAN64) || \
- AVR8_PART_IS_DEFINED(AT90PWM1) || \
- AVR8_PART_IS_DEFINED(AT90PWM216) || \
- AVR8_PART_IS_DEFINED(AT90PWM2B) || \
- AVR8_PART_IS_DEFINED(AT90PWM316) || \
- AVR8_PART_IS_DEFINED(AT90PWM3B) || \
- AVR8_PART_IS_DEFINED(AT90PWM81) || \
- AVR8_PART_IS_DEFINED(AT90USB1286) || \
- AVR8_PART_IS_DEFINED(AT90USB1287) || \
- AVR8_PART_IS_DEFINED(AT90USB162) || \
- AVR8_PART_IS_DEFINED(AT90USB646) || \
- AVR8_PART_IS_DEFINED(AT90USB647) || \
- AVR8_PART_IS_DEFINED(AT90USB82) || \
- AVR8_PART_IS_DEFINED(ATmega1284) || \
- AVR8_PART_IS_DEFINED(ATmega162) || \
- AVR8_PART_IS_DEFINED(ATmega164P) || \
- AVR8_PART_IS_DEFINED(ATmega165A) || \
- AVR8_PART_IS_DEFINED(ATmega165P) || \
- AVR8_PART_IS_DEFINED(ATmega165PA) || \
- AVR8_PART_IS_DEFINED(ATmega168P) || \
- AVR8_PART_IS_DEFINED(ATmega169A) || \
- AVR8_PART_IS_DEFINED(ATmega16M1) || \
- AVR8_PART_IS_DEFINED(ATmega16U2) || \
- AVR8_PART_IS_DEFINED(ATmega16U4) || \
- AVR8_PART_IS_DEFINED(ATmega256RFA2) || \
- AVR8_PART_IS_DEFINED(ATmega324P) || \
- AVR8_PART_IS_DEFINED(ATmega325) || \
- AVR8_PART_IS_DEFINED(ATmega3250) || \
- AVR8_PART_IS_DEFINED(ATmega3250A) || \
- AVR8_PART_IS_DEFINED(ATmega3250P) || \
- AVR8_PART_IS_DEFINED(ATmega3250PA) || \
- AVR8_PART_IS_DEFINED(ATmega325A) || \
- AVR8_PART_IS_DEFINED(ATmega325P) || \
- AVR8_PART_IS_DEFINED(ATmega325PA) || \
- AVR8_PART_IS_DEFINED(ATmega329) || \
- AVR8_PART_IS_DEFINED(ATmega3290) || \
- AVR8_PART_IS_DEFINED(ATmega3290A) || \
- AVR8_PART_IS_DEFINED(ATmega3290P) || \
- AVR8_PART_IS_DEFINED(ATmega3290PA) || \
- AVR8_PART_IS_DEFINED(ATmega329A) || \
- AVR8_PART_IS_DEFINED(ATmega32M1) || \
- AVR8_PART_IS_DEFINED(ATmega32U2) || \
- AVR8_PART_IS_DEFINED(ATmega32U4) || \
- AVR8_PART_IS_DEFINED(ATmega48P) || \
- AVR8_PART_IS_DEFINED(ATmega644P) || \
- AVR8_PART_IS_DEFINED(ATmega645) || \
- AVR8_PART_IS_DEFINED(ATmega6450) || \
- AVR8_PART_IS_DEFINED(ATmega6450A) || \
- AVR8_PART_IS_DEFINED(ATmega6450P) || \
- AVR8_PART_IS_DEFINED(ATmega645A) || \
- AVR8_PART_IS_DEFINED(ATmega645P) || \
- AVR8_PART_IS_DEFINED(ATmega649) || \
- AVR8_PART_IS_DEFINED(ATmega6490) || \
- AVR8_PART_IS_DEFINED(ATmega6490A) || \
- AVR8_PART_IS_DEFINED(ATmega6490P) || \
- AVR8_PART_IS_DEFINED(ATmega649A) || \
- AVR8_PART_IS_DEFINED(ATmega649P) || \
- AVR8_PART_IS_DEFINED(ATmega64M1) || \
- AVR8_PART_IS_DEFINED(ATmega64RFA2) || \
- AVR8_PART_IS_DEFINED(ATmega8) || \
- AVR8_PART_IS_DEFINED(ATmega8515) || \
- AVR8_PART_IS_DEFINED(ATmega8535) || \
- AVR8_PART_IS_DEFINED(ATmega88P) || \
- AVR8_PART_IS_DEFINED(ATmega8A) || \
- AVR8_PART_IS_DEFINED(ATmega8U2) \
- )
-
-/** Unspecified group */
-#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \
- MEGA_UNCATEGORIZED)
-
-/** @} */
-
-/** megaAVR product line */
-#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \
- MEGA_UNSPECIFIED)
-
-/** @} */
-
-/**
- * \defgroup sam_part_macros_group SAM parts
- * @{
- */
-
-/**
- * \name SAM3S series
- * @{
- */
-#define SAM3S1 ( \
- SAM_PART_IS_DEFINED(SAM3S1A) || \
- SAM_PART_IS_DEFINED(SAM3S1B) || \
- SAM_PART_IS_DEFINED(SAM3S1C) \
- )
-
-#define SAM3S2 ( \
- SAM_PART_IS_DEFINED(SAM3S2A) || \
- SAM_PART_IS_DEFINED(SAM3S2B) || \
- SAM_PART_IS_DEFINED(SAM3S2C) \
- )
-
-#define SAM3S4 ( \
- SAM_PART_IS_DEFINED(SAM3S4A) || \
- SAM_PART_IS_DEFINED(SAM3S4B) || \
- SAM_PART_IS_DEFINED(SAM3S4C) \
- )
-
-#define SAM3S8 ( \
- SAM_PART_IS_DEFINED(SAM3S8B) || \
- SAM_PART_IS_DEFINED(SAM3S8C) \
- )
-
-#define SAM3SD8 ( \
- SAM_PART_IS_DEFINED(SAM3SD8B) || \
- SAM_PART_IS_DEFINED(SAM3SD8C) \
- )
-/** @} */
-
-/**
- * \name SAM3U series
- * @{
- */
-#define SAM3U1 ( \
- SAM_PART_IS_DEFINED(SAM3U1C) || \
- SAM_PART_IS_DEFINED(SAM3U1E) \
- )
-
-#define SAM3U2 ( \
- SAM_PART_IS_DEFINED(SAM3U2C) || \
- SAM_PART_IS_DEFINED(SAM3U2E) \
- )
-
-#define SAM3U4 ( \
- SAM_PART_IS_DEFINED(SAM3U4C) || \
- SAM_PART_IS_DEFINED(SAM3U4E) \
- )
-/** @} */
-
-/**
- * \name SAM3N series
- * @{
- */
-#define SAM3N00 ( \
- SAM_PART_IS_DEFINED(SAM3N00A) || \
- SAM_PART_IS_DEFINED(SAM3N00B) \
- )
-
-#define SAM3N0 ( \
- SAM_PART_IS_DEFINED(SAM3N0A) || \
- SAM_PART_IS_DEFINED(SAM3N0B) || \
- SAM_PART_IS_DEFINED(SAM3N0C) \
- )
-
-#define SAM3N1 ( \
- SAM_PART_IS_DEFINED(SAM3N1A) || \
- SAM_PART_IS_DEFINED(SAM3N1B) || \
- SAM_PART_IS_DEFINED(SAM3N1C) \
- )
-
-#define SAM3N2 ( \
- SAM_PART_IS_DEFINED(SAM3N2A) || \
- SAM_PART_IS_DEFINED(SAM3N2B) || \
- SAM_PART_IS_DEFINED(SAM3N2C) \
- )
-
-#define SAM3N4 ( \
- SAM_PART_IS_DEFINED(SAM3N4A) || \
- SAM_PART_IS_DEFINED(SAM3N4B) || \
- SAM_PART_IS_DEFINED(SAM3N4C) \
- )
-/** @} */
-
-/**
- * \name SAM3X series
- * @{
- */
-#define SAM3X4 ( \
- SAM_PART_IS_DEFINED(SAM3X4C) || \
- SAM_PART_IS_DEFINED(SAM3X4E) \
- )
-
-#define SAM3X8 ( \
- SAM_PART_IS_DEFINED(SAM3X8C) || \
- SAM_PART_IS_DEFINED(SAM3X8E) || \
- SAM_PART_IS_DEFINED(SAM3X8H) \
- )
-/** @} */
-
-/**
- * \name SAM3A series
- * @{
- */
-#define SAM3A4 ( \
- SAM_PART_IS_DEFINED(SAM3A4C) \
- )
-
-#define SAM3A8 ( \
- SAM_PART_IS_DEFINED(SAM3A8C) \
- )
-/** @} */
-
-/**
- * \name SAM4S series
- * @{
- */
-#define SAM4S2 ( \
- SAM_PART_IS_DEFINED(SAM4S2A) || \
- SAM_PART_IS_DEFINED(SAM4S2B) || \
- SAM_PART_IS_DEFINED(SAM4S2C) \
- )
-
-#define SAM4S4 ( \
- SAM_PART_IS_DEFINED(SAM4S4A) || \
- SAM_PART_IS_DEFINED(SAM4S4B) || \
- SAM_PART_IS_DEFINED(SAM4S4C) \
- )
-
-#define SAM4S8 ( \
- SAM_PART_IS_DEFINED(SAM4S8B) || \
- SAM_PART_IS_DEFINED(SAM4S8C) \
- )
-
-#define SAM4S16 ( \
- SAM_PART_IS_DEFINED(SAM4S16B) || \
- SAM_PART_IS_DEFINED(SAM4S16C) \
- )
-
-#define SAM4SA16 ( \
- SAM_PART_IS_DEFINED(SAM4SA16B) || \
- SAM_PART_IS_DEFINED(SAM4SA16C) \
- )
-
-#define SAM4SD16 ( \
- SAM_PART_IS_DEFINED(SAM4SD16B) || \
- SAM_PART_IS_DEFINED(SAM4SD16C) \
- )
-
-#define SAM4SD32 ( \
- SAM_PART_IS_DEFINED(SAM4SD32B) || \
- SAM_PART_IS_DEFINED(SAM4SD32C) \
- )
-/** @} */
-
-/**
- * \name SAM4L series
- * @{
- */
-#define SAM4LS ( \
- SAM_PART_IS_DEFINED(SAM4LS2A) || \
- SAM_PART_IS_DEFINED(SAM4LS2B) || \
- SAM_PART_IS_DEFINED(SAM4LS2C) || \
- SAM_PART_IS_DEFINED(SAM4LS4A) || \
- SAM_PART_IS_DEFINED(SAM4LS4B) || \
- SAM_PART_IS_DEFINED(SAM4LS4C) || \
- SAM_PART_IS_DEFINED(SAM4LS8A) || \
- SAM_PART_IS_DEFINED(SAM4LS8B) || \
- SAM_PART_IS_DEFINED(SAM4LS8C) \
- )
-
-#define SAM4LC ( \
- SAM_PART_IS_DEFINED(SAM4LC2A) || \
- SAM_PART_IS_DEFINED(SAM4LC2B) || \
- SAM_PART_IS_DEFINED(SAM4LC2C) || \
- SAM_PART_IS_DEFINED(SAM4LC4A) || \
- SAM_PART_IS_DEFINED(SAM4LC4B) || \
- SAM_PART_IS_DEFINED(SAM4LC4C) || \
- SAM_PART_IS_DEFINED(SAM4LC8A) || \
- SAM_PART_IS_DEFINED(SAM4LC8B) || \
- SAM_PART_IS_DEFINED(SAM4LC8C) \
- )
-/** @} */
-
-/**
- * \name SAMD20 series
- * @{
- */
-#define SAMD20J ( \
- SAM_PART_IS_DEFINED(SAMD20J14) || \
- SAM_PART_IS_DEFINED(SAMD20J15) || \
- SAM_PART_IS_DEFINED(SAMD20J16) || \
- SAM_PART_IS_DEFINED(SAMD20J17) || \
- SAM_PART_IS_DEFINED(SAMD20J18) \
- )
-
-#define SAMD20G ( \
- SAM_PART_IS_DEFINED(SAMD20G14) || \
- SAM_PART_IS_DEFINED(SAMD20G15) || \
- SAM_PART_IS_DEFINED(SAMD20G16) || \
- SAM_PART_IS_DEFINED(SAMD20G17) || \
- SAM_PART_IS_DEFINED(SAMD20G17U) || \
- SAM_PART_IS_DEFINED(SAMD20G18) || \
- SAM_PART_IS_DEFINED(SAMD20G18U) \
- )
-
-#define SAMD20E ( \
- SAM_PART_IS_DEFINED(SAMD20E14) || \
- SAM_PART_IS_DEFINED(SAMD20E15) || \
- SAM_PART_IS_DEFINED(SAMD20E16) || \
- SAM_PART_IS_DEFINED(SAMD20E17) || \
- SAM_PART_IS_DEFINED(SAMD20E18) \
- )
-/** @} */
-
-/**
- * \name SAMD21 series
- * @{
- */
-#define SAMD21J ( \
- SAM_PART_IS_DEFINED(SAMD21J15A) || \
- SAM_PART_IS_DEFINED(SAMD21J16A) || \
- SAM_PART_IS_DEFINED(SAMD21J17A) || \
- SAM_PART_IS_DEFINED(SAMD21J18A) || \
- SAM_PART_IS_DEFINED(SAMD21J15B) || \
- SAM_PART_IS_DEFINED(SAMD21J16B) \
- )
-
-#define SAMD21G ( \
- SAM_PART_IS_DEFINED(SAMD21G15A) || \
- SAM_PART_IS_DEFINED(SAMD21G16A) || \
- SAM_PART_IS_DEFINED(SAMD21G17A) || \
- SAM_PART_IS_DEFINED(SAMD21G17AU) || \
- SAM_PART_IS_DEFINED(SAMD21G18A) || \
- SAM_PART_IS_DEFINED(SAMD21G18AU) || \
- SAM_PART_IS_DEFINED(SAMD21G15B) || \
- SAM_PART_IS_DEFINED(SAMD21G16B) || \
- SAM_PART_IS_DEFINED(SAMD21G15L) || \
- SAM_PART_IS_DEFINED(SAMD21G16L) \
- )
-
-#define SAMD21GXXL ( \
- SAM_PART_IS_DEFINED(SAMD21G15L) || \
- SAM_PART_IS_DEFINED(SAMD21G16L) \
- )
-
-#define SAMD21E ( \
- SAM_PART_IS_DEFINED(SAMD21E15A) || \
- SAM_PART_IS_DEFINED(SAMD21E16A) || \
- SAM_PART_IS_DEFINED(SAMD21E17A) || \
- SAM_PART_IS_DEFINED(SAMD21E18A) || \
- SAM_PART_IS_DEFINED(SAMD21E15B) || \
- SAM_PART_IS_DEFINED(SAMD21E15BU) || \
- SAM_PART_IS_DEFINED(SAMD21E16B) || \
- SAM_PART_IS_DEFINED(SAMD21E16BU) || \
- SAM_PART_IS_DEFINED(SAMD21E15L) || \
- SAM_PART_IS_DEFINED(SAMD21E16L) \
- )
-
-#define SAMD21EXXL ( \
- SAM_PART_IS_DEFINED(SAMD21E15L) || \
- SAM_PART_IS_DEFINED(SAMD21E16L) \
- )
-
-/** @} */
-
-/**
- * \name SAMR21 series
- * @{
- */
-#define SAMR21G ( \
- SAM_PART_IS_DEFINED(SAMR21G16A) || \
- SAM_PART_IS_DEFINED(SAMR21G17A) || \
- SAM_PART_IS_DEFINED(SAMR21G18A) \
- )
-
-#define SAMR21E ( \
- SAM_PART_IS_DEFINED(SAMR21E16A) || \
- SAM_PART_IS_DEFINED(SAMR21E17A) || \
- SAM_PART_IS_DEFINED(SAMR21E18A) || \
- SAM_PART_IS_DEFINED(SAMR21E19A) \
- )
-/** @} */
-
-/**
- * \name SAMR30 series
- * @{
- */
-#define SAMR30G ( \
- SAM_PART_IS_DEFINED(SAMR30G18A) \
- )
-
-#define SAMR30E ( \
- SAM_PART_IS_DEFINED(SAMR30E18A) \
- )
-/** @} */
-
-/**
- * \name SAMB11 series
- * @{
- */
-#define SAMB11G ( \
- SAM_PART_IS_DEFINED(SAMB11G18A) || \
- SAM_PART_IS_DEFINED(SAMB11ZR) \
- )
-#define BTLC1000 ( \
- SAM_PART_IS_DEFINED(BTLC1000WLCSP) \
- )
-
-/** @} */
-
-/**
- * \name SAMD09 series
- * @{
- */
-#define SAMD09C ( \
- SAM_PART_IS_DEFINED(SAMD09C13A) \
- )
-
-#define SAMD09D ( \
- SAM_PART_IS_DEFINED(SAMD09D14A) \
- )
-/** @} */
-
-/**
- * \name SAMD10 series
- * @{
- */
-#define SAMD10C ( \
- SAM_PART_IS_DEFINED(SAMD10C12A) || \
- SAM_PART_IS_DEFINED(SAMD10C13A) || \
- SAM_PART_IS_DEFINED(SAMD10C14A) \
- )
-
-#define SAMD10DS ( \
- SAM_PART_IS_DEFINED(SAMD10D12AS) || \
- SAM_PART_IS_DEFINED(SAMD10D13AS) || \
- SAM_PART_IS_DEFINED(SAMD10D14AS) \
- )
-
-#define SAMD10DM ( \
- SAM_PART_IS_DEFINED(SAMD10D12AM) || \
- SAM_PART_IS_DEFINED(SAMD10D13AM) || \
- SAM_PART_IS_DEFINED(SAMD10D14AM) \
- )
-
-#define SAMD10DU ( \
- SAM_PART_IS_DEFINED(SAMD10D14AU) \
- )
-/** @} */
-
-/**
- * \name SAMD11 series
- * @{
- */
-#define SAMD11C ( \
- SAM_PART_IS_DEFINED(SAMD11C14A) \
- )
-
-#define SAMD11DS ( \
- SAM_PART_IS_DEFINED(SAMD11D14AS) \
- )
-
-#define SAMD11DM ( \
- SAM_PART_IS_DEFINED(SAMD11D14AM) \
- )
-
-#define SAMD11DU ( \
- SAM_PART_IS_DEFINED(SAMD11D14AU) \
- )
-/** @} */
-
-/**
- * \name SAML21 series
- * @{
- */
-#define SAML21E ( \
- SAM_PART_IS_DEFINED(SAML21E18A) || \
- SAM_PART_IS_DEFINED(SAML21E15B) || \
- SAM_PART_IS_DEFINED(SAML21E16B) || \
- SAM_PART_IS_DEFINED(SAML21E17B) || \
- SAM_PART_IS_DEFINED(SAML21E18B) \
- )
-
-#define SAML21G ( \
- SAM_PART_IS_DEFINED(SAML21G18A) || \
- SAM_PART_IS_DEFINED(SAML21G16B) || \
- SAM_PART_IS_DEFINED(SAML21G17B) || \
- SAM_PART_IS_DEFINED(SAML21G18B) \
- )
-
-#define SAML21J ( \
- SAM_PART_IS_DEFINED(SAML21J18A) || \
- SAM_PART_IS_DEFINED(SAML21J16B) || \
- SAM_PART_IS_DEFINED(SAML21J17B) || \
- SAM_PART_IS_DEFINED(SAML21J18B) \
- )
-
-/* Group for SAML21 A variant: SAML21[E/G/J][18]A */
-#define SAML21XXXA ( \
- SAM_PART_IS_DEFINED(SAML21E18A) || \
- SAM_PART_IS_DEFINED(SAML21G18A) || \
- SAM_PART_IS_DEFINED(SAML21J18A) \
- )
-
-/* Group for SAML21 B variant: SAML21[E/G/J][15/16/1718]B */
-#define SAML21XXXB ( \
- SAM_PART_IS_DEFINED(SAML21E15B) || \
- SAM_PART_IS_DEFINED(SAML21E16B) || \
- SAM_PART_IS_DEFINED(SAML21E17B) || \
- SAM_PART_IS_DEFINED(SAML21E18B) || \
- SAM_PART_IS_DEFINED(SAML21G16B) || \
- SAM_PART_IS_DEFINED(SAML21G17B) || \
- SAM_PART_IS_DEFINED(SAML21G18B) || \
- SAM_PART_IS_DEFINED(SAML21J16B) || \
- SAM_PART_IS_DEFINED(SAML21J17B) || \
- SAM_PART_IS_DEFINED(SAML21J18B) \
- )
-
-/** @} */
-
-/**
- * \name SAML22 series
- * @{
- */
-#define SAML22N ( \
- SAM_PART_IS_DEFINED(SAML22N16A) || \
- SAM_PART_IS_DEFINED(SAML22N17A) || \
- SAM_PART_IS_DEFINED(SAML22N18A) \
- )
-
-#define SAML22G ( \
- SAM_PART_IS_DEFINED(SAML22G16A) || \
- SAM_PART_IS_DEFINED(SAML22G17A) || \
- SAM_PART_IS_DEFINED(SAML22G18A) \
- )
-
-#define SAML22J ( \
- SAM_PART_IS_DEFINED(SAML22J16A) || \
- SAM_PART_IS_DEFINED(SAML22J17A) || \
- SAM_PART_IS_DEFINED(SAML22J18A) \
- )
-/** @} */
-
-/**
- * \name SAMDA1 series
- * @{
- */
-#define SAMDA1J ( \
- SAM_PART_IS_DEFINED(SAMDA1J14A) || \
- SAM_PART_IS_DEFINED(SAMDA1J15A) || \
- SAM_PART_IS_DEFINED(SAMDA1J16A) \
- )
-
-#define SAMDA1G ( \
- SAM_PART_IS_DEFINED(SAMDA1G14A) || \
- SAM_PART_IS_DEFINED(SAMDA1G15A) || \
- SAM_PART_IS_DEFINED(SAMDA1G16A) \
- )
-
-#define SAMDA1E ( \
- SAM_PART_IS_DEFINED(SAMDA1E14A) || \
- SAM_PART_IS_DEFINED(SAMDA1E15A) || \
- SAM_PART_IS_DEFINED(SAMDA1E16A) \
- )
-/** @} */
-
-/**
- * \name SAMHA1 series
- * @{
- */
-#define SAMHA1G ( \
- SAM_PART_IS_DEFINED(SAMHA1G14A) || \
- SAM_PART_IS_DEFINED(SAMHA1G15A) || \
- SAM_PART_IS_DEFINED(SAMHA1G16A) \
- )
-
-/** @} */
-
-/**
- * \name SAMC20 series
- * @{
- */
-#define SAMC20E ( \
- SAM_PART_IS_DEFINED(SAMC20E15A) || \
- SAM_PART_IS_DEFINED(SAMC20E16A) || \
- SAM_PART_IS_DEFINED(SAMC20E17A) || \
- SAM_PART_IS_DEFINED(SAMC20E18A) \
- )
-
-#define SAMC20G ( \
- SAM_PART_IS_DEFINED(SAMC20G15A) || \
- SAM_PART_IS_DEFINED(SAMC20G16A) || \
- SAM_PART_IS_DEFINED(SAMC20G17A) || \
- SAM_PART_IS_DEFINED(SAMC20G18A) \
- )
-
-#define SAMC20J ( \
- SAM_PART_IS_DEFINED(SAMC20J15A) || \
- SAM_PART_IS_DEFINED(SAMC20J16A) || \
- SAM_PART_IS_DEFINED(SAMC20J17A) || \
- SAM_PART_IS_DEFINED(SAMC20J18A) \
- )
-/** @} */
-
-/**
- * \name SAMC21 series
- * @{
- */
-#define SAMC21E ( \
- SAM_PART_IS_DEFINED(SAMC21E15A) || \
- SAM_PART_IS_DEFINED(SAMC21E16A) || \
- SAM_PART_IS_DEFINED(SAMC21E17A) || \
- SAM_PART_IS_DEFINED(SAMC21E18A) \
- )
-
-#define SAMC21G ( \
- SAM_PART_IS_DEFINED(SAMC21G15A) || \
- SAM_PART_IS_DEFINED(SAMC21G16A) || \
- SAM_PART_IS_DEFINED(SAMC21G17A) || \
- SAM_PART_IS_DEFINED(SAMC21G18A) \
- )
-
-#define SAMC21J ( \
- SAM_PART_IS_DEFINED(SAMC21J15A) || \
- SAM_PART_IS_DEFINED(SAMC21J16A) || \
- SAM_PART_IS_DEFINED(SAMC21J17A) || \
- SAM_PART_IS_DEFINED(SAMC21J18A) \
- )
-/** @} */
-
-/**
- * \name SAM4E series
- * @{
- */
-#define SAM4E8 ( \
- SAM_PART_IS_DEFINED(SAM4E8C) || \
- SAM_PART_IS_DEFINED(SAM4E8CB) || \
- SAM_PART_IS_DEFINED(SAM4E8E) \
- )
-
-#define SAM4E16 ( \
- SAM_PART_IS_DEFINED(SAM4E16C) || \
- SAM_PART_IS_DEFINED(SAM4E16CB) || \
- SAM_PART_IS_DEFINED(SAM4E16E) \
- )
-/** @} */
-
-/**
- * \name SAM4N series
- * @{
- */
-#define SAM4N8 ( \
- SAM_PART_IS_DEFINED(SAM4N8A) || \
- SAM_PART_IS_DEFINED(SAM4N8B) || \
- SAM_PART_IS_DEFINED(SAM4N8C) \
- )
-
-#define SAM4N16 ( \
- SAM_PART_IS_DEFINED(SAM4N16B) || \
- SAM_PART_IS_DEFINED(SAM4N16C) \
- )
-/** @} */
-
-/**
- * \name SAM4C series
- * @{
- */
-#define SAM4C4_0 ( \
- SAM_PART_IS_DEFINED(SAM4C4C_0) \
- )
-
-#define SAM4C4_1 ( \
- SAM_PART_IS_DEFINED(SAM4C4C_1) \
- )
-
-#define SAM4C4 (SAM4C4_0 || SAM4C4_1)
-
-#define SAM4C8_0 ( \
- SAM_PART_IS_DEFINED(SAM4C8C_0) \
- )
-
-#define SAM4C8_1 ( \
- SAM_PART_IS_DEFINED(SAM4C8C_1) \
- )
-
-#define SAM4C8 (SAM4C8_0 || SAM4C8_1)
-
-#define SAM4C16_0 ( \
- SAM_PART_IS_DEFINED(SAM4C16C_0) \
- )
-
-#define SAM4C16_1 ( \
- SAM_PART_IS_DEFINED(SAM4C16C_1) \
- )
-
-#define SAM4C16 (SAM4C16_0 || SAM4C16_1)
-
-#define SAM4C32_0 ( \
- SAM_PART_IS_DEFINED(SAM4C32C_0) ||\
- SAM_PART_IS_DEFINED(SAM4C32E_0) \
- )
-
-#define SAM4C32_1 ( \
- SAM_PART_IS_DEFINED(SAM4C32C_1) ||\
- SAM_PART_IS_DEFINED(SAM4C32E_1) \
- )
-
-
-#define SAM4C32 (SAM4C32_0 || SAM4C32_1)
-
-/** @} */
-
-/**
- * \name SAM4CM series
- * @{
- */
-#define SAM4CMP8_0 ( \
- SAM_PART_IS_DEFINED(SAM4CMP8C_0) \
- )
-
-#define SAM4CMP8_1 ( \
- SAM_PART_IS_DEFINED(SAM4CMP8C_1) \
- )
-
-#define SAM4CMP8 (SAM4CMP8_0 || SAM4CMP8_1)
-
-#define SAM4CMP16_0 ( \
- SAM_PART_IS_DEFINED(SAM4CMP16C_0) \
- )
-
-#define SAM4CMP16_1 ( \
- SAM_PART_IS_DEFINED(SAM4CMP16C_1) \
- )
-
-#define SAM4CMP16 (SAM4CMP16_0 || SAM4CMP16_1)
-
-#define SAM4CMP32_0 ( \
- SAM_PART_IS_DEFINED(SAM4CMP32C_0) \
- )
-
-#define SAM4CMP32_1 ( \
- SAM_PART_IS_DEFINED(SAM4CMP32C_1) \
- )
-
-#define SAM4CMP32 (SAM4CMP32_0 || SAM4CMP32_1)
-
-#define SAM4CMS4_0 ( \
- SAM_PART_IS_DEFINED(SAM4CMS4C_0) \
- )
-
-#define SAM4CMS4_1 ( \
- SAM_PART_IS_DEFINED(SAM4CMS4C_1) \
- )
-
-#define SAM4CMS4 (SAM4CMS4_0 || SAM4CMS4_1)
-
-#define SAM4CMS8_0 ( \
- SAM_PART_IS_DEFINED(SAM4CMS8C_0) \
- )
-
-#define SAM4CMS8_1 ( \
- SAM_PART_IS_DEFINED(SAM4CMS8C_1) \
- )
-
-#define SAM4CMS8 (SAM4CMS8_0 || SAM4CMS8_1)
-
-#define SAM4CMS16_0 ( \
- SAM_PART_IS_DEFINED(SAM4CMS16C_0) \
- )
-
-#define SAM4CMS16_1 ( \
- SAM_PART_IS_DEFINED(SAM4CMS16C_1) \
- )
-
-#define SAM4CMS16 (SAM4CMS16_0 || SAM4CMS16_1)
-
-#define SAM4CMS32_0 ( \
- SAM_PART_IS_DEFINED(SAM4CMS32C_0) \
- )
-
-#define SAM4CMS32_1 ( \
- SAM_PART_IS_DEFINED(SAM4CMS32C_1) \
- )
-
-#define SAM4CMS32 (SAM4CMS32_0 || SAM4CMS32_1)
-
-/** @} */
-
-/**
- * \name SAM4CP series
- * @{
- */
-#define SAM4CP16_0 ( \
- SAM_PART_IS_DEFINED(SAM4CP16B_0) \
- )
-
-#define SAM4CP16_1 ( \
- SAM_PART_IS_DEFINED(SAM4CP16B_1) \
- )
-
-#define SAM4CP16 (SAM4CP16_0 || SAM4CP16_1)
-/** @} */
-
-/**
- * \name SAMG series
- * @{
- */
-#define SAMG51 ( \
- SAM_PART_IS_DEFINED(SAMG51G18) \
- )
-
-#define SAMG53 ( \
- SAM_PART_IS_DEFINED(SAMG53G19) ||\
- SAM_PART_IS_DEFINED(SAMG53N19) \
- )
-
-#define SAMG54 ( \
- SAM_PART_IS_DEFINED(SAMG54G19) ||\
- SAM_PART_IS_DEFINED(SAMG54J19) ||\
- SAM_PART_IS_DEFINED(SAMG54N19) \
- )
-
-#define SAMG55 ( \
- SAM_PART_IS_DEFINED(SAMG55G18) ||\
- SAM_PART_IS_DEFINED(SAMG55G19) ||\
- SAM_PART_IS_DEFINED(SAMG55J18) ||\
- SAM_PART_IS_DEFINED(SAMG55J19) ||\
- SAM_PART_IS_DEFINED(SAMG55N19) \
- )
-/** @} */
-
-/**
- * \name SAMV71 series
- * @{
- */
-#define SAMV71J ( \
- SAM_PART_IS_DEFINED(SAMV71J19) || \
- SAM_PART_IS_DEFINED(SAMV71J20) || \
- SAM_PART_IS_DEFINED(SAMV71J21) \
- )
-
-#define SAMV71N ( \
- SAM_PART_IS_DEFINED(SAMV71N19) || \
- SAM_PART_IS_DEFINED(SAMV71N20) || \
- SAM_PART_IS_DEFINED(SAMV71N21) \
- )
-
-#define SAMV71Q ( \
- SAM_PART_IS_DEFINED(SAMV71Q19) || \
- SAM_PART_IS_DEFINED(SAMV71Q20) || \
- SAM_PART_IS_DEFINED(SAMV71Q21) \
- )
-/** @} */
-
-/**
- * \name SAMV70 series
- * @{
- */
-#define SAMV70J ( \
- SAM_PART_IS_DEFINED(SAMV70J19) || \
- SAM_PART_IS_DEFINED(SAMV70J20) \
- )
-
-#define SAMV70N ( \
- SAM_PART_IS_DEFINED(SAMV70N19) || \
- SAM_PART_IS_DEFINED(SAMV70N20) \
- )
-
-#define SAMV70Q ( \
- SAM_PART_IS_DEFINED(SAMV70Q19) || \
- SAM_PART_IS_DEFINED(SAMV70Q20) \
- )
-/** @} */
-
-/**
- * \name SAMS70 series
- * @{
- */
-#define SAMS70J ( \
- SAM_PART_IS_DEFINED(SAMS70J19) || \
- SAM_PART_IS_DEFINED(SAMS70J20) || \
- SAM_PART_IS_DEFINED(SAMS70J21) \
- )
-
-#define SAMS70N ( \
- SAM_PART_IS_DEFINED(SAMS70N19) || \
- SAM_PART_IS_DEFINED(SAMS70N20) || \
- SAM_PART_IS_DEFINED(SAMS70N21) \
- )
-
-#define SAMS70Q ( \
- SAM_PART_IS_DEFINED(SAMS70Q19) || \
- SAM_PART_IS_DEFINED(SAMS70Q20) || \
- SAM_PART_IS_DEFINED(SAMS70Q21) \
- )
-/** @} */
-
-/**
- * \name SAME70 series
- * @{
- */
-#define SAME70J ( \
- SAM_PART_IS_DEFINED(SAME70J19) || \
- SAM_PART_IS_DEFINED(SAME70J20) || \
- SAM_PART_IS_DEFINED(SAME70J21) \
- )
-
-#define SAME70N ( \
- SAM_PART_IS_DEFINED(SAME70N19) || \
- SAM_PART_IS_DEFINED(SAME70N20) || \
- SAM_PART_IS_DEFINED(SAME70N21) \
- )
-
-#define SAME70Q ( \
- SAM_PART_IS_DEFINED(SAME70Q19) || \
- SAM_PART_IS_DEFINED(SAME70Q20) || \
- SAM_PART_IS_DEFINED(SAME70Q21) \
- )
-/** @} */
-
-/**
- * \name SAM families
- * @{
- */
-/** SAM3S Family */
-#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8)
-
-/** SAM3U Family */
-#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4)
-
-/** SAM3N Family */
-#define SAM3N (SAM3N00 || SAM3N0 || SAM3N1 || SAM3N2 || SAM3N4)
-
-/** SAM3XA Family */
-#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8)
-
-/** SAM4S Family */
-#define SAM4S (SAM4S2 || SAM4S4 || SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32)
-
-/** SAM4L Family */
-#define SAM4L (SAM4LS || SAM4LC)
-
-/** SAMD20 Family */
-#define SAMD20 (SAMD20J || SAMD20G || SAMD20E)
-
-/** SAMD21 Family */
-#define SAMD21 (SAMD21J || SAMD21G || SAMD21E)
-
-/** SAMD09 Family */
-#define SAMD09 (SAMD09C || SAMD09D)
-
-/** SAMD10 Family */
-#define SAMD10 (SAMD10C || SAMD10DS || SAMD10DM || SAMD10DU)
-
-/** SAMD11 Family */
-#define SAMD11 (SAMD11C || SAMD11DS || SAMD11DM || SAMD11DU)
-
-/** SAMDA1 Family */
-#define SAMDA1 (SAMDA1J || SAMDA1G || SAMDA1E)
-
-/** SAMHA1 Family */
-#define SAMHA1 (SAMHA1G)
-
-/** SAMD Family */
-#define SAMD (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAMDA1)
-
-/** SAMR21 Family */
-#define SAMR21 (SAMR21G || SAMR21E)
-
-/** SAMR30 Family */
-#define SAMR30 (SAMR30G || SAMR30E)
-
-/** SAMB11 Family */
-#define SAMB11 (SAMB11G || BTLC1000)
-
-/** SAML21 Family */
-#define SAML21 (SAML21J || SAML21G || SAML21E)
-
-/** SAML22 Family */
-#define SAML22 (SAML22J || SAML22G || SAML22N)
-/** SAMC20 Family */
-#define SAMC20 (SAMC20J || SAMC20G || SAMC20E)
-
-/** SAMC21 Family */
-#define SAMC21 (SAMC21J || SAMC21G || SAMC21E)
-
-/** SAM4E Family */
-#define SAM4E (SAM4E8 || SAM4E16)
-
-/** SAM4N Family */
-#define SAM4N (SAM4N8 || SAM4N16)
-
-/** SAM4C Family */
-#define SAM4C_0 (SAM4C4_0 || SAM4C8_0 || SAM4C16_0 || SAM4C32_0)
-#define SAM4C_1 (SAM4C4_1 || SAM4C8_1 || SAM4C16_1 || SAM4C32_1)
-#define SAM4C (SAM4C4 || SAM4C8 || SAM4C16 || SAM4C32)
-
-/** SAM4CM Family */
-#define SAM4CM_0 (SAM4CMP8_0 || SAM4CMP16_0 || SAM4CMP32_0 || \
- SAM4CMS4_0 || SAM4CMS8_0 || SAM4CMS16_0 || SAM4CMS32_0)
-#define SAM4CM_1 (SAM4CMP8_1 || SAM4CMP16_1 || SAM4CMP32_1 || \
- SAM4CMS4_1 || SAM4CMS8_1 || SAM4CMS16_1 || SAM4CMS32_1)
-#define SAM4CM (SAM4CMP8 || SAM4CMP16 || SAM4CMP32 || \
- SAM4CMS4 || SAM4CMS8 || SAM4CMS16 || SAM4CMS32)
-
-/** SAM4CP Family */
-#define SAM4CP_0 (SAM4CP16_0)
-#define SAM4CP_1 (SAM4CP16_1)
-#define SAM4CP (SAM4CP16)
-
-/** SAMG Family */
-#define SAMG (SAMG51 || SAMG53 || SAMG54 || SAMG55)
-
-/** SAMB Family */
-#define SAMB (SAMB11)
-
-/** SAMV71 Family */
-#define SAMV71 (SAMV71J || SAMV71N || SAMV71Q)
-
-/** SAMV70 Family */
-#define SAMV70 (SAMV70J || SAMV70N || SAMV70Q)
-
-/** SAME70 Family */
-#define SAME70 (SAME70J || SAME70N || SAME70Q)
-
-/** SAMS70 Family */
-#define SAMS70 (SAMS70J || SAMS70N || SAMS70Q)
-
-/** SAM0 product line (cortex-m0+) */
-#define SAM0 (SAMD20 || SAMD21 || SAMR21 || SAMD10 || SAMD11 || SAML21 ||\
- SAMDA1 || SAMC20 || SAMC21 || SAML22 || SAMD09 || SAMR30 || SAMHA1)
-
-/** @} */
-
-/** SAM product line */
-#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || \
- SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAME70 || SAMS70)
-
-/** @} */
-
-/** @} */
-
-/** @} */
-
-#endif /* ATMEL_PARTS_H */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/pmc.c b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/pmc.c
deleted file mode 100644
index bb330e4..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/pmc.c
+++ /dev/null
@@ -1,1657 +0,0 @@
-/**
- * \file
- *
- * \brief Power Management Controller (PMC) driver for SAM.
- *
- * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include "pmc.h"
-
-#if (SAM3N)
-# define MAX_PERIPH_ID 31
-#elif (SAM3XA)
-# define MAX_PERIPH_ID 44
-#elif (SAM3U)
-# define MAX_PERIPH_ID 29
-#elif (SAM3S || SAM4S)
-# define MAX_PERIPH_ID 34
-#elif (SAM4E)
-# define MAX_PERIPH_ID 47
-#elif (SAMV71)
-# define MAX_PERIPH_ID 63
-#elif (SAMV70)
-# define MAX_PERIPH_ID 63
-#elif (SAME70)
-# define MAX_PERIPH_ID 63
-#elif (SAMS70)
-# define MAX_PERIPH_ID 63
-#elif (SAM4N)
-# define MAX_PERIPH_ID 31
-#elif (SAM4C || SAM4CM || SAM4CP)
-# define MAX_PERIPH_ID 43
-#elif (SAMG51)
-# define MAX_PERIPH_ID 47
-#elif (SAMG53)
-# define MAX_PERIPH_ID 47
-#elif (SAMG54)
-# define MAX_PERIPH_ID 47
-#elif (SAMG55)
-# define MAX_PERIPH_ID 50
-#endif
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-/**
- * \defgroup sam_drivers_pmc_group Power Management Controller (PMC)
- *
- * \par Purpose
- *
- * The Power Management Controller (PMC) optimizes power consumption by
- * controlling all system and user peripheral clocks. The PMC enables/disables
- * the clock inputs to many of the peripherals and the Cortex-M Processor.
- *
- * @{
- */
-
-/**
- * \brief Set the prescaler of the MCK.
- *
- * \param ul_pres Prescaler value.
- */
-void pmc_mck_set_prescaler(uint32_t ul_pres)
-{
- PMC->PMC_MCKR =
- (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-}
-
-#if SAMV71 || SAMV70 || SAME70 || SAMS70
-/**
- * \brief Set the division of the MCK.
- *
- * \param ul_div Division value.
- */
-void pmc_mck_set_division(uint32_t ul_div)
-{
- switch (ul_div) {
- case 1:
- ul_div = PMC_MCKR_MDIV_EQ_PCK;
- break;
- case 2:
- ul_div = PMC_MCKR_MDIV_PCK_DIV2;
- break;
- case 3:
- ul_div = PMC_MCKR_MDIV_PCK_DIV3;
- break;
- case 4:
- ul_div = PMC_MCKR_MDIV_PCK_DIV4;
- break;
- default:
- ul_div = PMC_MCKR_MDIV_EQ_PCK;
- break;
- }
- PMC->PMC_MCKR =
- (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | ul_div;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-}
-#endif
-
-/**
- * \brief Set the source of the MCK.
- *
- * \param ul_source Source selection value.
- */
-void pmc_mck_set_source(uint32_t ul_source)
-{
- PMC->PMC_MCKR =
- (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-}
-
-/**
- * \brief Switch master clock source selection to slow clock.
- *
- * \param ul_pres Processor clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
- PMC_MCKR_CSS_SLOW_CLK;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-
-/**
- * \brief Switch master clock source selection to main clock.
- *
- * \param ul_pres Processor clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
- PMC_MCKR_CSS_MAIN_CLK;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-
-/**
- * \brief Switch master clock source selection to PLLA clock.
- *
- * \param ul_pres Processor clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
- PMC_MCKR_CSS_PLLA_CLK;
-
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
-/**
- * \brief Switch master clock source selection to PLLB clock.
- *
- * \param ul_pres Processor clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
- PMC_MCKR_CSS_PLLB_CLK;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-#endif
-
-#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Switch master clock source selection to UPLL clock.
- *
- * \param ul_pres Processor clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
- PMC_MCKR_CSS_UPLL_CLK;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-#endif
-
-/**
- * \brief Switch slow clock source selection to external 32k (Xtal or Bypass).
- *
- * \note Switching SCLK back to 32krc is only possible by shutting down the
- * VDDIO power supply.
- *
- * \param ul_bypass 0 for Xtal, 1 for bypass.
- */
-void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass)
-{
- /* Set Bypass mode if required */
- if (ul_bypass == 1) {
- SUPC->SUPC_MR |= SUPC_MR_KEY_PASSWD |
- SUPC_MR_OSCBYPASS;
- }
-
- SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL;
-}
-
-/**
- * \brief Check if the external 32k Xtal is ready.
- *
- * \retval 1 External 32k Xtal is ready.
- * \retval 0 External 32k Xtal is not ready.
- */
-uint32_t pmc_osc_is_ready_32kxtal(void)
-{
- return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL)
- && (PMC->PMC_SR & PMC_SR_OSCSELS));
-}
-
-/**
- * \brief Switch main clock source selection to internal fast RC.
- *
- * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz).
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- * \retval 2 Invalid frequency.
- */
-void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf)
-{
- /* Enable Fast RC oscillator but DO NOT switch to RC now */
- PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
-
- /* Wait the Fast RC to stabilize */
- while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
-
- /* Change Fast RC oscillator frequency */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
- CKGR_MOR_KEY_PASSWD | ul_moscrcf;
-
- /* Wait the Fast RC to stabilize */
- while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
-
- /* Switch to Fast RC */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) |
- CKGR_MOR_KEY_PASSWD;
-}
-
-/**
- * \brief Enable fast RC oscillator.
- *
- * \param ul_rc Fast RC oscillator(4/8/12Mhz).
- */
-void pmc_osc_enable_fastrc(uint32_t ul_rc)
-{
- /* Enable Fast RC oscillator but DO NOT switch to RC */
- PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
- /* Wait the Fast RC to stabilize */
- while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
-
- /* Change Fast RC oscillator frequency */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
- CKGR_MOR_KEY_PASSWD | ul_rc;
- /* Wait the Fast RC to stabilize */
- while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
-}
-
-/**
- * \brief Disable the internal fast RC.
- */
-void pmc_osc_disable_fastrc(void)
-{
- /* Disable Fast RC oscillator */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN &
- ~CKGR_MOR_MOSCRCF_Msk)
- | CKGR_MOR_KEY_PASSWD;
-}
-
-/**
- * \brief Check if the main fastrc is ready.
- *
- * \retval 0 Xtal is not ready, otherwise ready.
- */
-uint32_t pmc_osc_is_ready_fastrc(void)
-{
- return (PMC->PMC_SR & PMC_SR_MOSCRCS);
-}
-
-/**
- * \brief Enable main XTAL oscillator.
- *
- * \param ul_xtal_startup_time Xtal start-up time, in number of slow clocks.
- */
-void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time)
-{
- uint32_t mor = PMC->CKGR_MOR;
- mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
- mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN |
- CKGR_MOR_MOSCXTST(ul_xtal_startup_time);
- PMC->CKGR_MOR = mor;
- /* Wait the main Xtal to stabilize */
- while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
-}
-
-/**
- * \brief Bypass main XTAL.
- */
-void pmc_osc_bypass_main_xtal(void)
-{
- uint32_t mor = PMC->CKGR_MOR;
- mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
- mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY;
- /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */
- PMC->CKGR_MOR = mor;
- /* The MOSCXTS in PMC_SR is automatically set */
-}
-
-/**
- * \brief Disable the main Xtal.
- */
-void pmc_osc_disable_main_xtal(void)
-{
- uint32_t mor = PMC->CKGR_MOR;
- mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
-}
-
-/**
- * \brief Check if the main crystal is bypassed.
- *
- * \retval 0 Xtal is bypassed, otherwise not.
- */
-uint32_t pmc_osc_is_bypassed_main_xtal(void)
-{
- return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY);
-}
-
-/**
- * \brief Check if the main crystal is ready.
- *
- * \note If main crystal is bypassed, it's always ready.
- *
- * \retval 0 main crystal is not ready, otherwise ready.
- */
-uint32_t pmc_osc_is_ready_main_xtal(void)
-{
- return (PMC->PMC_SR & PMC_SR_MOSCXTS);
-}
-
-/**
- * \brief Switch main clock source selection to external Xtal/Bypass.
- *
- * \note The function may switch MCK to SCLK if MCK source is MAINCK to avoid
- * any system crash.
- *
- * \note If used in Xtal mode, the Xtal is automatically enabled.
- *
- * \param ul_bypass 0 for Xtal, 1 for bypass.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-void pmc_switch_mainck_to_xtal(uint32_t ul_bypass,
- uint32_t ul_xtal_startup_time)
-{
- /* Enable Main Xtal oscillator */
- if (ul_bypass) {
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
- CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY |
- CKGR_MOR_MOSCSEL;
- } else {
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
- CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN |
- CKGR_MOR_MOSCXTST(ul_xtal_startup_time);
- /* Wait the Xtal to stabilize */
- while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
-
- PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;
- }
-}
-
-/**
- * \brief Disable the external Xtal.
- *
- * \param ul_bypass 0 for Xtal, 1 for bypass.
- */
-void pmc_osc_disable_xtal(uint32_t ul_bypass)
-{
- /* Disable xtal oscillator */
- if (ul_bypass) {
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
- CKGR_MOR_KEY_PASSWD;
- } else {
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
- CKGR_MOR_KEY_PASSWD;
- }
-}
-
-/**
- * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one
- * of Xtal, bypass or internal RC.
- *
- * \retval 1 Xtal is ready.
- * \retval 0 Xtal is not ready.
- */
-uint32_t pmc_osc_is_ready_mainck(void)
-{
- return PMC->PMC_SR & PMC_SR_MOSCSELS;
-}
-
-/**
- * \brief Select Main Crystal or internal RC as main clock source.
- *
- * \note This function will not enable/disable RC or Main Crystal.
- *
- * \param ul_xtal_rc 0 internal RC is selected, otherwise Main Crystal.
- */
-void pmc_mainck_osc_select(uint32_t ul_xtal_rc)
-{
- uint32_t mor = PMC->CKGR_MOR;
- if (ul_xtal_rc) {
- mor |= CKGR_MOR_MOSCSEL;
- } else {
- mor &= ~CKGR_MOR_MOSCSEL;
- }
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
-}
-
-/**
- * \brief Enable PLLA clock.
- *
- * \param mula PLLA multiplier.
- * \param pllacount PLLA counter.
- * \param diva Divider.
- */
-void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)
-{
- /* first disable the PLL to unlock the lock */
- pmc_disable_pllack();
-
-#if (SAM4C || SAM4CM || SAM4CP || SAMG)
- PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(diva) |
- CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
-#else
- PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) |
- CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
-#endif
- while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0);
-}
-
-/**
- * \brief Disable PLLA clock.
- */
-void pmc_disable_pllack(void)
-{
-#if (SAM4C || SAM4CM || SAM4CP || SAMG)
- PMC->CKGR_PLLAR = CKGR_PLLAR_MULA(0);
-#else
- PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);
-#endif
-}
-
-/**
- * \brief Is PLLA locked?
- *
- * \retval 0 Not locked.
- * \retval 1 Locked.
- */
-uint32_t pmc_is_locked_pllack(void)
-{
- return (PMC->PMC_SR & PMC_SR_LOCKA);
-}
-
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
-/**
- * \brief Enable PLLB clock.
- *
- * \param mulb PLLB multiplier.
- * \param pllbcount PLLB counter.
- * \param divb Divider.
- */
-void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb)
-{
- /* first disable the PLL to unlock the lock */
- pmc_disable_pllbck();
-
-#if SAMG55
- PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(divb) |
- CKGR_PLLAR_PLLACOUNT(pllbcount) | CKGR_PLLAR_MULA(mulb);
-#else
- PMC->CKGR_PLLBR =
- CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount)
- | CKGR_PLLBR_MULB(mulb);
-#endif
- while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0);
-}
-
-/**
- * \brief Disable PLLB clock.
- */
-void pmc_disable_pllbck(void)
-{
- PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);
-}
-
-/**
- * \brief Is PLLB locked?
- *
- * \retval 0 Not locked.
- * \retval 1 Locked.
- */
-uint32_t pmc_is_locked_pllbck(void)
-{
- return (PMC->PMC_SR & PMC_SR_LOCKB);
-}
-#endif
-
-#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Enable UPLL clock.
- */
-void pmc_enable_upll_clock(void)
-{
- PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN;
-
- /* Wait UTMI PLL Lock Status */
- while (!(PMC->PMC_SR & PMC_SR_LOCKU));
-}
-
-/**
- * \brief Disable UPLL clock.
- */
-void pmc_disable_upll_clock(void)
-{
- PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
-}
-
-/**
- * \brief Is UPLL locked?
- *
- * \retval 0 Not locked.
- * \retval 1 Locked.
- */
-uint32_t pmc_is_locked_upll(void)
-{
- return (PMC->PMC_SR & PMC_SR_LOCKU);
-}
-#endif
-
-/**
- * \brief Enable the specified peripheral clock.
- *
- * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
- *
- * \param ul_id Peripheral ID (ID_xxx).
- *
- * \retval 0 Success.
- * \retval 1 Invalid parameter.
- */
-uint32_t pmc_enable_periph_clk(uint32_t ul_id)
-{
- if (ul_id > MAX_PERIPH_ID) {
- return 1;
- }
-
- if (ul_id < 32) {
- if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) {
- PMC->PMC_PCER0 = 1 << ul_id;
- }
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
- } else {
- ul_id -= 32;
- if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) {
- PMC->PMC_PCER1 = 1 << ul_id;
- }
-#endif
- }
-
- return 0;
-}
-
-/**
- * \brief Disable the specified peripheral clock.
- *
- * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
- *
- * \param ul_id Peripheral ID (ID_xxx).
- *
- * \retval 0 Success.
- * \retval 1 Invalid parameter.
- */
-uint32_t pmc_disable_periph_clk(uint32_t ul_id)
-{
- if (ul_id > MAX_PERIPH_ID) {
- return 1;
- }
-
- if (ul_id < 32) {
- if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) {
- PMC->PMC_PCDR0 = 1 << ul_id;
- }
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 \
- || SAMV70 || SAME70 || SAMS70)
- } else {
- ul_id -= 32;
- if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) {
- PMC->PMC_PCDR1 = 1 << ul_id;
- }
-#endif
- }
- return 0;
-}
-
-/**
- * \brief Enable all peripheral clocks.
- */
-void pmc_enable_all_periph_clk(void)
-{
- PMC->PMC_PCER0 = PMC_MASK_STATUS0;
- while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0);
-
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
- || SAMV70 || SAME70 || SAMS70)
- PMC->PMC_PCER1 = PMC_MASK_STATUS1;
- while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1);
-#endif
-}
-
-/**
- * \brief Disable all peripheral clocks.
- */
-void pmc_disable_all_periph_clk(void)
-{
- PMC->PMC_PCDR0 = PMC_MASK_STATUS0;
- while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0);
-
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
- || SAMV70 || SAME70 || SAMS70)
- PMC->PMC_PCDR1 = PMC_MASK_STATUS1;
- while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0);
-#endif
-}
-
-/**
- * \brief Check if the specified peripheral clock is enabled.
- *
- * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
- *
- * \param ul_id Peripheral ID (ID_xxx).
- *
- * \retval 0 Peripheral clock is disabled or unknown.
- * \retval 1 Peripheral clock is enabled.
- */
-uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id)
-{
- if (ul_id > MAX_PERIPH_ID) {
- return 0;
- }
-
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
- || SAMV70 || SAME70 || SAMS70)
- if (ul_id < 32) {
-#endif
- if ((PMC->PMC_PCSR0 & (1u << ul_id))) {
- return 1;
- } else {
- return 0;
- }
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
- || SAMV70 || SAME70 || SAMS70)
- } else {
- ul_id -= 32;
- if ((PMC->PMC_PCSR1 & (1u << ul_id))) {
- return 1;
- } else {
- return 0;
- }
- }
-#endif
-}
-
-/**
- * \brief Set the prescaler for the specified programmable clock.
- *
- * \param ul_id Peripheral ID.
- * \param ul_pres Prescaler value.
- */
-void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres)
-{
- PMC->PMC_PCK[ul_id] =
- (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres;
- while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
- && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
-}
-
-/**
- * \brief Set the source oscillator for the specified programmable clock.
- *
- * \param ul_id Peripheral ID.
- * \param ul_source Source selection value.
- */
-void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source)
-{
- PMC->PMC_PCK[ul_id] =
- (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source;
- while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
- && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
-}
-
-/**
- * \brief Switch programmable clock source selection to slow clock.
- *
- * \param ul_id Id of the programmable clock.
- * \param ul_pres Programmable clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres;
- for (ul_timeout = PMC_TIMEOUT;
- !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-
-/**
- * \brief Switch programmable clock source selection to main clock.
- *
- * \param ul_id Id of the programmable clock.
- * \param ul_pres Programmable clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres;
- for (ul_timeout = PMC_TIMEOUT;
- !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-
-/**
- * \brief Switch programmable clock source selection to PLLA clock.
- *
- * \param ul_id Id of the programmable clock.
- * \param ul_pres Programmable clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres;
- for (ul_timeout = PMC_TIMEOUT;
- !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
-/**
- * \brief Switch programmable clock source selection to PLLB clock.
- *
- * \param ul_id Id of the programmable clock.
- * \param ul_pres Programmable clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres;
- for (ul_timeout = PMC_TIMEOUT;
- !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-#endif
-
-#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Switch programmable clock source selection to UPLL clock.
- *
- * \param ul_id Id of the programmable clock.
- * \param ul_pres Programmable clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres;
- for (ul_timeout = PMC_TIMEOUT;
- !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-#endif
-
-/**
- * \brief Switch programmable clock source selection to mck.
- *
- * \param ul_id Id of the programmable clock.
- * \param ul_pres Programmable clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MCK | ul_pres;
- for (ul_timeout = PMC_TIMEOUT;
- !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-
-/**
- * \brief Enable the specified programmable clock.
- *
- * \param ul_id Id of the programmable clock.
- */
-void pmc_enable_pck(uint32_t ul_id)
-{
- PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id;
-}
-
-/**
- * \brief Disable the specified programmable clock.
- *
- * \param ul_id Id of the programmable clock.
- */
-void pmc_disable_pck(uint32_t ul_id)
-{
- PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id;
-}
-
-/**
- * \brief Enable all programmable clocks.
- */
-void pmc_enable_all_pck(void)
-{
- PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2;
-}
-
-/**
- * \brief Disable all programmable clocks.
- */
-void pmc_disable_all_pck(void)
-{
- PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2;
-}
-
-/**
- * \brief Check if the specified programmable clock is enabled.
- *
- * \param ul_id Id of the programmable clock.
- *
- * \retval 0 Programmable clock is disabled or unknown.
- * \retval 1 Programmable clock is enabled.
- */
-uint32_t pmc_is_pck_enabled(uint32_t ul_id)
-{
- if (ul_id > 2) {
- return 0;
- }
-
- return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id));
-}
-
-#if (SAM4C || SAM4CM || SAM4CP)
-/**
- * \brief Enable Coprocessor Clocks.
- */
-void pmc_enable_cpck(void)
-{
- PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD;
-}
-
-/**
- * \brief Disable Coprocessor Clocks.
- */
-void pmc_disable_cpck(void)
-{
- PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD;
-}
-
-/**
- * \brief Check if the Coprocessor Clocks is enabled.
- *
- * \retval 0 Coprocessor Clocks is disabled.
- * \retval 1 Coprocessor Clocks is enabled.
- */
-bool pmc_is_cpck_enabled(void)
-{
- if(PMC->PMC_SCSR & PMC_SCSR_CPCK) {
- return 1;
- } else {
- return 0;
- }
-}
-
-/**
- * \brief Enable Coprocessor Bus Master Clocks.
- */
-void pmc_enable_cpbmck(void)
-{
- PMC->PMC_SCER = PMC_SCER_CPBMCK | PMC_SCER_CPKEY_PASSWD;
-}
-
-/**
- * \brief Disable Coprocessor Bus Master Clocks.
- */
-void pmc_disable_cpbmck(void)
-{
- PMC->PMC_SCDR = PMC_SCDR_CPBMCK | PMC_SCDR_CPKEY_PASSWD;
-}
-
-/**
- * \brief Check if the Coprocessor Bus Master Clocks is enabled.
- *
- * \retval 0 Coprocessor Bus Master Clocks is disabled.
- * \retval 1 Coprocessor Bus Master Clocks is enabled.
- */
-bool pmc_is_cpbmck_enabled(void)
-{
- if(PMC->PMC_SCSR & PMC_SCSR_CPBMCK) {
- return 1;
- } else {
- return 0;
- }
-}
-
-/**
- * \brief Set the prescaler for the Coprocessor Master Clock.
- *
- * \param ul_pres Prescaler value.
- */
-void pmc_cpck_set_prescaler(uint32_t ul_pres)
-{
- PMC->PMC_MCKR =
- (PMC->PMC_MCKR & (~PMC_MCKR_CPPRES_Msk)) | PMC_MCKR_CPPRES(ul_pres);
-}
-
-/**
- * \brief Set the source for the Coprocessor Master Clock.
- *
- * \param ul_source Source selection value.
- */
-void pmc_cpck_set_source(uint32_t ul_source)
-{
- PMC->PMC_MCKR =
- (PMC->PMC_MCKR & (~PMC_MCKR_CPCSS_Msk)) | ul_source;
-}
-#endif
-
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Switch UDP (USB) clock source selection to PLLA clock.
- *
- * \param ul_usbdiv Clock divisor.
- */
-void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv)
-{
- PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
-}
-#endif
-
-#if (SAM3S || SAM4S || SAMG55)
-/**
- * \brief Switch UDP (USB) clock source selection to PLLB clock.
- *
- * \param ul_usbdiv Clock divisor.
- */
-void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv)
-{
- PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
-}
-#endif
-
-#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Switch UDP (USB) clock source selection to UPLL clock.
- *
- * \param ul_usbdiv Clock divisor.
- */
-void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv)
-{
- PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv);
-}
-#endif
-
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Enable UDP (USB) clock.
- */
-void pmc_enable_udpck(void)
-{
-#if (SAM3S || SAM4S || SAM4E || SAMG55)
- PMC->PMC_SCER = PMC_SCER_UDP;
-#elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
- PMC->PMC_SCER = PMC_SCER_USBCLK;
-#else
- PMC->PMC_SCER = PMC_SCER_UOTGCLK;
-# endif
-}
-
-/**
- * \brief Disable UDP (USB) clock.
- */
-void pmc_disable_udpck(void)
-{
-#if (SAM3S || SAM4S || SAM4E || SAMG55)
- PMC->PMC_SCDR = PMC_SCDR_UDP;
-#elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
- PMC->PMC_SCDR = PMC_SCDR_USBCLK;
-#else
- PMC->PMC_SCDR = PMC_SCDR_UOTGCLK;
-# endif
-}
-#endif
-
-#if SAMG55
-/**
- * \brief Switch UHP (USB) clock source selection to PLLA clock.
- *
- * \param ul_usbdiv Clock divisor.
- */
-void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv)
-{
- PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
-}
-
-/**
- * \brief Switch UHP (USB) clock source selection to PLLB clock.
- *
- * \param ul_usbdiv Clock divisor.
- */
-void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv)
-{
- PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
-}
-
-/**
- * \brief Enable UHP (USB) clock.
- */
-void pmc_enable_uhpck(void)
-{
- PMC->PMC_SCER = PMC_SCER_UHP;
-}
-#endif
-
-/**
- * \brief Enable PMC interrupts.
- *
- * \param ul_sources Interrupt sources bit map.
- */
-void pmc_enable_interrupt(uint32_t ul_sources)
-{
- PMC->PMC_IER = ul_sources;
-}
-
-/**
- * \brief Disable PMC interrupts.
- *
- * \param ul_sources Interrupt sources bit map.
- */
-void pmc_disable_interrupt(uint32_t ul_sources)
-{
- PMC->PMC_IDR = ul_sources;
-}
-
-/**
- * \brief Get PMC interrupt mask.
- *
- * \return The interrupt mask value.
- */
-uint32_t pmc_get_interrupt_mask(void)
-{
- return PMC->PMC_IMR;
-}
-
-/**
- * \brief Get current status.
- *
- * \return The current PMC status.
- */
-uint32_t pmc_get_status(void)
-{
- return PMC->PMC_SR;
-}
-
-/**
- * \brief Set the wake-up inputs for fast startup mode registers
- * (event generation).
- *
- * \param ul_inputs Wake up inputs to enable.
- */
-void pmc_set_fast_startup_input(uint32_t ul_inputs)
-{
- ul_inputs &= PMC_FAST_STARTUP_Msk;
- PMC->PMC_FSMR |= ul_inputs;
-}
-
-/**
- * \brief Clear the wake-up inputs for fast startup mode registers
- * (remove event generation).
- *
- * \param ul_inputs Wake up inputs to disable.
- */
-void pmc_clr_fast_startup_input(uint32_t ul_inputs)
-{
- ul_inputs &= PMC_FAST_STARTUP_Msk;
- PMC->PMC_FSMR &= ~ul_inputs;
-}
-
-#if (SAM4C || SAM4CM || SAM4CP)
-/**
- * \brief Set the wake-up inputs of coprocessor for fast startup mode registers
- * (event generation).
- *
- * \param ul_inputs Wake up inputs to enable.
- */
-void pmc_cp_set_fast_startup_input(uint32_t ul_inputs)
-{
- ul_inputs &= PMC_FAST_STARTUP_Msk;
- PMC->PMC_CPFSMR |= ul_inputs;
-}
-
-/**
- * \brief Clear the wake-up inputs of coprocessor for fast startup mode registers
- * (remove event generation).
- *
- * \param ul_inputs Wake up inputs to disable.
- */
-void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs)
-{
- ul_inputs &= PMC_FAST_STARTUP_Msk;
- PMC->PMC_CPFSMR &= ~ul_inputs;
-}
-#endif
-
-/**
- * \brief Enable Sleep Mode.
- * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0)
- *
- * \param uc_type 0 for wait for interrupt, 1 for wait for event.
- * \note For SAM4S, SAM4C, SAM4CM, SAM4CP, SAMV71 and SAM4E series,
- * since only WFI is effective, uc_type = 1 will be treated as uc_type = 0.
- */
-void pmc_enable_sleepmode(uint8_t uc_type)
-{
-#if !(SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
- PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode
-#endif
- SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep
-
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
- UNUSED(uc_type);
- __DSB();
- __WFI();
-#else
- if (uc_type == 0) {
- __DSB();
- __WFI();
- } else {
- __DSB();
- __WFE();
- }
-#endif
-}
-
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
-static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN;
-/**
- * \brief Set the embedded flash state in wait mode
- *
- * \param ul_flash_state PMC_WAIT_MODE_FLASH_STANDBY flash in standby mode,
- * PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN flash in deep power down mode.
- */
-void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state)
-{
- ul_flash_in_wait_mode = ul_flash_state;
-}
-
-/**
- * \brief Enable Wait Mode. Enter condition: (WAITMODE bit = 1) + FLPM
- *
- * \note In this function, FLPM will retain, WAITMODE bit will be set,
- * Generally, this function will be called by pmc_sleep() in order to
- * complete all sequence entering wait mode.
- * See \ref pmc_sleep() for entering different sleep modes.
- */
-void pmc_enable_waitmode(void)
-{
- uint32_t i;
-
- /* Flash in wait mode */
- i = PMC->PMC_FSMR;
- i &= ~PMC_FSMR_FLPM_Msk;
-#if !(SAMV71 || SAMV70 || SAME70 || SAMS70)
- i |= ul_flash_in_wait_mode;
-#else
- i |= PMC_WAIT_MODE_FLASH_IDLE;
-#endif
- PMC->PMC_FSMR = i;
-
- /* Set the WAITMODE bit = 1 */
- PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_WAITMODE;
-
- /* Waiting for Master Clock Ready MCKRDY = 1 */
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-
- /* Waiting for MOSCRCEN bit cleared is strongly recommended
- * to ensure that the core will not execute undesired instructions
- */
- for (i = 0; i < 500; i++) {
- __NOP();
- }
- while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));
-
-#if (!SAMG)
- /* Restore Flash in idle mode */
- i = PMC->PMC_FSMR;
- i &= ~PMC_FSMR_FLPM_Msk;
- i |= PMC_WAIT_MODE_FLASH_IDLE;
- PMC->PMC_FSMR = i;
-#endif
-}
-#else
-/**
- * \brief Enable Wait Mode. Enter condition: WFE + (SLEEPDEEP bit = 0) +
- * (LPM bit = 1)
- */
-void pmc_enable_waitmode(void)
-{
- uint32_t i;
-
- PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */
- SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */
-
- __DSB();
- __WFE();
-
- /* Waiting for MOSCRCEN bit cleared is strongly recommended
- * to ensure that the core will not execute undesired instructions
- */
- for (i = 0; i < 500; i++) {
- __NOP();
- }
- while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));
-
-}
-#endif
-
-#if (!(SAMG51 || SAMG53 || SAMG54))
-/**
- * \brief Enable Backup Mode. Enter condition: WFE/(VROFF bit = 1) +
- * (SLEEPDEEP bit = 1)
- */
-void pmc_enable_backupmode(void)
-{
-#if (SAM4C || SAM4CM || SAM4CP)
- uint32_t tmp = SUPC->SUPC_MR & ~(SUPC_MR_BUPPOREN | SUPC_MR_KEY_Msk);
- SUPC->SUPC_MR = tmp | SUPC_MR_KEY_PASSWD;
- while (SUPC->SUPC_SR & SUPC_SR_BUPPORS);
-#endif
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
- SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG;
- uint32_t ul_dummy = SUPC->SUPC_MR;
- UNUSED(ul_dummy);
- __DSB();
- __WFE();
- __WFI();
-#else
- __DSB();
- __WFE();
-#endif
-}
-#endif
-
-/**
- * \brief Enable Clock Failure Detector.
- */
-void pmc_enable_clock_failure_detector(void)
-{
- uint32_t ul_reg = PMC->CKGR_MOR;
-
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | ul_reg;
-}
-
-/**
- * \brief Disable Clock Failure Detector.
- */
-void pmc_disable_clock_failure_detector(void)
-{
- uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN);
-
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg;
-}
-
-#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Enable Slow Crystal Oscillator Frequency Monitoring.
- */
-void pmc_enable_sclk_osc_freq_monitor(void)
-{
- uint32_t ul_reg = PMC->CKGR_MOR;
-
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_XT32KFME | ul_reg;
-}
-
-/**
- * \brief Disable Slow Crystal Oscillator Frequency Monitoring.
- */
-void pmc_disable_sclk_osc_freq_monitor(void)
-{
- uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME);
-
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg;
-}
-#endif
-
-/**
- * \brief Enable or disable write protect of PMC registers.
- *
- * \param ul_enable 1 to enable, 0 to disable.
- */
-void pmc_set_writeprotect(uint32_t ul_enable)
-{
- if (ul_enable) {
- PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD | PMC_WPMR_WPEN;
- } else {
- PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD;
- }
-}
-
-/**
- * \brief Return write protect status.
- *
- * \return Return write protect status.
- */
-uint32_t pmc_get_writeprotect_status(void)
-{
- return PMC->PMC_WPSR;
-}
-
-#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Enable the specified peripheral clock.
- *
- * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
- *
- * \param ul_id Peripheral ID (ID_xxx).
- *
- * \retval 0 Success.
- * \retval 1 Fail.
- */
-uint32_t pmc_enable_sleepwalking(uint32_t ul_id)
-{
- uint32_t temp;
-#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
- if ((7 <= ul_id) && (ul_id<= 29)) {
-#else
- if ((8 <= ul_id) && (ul_id<= 29)) {
-#endif
- temp = pmc_get_active_status0();
- if (temp & (1 << ul_id)) {
- return 1;
- }
- PMC->PMC_SLPWK_ER0 = 1 << ul_id;
- temp = pmc_get_active_status0();
- if (temp & (1 << ul_id)) {
- pmc_disable_sleepwalking(ul_id);
- return 1;
- }
- return 0;
- }
-#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
- else if ((32 <= ul_id) && (ul_id<= 60)) {
- ul_id -= 32;
- temp = pmc_get_active_status1();
- if (temp & (1 << ul_id)) {
- return 1;
- }
- PMC->PMC_SLPWK_ER1 = 1 << ul_id;
- temp = pmc_get_active_status1();
- if (temp & (1 << ul_id)) {
- pmc_disable_sleepwalking(ul_id);
- return 1;
- }
- return 0;
- }
-#endif
- else {
- return 1;
- }
-}
-
-/**
- * \brief Disable the sleepwalking of specified peripheral.
- *
- * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
- *
- * \param ul_id Peripheral ID (ID_xxx).
- *
- * \retval 0 Success.
- * \retval 1 Invalid parameter.
- */
-uint32_t pmc_disable_sleepwalking(uint32_t ul_id)
-{
-#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
- if ((7 <= ul_id) && (ul_id<= 29)) {
-#else
- if ((8 <= ul_id) && (ul_id<= 29)) {
-#endif
- PMC->PMC_SLPWK_DR0 = 1 << ul_id;
- return 0;
- }
-#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
- else if ((32 <= ul_id) && (ul_id<= 60)) {
- ul_id -= 32;
- PMC->PMC_SLPWK_DR1 = 1 << ul_id;
- return 0;
- }
-#endif
- else {
- return 1;
- }
-}
-
-/**
- * \brief Return peripheral sleepwalking enable status.
- *
- * \return the status register value.
- */
-uint32_t pmc_get_sleepwalking_status0(void)
-{
- return PMC->PMC_SLPWK_SR0;
-}
-
-/**
- * \brief Return peripheral active status.
- *
- * \return the status register value.
- */
-uint32_t pmc_get_active_status0(void)
-{
- return PMC->PMC_SLPWK_ASR0;
-}
-
-#endif
-
-#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Return peripheral sleepwalking enable status.
- *
- * \return the status register value.
- */
-uint32_t pmc_get_sleepwalking_status1(void)
-{
- return PMC->PMC_SLPWK_SR1;
-}
-
-/**
- * \brief Return peripheral active status.
- *
- * \return the status register value.
- */
-uint32_t pmc_get_active_status1(void)
-{
- return PMC->PMC_SLPWK_ASR1;
-}
-#endif
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/pmc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/pmc.h
deleted file mode 100644
index 497825f..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/pmc.h
+++ /dev/null
@@ -1,550 +0,0 @@
-/**
- * \file
- *
- * \brief Power Management Controller (PMC) driver for SAM.
- *
- * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef PMC_H_INCLUDED
-#define PMC_H_INCLUDED
-
-#include "compiler.h"
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-/** Bit mask for peripheral clocks (PCER0) */
-#define PMC_MASK_STATUS0 (0xFFFFFFFC)
-
-/** Bit mask for peripheral clocks (PCER1) */
-#define PMC_MASK_STATUS1 (0xFFFFFFFF)
-
-/** Loop counter timeout value */
-#if !(SAME70)
-#define PMC_TIMEOUT (2048)
-#else
-#define PMC_TIMEOUT (4096)
-#endif
-
-/** Key to unlock CKGR_MOR register */
-#ifndef CKGR_MOR_KEY_PASSWD
-#define CKGR_MOR_KEY_PASSWD CKGR_MOR_KEY(0x37U)
-#endif
-
-/** Key used to write SUPC registers */
-#ifndef SUPC_CR_KEY_PASSWD
-#define SUPC_CR_KEY_PASSWD SUPC_CR_KEY(0xA5U)
-#endif
-
-#ifndef SUPC_MR_KEY_PASSWD
-#define SUPC_MR_KEY_PASSWD SUPC_MR_KEY(0xA5U)
-#endif
-
-/** Mask to access fast startup input */
-#define PMC_FAST_STARTUP_Msk (0x7FFFFu)
-
-/** PMC_WPMR Write Protect KEY, unlock it */
-#ifndef PMC_WPMR_WPKEY_PASSWD
-#define PMC_WPMR_WPKEY_PASSWD PMC_WPMR_WPKEY((uint32_t) 0x504D43)
-#endif
-
-/** Using external oscillator */
-#define PMC_OSC_XTAL 0
-
-/** Oscillator in bypass mode */
-#define PMC_OSC_BYPASS 1
-
-#define PMC_PCK_0 0 /* PCK0 ID */
-#define PMC_PCK_1 1 /* PCK1 ID */
-#define PMC_PCK_2 2 /* PCK2 ID */
-#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
-#define PMC_PCK_3 3 /* PCK3 ID */
-#define PMC_PCK_4 4 /* PCK4 ID */
-#define PMC_PCK_5 5 /* PCK5 ID */
-#define PMC_PCK_6 6 /* PCK6 ID */
-#if SAMG55
-#define PMC_PCK_7 7 /* PCK7 ID */
-#endif
-#endif
-
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/** Flash state in Wait Mode */
-#define PMC_WAIT_MODE_FLASH_STANDBY PMC_FSMR_FLPM_FLASH_STANDBY
-#define PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN
-#define PMC_WAIT_MODE_FLASH_IDLE PMC_FSMR_FLPM_FLASH_IDLE
-#endif
-
-/** Convert startup time from us to MOSCXTST */
-#define pmc_us_to_moscxtst(startup_us, slowck_freq) \
- ((startup_us * slowck_freq / 8 / 1000000) < 0x100 ? \
- (startup_us * slowck_freq / 8 / 1000000) : 0xFF)
-
-/**
- * \name Master clock (MCK) Source and Prescaler configuration
- *
- * \note The following functions may be used to select the clock source and
- * prescaler for the master clock.
- */
-//@{
-
-void pmc_mck_set_prescaler(uint32_t ul_pres);
-#if SAMV71 || SAMV70 || SAME70 || SAMS70
-void pmc_mck_set_division(uint32_t ul_div);
-#endif
-void pmc_mck_set_source(uint32_t ul_source);
-uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres);
-uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres);
-uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres);
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
-uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres);
-#endif
-#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
-uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres);
-#endif
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
-void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state);
-#endif
-
-
-//@}
-
-/**
- * \name Slow clock (SLCK) oscillator and configuration
- *
- */
-//@{
-
-void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass);
-uint32_t pmc_osc_is_ready_32kxtal(void);
-
-//@}
-
-/**
- * \name Main Clock (MAINCK) oscillator and configuration
- *
- */
-//@{
-
-void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf);
-void pmc_osc_enable_fastrc(uint32_t ul_rc);
-void pmc_osc_disable_fastrc(void);
-uint32_t pmc_osc_is_ready_fastrc(void);
-void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time);
-void pmc_osc_bypass_main_xtal(void);
-void pmc_osc_disable_main_xtal(void);
-uint32_t pmc_osc_is_bypassed_main_xtal(void);
-uint32_t pmc_osc_is_ready_main_xtal(void);
-void pmc_switch_mainck_to_xtal(uint32_t ul_bypass,
- uint32_t ul_xtal_startup_time);
-void pmc_osc_disable_xtal(uint32_t ul_bypass);
-uint32_t pmc_osc_is_ready_mainck(void);
-void pmc_mainck_osc_select(uint32_t ul_xtal_rc);
-
-//@}
-
-/**
- * \name PLL oscillator and configuration
- *
- */
-//@{
-
-void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva);
-void pmc_disable_pllack(void);
-uint32_t pmc_is_locked_pllack(void);
-
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
-void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb);
-void pmc_disable_pllbck(void);
-uint32_t pmc_is_locked_pllbck(void);
-#endif
-
-#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
-void pmc_enable_upll_clock(void);
-void pmc_disable_upll_clock(void);
-uint32_t pmc_is_locked_upll(void);
-#endif
-
-//@}
-
-/**
- * \name Peripherals clock configuration
- *
- */
-//@{
-
-uint32_t pmc_enable_periph_clk(uint32_t ul_id);
-uint32_t pmc_disable_periph_clk(uint32_t ul_id);
-void pmc_enable_all_periph_clk(void);
-void pmc_disable_all_periph_clk(void);
-uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id);
-
-//@}
-
-/**
- * \name Programmable clock Source and Prescaler configuration
- *
- * The following functions may be used to select the clock source and
- * prescaler for the specified programmable clock.
- */
-//@{
-
-void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres);
-void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source);
-uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres);
-uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres);
-uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres);
-#if (SAM4C || SAM4CM || SAM4CP)
-void pmc_enable_cpck(void);
-void pmc_disable_cpck(void);
-bool pmc_is_cpck_enabled(void);
-void pmc_enable_cpbmck(void);
-void pmc_disable_cpbmck(void);
-bool pmc_is_cpbmck_enabled(void);
-void pmc_cpck_set_prescaler(uint32_t ul_pres);
-void pmc_cpck_set_source(uint32_t ul_source);
-#endif
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
-uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres);
-#endif
-#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
-uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres);
-#endif
-uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres);
-void pmc_enable_pck(uint32_t ul_id);
-void pmc_disable_pck(uint32_t ul_id);
-void pmc_enable_all_pck(void);
-void pmc_disable_all_pck(void);
-uint32_t pmc_is_pck_enabled(uint32_t ul_id);
-
-//@}
-
-/**
- * \name USB clock configuration
- *
- */
-//@{
-
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
-void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv);
-#endif
-#if (SAM3S || SAM4S || SAMG55)
-void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv);
-#endif
-#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70)
-void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv);
-#endif
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
-void pmc_enable_udpck(void);
-void pmc_disable_udpck(void);
-#endif
-#if SAMG55
-void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv);
-void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv);
-void pmc_enable_uhpck(void);
-#endif
-
-//@}
-
-/**
- * \name Interrupt and status management
- *
- */
-//@{
-
-void pmc_enable_interrupt(uint32_t ul_sources);
-void pmc_disable_interrupt(uint32_t ul_sources);
-uint32_t pmc_get_interrupt_mask(void);
-uint32_t pmc_get_status(void);
-
-//@}
-
-/**
- * \name Power management
- *
- * The following functions are used to configure sleep mode and additional
- * wake up inputs.
- */
-//@{
-
-void pmc_set_fast_startup_input(uint32_t ul_inputs);
-void pmc_clr_fast_startup_input(uint32_t ul_inputs);
-#if (SAM4C || SAM4CM || SAM4CP)
-void pmc_cp_set_fast_startup_input(uint32_t ul_inputs);
-void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs);
-#endif
-void pmc_enable_sleepmode(uint8_t uc_type);
-void pmc_enable_waitmode(void);
-#if (!(SAMG51 || SAMG53 || SAMG54))
-void pmc_enable_backupmode(void);
-#endif
-//@}
-
-/**
- * \name Failure detector
- *
- */
-//@{
-
-void pmc_enable_clock_failure_detector(void);
-void pmc_disable_clock_failure_detector(void);
-
-//@}
-
-#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \name Slow Crystal Oscillator Frequency Monitoring
- *
- */
-//@{
-
-void pmc_enable_sclk_osc_freq_monitor(void);
-void pmc_disable_sclk_osc_freq_monitor(void);
-
-//@}
-#endif
-
-/**
- * \name Write protection
- *
- */
-//@{
-
-void pmc_set_writeprotect(uint32_t ul_enable);
-uint32_t pmc_get_writeprotect_status(void);
-
-//@}
-
-#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \name Sleepwalking configuration
- *
- */
-//@{
-
-uint32_t pmc_enable_sleepwalking(uint32_t ul_id);
-uint32_t pmc_disable_sleepwalking(uint32_t ul_id);
-uint32_t pmc_get_sleepwalking_status0(void);
-uint32_t pmc_get_active_status0(void);
-#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
-uint32_t pmc_get_sleepwalking_status1(void);
-uint32_t pmc_get_active_status1(void);
-#endif
-//@}
-#endif
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-//! @}
-
-/**
- * \page sam_pmc_quickstart Quick start guide for the SAM PMC module
- *
- * This is the quick start guide for the \ref sam_drivers_pmc_group "PMC module",
- * with step-by-step instructions on how to configure and use the driver in a
- * selection of use cases.
- *
- * The use cases contain several code fragments. The code fragments in the
- * steps for setup can be copied into a custom initialization function, while
- * the steps for usage can be copied into, e.g., the main application function.
- *
- * \section pmc_use_cases PMC use cases
- * - \ref pmc_basic_use_case Basic use case - Switch Main Clock sources
- * - \ref pmc_use_case_2 Advanced use case - Configure Programmable Clocks
- *
- * \section pmc_basic_use_case Basic use case - Switch Main Clock sources
- * In this use case, the PMC module is configured for a variety of system clock
- * sources and speeds. A LED is used to visually indicate the current clock
- * speed as the source is switched.
- *
- * \section pmc_basic_use_case_setup Setup
- *
- * \subsection pmc_basic_use_case_setup_prereq Prerequisites
- * -# \ref gpio_group "General Purpose I/O Management (gpio)"
- *
- * \subsection pmc_basic_use_case_setup_code Code
- * The following function needs to be added to the user application, to flash a
- * board LED a variable number of times at a rate given in CPU ticks.
- *
- * \code
- #define FLASH_TICK_COUNT 0x00012345
-
- void flash_led(uint32_t tick_count, uint8_t flash_count)
- {
- SysTick->CTRL = SysTick_CTRL_ENABLE_Msk;
- SysTick->LOAD = tick_count;
-
- while (flash_count--)
- {
- gpio_toggle_pin(LED0_GPIO);
- while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));
- gpio_toggle_pin(LED0_GPIO);
- while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));
- }
- }
-\endcode
- *
- * \section pmc_basic_use_case_usage Use case
- *
- * \subsection pmc_basic_use_case_usage_code Example code
- * Add to application C-file:
- * \code
- for (;;)
- {
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);
- flash_led(FLASH_TICK_COUNT, 5);
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);
- flash_led(FLASH_TICK_COUNT, 5);
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);
- flash_led(FLASH_TICK_COUNT, 5);
- pmc_switch_mainck_to_xtal(0);
- flash_led(FLASH_TICK_COUNT, 5);
- }
-\endcode
- *
- * \subsection pmc_basic_use_case_usage_flow Workflow
- * -# Wrap the code in an infinite loop:
- * \code
- for (;;)
-\endcode
- * -# Switch the Master CPU frequency to the internal 12MHz RC oscillator, flash
- * a LED on the board several times:
- * \code
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);
- flash_led(FLASH_TICK_COUNT, 5);
-\endcode
- * -# Switch the Master CPU frequency to the internal 8MHz RC oscillator, flash
- * a LED on the board several times:
- * \code
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);
- flash_led(FLASH_TICK_COUNT, 5);
-\endcode
- * -# Switch the Master CPU frequency to the internal 4MHz RC oscillator, flash
- * a LED on the board several times:
- * \code
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);
- flash_led(FLASH_TICK_COUNT, 5);
-\endcode
- * -# Switch the Master CPU frequency to the external crystal oscillator, flash
- * a LED on the board several times:
- * \code
- pmc_switch_mainck_to_xtal(0, BOARD_OSC_STARTUP_US);
- flash_led(FLASH_TICK_COUNT, 5);
-\endcode
- *
- * \section pmc_use_case_2 Use case #2 - Configure Programmable Clocks
- * In this use case, the PMC module is configured to start the Slow Clock from
- * an attached 32KHz crystal, and start one of the Programmable Clock modules
- * sourced from the Slow Clock divided down with a prescale factor of 64.
- *
- * \section pmc_use_case_2_setup Setup
- *
- * \subsection pmc_use_case_2_setup_prereq Prerequisites
- * -# \ref pio_group "Parallel Input/Output Controller (pio)"
- *
- * \subsection pmc_use_case_2_setup_code Code
- * The following code must be added to the user application:
- * \code
- pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);
-\endcode
- *
- * \subsection pmc_use_case_2_setup_code_workflow Workflow
- * -# Configure the PCK1 pin to output on a specific port pin (in this case,
- * PIOA pin 17) of the microcontroller.
- * \code
- pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);
-\endcode
- * \note The peripheral selection and pin will vary according to your selected
- * SAM device model. Refer to the "Peripheral Signal Multiplexing on I/O
- * Lines" of your device's datasheet.
- *
- * \section pmc_use_case_2_usage Use case
- * The generated PCK1 clock output can be viewed on an oscilloscope attached to
- * the correct pin of the microcontroller.
- *
- * \subsection pmc_use_case_2_usage_code Example code
- * Add to application C-file:
- * \code
- pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);
- pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);
- pmc_enable_pck(PMC_PCK_1);
-
- for (;;)
- {
- // Do Nothing
- }
-\endcode
- *
- * \subsection pmc_use_case_2_usage_flow Workflow
- * -# Switch the Slow Clock source input to an external 32KHz crystal:
- * \code
- pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);
-\endcode
- * -# Switch the Programmable Clock module PCK1 source clock to the Slow Clock,
- * with a prescaler of 64:
- * \code
- pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);
-\endcode
- * -# Enable Programmable Clock module PCK1:
- * \code
- pmc_enable_pck(PMC_PCK_1);
-\endcode
- * -# Enter an infinite loop:
- * \code
- for (;;)
- {
- // Do Nothing
- }
-\endcode
- */
-
-#endif /* PMC_H_INCLUDED */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/sleep.c b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/sleep.c
deleted file mode 100644
index 5d461e4..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/sleep.c
+++ /dev/null
@@ -1,391 +0,0 @@
-/**
- * \file
- *
- * \brief Sleep mode access
- *
- * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include <compiler.h>
-#include "sleep.h"
-
-/* SAM3,SAM4,SAMG,SAMV,SAMS and SAME series */
-#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \
- SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAMS70 || SAME70)
-# include "pmc.h"
-# include "board.h"
-
-/* Checking board configuration of main clock xtal statup time */
-#if !defined(BOARD_OSC_STARTUP_US)
-# warning The board main clock xtal statup time has not been defined. Using default settings.
-# define BOARD_OSC_STARTUP_US (15625UL)
-#endif
-
-#if !defined(EFC0)
-# define EFC0 EFC
-#endif
-
-/**
- * Save clock settings and shutdown PLLs
- */
-__always_inline static void pmc_save_clock_settings(
- uint32_t *p_osc_setting,
- uint32_t *p_pll0_setting,
- uint32_t *p_pll1_setting,
- uint32_t *p_mck_setting,
- uint32_t *p_fmr_setting,
-#if defined(EFC1)
- uint32_t *p_fmr_setting1,
-#endif
- const bool disable_xtal)
-{
- uint32_t mor = PMC->CKGR_MOR;
- uint32_t mckr = PMC->PMC_MCKR;
- uint32_t fmr = EFC0->EEFC_FMR;
-# if defined(EFC1)
- uint32_t fmr1 = EFC1->EEFC_FMR;
-# endif
-
- if (p_osc_setting) {
- *p_osc_setting = mor;
- }
- if (p_pll0_setting) {
- *p_pll0_setting = PMC->CKGR_PLLAR;
- }
- if (p_pll1_setting) {
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP)
- *p_pll1_setting = PMC->CKGR_PLLBR;
-#elif (SAM3U || SAM3XA)
- *p_pll1_setting = PMC->CKGR_UCKR;
-#else
- *p_pll1_setting = 0;
-#endif
- }
- if (p_mck_setting) {
- *p_mck_setting = mckr;
- }
- if (p_fmr_setting) {
- *p_fmr_setting = fmr;
- }
-#if defined(EFC1)
- if (p_fmr_setting1) {
- *p_fmr_setting1 = fmr1;
- }
-#endif
-
- /* Enable FAST RC */
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor | CKGR_MOR_MOSCRCEN;
- /* if MCK source is PLL, switch to mainck */
- if ((mckr & PMC_MCKR_CSS_Msk) > PMC_MCKR_CSS_MAIN_CLK) {
- /* MCK -> MAINCK */
- mckr = (mckr & (~PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_MAIN_CLK;
- PMC->PMC_MCKR = mckr;
- while(!(PMC->PMC_SR & PMC_SR_MCKRDY));
- }
- /* MCK prescale -> 1 */
- if (mckr & PMC_MCKR_PRES_Msk) {
- mckr = (mckr & (~PMC_MCKR_PRES_Msk));
- PMC->PMC_MCKR = mckr;
- while(!(PMC->PMC_SR & PMC_SR_MCKRDY));
- }
- /* Disable PLLs */
- pmc_disable_pllack();
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP)
- pmc_disable_pllbck();
-#elif (SAM3U || SAM3XA)
- pmc_disable_upll_clock();
-#endif
-
- /* Prepare for entering WAIT mode */
- /* Wait fast RC ready */
- while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
-
- /* Switch mainck to FAST RC */
-#if SAMG
- /**
- * For the sleepwalking feature, we need an accurate RC clock. Only 24M and
- * 16M are trimmed in production. Here we select the 24M.
- * And so wait state need to be 1.
- */
- EFC0->EEFC_FMR = (fmr & (~EEFC_FMR_FWS_Msk)) | EEFC_FMR_FWS(1);
-
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | CKGR_MOR_MOSCRCF_24_MHz |
- CKGR_MOR_KEY_PASSWD;
-#else
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) |
- CKGR_MOR_KEY_PASSWD;
-#endif
- while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));
-
-#if (!SAMG)
- /* FWS update */
- EFC0->EEFC_FMR = fmr & (~EEFC_FMR_FWS_Msk);
-#if defined(EFC1)
- EFC1->EEFC_FMR = fmr1 & (~EEFC_FMR_FWS_Msk);
-#endif
-#endif
-
- /* Disable XTALs */
- if (disable_xtal) {
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
- CKGR_MOR_KEY_PASSWD;
- }
-}
-
-/**
- * Restore clock settings
- */
-__always_inline static void pmc_restore_clock_setting(
- const uint32_t osc_setting,
- const uint32_t pll0_setting,
- const uint32_t pll1_setting,
- const uint32_t mck_setting,
- const uint32_t fmr_setting
-#if defined(EFC1)
- , const uint32_t fmr_setting1
-#endif
- )
-{
- uint32_t mckr;
- uint32_t pll_sr = 0;
-
- /* Switch mainck to external xtal */
- if (CKGR_MOR_MOSCXTBY == (osc_setting & CKGR_MOR_MOSCXTBY)) {
- /* Bypass mode */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
- CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY |
- CKGR_MOR_MOSCSEL;
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN &
- ~CKGR_MOR_MOSCRCF_Msk)
- | CKGR_MOR_KEY_PASSWD;
- } else if (CKGR_MOR_MOSCXTEN == (osc_setting & CKGR_MOR_MOSCXTEN)) {
- /* Enable External XTAL */
- if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN)) {
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
- CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN;
- /* Wait the Xtal to stabilize */
- while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
- }
- /* Select External XTAL */
- if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
- PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;
- while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));
- }
- /* Disable Fast RC */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN &
- ~CKGR_MOR_MOSCRCF_Msk)
- | CKGR_MOR_KEY_PASSWD;
- }
-
- if (pll0_setting & CKGR_PLLAR_MULA_Msk) {
-#if (SAM4C || SAM4CM || SAMG || SAM4CP)
- PMC->CKGR_PLLAR = pll0_setting;
-#else
- PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | pll0_setting;
-#endif
- pll_sr |= PMC_SR_LOCKA;
- }
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP)
- if (pll1_setting & CKGR_PLLBR_MULB_Msk) {
- PMC->CKGR_PLLBR = pll1_setting;
- pll_sr |= PMC_SR_LOCKB;
- }
-#elif (SAM3U || SAM3XA)
- if (pll1_setting & CKGR_UCKR_UPLLEN) {
- PMC->CKGR_UCKR = pll1_setting;
- pll_sr |= PMC_SR_LOCKU;
- }
-#else
- UNUSED(pll1_setting);
-#endif
- /* Wait MCK source ready */
- switch(mck_setting & PMC_MCKR_CSS_Msk) {
- case PMC_MCKR_CSS_PLLA_CLK:
- while (!(PMC->PMC_SR & PMC_SR_LOCKA));
- break;
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP)
- case PMC_MCKR_CSS_PLLB_CLK:
- while (!(PMC->PMC_SR & PMC_SR_LOCKB));
- break;
-#elif (SAM3U || SAM3XA)
- case PMC_MCKR_CSS_UPLL_CLK:
- while (!(PMC->PMC_SR & PMC_SR_LOCKU));
- break;
-#endif
- }
-
- /* Switch to faster clock */
- mckr = PMC->PMC_MCKR;
-
- /* Set PRES */
- PMC->PMC_MCKR = (mckr & ~PMC_MCKR_PRES_Msk)
- | (mck_setting & PMC_MCKR_PRES_Msk);
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-
- /* Restore flash wait states */
- EFC0->EEFC_FMR = fmr_setting;
-#if defined(EFC1)
- EFC1->EEFC_FMR = fmr_setting1;
-#endif
-
- /* Set CSS and others */
- PMC->PMC_MCKR = mck_setting;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-
- /* Waiting all restored PLLs ready */
- while (!(PMC->PMC_SR & pll_sr));
-}
-
-/** If clocks are switched for some sleep mode */
-static volatile bool b_is_sleep_clock_used = false;
-/** Callback invoked once when clocks are restored */
-static pmc_callback_wakeup_clocks_restored_t callback_clocks_restored = NULL;
-
-void pmc_sleep(int sleep_mode)
-{
- switch (sleep_mode) {
- case SAM_PM_SMODE_SLEEP_WFI:
- case SAM_PM_SMODE_SLEEP_WFE:
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAMS70 || SAME70)
- SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;
- cpu_irq_enable();
- __DSB();
- __WFI();
- break;
-#else
- PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM;
- SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;
- cpu_irq_enable();
- if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI) {
- __DSB();
- __WFI();
- } else {
- __DSB();
- __WFE();
- }
- break;
-#endif
-
- case SAM_PM_SMODE_WAIT_FAST:
- case SAM_PM_SMODE_WAIT: {
- uint32_t mor, pllr0, pllr1, mckr;
- uint32_t fmr;
-#if defined(EFC1)
- uint32_t fmr1;
-#endif
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAMS70 || SAME70)
- (sleep_mode == SAM_PM_SMODE_WAIT_FAST) ?
- pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_STANDBY) :
- pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN);
-#endif
- cpu_irq_disable();
- b_is_sleep_clock_used = true;
-
-#if (SAM4C || SAM4CM || SAM4CP)
- /* Backup the sub-system 1 status and stop sub-system 1 */
- uint32_t cpclk_backup = PMC->PMC_SCSR &
- (PMC_SCSR_CPCK | PMC_SCSR_CPBMCK);
- PMC->PMC_SCDR = cpclk_backup | PMC_SCDR_CPKEY_PASSWD;
-#endif
- pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr, &fmr,
-#if defined(EFC1)
- &fmr1,
-#endif
- (sleep_mode == SAM_PM_SMODE_WAIT));
-
- /* Enter wait mode */
- cpu_irq_enable();
-
- pmc_enable_waitmode();
-
- cpu_irq_disable();
- pmc_restore_clock_setting(mor, pllr0, pllr1, mckr, fmr
-#if defined(EFC1)
- , fmr1
-#endif
- );
-
-#if (SAM4C || SAM4CM || SAM4CP)
- /* Restore the sub-system 1 */
- PMC->PMC_SCER = cpclk_backup | PMC_SCER_CPKEY_PASSWD;
-#endif
- b_is_sleep_clock_used = false;
- if (callback_clocks_restored) {
- callback_clocks_restored();
- callback_clocks_restored = NULL;
- }
- cpu_irq_enable();
-
- break;
- }
-#if (!(SAMG51 || SAMG53 || SAMG54))
- case SAM_PM_SMODE_BACKUP:
- SCB->SCR |= SCR_SLEEPDEEP;
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70)
- SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG;
- cpu_irq_enable();
- __WFI() ;
-#else
- cpu_irq_enable();
- __WFE() ;
-#endif
- break;
-#endif
- }
-}
-
-bool pmc_is_wakeup_clocks_restored(void)
-{
- return !b_is_sleep_clock_used;
-}
-
-void pmc_wait_wakeup_clocks_restore(
- pmc_callback_wakeup_clocks_restored_t callback)
-{
- if (b_is_sleep_clock_used) {
- cpu_irq_disable();
- callback_clocks_restored = callback;
- } else if (callback) {
- callback();
- }
-}
-
-#endif
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/sleep.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/sleep.h
deleted file mode 100644
index 868c57f..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/drivers/pmc/sleep.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/**
- * \file
- *
- * \brief Sleep mode access
- *
- * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <compiler.h>
-
-/**
- * \defgroup sleep_group Power Manager (PM)
- *
- * This is a stub on the SAM Power Manager Control (PMC) for the sleepmgr
- * service.
- *
- * \note To minimize the code overhead, these functions do not feature
- * interrupt-protected access since they are likely to be called inside
- * interrupt handlers or in applications where such protection is not
- * necessary. If such protection is needed, it must be ensured by the calling
- * code.
- *
- * @{
- */
-
-#if defined(__DOXYGEN__)
-/**
- * \brief Sets the MCU in the specified sleep mode
- * \param sleep_mode Sleep mode to set.
- */
-#endif
-/* SAM3,SAM4,SAMG,SAMV,SAME and SAMS series */
-#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \
- SAM4CM || SAM4CP || SAMG || SAMV71 || SAME70 || SAMS70)
-# define SAM_PM_SMODE_ACTIVE 0 /**< Active */
-# define SAM_PM_SMODE_SLEEP_WFE 1 /**< Wait for Events */
-# define SAM_PM_SMODE_SLEEP_WFI 2 /**< Wait for Interrupts */
-# define SAM_PM_SMODE_WAIT_FAST 3 /**< Wait Mode, startup fast (in 3ms) */
-# define SAM_PM_SMODE_WAIT 4 /**< Wait Mode */
-#if (!(SAMG51 || SAMG53 || SAMG54))
-# define SAM_PM_SMODE_BACKUP 5 /**< Backup Mode */
-#endif
-
-/** (SCR) Sleep deep bit */
-#define SCR_SLEEPDEEP (0x1 << 2)
-
-/**
- * Clocks restored callback function type.
- * Registered by routine pmc_wait_wakeup_clocks_restore()
- * Callback called when all clocks are restored.
- */
-typedef void (*pmc_callback_wakeup_clocks_restored_t) (void);
-
-/**
- * Enter sleep mode
- * \param sleep_mode Sleep mode to enter
- */
-void pmc_sleep(int sleep_mode);
-
-/**
- * Check if clocks are restored after wakeup
- * (For WAIT mode. In WAIT mode, clocks are switched to FASTRC.
- * After wakeup clocks should be restored, before that some of the
- * ISR should not be served, otherwise there may be timing or clock issue.)
- */
-bool pmc_is_wakeup_clocks_restored(void);
-
-/**
- * \return true if start waiting
- */
-void pmc_wait_wakeup_clocks_restore(
- pmc_callback_wakeup_clocks_restored_t callback);
-
-#endif
-
-//! @}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SLEEP_H */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/acc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/acc.h
deleted file mode 100644
index 9b87664..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/acc.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_ACC_COMPONENT_
-#define _SAMS70_ACC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_ACC Analog Comparator Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Acc hardware registers */
-typedef struct {
- __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */
- __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */
- __I uint32_t Reserved1[7];
- __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */
- __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */
- __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */
- __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */
- __I uint32_t Reserved2[24];
- __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */
- __I uint32_t Reserved3[19];
- __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */
- __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */
-} Acc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
-#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */
-/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
-#define ACC_MR_SELMINUS_Pos 0
-#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */
-#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos)))
-#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */
-#define ACC_MR_SELMINUS_ADVREFP (0x1u << 0) /**< \brief (ACC_MR) Select ADVREFP */
-#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */
-#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */
-#define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AFE0_AD0 */
-#define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AFE0_AD1 */
-#define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AFE0_AD2 */
-#define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AFE0_AD3 */
-#define ACC_MR_SELPLUS_Pos 4
-#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */
-#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos)))
-#define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AFE0_AD0 */
-#define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AFE0_AD1 */
-#define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AFE0_AD2 */
-#define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AFE0_AD3 */
-#define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AFE0_AD4 */
-#define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AFE0_AD5 */
-#define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) /**< \brief (ACC_MR) Select AFE1_AD0 */
-#define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) /**< \brief (ACC_MR) Select AFE1_AD1 */
-#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */
-#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */
-#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */
-#define ACC_MR_EDGETYP_Pos 9
-#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */
-#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos)))
-#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */
-#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */
-#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */
-#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */
-#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */
-#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */
-#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */
-#define ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */
-#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */
-#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */
-#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */
-#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */
-/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
-#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */
-/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
-#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */
-/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
-#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */
-/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
-#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */
-#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */
-#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */
-/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
-#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */
-#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */
-#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */
-#define ACC_ACR_HYST_Pos 1
-#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */
-#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))
-/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */
-#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */
-#define ACC_WPMR_WPKEY_Pos 8
-#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */
-#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))
-#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
-/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */
-#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */
-
-/*@}*/
-
-
-#endif /* _SAMS70_ACC_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/aes.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/aes.h
deleted file mode 100644
index 963f22a..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/aes.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_AES_COMPONENT_
-#define _SAMS70_AES_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */
-/* ============================================================================= */
-/** \addtogroup SAMS70_AES Advanced Encryption Standard */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Aes hardware registers */
-typedef struct {
- __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */
- __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */
- __I uint32_t Reserved1[2];
- __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */
- __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */
- __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */
- __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */
- __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */
- __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */
- __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */
- __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */
- __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */
- __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */
- __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */
- __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */
- __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */
- __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H Word Register */
-} Aes;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */
-#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */
-#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */
-/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */
-#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */
-#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */
-#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */
-#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */
-#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. */
-#define AES_MR_PROCDLY_Pos 4
-#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */
-#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)))
-#define AES_MR_SMOD_Pos 8
-#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */
-#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos)))
-#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */
-#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */
-#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */
-#define AES_MR_KEYSIZE_Pos 10
-#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */
-#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos)))
-#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */
-#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */
-#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */
-#define AES_MR_OPMOD_Pos 12
-#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */
-#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos)))
-#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */
-#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */
-#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */
-#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */
-#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */
-#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */
-#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */
-#define AES_MR_CFBS_Pos 16
-#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */
-#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos)))
-#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */
-#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */
-#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */
-#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */
-#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */
-#define AES_MR_CKEY_Pos 20
-#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Key */
-#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)))
-#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE the first time that AES_MR is programmed. For subsequent programming of the AES_MR, any value can be written, including that of 0xE.Always reads as 0. */
-/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
-#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */
-#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */
-#define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */
-/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
-#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */
-#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */
-#define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */
-/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
-#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */
-#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */
-#define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */
-/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */
-#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */
-#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */
-#define AES_ISR_URAT_Pos 12
-#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */
-#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */
-#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */
-#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */
-#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */
-#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */
-#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */
-#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */
-/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */
-#define AES_KEYWR_KEYW_Pos 0
-#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */
-#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)))
-/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */
-#define AES_IDATAR_IDATA_Pos 0
-#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */
-#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)))
-/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */
-#define AES_ODATAR_ODATA_Pos 0
-#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */
-/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */
-#define AES_IVR_IV_Pos 0
-#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */
-#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)))
-/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */
-#define AES_AADLENR_AADLEN_Pos 0
-#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */
-#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)))
-/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */
-#define AES_CLENR_CLEN_Pos 0
-#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */
-#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)))
-/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */
-#define AES_GHASHR_GHASH_Pos 0
-#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */
-#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)))
-/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */
-#define AES_TAGR_TAG_Pos 0
-#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */
-/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */
-#define AES_CTRR_CTR_Pos 0
-#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */
-/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */
-#define AES_GCMHR_H_Pos 0
-#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */
-#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)))
-
-/*@}*/
-
-
-#endif /* _SAMS70_AES_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/afec.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/afec.h
deleted file mode 100644
index f8ee47e..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/afec.h
+++ /dev/null
@@ -1,498 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_AFEC_COMPONENT_
-#define _SAMS70_AFEC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Analog Front-End Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_AFEC Analog Front-End Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Afec hardware registers */
-typedef struct {
- __O uint32_t AFEC_CR; /**< \brief (Afec Offset: 0x00) AFEC Control Register */
- __IO uint32_t AFEC_MR; /**< \brief (Afec Offset: 0x04) AFEC Mode Register */
- __IO uint32_t AFEC_EMR; /**< \brief (Afec Offset: 0x08) AFEC Extended Mode Register */
- __IO uint32_t AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register */
- __IO uint32_t AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) AFEC Channel Sequence 2 Register */
- __O uint32_t AFEC_CHER; /**< \brief (Afec Offset: 0x14) AFEC Channel Enable Register */
- __O uint32_t AFEC_CHDR; /**< \brief (Afec Offset: 0x18) AFEC Channel Disable Register */
- __I uint32_t AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) AFEC Channel Status Register */
- __I uint32_t AFEC_LCDR; /**< \brief (Afec Offset: 0x20) AFEC Last Converted Data Register */
- __O uint32_t AFEC_IER; /**< \brief (Afec Offset: 0x24) AFEC Interrupt Enable Register */
- __O uint32_t AFEC_IDR; /**< \brief (Afec Offset: 0x28) AFEC Interrupt Disable Register */
- __I uint32_t AFEC_IMR; /**< \brief (Afec Offset: 0x2C) AFEC Interrupt Mask Register */
- __I uint32_t AFEC_ISR; /**< \brief (Afec Offset: 0x30) AFEC Interrupt Status Register */
- __I uint32_t Reserved1[6];
- __I uint32_t AFEC_OVER; /**< \brief (Afec Offset: 0x4C) AFEC Overrun Status Register */
- __IO uint32_t AFEC_CWR; /**< \brief (Afec Offset: 0x50) AFEC Compare Window Register */
- __IO uint32_t AFEC_CGR; /**< \brief (Afec Offset: 0x54) AFEC Channel Gain Register */
- __I uint32_t Reserved2[2];
- __IO uint32_t AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) AFEC Channel Differential Register */
- __IO uint32_t AFEC_CSELR; /**< \brief (Afec Offset: 0x64) AFEC Channel Selection Register */
- __I uint32_t AFEC_CDR; /**< \brief (Afec Offset: 0x68) AFEC Channel Data Register */
- __IO uint32_t AFEC_COCR; /**< \brief (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register */
- __IO uint32_t AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register */
- __IO uint32_t AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) AFEC Temperature Compare Window Register */
- __I uint32_t Reserved3[7];
- __IO uint32_t AFEC_ACR; /**< \brief (Afec Offset: 0x94) AFEC Analog Control Register */
- __I uint32_t Reserved4[2];
- __IO uint32_t AFEC_SHMR; /**< \brief (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register */
- __I uint32_t Reserved5[11];
- __IO uint32_t AFEC_COSR; /**< \brief (Afec Offset: 0xD0) AFEC Correction Select Register */
- __IO uint32_t AFEC_CVR; /**< \brief (Afec Offset: 0xD4) AFEC Correction Values Register */
- __IO uint32_t AFEC_CECR; /**< \brief (Afec Offset: 0xD8) AFEC Channel Error Correction Register */
- __I uint32_t Reserved6[2];
- __IO uint32_t AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) AFEC Write Protection Mode Register */
- __I uint32_t AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) AFEC Write Protection Status Register */
-} Afec;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */
-#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */
-#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */
-/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */
-#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */
-#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
-#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */
-#define AFEC_MR_TRGSEL_Pos 1
-#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */
-#define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos)))
-#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */
-#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */
-#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */
-#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */
-#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */
-#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */
-#define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) /**< \brief (AFEC_MR) Analog Comparator */
-#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */
-#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */
-#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */
-#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake-up */
-#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */
-#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */
-#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */
-#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal mode */
-#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run mode: Never wait for any trigger. */
-#define AFEC_MR_PRESCAL_Pos 8
-#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */
-#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos)))
-#define AFEC_MR_STARTUP_Pos 16
-#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start-up Time */
-#define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos)))
-#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFE clock */
-#define AFEC_MR_ONE (0x1u << 23) /**< \brief (AFEC_MR) One */
-#define AFEC_MR_TRACKTIM_Pos 24
-#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */
-#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos)))
-#define AFEC_MR_TRANSFER_Pos 28
-#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */
-#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos)))
-#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Enable */
-#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */
-#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */
-/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */
-#define AFEC_EMR_CMPMODE_Pos 0
-#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */
-#define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos)))
-#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
-#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
-#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */
-#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */
-#define AFEC_EMR_CMPSEL_Pos 3
-#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */
-#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos)))
-#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */
-#define AFEC_EMR_CMPFILTER_Pos 12
-#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */
-#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos)))
-#define AFEC_EMR_RES_Pos 16
-#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */
-#define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos)))
-#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */
-#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */
-#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */
-#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */
-#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */
-#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR */
-#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */
-#define AFEC_EMR_SIGNMODE_Pos 28
-#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) /**< \brief (AFEC_EMR) Sign Mode */
-#define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos)))
-#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */
-#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */
-#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) /**< \brief (AFEC_EMR) All channels: Unsigned conversions. */
-#define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) /**< \brief (AFEC_EMR) All channels: Signed conversions. */
-/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */
-#define AFEC_SEQ1R_USCH0_Pos 0
-#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */
-#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos)))
-#define AFEC_SEQ1R_USCH1_Pos 4
-#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */
-#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos)))
-#define AFEC_SEQ1R_USCH2_Pos 8
-#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */
-#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos)))
-#define AFEC_SEQ1R_USCH3_Pos 12
-#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */
-#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos)))
-#define AFEC_SEQ1R_USCH4_Pos 16
-#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */
-#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos)))
-#define AFEC_SEQ1R_USCH5_Pos 20
-#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */
-#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos)))
-#define AFEC_SEQ1R_USCH6_Pos 24
-#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */
-#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos)))
-#define AFEC_SEQ1R_USCH7_Pos 28
-#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */
-#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos)))
-/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */
-#define AFEC_SEQ2R_USCH8_Pos 0
-#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */
-#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos)))
-#define AFEC_SEQ2R_USCH9_Pos 4
-#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */
-#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos)))
-#define AFEC_SEQ2R_USCH10_Pos 8
-#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */
-#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos)))
-#define AFEC_SEQ2R_USCH11_Pos 12
-#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */
-#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos)))
-#define AFEC_SEQ2R_USCH12_Pos 16
-#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */
-#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos)))
-#define AFEC_SEQ2R_USCH13_Pos 20
-#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */
-#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos)))
-#define AFEC_SEQ2R_USCH14_Pos 24
-#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */
-#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos)))
-#define AFEC_SEQ2R_USCH15_Pos 28
-#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */
-#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos)))
-/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */
-#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */
-#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */
-#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */
-#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */
-#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */
-#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */
-#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */
-#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */
-#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */
-#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */
-#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */
-#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */
-/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */
-#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */
-#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */
-#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */
-#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */
-#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */
-#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */
-#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */
-#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */
-#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */
-#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */
-#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */
-#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */
-/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */
-#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */
-#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */
-#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */
-#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */
-#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */
-#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */
-#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */
-#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */
-#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */
-#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */
-#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */
-#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */
-/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */
-#define AFEC_LCDR_LDATA_Pos 0
-#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */
-#define AFEC_LCDR_CHNB_Pos 24
-#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */
-/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */
-#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */
-#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */
-#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */
-#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */
-#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */
-#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */
-#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */
-#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */
-#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */
-#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */
-#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */
-#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */
-#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */
-#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */
-#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable */
-#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */
-/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */
-#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */
-#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */
-#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */
-#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */
-#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */
-#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */
-#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */
-#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */
-#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */
-#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */
-#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */
-#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */
-#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */
-#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */
-#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */
-#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */
-/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */
-#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */
-#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */
-#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */
-#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */
-#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */
-#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */
-#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */
-#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */
-#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */
-#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */
-#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */
-#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */
-#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */
-#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */
-#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */
-#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */
-/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */
-#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) */
-#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) */
-#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) */
-#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change (cleared on read) */
-/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */
-#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */
-#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */
-#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */
-#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */
-#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */
-#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */
-#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */
-#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */
-#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */
-#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */
-#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */
-#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */
-/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */
-#define AFEC_CWR_LOWTHRES_Pos 0
-#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */
-#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos)))
-#define AFEC_CWR_HIGHTHRES_Pos 16
-#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */
-#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos)))
-/* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */
-#define AFEC_CGR_GAIN0_Pos 0
-#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for Channel 0 */
-#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos)))
-#define AFEC_CGR_GAIN1_Pos 2
-#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for Channel 1 */
-#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos)))
-#define AFEC_CGR_GAIN2_Pos 4
-#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for Channel 2 */
-#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos)))
-#define AFEC_CGR_GAIN3_Pos 6
-#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for Channel 3 */
-#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos)))
-#define AFEC_CGR_GAIN4_Pos 8
-#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for Channel 4 */
-#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos)))
-#define AFEC_CGR_GAIN5_Pos 10
-#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for Channel 5 */
-#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos)))
-#define AFEC_CGR_GAIN6_Pos 12
-#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for Channel 6 */
-#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos)))
-#define AFEC_CGR_GAIN7_Pos 14
-#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for Channel 7 */
-#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos)))
-#define AFEC_CGR_GAIN8_Pos 16
-#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for Channel 8 */
-#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos)))
-#define AFEC_CGR_GAIN9_Pos 18
-#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for Channel 9 */
-#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos)))
-#define AFEC_CGR_GAIN10_Pos 20
-#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for Channel 10 */
-#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos)))
-#define AFEC_CGR_GAIN11_Pos 22
-#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for Channel 11 */
-#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos)))
-/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */
-#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */
-#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */
-#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */
-#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */
-#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */
-#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */
-#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */
-#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */
-#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */
-#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */
-#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */
-#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */
-/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */
-#define AFEC_CSELR_CSEL_Pos 0
-#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */
-#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos)))
-/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */
-#define AFEC_CDR_DATA_Pos 0
-#define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */
-/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */
-#define AFEC_COCR_AOFF_Pos 0
-#define AFEC_COCR_AOFF_Msk (0xfffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */
-#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos)))
-/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */
-#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode */
-#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4
-#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */
-#define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos)))
-#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */
-#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */
-#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */
-#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */
-/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */
-#define AFEC_TEMPCWR_TLOWTHRES_Pos 0
-#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */
-#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos)))
-#define AFEC_TEMPCWR_THIGHTHRES_Pos 16
-#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */
-#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos)))
-/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */
-#define AFEC_ACR_PGA0EN (0x1u << 2) /**< \brief (AFEC_ACR) PGA0 Enable */
-#define AFEC_ACR_PGA1EN (0x1u << 3) /**< \brief (AFEC_ACR) PGA1 Enable */
-#define AFEC_ACR_IBCTL_Pos 8
-#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFE Bias Current Control */
-#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos)))
-/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */
-#define AFEC_SHMR_DUAL0 (0x1u << 0) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 0 */
-#define AFEC_SHMR_DUAL1 (0x1u << 1) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 1 */
-#define AFEC_SHMR_DUAL2 (0x1u << 2) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 2 */
-#define AFEC_SHMR_DUAL3 (0x1u << 3) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 3 */
-#define AFEC_SHMR_DUAL4 (0x1u << 4) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 4 */
-#define AFEC_SHMR_DUAL5 (0x1u << 5) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 5 */
-#define AFEC_SHMR_DUAL6 (0x1u << 6) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 6 */
-#define AFEC_SHMR_DUAL7 (0x1u << 7) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 7 */
-#define AFEC_SHMR_DUAL8 (0x1u << 8) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 8 */
-#define AFEC_SHMR_DUAL9 (0x1u << 9) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 9 */
-#define AFEC_SHMR_DUAL10 (0x1u << 10) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 10 */
-#define AFEC_SHMR_DUAL11 (0x1u << 11) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 11 */
-/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */
-#define AFEC_COSR_CSEL (0x1u << 0) /**< \brief (AFEC_COSR) Sample & Hold unit Correction Select */
-/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */
-#define AFEC_CVR_OFFSETCORR_Pos 0
-#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) /**< \brief (AFEC_CVR) Offset Correction */
-#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos)))
-#define AFEC_CVR_GAINCORR_Pos 16
-#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) /**< \brief (AFEC_CVR) Gain Correction */
-#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos)))
-/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */
-#define AFEC_CECR_ECORR0 (0x1u << 0) /**< \brief (AFEC_CECR) Error Correction Enable for channel 0 */
-#define AFEC_CECR_ECORR1 (0x1u << 1) /**< \brief (AFEC_CECR) Error Correction Enable for channel 1 */
-#define AFEC_CECR_ECORR2 (0x1u << 2) /**< \brief (AFEC_CECR) Error Correction Enable for channel 2 */
-#define AFEC_CECR_ECORR3 (0x1u << 3) /**< \brief (AFEC_CECR) Error Correction Enable for channel 3 */
-#define AFEC_CECR_ECORR4 (0x1u << 4) /**< \brief (AFEC_CECR) Error Correction Enable for channel 4 */
-#define AFEC_CECR_ECORR5 (0x1u << 5) /**< \brief (AFEC_CECR) Error Correction Enable for channel 5 */
-#define AFEC_CECR_ECORR6 (0x1u << 6) /**< \brief (AFEC_CECR) Error Correction Enable for channel 6 */
-#define AFEC_CECR_ECORR7 (0x1u << 7) /**< \brief (AFEC_CECR) Error Correction Enable for channel 7 */
-#define AFEC_CECR_ECORR8 (0x1u << 8) /**< \brief (AFEC_CECR) Error Correction Enable for channel 8 */
-#define AFEC_CECR_ECORR9 (0x1u << 9) /**< \brief (AFEC_CECR) Error Correction Enable for channel 9 */
-#define AFEC_CECR_ECORR10 (0x1u << 10) /**< \brief (AFEC_CECR) Error Correction Enable for channel 10 */
-#define AFEC_CECR_ECORR11 (0x1u << 11) /**< \brief (AFEC_CECR) Error Correction Enable for channel 11 */
-/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */
-#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protection Enable */
-#define AFEC_WPMR_WPKEY_Pos 8
-#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */
-#define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos)))
-#define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
-/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */
-#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */
-#define AFEC_WPSR_WPVSRC_Pos 8
-#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_AFEC_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/chipid.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/chipid.h
deleted file mode 100644
index 57f14ab..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/chipid.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_CHIPID_COMPONENT_
-#define _SAMS70_CHIPID_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Chip Identifier */
-/* ============================================================================= */
-/** \addtogroup SAMS70_CHIPID Chip Identifier */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Chipid hardware registers */
-typedef struct {
- __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
- __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
-} Chipid;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
-#define CHIPID_CIDR_VERSION_Pos 0
-#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
-#define CHIPID_CIDR_EPROC_Pos 5
-#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
-#define CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) /**< \brief (CHIPID_CIDR) Cortex-M7 */
-#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
-#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
-#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
-#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
-#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
-#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
-#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
-#define CHIPID_CIDR_NVPSIZ_Pos 8
-#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
-#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
-#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_Pos 12
-#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
-#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
-#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_Pos 16
-#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
-#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */
-#define CHIPID_CIDR_ARCH_Pos 20
-#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
-#define CHIPID_CIDR_ARCH_SAME70 (0x10u << 20) /**< \brief (CHIPID_CIDR) SAM E70 */
-#define CHIPID_CIDR_ARCH_SAMS70 (0x11u << 20) /**< \brief (CHIPID_CIDR) SAM S70 */
-#define CHIPID_CIDR_ARCH_SAMV71 (0x12u << 20) /**< \brief (CHIPID_CIDR) SAM V71 */
-#define CHIPID_CIDR_ARCH_SAMV70 (0x13u << 20) /**< \brief (CHIPID_CIDR) SAM V70 */
-#define CHIPID_CIDR_NVPTYP_Pos 28
-#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
-#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
-#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
-#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
-#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */
-#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
-#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
-/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
-#define CHIPID_EXID_EXID_Pos 0
-#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
-
-/*@}*/
-
-
-#endif /* _SAMS70_CHIPID_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/dacc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/dacc.h
deleted file mode 100644
index 7aec4a9..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/dacc.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_DACC_COMPONENT_
-#define _SAMS70_DACC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_DACC Digital-to-Analog Converter Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Dacc hardware registers */
-typedef struct {
- __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */
- __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */
- __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */
- __I uint32_t Reserved1[1];
- __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */
- __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */
- __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */
- __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */
- __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */
- __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */
- __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */
- __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */
- __I uint32_t Reserved2[24];
- __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */
- __I uint32_t Reserved3[19];
- __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode register */
- __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status register */
-} Dacc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
-#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
-/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
-#define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */
-#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) Triggered by selected event */
-#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode enabled */
-#define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */
-#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) Triggered by selected event */
-#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode enabled */
-#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */
-#define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC */
-#define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces number of requests to DMA and the number of system bus accesses) */
-#define DACC_MR_REFRESH_Pos 8
-#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */
-#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
-#define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */
-#define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 outputs can be separately configured */
-#define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN outputs are configured by the channel 0 value. */
-#define DACC_MR_PRESCALER_Pos 24
-#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */
-#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos)))
-/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */
-#define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */
-#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */
-#define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */
-#define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */
-#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */
-#define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */
-#define DACC_TRIGR_TRGSEL0_Pos 4
-#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */
-#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos)))
-#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) TC0 output */
-#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TC1 output */
-#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TC2 output */
-#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) PWM0 event 0 */
-#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) PWM0 event 1 */
-#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) PWM1 event 0 */
-#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) PWM1 event 1 */
-#define DACC_TRIGR_TRGSEL1_Pos 8
-#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */
-#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos)))
-#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) TC0 output */
-#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TC1 output */
-#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TC2 output */
-#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) PWM0 event 0 */
-#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) PWM0 event 1 */
-#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) PWM1 event 0 */
-#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) PWM1 event 1 */
-#define DACC_TRIGR_OSR0_Pos 16
-#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */
-#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos)))
-#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */
-#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */
-#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */
-#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */
-#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */
-#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */
-#define DACC_TRIGR_OSR1_Pos 20
-#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */
-#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos)))
-#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */
-#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */
-#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */
-#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */
-#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */
-#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */
-/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
-#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */
-#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */
-/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
-#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */
-#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */
-/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
-#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */
-#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */
-#define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC ready flag */
-#define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC ready flag */
-/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */
-#define DACC_CDR_DATA0_Pos 0
-#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */
-#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos)))
-#define DACC_CDR_DATA1_Pos 16
-#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */
-#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos)))
-/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
-#define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */
-#define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */
-#define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */
-#define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */
-#define DACC_IER_ENDTX0 (0x1u << 8) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 0 */
-#define DACC_IER_ENDTX1 (0x1u << 9) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 1 */
-#define DACC_IER_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 0 */
-#define DACC_IER_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 1 */
-/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
-#define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */
-#define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */
-#define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */
-#define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */
-#define DACC_IDR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 0 */
-#define DACC_IDR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 1 */
-#define DACC_IDR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 0 */
-#define DACC_IDR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 1 */
-/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
-#define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */
-#define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */
-#define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */
-#define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */
-#define DACC_IMR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 0 */
-#define DACC_IMR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 1 */
-#define DACC_IMR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 0 */
-#define DACC_IMR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 1 */
-/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
-#define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */
-#define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */
-#define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */
-#define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */
-#define DACC_ISR_ENDTX0 (0x1u << 8) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 0 */
-#define DACC_ISR_ENDTX1 (0x1u << 9) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 1 */
-#define DACC_ISR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 0 */
-#define DACC_ISR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 1 */
-/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
-#define DACC_ACR_IBCTLCH0_Pos 0
-#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
-#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
-#define DACC_ACR_IBCTLCH1_Pos 2
-#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
-#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
-/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode register -------- */
-#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */
-#define DACC_WPMR_WPKEY_Pos 8
-#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */
-#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
-#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */
-/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status register -------- */
-#define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */
-#define DACC_WPSR_WPVSRC_Pos 8
-#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_DACC_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/efc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/efc.h
deleted file mode 100644
index e316688..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/efc.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_EFC_COMPONENT_
-#define _SAMS70_EFC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_EFC Embedded Flash Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Efc hardware registers */
-typedef struct {
- __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
- __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
- __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
- __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
- __I uint32_t Reserved1[1];
- __I uint32_t EEFC_VERSION; /**< \brief (Efc Offset: 0x14) EEFC Version Register */
- __I uint32_t Reserved2[51];
- __IO uint32_t EEFC_WPMR; /**< \brief (Efc Offset: 0xE4) Write Protection Mode Register */
-} Efc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
-#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Flash Ready Interrupt Enable */
-#define EEFC_FMR_FWS_Pos 8
-#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
-#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
-#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
-#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */
-/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
-#define EEFC_FCR_FCMD_Pos 0
-#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
-#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
-#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */
-#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */
-#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */
-#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */
-#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */
-#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */
-#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */
-#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */
-#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */
-#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */
-#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */
-#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */
-#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */
-#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */
-#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */
-#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */
-#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */
-#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */
-#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */
-#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */
-#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */
-#define EEFC_FCR_FARG_Pos 8
-#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
-#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
-#define EEFC_FCR_FKEY_Pos 24
-#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
-#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
-#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */
-/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
-#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) */
-#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) */
-#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status (cleared on read) */
-#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) */
-#define EEFC_FSR_UECCELSB (0x1u << 16) /**< \brief (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */
-#define EEFC_FSR_MECCELSB (0x1u << 17) /**< \brief (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */
-#define EEFC_FSR_UECCEMSB (0x1u << 18) /**< \brief (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */
-#define EEFC_FSR_MECCEMSB (0x1u << 19) /**< \brief (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */
-/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
-#define EEFC_FRR_FVALUE_Pos 0
-#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
-/* -------- EEFC_VERSION : (EFC Offset: 0x14) EEFC Version Register -------- */
-#define EEFC_VERSION_VERSION_Pos 0
-#define EEFC_VERSION_VERSION_Msk (0xfffu << EEFC_VERSION_VERSION_Pos) /**< \brief (EEFC_VERSION) Version of the Hardware Module */
-#define EEFC_VERSION_MFN_Pos 16
-#define EEFC_VERSION_MFN_Msk (0x7u << EEFC_VERSION_MFN_Pos) /**< \brief (EEFC_VERSION) Metal Fix Number */
-/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */
-#define EEFC_WPMR_WPEN (0x1u << 0) /**< \brief (EEFC_WPMR) Write Protection Enable */
-#define EEFC_WPMR_WPKEY_Pos 8
-#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) /**< \brief (EEFC_WPMR) Write Protection Key */
-#define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos)))
-#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) /**< \brief (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */
-
-/*@}*/
-
-
-#endif /* _SAMS70_EFC_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/gpbr.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/gpbr.h
deleted file mode 100644
index 21de664..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/gpbr.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_GPBR_COMPONENT_
-#define _SAMS70_GPBR_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */
-/* ============================================================================= */
-/** \addtogroup SAMS70_GPBR General Purpose Backup Registers */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Gpbr hardware registers */
-typedef struct {
- __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
-} Gpbr;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
-#define SYS_GPBR_GPBR_VALUE_Pos 0
-#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */
-#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
-
-/*@}*/
-
-
-#endif /* _SAMS70_GPBR_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/hsmci.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/hsmci.h
deleted file mode 100644
index ef86451..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/hsmci.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_HSMCI_COMPONENT_
-#define _SAMS70_HSMCI_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
-/* ============================================================================= */
-/** \addtogroup SAMS70_HSMCI High Speed MultiMedia Card Interface */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Hsmci hardware registers */
-typedef struct {
- __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */
- __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */
- __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
- __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
- __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */
- __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */
- __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */
- __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
- __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */
- __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
- __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
- __I uint32_t Reserved1[2];
- __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */
- __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
- __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
- __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
- __IO uint32_t HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */
- __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */
- __I uint32_t Reserved2[35];
- __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
- __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
- __I uint32_t Reserved3[69];
- __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
-} Hsmci;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
-#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
-#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
-#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
-#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
-#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
-/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
-#define HSMCI_MR_CLKDIV_Pos 0
-#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
-#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
-#define HSMCI_MR_PWSDIV_Pos 8
-#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
-#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
-#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */
-#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */
-#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
-#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
-#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */
-/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
-#define HSMCI_DTOR_DTOCYC_Pos 0
-#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
-#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
-#define HSMCI_DTOR_DTOMUL_Pos 4
-#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
-#define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos)))
-#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
-#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
-#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
-#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
-#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
-#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
-#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
-#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
-/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
-#define HSMCI_SDCR_SDCSEL_Pos 0
-#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
-#define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos)))
-#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
-#define HSMCI_SDCR_SDCBUS_Pos 6
-#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
-#define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos)))
-#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
-#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bits */
-#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bits */
-/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
-#define HSMCI_ARGR_ARG_Pos 0
-#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
-#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
-/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
-#define HSMCI_CMDR_CMDNB_Pos 0
-#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
-#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
-#define HSMCI_CMDR_RSPTYP_Pos 6
-#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
-#define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos)))
-#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response */
-#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response */
-#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response */
-#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
-#define HSMCI_CMDR_SPCMD_Pos 8
-#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
-#define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos)))
-#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
-#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
-#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
-#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
-#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
-#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
-#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
-#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
-#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
-#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
-#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
-#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
-#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
-#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
-#define HSMCI_CMDR_TRCMD_Pos 16
-#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
-#define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos)))
-#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
-#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
-#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
-#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
-#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
-#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
-#define HSMCI_CMDR_TRTYP_Pos 19
-#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
-#define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos)))
-#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */
-#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */
-#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
-#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
-#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
-#define HSMCI_CMDR_IOSPCMD_Pos 24
-#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
-#define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos)))
-#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
-#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
-#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
-#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
-#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
-#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
-#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge */
-/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
-#define HSMCI_BLKR_BCNT_Pos 0
-#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
-#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos)))
-#define HSMCI_BLKR_BLKLEN_Pos 16
-#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
-#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
-/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
-#define HSMCI_CSTOR_CSTOCYC_Pos 0
-#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
-#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
-#define HSMCI_CSTOR_CSTOMUL_Pos 4
-#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
-#define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos)))
-#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
-#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
-#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
-#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
-#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
-#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
-#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
-#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
-/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
-#define HSMCI_RSPR_RSP_Pos 0
-#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
-/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
-#define HSMCI_RDR_DATA_Pos 0
-#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
-/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
-#define HSMCI_TDR_DATA_Pos 0
-#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
-#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
-/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
-#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) */
-#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) */
-#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) */
-#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended (cleared on read) */
-#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) */
-#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
-#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) */
-#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
-#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) */
-#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) */
-#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) */
-#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) */
-#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) */
-#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) */
-#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error (cleared on read) */
-#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error (cleared on read) */
-#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error (cleared on read) */
-#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error (cleared on read) */
-#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
-#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
-#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) */
-#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) */
-#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */
-#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */
-/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
-#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
-#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
-#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
-#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
-#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
-#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
-#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */
-#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
-#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
-#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
-#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
-#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
-#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
-#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
-#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
-#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
-#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
-#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */
-#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
-#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
-#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
-#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
-#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
-#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
-/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
-#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
-#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
-#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
-#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
-#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
-#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
-#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */
-#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
-#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
-#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
-#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
-#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
-#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
-#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
-#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
-#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
-#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
-#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */
-#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
-#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
-#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
-#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
-#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
-#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
-/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
-#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
-#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
-#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
-#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
-#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
-#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
-#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */
-#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
-#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
-#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
-#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
-#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
-#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
-#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
-#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
-#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
-#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
-#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */
-#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
-#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
-#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
-#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
-#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
-#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
-/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
-#define HSMCI_DMA_CHKSIZE_Pos 4
-#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */
-#define HSMCI_DMA_CHKSIZE(value) ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos)))
-#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */
-#define HSMCI_DMA_CHKSIZE_2 (0x1u << 4) /**< \brief (HSMCI_DMA) 2 data available */
-#define HSMCI_DMA_CHKSIZE_4 (0x2u << 4) /**< \brief (HSMCI_DMA) 4 data available */
-#define HSMCI_DMA_CHKSIZE_8 (0x3u << 4) /**< \brief (HSMCI_DMA) 8 data available */
-#define HSMCI_DMA_CHKSIZE_16 (0x4u << 4) /**< \brief (HSMCI_DMA) 16 data available */
-#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */
-/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
-#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
-#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
-#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
-#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
-/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
-#define HSMCI_WPMR_WPEN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protect Enable */
-#define HSMCI_WPMR_WPKEY_Pos 8
-#define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos) /**< \brief (HSMCI_WPMR) Write Protect Key */
-#define HSMCI_WPMR_WPKEY(value) ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos)))
-#define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8) /**< \brief (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
-/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
-#define HSMCI_WPSR_WPVS (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
-#define HSMCI_WPSR_WPVSRC_Pos 8
-#define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Source */
-/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
-#define HSMCI_FIFO_DATA_Pos 0
-#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */
-#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))
-
-/*@}*/
-
-
-#endif /* _SAMS70_HSMCI_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/icm.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/icm.h
deleted file mode 100644
index f4c7a1e..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/icm.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_ICM_COMPONENT_
-#define _SAMS70_ICM_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Integrity Check Monitor */
-/* ============================================================================= */
-/** \addtogroup SAMS70_ICM Integrity Check Monitor */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Icm hardware registers */
-typedef struct {
- __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */
- __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */
- __O uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */
- __I uint32_t Reserved1[1];
- __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */
- __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */
- __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */
- __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */
- __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */
- __I uint32_t Reserved2[3];
- __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */
- __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */
- __O uint32_t ICM_UIHVAL[8]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */
-} Icm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */
-#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */
-#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */
-#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */
-#define ICM_CFG_BBC_Pos 4
-#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */
-#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)))
-#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */
-#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */
-#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */
-#define ICM_CFG_UALGO_Pos 13
-#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */
-#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)))
-#define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */
-#define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */
-#define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */
-#define ICM_CFG_HAPROT_Pos 16
-#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */
-#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos)))
-#define ICM_CFG_DAPROT_Pos 24
-#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */
-#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos)))
-/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */
-#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */
-#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */
-#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */
-#define ICM_CTRL_REHASH_Pos 4
-#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */
-#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)))
-#define ICM_CTRL_RMDIS_Pos 8
-#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */
-#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)))
-#define ICM_CTRL_RMEN_Pos 12
-#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */
-#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)))
-/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */
-#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */
-#define ICM_SR_RAWRMDIS_Pos 8
-#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */
-#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)))
-#define ICM_SR_RMDIS_Pos 12
-#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */
-#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)))
-/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */
-#define ICM_IER_RHC_Pos 0
-#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */
-#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)))
-#define ICM_IER_RDM_Pos 4
-#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */
-#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)))
-#define ICM_IER_RBE_Pos 8
-#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */
-#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)))
-#define ICM_IER_RWC_Pos 12
-#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */
-#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)))
-#define ICM_IER_REC_Pos 16
-#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */
-#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)))
-#define ICM_IER_RSU_Pos 20
-#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */
-#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)))
-#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */
-/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */
-#define ICM_IDR_RHC_Pos 0
-#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */
-#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)))
-#define ICM_IDR_RDM_Pos 4
-#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */
-#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)))
-#define ICM_IDR_RBE_Pos 8
-#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */
-#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)))
-#define ICM_IDR_RWC_Pos 12
-#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */
-#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)))
-#define ICM_IDR_REC_Pos 16
-#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */
-#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)))
-#define ICM_IDR_RSU_Pos 20
-#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */
-#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)))
-#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */
-/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */
-#define ICM_IMR_RHC_Pos 0
-#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */
-#define ICM_IMR_RDM_Pos 4
-#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */
-#define ICM_IMR_RBE_Pos 8
-#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */
-#define ICM_IMR_RWC_Pos 12
-#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */
-#define ICM_IMR_REC_Pos 16
-#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */
-#define ICM_IMR_RSU_Pos 20
-#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */
-#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */
-/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */
-#define ICM_ISR_RHC_Pos 0
-#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */
-#define ICM_ISR_RDM_Pos 4
-#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */
-#define ICM_ISR_RBE_Pos 8
-#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */
-#define ICM_ISR_RWC_Pos 12
-#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */
-#define ICM_ISR_REC_Pos 16
-#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */
-#define ICM_ISR_RSU_Pos 20
-#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */
-#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */
-/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */
-#define ICM_UASR_URAT_Pos 0
-#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */
-#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */
-#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */
-#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */
-#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */
-#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */
-/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */
-#define ICM_DSCR_DASA_Pos 6
-#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */
-#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)))
-/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */
-#define ICM_HASH_HASA_Pos 7
-#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */
-#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)))
-/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */
-#define ICM_UIHVAL_VAL_Pos 0
-#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[8]) Initial Hash Value */
-#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)))
-
-/*@}*/
-
-
-#endif /* _SAMS70_ICM_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/isi.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/isi.h
deleted file mode 100644
index 1ceb845..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/isi.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_ISI_COMPONENT_
-#define _SAMS70_ISI_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Image Sensor Interface */
-/* ============================================================================= */
-/** \addtogroup SAMS70_ISI Image Sensor Interface */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Isi hardware registers */
-typedef struct {
- __IO uint32_t ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */
- __IO uint32_t ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */
- __IO uint32_t ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */
- __IO uint32_t ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */
- __IO uint32_t ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */
- __IO uint32_t ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */
- __IO uint32_t ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */
- __IO uint32_t ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */
- __IO uint32_t ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */
- __O uint32_t ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */
- __I uint32_t ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */
- __O uint32_t ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */
- __O uint32_t ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */
- __I uint32_t ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */
- __O uint32_t ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */
- __O uint32_t ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */
- __I uint32_t ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */
- __IO uint32_t ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */
- __IO uint32_t ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */
- __IO uint32_t ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */
- __IO uint32_t ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */
- __IO uint32_t ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */
- __IO uint32_t ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */
- __I uint32_t Reserved1[34];
- __IO uint32_t ISI_WPMR; /**< \brief (Isi Offset: 0xE4) Write Protection Mode Register */
- __I uint32_t ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */
-} Isi;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */
-#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */
-#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */
-#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */
-#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */
-#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */
-#define ISI_CFG1_FRATE_Pos 8
-#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */
-#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos)))
-#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */
-#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */
-#define ISI_CFG1_THMASK_Pos 13
-#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */
-#define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos)))
-#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */
-#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */
-#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */
-#define ISI_CFG1_SLD_Pos 16
-#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */
-#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos)))
-#define ISI_CFG1_SFD_Pos 24
-#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */
-#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos)))
-/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */
-#define ISI_CFG2_IM_VSIZE_Pos 0
-#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] */
-#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos)))
-#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) Grayscale Pixel Format Mode */
-#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode */
-#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) Grayscale Mode Format Enable */
-#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) RGB Format Swap Mode */
-#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */
-#define ISI_CFG2_IM_HSIZE_Pos 16
-#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */
-#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos)))
-#define ISI_CFG2_YCC_SWAP_Pos 28
-#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) YCrCb Format Swap Mode */
-#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos)))
-#define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28) /**< \brief (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */
-#define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28) /**< \brief (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */
-#define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */
-#define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */
-#define ISI_CFG2_RGB_CFG_Pos 30
-#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) RGB Pixel Mapping Configuration */
-#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos)))
-#define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30) /**< \brief (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */
-#define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30) /**< \brief (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */
-#define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */
-#define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */
-/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */
-#define ISI_PSIZE_PREV_VSIZE_Pos 0
-#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */
-#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos)))
-#define ISI_PSIZE_PREV_HSIZE_Pos 16
-#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */
-#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos)))
-/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */
-#define ISI_PDECF_DEC_FACTOR_Pos 0
-#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */
-#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos)))
-/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */
-#define ISI_Y2R_SET0_C0_Pos 0
-#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */
-#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos)))
-#define ISI_Y2R_SET0_C1_Pos 8
-#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */
-#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos)))
-#define ISI_Y2R_SET0_C2_Pos 16
-#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */
-#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos)))
-#define ISI_Y2R_SET0_C3_Pos 24
-#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */
-#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos)))
-/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */
-#define ISI_Y2R_SET1_C4_Pos 0
-#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */
-#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos)))
-#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */
-#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */
-#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */
-/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */
-#define ISI_R2Y_SET0_C0_Pos 0
-#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */
-#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos)))
-#define ISI_R2Y_SET0_C1_Pos 8
-#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */
-#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos)))
-#define ISI_R2Y_SET0_C2_Pos 16
-#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */
-#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos)))
-#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */
-/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */
-#define ISI_R2Y_SET1_C3_Pos 0
-#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */
-#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos)))
-#define ISI_R2Y_SET1_C4_Pos 8
-#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */
-#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos)))
-#define ISI_R2Y_SET1_C5_Pos 16
-#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */
-#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos)))
-#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */
-/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */
-#define ISI_R2Y_SET2_C6_Pos 0
-#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */
-#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos)))
-#define ISI_R2Y_SET2_C7_Pos 8
-#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */
-#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos)))
-#define ISI_R2Y_SET2_C8_Pos 16
-#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */
-#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos)))
-#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */
-/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */
-#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */
-#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */
-#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */
-#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */
-/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */
-#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) Module Enable */
-#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated (cleared on read) */
-#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated (cleared on read) */
-#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request */
-#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization (cleared on read) */
-#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) */
-#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) */
-#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress */
-#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow (cleared on read) */
-#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow (cleared on read) */
-#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error (cleared on read) */
-#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun (cleared on read) */
-/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */
-#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */
-#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */
-#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */
-#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */
-#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */
-#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */
-#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */
-#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */
-#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */
-/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */
-#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */
-#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */
-#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */
-#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */
-#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */
-#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */
-#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */
-#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */
-#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */
-/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */
-#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */
-#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */
-#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */
-#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Completed */
-#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Completed */
-#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) Preview FIFO Overflow */
-#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) Codec FIFO Overflow */
-#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */
-#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */
-/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */
-#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */
-#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */
-/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */
-#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) Preview Channel Disable Request */
-#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) Codec Channel Disable Request */
-/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */
-#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) Preview DMA Channel Status */
-#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) Code DMA Channel Status */
-/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */
-#define ISI_DMA_P_ADDR_P_ADDR_Pos 2
-#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address */
-#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos)))
-/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */
-#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit */
-#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit */
-#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */
-#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) Preview Transfer Done */
-/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */
-#define ISI_DMA_P_DSCR_P_DSCR_Pos 2
-#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address */
-#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos)))
-/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */
-#define ISI_DMA_C_ADDR_C_ADDR_Pos 2
-#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address */
-#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos)))
-/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */
-#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit */
-#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit */
-#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done Flag Control */
-#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) Codec Transfer Done */
-/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */
-#define ISI_DMA_C_DSCR_C_DSCR_Pos 2
-#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address */
-#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos)))
-/* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */
-#define ISI_WPMR_WPEN (0x1u << 0) /**< \brief (ISI_WPMR) Write Protection Enable */
-#define ISI_WPMR_WPKEY_Pos 8
-#define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos) /**< \brief (ISI_WPMR) Write Protection Key Password */
-#define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos)))
-#define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8) /**< \brief (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
-/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */
-#define ISI_WPSR_WPVS (0x1u << 0) /**< \brief (ISI_WPSR) Write Protection Violation Status */
-#define ISI_WPSR_WPVSRC_Pos 8
-#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_ISI_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/matrix.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/matrix.h
deleted file mode 100644
index 8bb7f21..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/matrix.h
+++ /dev/null
@@ -1,476 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_MATRIX_COMPONENT_
-#define _SAMS70_MATRIX_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */
-/* ============================================================================= */
-/** \addtogroup SAMS70_MATRIX AHB Bus Matrix */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Matrix hardware registers */
-typedef struct {
- __IO uint32_t MATRIX_MCFG0; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register 0 */
- __IO uint32_t MATRIX_MCFG1; /**< \brief (Matrix Offset: 0x0004) Master Configuration Register 1 */
- __IO uint32_t MATRIX_MCFG2; /**< \brief (Matrix Offset: 0x0008) Master Configuration Register 2 */
- __IO uint32_t MATRIX_MCFG3; /**< \brief (Matrix Offset: 0x000C) Master Configuration Register 3 */
- __IO uint32_t MATRIX_MCFG4; /**< \brief (Matrix Offset: 0x0010) Master Configuration Register 4 */
- __IO uint32_t MATRIX_MCFG5; /**< \brief (Matrix Offset: 0x0014) Master Configuration Register 5 */
- __IO uint32_t MATRIX_MCFG6; /**< \brief (Matrix Offset: 0x0018) Master Configuration Register 6 */
- __I uint32_t Reserved1[1];
- __IO uint32_t MATRIX_MCFG8; /**< \brief (Matrix Offset: 0x0020) Master Configuration Register 8 */
- __I uint32_t Reserved2[7];
- __IO uint32_t MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
- __I uint32_t Reserved3[7];
- __IO uint32_t MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
- __IO uint32_t MATRIX_PRBS0; /**< \brief (Matrix Offset: 0x0084) Priority Register B for Slave 0 */
- __IO uint32_t MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
- __IO uint32_t MATRIX_PRBS1; /**< \brief (Matrix Offset: 0x008C) Priority Register B for Slave 1 */
- __IO uint32_t MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
- __IO uint32_t MATRIX_PRBS2; /**< \brief (Matrix Offset: 0x0094) Priority Register B for Slave 2 */
- __IO uint32_t MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
- __IO uint32_t MATRIX_PRBS3; /**< \brief (Matrix Offset: 0x009C) Priority Register B for Slave 3 */
- __IO uint32_t MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
- __IO uint32_t MATRIX_PRBS4; /**< \brief (Matrix Offset: 0x00A4) Priority Register B for Slave 4 */
- __IO uint32_t MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */
- __IO uint32_t MATRIX_PRBS5; /**< \brief (Matrix Offset: 0x00AC) Priority Register B for Slave 5 */
- __IO uint32_t MATRIX_PRAS6; /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */
- __IO uint32_t MATRIX_PRBS6; /**< \brief (Matrix Offset: 0x00B4) Priority Register B for Slave 6 */
- __IO uint32_t MATRIX_PRAS7; /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */
- __IO uint32_t MATRIX_PRBS7; /**< \brief (Matrix Offset: 0x00BC) Priority Register B for Slave 7 */
- __IO uint32_t MATRIX_PRAS8; /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */
- __IO uint32_t MATRIX_PRBS8; /**< \brief (Matrix Offset: 0x00C4) Priority Register B for Slave 8 */
- __I uint32_t Reserved4[14];
- __IO uint32_t MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */
- __I uint32_t Reserved5[4];
- __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration Register */
- __I uint32_t Reserved6[3];
- __IO uint32_t CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register */
- __I uint32_t Reserved7[47];
- __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register */
- __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protection Status Register */
-} Matrix;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */
-#define MATRIX_MCFG0_ULBT_Pos 0
-#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos) /**< \brief (MATRIX_MCFG0) Undefined Length Burst Type */
-#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos)))
-#define MATRIX_MCFG0_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG0) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG0_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG0) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG0_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG0) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG0_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG0) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG0_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG0) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG0_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG0) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG0_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG0) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG0_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG0) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */
-#define MATRIX_MCFG1_ULBT_Pos 0
-#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos) /**< \brief (MATRIX_MCFG1) Undefined Length Burst Type */
-#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos)))
-#define MATRIX_MCFG1_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG1) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG1_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG1) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG1_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG1) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG1_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG1) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG1_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG1) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG1_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG1) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG1_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG1) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG1_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG1) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */
-#define MATRIX_MCFG2_ULBT_Pos 0
-#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos) /**< \brief (MATRIX_MCFG2) Undefined Length Burst Type */
-#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos)))
-#define MATRIX_MCFG2_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG2) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG2_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG2) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG2_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG2) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG2_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG2) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG2_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG2) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG2_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG2) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG2_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG2) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG2_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG2) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */
-#define MATRIX_MCFG3_ULBT_Pos 0
-#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos) /**< \brief (MATRIX_MCFG3) Undefined Length Burst Type */
-#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos)))
-#define MATRIX_MCFG3_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG3) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG3_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG3) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG3_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG3) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG3_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG3) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG3_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG3) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG3_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG3) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG3_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG3) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG3_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG3) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */
-#define MATRIX_MCFG4_ULBT_Pos 0
-#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos) /**< \brief (MATRIX_MCFG4) Undefined Length Burst Type */
-#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos)))
-#define MATRIX_MCFG4_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG4) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG4_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG4) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG4_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG4) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG4_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG4) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG4_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG4) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG4_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG4) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG4_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG4) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG4_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG4) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */
-#define MATRIX_MCFG5_ULBT_Pos 0
-#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos) /**< \brief (MATRIX_MCFG5) Undefined Length Burst Type */
-#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos)))
-#define MATRIX_MCFG5_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG5) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG5_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG5) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG5_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG5) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG5_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG5) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG5_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG5) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG5_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG5) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG5_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG5) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG5_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG5) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */
-#define MATRIX_MCFG6_ULBT_Pos 0
-#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos) /**< \brief (MATRIX_MCFG6) Undefined Length Burst Type */
-#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos)))
-#define MATRIX_MCFG6_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG6) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG6_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG6) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG6_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG6) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG6_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG6) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG6_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG6) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG6_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG6) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG6_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG6) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG6_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG6) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */
-#define MATRIX_MCFG8_ULBT_Pos 0
-#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos) /**< \brief (MATRIX_MCFG8) Undefined Length Burst Type */
-#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos)))
-#define MATRIX_MCFG8_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG8) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG8_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG8) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG8_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG8) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG8_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG8) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG8_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG8) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG8_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG8) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG8_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG8) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG8_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG8) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
-#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
-#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Bus Grant Duration for Masters */
-#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
-#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
-#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */
-#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
-#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG[9]) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
-#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG[9]) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
-#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
-#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
-#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */
-#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
-/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
-#define MATRIX_PRAS0_M0PR_Pos 0
-#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
-#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
-#define MATRIX_PRAS0_M1PR_Pos 4
-#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
-#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
-#define MATRIX_PRAS0_M2PR_Pos 8
-#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
-#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
-#define MATRIX_PRAS0_M3PR_Pos 12
-#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
-#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
-#define MATRIX_PRAS0_M4PR_Pos 16
-#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
-#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
-#define MATRIX_PRAS0_M5PR_Pos 20
-#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos) /**< \brief (MATRIX_PRAS0) Master 5 Priority */
-#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos)))
-#define MATRIX_PRAS0_M6PR_Pos 24
-#define MATRIX_PRAS0_M6PR_Msk (0x3u << MATRIX_PRAS0_M6PR_Pos) /**< \brief (MATRIX_PRAS0) Master 6 Priority */
-#define MATRIX_PRAS0_M6PR(value) ((MATRIX_PRAS0_M6PR_Msk & ((value) << MATRIX_PRAS0_M6PR_Pos)))
-/* -------- MATRIX_PRBS0 : (MATRIX Offset: 0x0084) Priority Register B for Slave 0 -------- */
-#define MATRIX_PRBS0_M8PR_Pos 0
-#define MATRIX_PRBS0_M8PR_Msk (0x3u << MATRIX_PRBS0_M8PR_Pos) /**< \brief (MATRIX_PRBS0) Master 8 Priority */
-#define MATRIX_PRBS0_M8PR(value) ((MATRIX_PRBS0_M8PR_Msk & ((value) << MATRIX_PRBS0_M8PR_Pos)))
-/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
-#define MATRIX_PRAS1_M0PR_Pos 0
-#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
-#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
-#define MATRIX_PRAS1_M1PR_Pos 4
-#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
-#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
-#define MATRIX_PRAS1_M2PR_Pos 8
-#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
-#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
-#define MATRIX_PRAS1_M3PR_Pos 12
-#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
-#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
-#define MATRIX_PRAS1_M4PR_Pos 16
-#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
-#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
-#define MATRIX_PRAS1_M5PR_Pos 20
-#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos) /**< \brief (MATRIX_PRAS1) Master 5 Priority */
-#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos)))
-#define MATRIX_PRAS1_M6PR_Pos 24
-#define MATRIX_PRAS1_M6PR_Msk (0x3u << MATRIX_PRAS1_M6PR_Pos) /**< \brief (MATRIX_PRAS1) Master 6 Priority */
-#define MATRIX_PRAS1_M6PR(value) ((MATRIX_PRAS1_M6PR_Msk & ((value) << MATRIX_PRAS1_M6PR_Pos)))
-/* -------- MATRIX_PRBS1 : (MATRIX Offset: 0x008C) Priority Register B for Slave 1 -------- */
-#define MATRIX_PRBS1_M8PR_Pos 0
-#define MATRIX_PRBS1_M8PR_Msk (0x3u << MATRIX_PRBS1_M8PR_Pos) /**< \brief (MATRIX_PRBS1) Master 8 Priority */
-#define MATRIX_PRBS1_M8PR(value) ((MATRIX_PRBS1_M8PR_Msk & ((value) << MATRIX_PRBS1_M8PR_Pos)))
-/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
-#define MATRIX_PRAS2_M0PR_Pos 0
-#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
-#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
-#define MATRIX_PRAS2_M1PR_Pos 4
-#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
-#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
-#define MATRIX_PRAS2_M2PR_Pos 8
-#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
-#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
-#define MATRIX_PRAS2_M3PR_Pos 12
-#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
-#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
-#define MATRIX_PRAS2_M4PR_Pos 16
-#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
-#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
-#define MATRIX_PRAS2_M5PR_Pos 20
-#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos) /**< \brief (MATRIX_PRAS2) Master 5 Priority */
-#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos)))
-#define MATRIX_PRAS2_M6PR_Pos 24
-#define MATRIX_PRAS2_M6PR_Msk (0x3u << MATRIX_PRAS2_M6PR_Pos) /**< \brief (MATRIX_PRAS2) Master 6 Priority */
-#define MATRIX_PRAS2_M6PR(value) ((MATRIX_PRAS2_M6PR_Msk & ((value) << MATRIX_PRAS2_M6PR_Pos)))
-/* -------- MATRIX_PRBS2 : (MATRIX Offset: 0x0094) Priority Register B for Slave 2 -------- */
-#define MATRIX_PRBS2_M8PR_Pos 0
-#define MATRIX_PRBS2_M8PR_Msk (0x3u << MATRIX_PRBS2_M8PR_Pos) /**< \brief (MATRIX_PRBS2) Master 8 Priority */
-#define MATRIX_PRBS2_M8PR(value) ((MATRIX_PRBS2_M8PR_Msk & ((value) << MATRIX_PRBS2_M8PR_Pos)))
-/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
-#define MATRIX_PRAS3_M0PR_Pos 0
-#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
-#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
-#define MATRIX_PRAS3_M1PR_Pos 4
-#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
-#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
-#define MATRIX_PRAS3_M2PR_Pos 8
-#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
-#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
-#define MATRIX_PRAS3_M3PR_Pos 12
-#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
-#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
-#define MATRIX_PRAS3_M4PR_Pos 16
-#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
-#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
-#define MATRIX_PRAS3_M5PR_Pos 20
-#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos) /**< \brief (MATRIX_PRAS3) Master 5 Priority */
-#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos)))
-#define MATRIX_PRAS3_M6PR_Pos 24
-#define MATRIX_PRAS3_M6PR_Msk (0x3u << MATRIX_PRAS3_M6PR_Pos) /**< \brief (MATRIX_PRAS3) Master 6 Priority */
-#define MATRIX_PRAS3_M6PR(value) ((MATRIX_PRAS3_M6PR_Msk & ((value) << MATRIX_PRAS3_M6PR_Pos)))
-/* -------- MATRIX_PRBS3 : (MATRIX Offset: 0x009C) Priority Register B for Slave 3 -------- */
-#define MATRIX_PRBS3_M8PR_Pos 0
-#define MATRIX_PRBS3_M8PR_Msk (0x3u << MATRIX_PRBS3_M8PR_Pos) /**< \brief (MATRIX_PRBS3) Master 8 Priority */
-#define MATRIX_PRBS3_M8PR(value) ((MATRIX_PRBS3_M8PR_Msk & ((value) << MATRIX_PRBS3_M8PR_Pos)))
-/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
-#define MATRIX_PRAS4_M0PR_Pos 0
-#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
-#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
-#define MATRIX_PRAS4_M1PR_Pos 4
-#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
-#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
-#define MATRIX_PRAS4_M2PR_Pos 8
-#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
-#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
-#define MATRIX_PRAS4_M3PR_Pos 12
-#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
-#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
-#define MATRIX_PRAS4_M4PR_Pos 16
-#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
-#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
-#define MATRIX_PRAS4_M5PR_Pos 20
-#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos) /**< \brief (MATRIX_PRAS4) Master 5 Priority */
-#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos)))
-#define MATRIX_PRAS4_M6PR_Pos 24
-#define MATRIX_PRAS4_M6PR_Msk (0x3u << MATRIX_PRAS4_M6PR_Pos) /**< \brief (MATRIX_PRAS4) Master 6 Priority */
-#define MATRIX_PRAS4_M6PR(value) ((MATRIX_PRAS4_M6PR_Msk & ((value) << MATRIX_PRAS4_M6PR_Pos)))
-/* -------- MATRIX_PRBS4 : (MATRIX Offset: 0x00A4) Priority Register B for Slave 4 -------- */
-#define MATRIX_PRBS4_M8PR_Pos 0
-#define MATRIX_PRBS4_M8PR_Msk (0x3u << MATRIX_PRBS4_M8PR_Pos) /**< \brief (MATRIX_PRBS4) Master 8 Priority */
-#define MATRIX_PRBS4_M8PR(value) ((MATRIX_PRBS4_M8PR_Msk & ((value) << MATRIX_PRBS4_M8PR_Pos)))
-/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */
-#define MATRIX_PRAS5_M0PR_Pos 0
-#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */
-#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))
-#define MATRIX_PRAS5_M1PR_Pos 4
-#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */
-#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))
-#define MATRIX_PRAS5_M2PR_Pos 8
-#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */
-#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))
-#define MATRIX_PRAS5_M3PR_Pos 12
-#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */
-#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))
-#define MATRIX_PRAS5_M4PR_Pos 16
-#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */
-#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))
-#define MATRIX_PRAS5_M5PR_Pos 20
-#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos) /**< \brief (MATRIX_PRAS5) Master 5 Priority */
-#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos)))
-#define MATRIX_PRAS5_M6PR_Pos 24
-#define MATRIX_PRAS5_M6PR_Msk (0x3u << MATRIX_PRAS5_M6PR_Pos) /**< \brief (MATRIX_PRAS5) Master 6 Priority */
-#define MATRIX_PRAS5_M6PR(value) ((MATRIX_PRAS5_M6PR_Msk & ((value) << MATRIX_PRAS5_M6PR_Pos)))
-/* -------- MATRIX_PRBS5 : (MATRIX Offset: 0x00AC) Priority Register B for Slave 5 -------- */
-#define MATRIX_PRBS5_M8PR_Pos 0
-#define MATRIX_PRBS5_M8PR_Msk (0x3u << MATRIX_PRBS5_M8PR_Pos) /**< \brief (MATRIX_PRBS5) Master 8 Priority */
-#define MATRIX_PRBS5_M8PR(value) ((MATRIX_PRBS5_M8PR_Msk & ((value) << MATRIX_PRBS5_M8PR_Pos)))
-/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */
-#define MATRIX_PRAS6_M0PR_Pos 0
-#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */
-#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos)))
-#define MATRIX_PRAS6_M1PR_Pos 4
-#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */
-#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos)))
-#define MATRIX_PRAS6_M2PR_Pos 8
-#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */
-#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos)))
-#define MATRIX_PRAS6_M3PR_Pos 12
-#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */
-#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos)))
-#define MATRIX_PRAS6_M4PR_Pos 16
-#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */
-#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos)))
-#define MATRIX_PRAS6_M5PR_Pos 20
-#define MATRIX_PRAS6_M5PR_Msk (0x3u << MATRIX_PRAS6_M5PR_Pos) /**< \brief (MATRIX_PRAS6) Master 5 Priority */
-#define MATRIX_PRAS6_M5PR(value) ((MATRIX_PRAS6_M5PR_Msk & ((value) << MATRIX_PRAS6_M5PR_Pos)))
-#define MATRIX_PRAS6_M6PR_Pos 24
-#define MATRIX_PRAS6_M6PR_Msk (0x3u << MATRIX_PRAS6_M6PR_Pos) /**< \brief (MATRIX_PRAS6) Master 6 Priority */
-#define MATRIX_PRAS6_M6PR(value) ((MATRIX_PRAS6_M6PR_Msk & ((value) << MATRIX_PRAS6_M6PR_Pos)))
-/* -------- MATRIX_PRBS6 : (MATRIX Offset: 0x00B4) Priority Register B for Slave 6 -------- */
-#define MATRIX_PRBS6_M8PR_Pos 0
-#define MATRIX_PRBS6_M8PR_Msk (0x3u << MATRIX_PRBS6_M8PR_Pos) /**< \brief (MATRIX_PRBS6) Master 8 Priority */
-#define MATRIX_PRBS6_M8PR(value) ((MATRIX_PRBS6_M8PR_Msk & ((value) << MATRIX_PRBS6_M8PR_Pos)))
-/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */
-#define MATRIX_PRAS7_M0PR_Pos 0
-#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */
-#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos)))
-#define MATRIX_PRAS7_M1PR_Pos 4
-#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */
-#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos)))
-#define MATRIX_PRAS7_M2PR_Pos 8
-#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */
-#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos)))
-#define MATRIX_PRAS7_M3PR_Pos 12
-#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */
-#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos)))
-#define MATRIX_PRAS7_M4PR_Pos 16
-#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */
-#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos)))
-#define MATRIX_PRAS7_M5PR_Pos 20
-#define MATRIX_PRAS7_M5PR_Msk (0x3u << MATRIX_PRAS7_M5PR_Pos) /**< \brief (MATRIX_PRAS7) Master 5 Priority */
-#define MATRIX_PRAS7_M5PR(value) ((MATRIX_PRAS7_M5PR_Msk & ((value) << MATRIX_PRAS7_M5PR_Pos)))
-#define MATRIX_PRAS7_M6PR_Pos 24
-#define MATRIX_PRAS7_M6PR_Msk (0x3u << MATRIX_PRAS7_M6PR_Pos) /**< \brief (MATRIX_PRAS7) Master 6 Priority */
-#define MATRIX_PRAS7_M6PR(value) ((MATRIX_PRAS7_M6PR_Msk & ((value) << MATRIX_PRAS7_M6PR_Pos)))
-/* -------- MATRIX_PRBS7 : (MATRIX Offset: 0x00BC) Priority Register B for Slave 7 -------- */
-#define MATRIX_PRBS7_M8PR_Pos 0
-#define MATRIX_PRBS7_M8PR_Msk (0x3u << MATRIX_PRBS7_M8PR_Pos) /**< \brief (MATRIX_PRBS7) Master 8 Priority */
-#define MATRIX_PRBS7_M8PR(value) ((MATRIX_PRBS7_M8PR_Msk & ((value) << MATRIX_PRBS7_M8PR_Pos)))
-/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */
-#define MATRIX_PRAS8_M0PR_Pos 0
-#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */
-#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos)))
-#define MATRIX_PRAS8_M1PR_Pos 4
-#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */
-#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos)))
-#define MATRIX_PRAS8_M2PR_Pos 8
-#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */
-#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos)))
-#define MATRIX_PRAS8_M3PR_Pos 12
-#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */
-#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos)))
-#define MATRIX_PRAS8_M4PR_Pos 16
-#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */
-#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos)))
-#define MATRIX_PRAS8_M5PR_Pos 20
-#define MATRIX_PRAS8_M5PR_Msk (0x3u << MATRIX_PRAS8_M5PR_Pos) /**< \brief (MATRIX_PRAS8) Master 5 Priority */
-#define MATRIX_PRAS8_M5PR(value) ((MATRIX_PRAS8_M5PR_Msk & ((value) << MATRIX_PRAS8_M5PR_Pos)))
-#define MATRIX_PRAS8_M6PR_Pos 24
-#define MATRIX_PRAS8_M6PR_Msk (0x3u << MATRIX_PRAS8_M6PR_Pos) /**< \brief (MATRIX_PRAS8) Master 6 Priority */
-#define MATRIX_PRAS8_M6PR(value) ((MATRIX_PRAS8_M6PR_Msk & ((value) << MATRIX_PRAS8_M6PR_Pos)))
-/* -------- MATRIX_PRBS8 : (MATRIX Offset: 0x00C4) Priority Register B for Slave 8 -------- */
-#define MATRIX_PRBS8_M8PR_Pos 0
-#define MATRIX_PRBS8_M8PR_Msk (0x3u << MATRIX_PRBS8_M8PR_Pos) /**< \brief (MATRIX_PRBS8) Master 8 Priority */
-#define MATRIX_PRBS8_M8PR(value) ((MATRIX_PRBS8_M8PR_Msk & ((value) << MATRIX_PRBS8_M8PR_Pos)))
-/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
-#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 */
-#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 */
-#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 */
-#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 */
-#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 */
-#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 */
-#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 */
-#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 8 */
-/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration Register -------- */
-#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */
-#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */
-#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */
-#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */
-#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */
-/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */
-#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */
-#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */
-#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */
-#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */
-#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) /**< \brief (CCFG_SMCNFCS) SDRAM Enable */
-/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */
-#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */
-#define MATRIX_WPMR_WPKEY_Pos 8
-#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key */
-#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
-#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
-/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */
-#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */
-#define MATRIX_WPSR_WPVSRC_Pos 8
-#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_MATRIX_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/pio.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/pio.h
deleted file mode 100644
index 94bc5c2..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/pio.h
+++ /dev/null
@@ -1,1629 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PIO_COMPONENT_
-#define _SAMS70_PIO_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_PIO Parallel Input/Output Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Pio hardware registers */
-typedef struct {
- __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
- __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
- __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */
- __I uint32_t Reserved1[1];
- __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */
- __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */
- __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */
- __I uint32_t Reserved2[1];
- __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
- __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
- __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
- __I uint32_t Reserved3[1];
- __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
- __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
- __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
- __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
- __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
- __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
- __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
- __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
- __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
- __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
- __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
- __I uint32_t Reserved4[1];
- __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
- __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
- __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
- __I uint32_t Reserved5[1];
- __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */
- __I uint32_t Reserved6[2];
- __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */
- __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */
- __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */
- __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
- __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */
- __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */
- __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */
- __I uint32_t Reserved7[1];
- __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
- __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
- __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
- __I uint32_t Reserved8[1];
- __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
- __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */
- __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
- __I uint32_t Reserved9[1];
- __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
- __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */
- __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
- __I uint32_t Reserved10[1];
- __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */
- __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register */
- __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
- __I uint32_t Reserved11[1];
- __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */
- __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */
- __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */
- __I uint32_t Reserved12[5];
- __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */
- __I uint32_t Reserved13[5];
- __IO uint32_t PIO_DRIVER; /**< \brief (Pio Offset: 0x0118) I/O Drive Register */
- __I uint32_t Reserved14[13];
- __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x0150) Parallel Capture Mode Register */
- __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x0154) Parallel Capture Interrupt Enable Register */
- __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x0158) Parallel Capture Interrupt Disable Register */
- __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x015C) Parallel Capture Interrupt Mask Register */
- __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x0160) Parallel Capture Interrupt Status Register */
- __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x0164) Parallel Capture Reception Holding Register */
-} Pio;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
-#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
-/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
-#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
-/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
-#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
-/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
-#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
-/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
-#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
-/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
-#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
-/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
-#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
-/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
-#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
-/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
-#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filter Status */
-/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
-#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
-/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
-#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
-/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
-#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
-/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
-#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
-/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
-#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
-#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
-#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
-#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
-#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-drive Enable */
-/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
-#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-drive Disable */
-/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
-#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-drive Status */
-/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
-#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */
-/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
-#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */
-/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
-#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */
-/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
-#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */
-#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */
-#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */
-#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
-#define PIO_SCDR_DIV_Pos 0
-#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
-/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
-#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
-#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */
-/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
-#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */
-/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
-#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */
-/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
-#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */
-/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
-#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */
-/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
-#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */
-#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
-#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) IO Line Index */
-/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
-#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
-#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */
-/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
-#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */
-#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/High-Level Select Register -------- */
-#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
-#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
-#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */
-/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */
-#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */
-#define PIO_WPMR_WPKEY_Pos 8
-#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */
-#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
-#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
-/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */
-#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */
-#define PIO_WPSR_WPVSRC_Pos 8
-#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */
-/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
-#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-/* -------- PIO_PCMR : (PIO Offset: 0x0150) Parallel Capture Mode Register -------- */
-#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */
-#define PIO_PCMR_DSIZE_Pos 4
-#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */
-#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos)))
-#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */
-#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */
-#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */
-#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */
-#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */
-#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */
-/* -------- PIO_PCIER : (PIO Offset: 0x0154) Parallel Capture Interrupt Enable Register -------- */
-#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */
-#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */
-#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */
-#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */
-/* -------- PIO_PCIDR : (PIO Offset: 0x0158) Parallel Capture Interrupt Disable Register -------- */
-#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */
-#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */
-#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */
-#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */
-/* -------- PIO_PCIMR : (PIO Offset: 0x015C) Parallel Capture Interrupt Mask Register -------- */
-#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */
-#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */
-#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */
-#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */
-/* -------- PIO_PCISR : (PIO Offset: 0x0160) Parallel Capture Interrupt Status Register -------- */
-#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */
-#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error */
-/* -------- PIO_PCRHR : (PIO Offset: 0x0164) Parallel Capture Reception Holding Register -------- */
-#define PIO_PCRHR_RDATA_Pos 0
-#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data */
-
-/*@}*/
-
-
-#endif /* _SAMS70_PIO_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/pmc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/pmc.h
deleted file mode 100644
index 0c973cf..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/pmc.h
+++ /dev/null
@@ -1,736 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PMC_COMPONENT_
-#define _SAMS70_PMC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Power Management Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_PMC Power Management Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Pmc hardware registers */
-typedef struct {
- __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
- __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
- __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
- __I uint32_t Reserved1[1];
- __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
- __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
- __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
- __IO uint32_t CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */
- __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
- __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
- __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */
- __I uint32_t Reserved2[1];
- __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
- __I uint32_t Reserved3[1];
- __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
- __I uint32_t Reserved4[1];
- __IO uint32_t PMC_PCK[7]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
- __I uint32_t Reserved5[1];
- __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
- __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
- __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */
- __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
- __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
- __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
- __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
- __I uint32_t Reserved6[26];
- __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */
- __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */
- __I uint32_t Reserved7[5];
- __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
- __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
- __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
- __IO uint32_t PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */
- __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */
- __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x0114) SleepWalking Enable Register 0 */
- __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x0118) SleepWalking Disable Register 0 */
- __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x011C) SleepWalking Status Register 0 */
- __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0 */
- __I uint32_t Reserved8[4];
- __O uint32_t PMC_SLPWK_ER1; /**< \brief (Pmc Offset: 0x0134) SleepWalking Enable Register 1 */
- __O uint32_t PMC_SLPWK_DR1; /**< \brief (Pmc Offset: 0x0138) SleepWalking Disable Register 1 */
- __I uint32_t PMC_SLPWK_SR1; /**< \brief (Pmc Offset: 0x013C) SleepWalking Status Register 1 */
- __I uint32_t PMC_SLPWK_ASR1; /**< \brief (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1 */
- __I uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register */
-} Pmc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
-#define PMC_SCER_USBCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB FS Clock */
-#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
-#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
-#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
-#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */
-#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */
-#define PMC_SCER_PCK5 (0x1u << 13) /**< \brief (PMC_SCER) Programmable Clock 5 Output Enable */
-#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */
-/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
-#define PMC_SCDR_USBCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB FS Clock */
-#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
-#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
-#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
-#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */
-#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */
-#define PMC_SCDR_PCK5 (0x1u << 13) /**< \brief (PMC_SCDR) Programmable Clock 5 Output Disable */
-#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */
-/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
-#define PMC_SCSR_USBCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB FS Clock Status */
-#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
-#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
-#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
-#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */
-#define PMC_SCSR_PCK4 (0x1u << 12) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */
-#define PMC_SCSR_PCK5 (0x1u << 13) /**< \brief (PMC_SCSR) Programmable Clock 5 Output Status */
-#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */
-/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
-#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
-#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
-#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
-#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
-#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
-#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
-#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
-#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
-#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
-#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
-#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */
-#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
-#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
-#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
-#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
-#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
-#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
-#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
-#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
-#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
-#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
-#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
-#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
-#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
-#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
-/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
-#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
-#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
-#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
-#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
-#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
-#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
-#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
-#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
-#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
-#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
-#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */
-#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
-#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
-#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
-#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
-#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
-#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
-#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
-#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
-#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
-#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
-#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
-#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
-#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
-#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
-/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
-#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
-#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
-#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
-#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
-#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
-#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
-#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
-#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
-#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
-#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
-#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */
-#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
-#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
-#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
-#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
-#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
-#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
-#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
-#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
-#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
-#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
-#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
-#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
-#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
-#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
-/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
-#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */
-#define CKGR_UCKR_UPLLCOUNT_Pos 20
-#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */
-#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
-/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
-#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
-#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
-#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command (Write-only) */
-#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
-#define CKGR_MOR_MOSCRCF_Pos 4
-#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
-#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)))
-#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 4 MHz (default) */
-#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 8 MHz */
-#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 12 MHz */
-#define CKGR_MOR_MOSCXTST_Pos 8
-#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
-#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
-#define CKGR_MOR_KEY_Pos 16
-#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */
-#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
-#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */
-#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
-#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
-#define CKGR_MOR_XT32KFME (0x1u << 26) /**< \brief (CKGR_MOR) Slow Crystal Oscillator Frequency Monitoring Enable */
-/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
-#define CKGR_MCFR_MAINF_Pos 0
-#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
-#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))
-#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready */
-#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */
-#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */
-/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
-#define CKGR_PLLAR_DIVA_Pos 0
-#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) PLLA Front End Divider */
-#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
-#define CKGR_PLLAR_DIVA_0 (0x0u << 0) /**< \brief (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */
-#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /**< \brief (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */
-#define CKGR_PLLAR_PLLACOUNT_Pos 8
-#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
-#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
-#define CKGR_PLLAR_MULA_Pos 16
-#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
-#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
-#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
-/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
-#define PMC_MCKR_CSS_Pos 0
-#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
-#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)))
-#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
-#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
-#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
-#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) Divided UPLL Clock is selected */
-#define PMC_MCKR_PRES_Pos 4
-#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
-#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)))
-#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
-#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
-#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
-#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
-#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
-#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
-#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
-#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
-#define PMC_MCKR_MDIV_Pos 8
-#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */
-#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)))
-#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */
-#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */
-#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */
-#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */
-#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */
-/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
-#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */
-#define PMC_USB_USBDIV_Pos 8
-#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */
-#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
-/* -------- PMC_PCK[7] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
-#define PMC_PCK_CSS_Pos 0
-#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[7]) Master Clock Source Selection */
-#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)))
-#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[7]) Slow Clock is selected */
-#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[7]) Main Clock is selected */
-#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[7]) PLLA Clock is selected */
-#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[7]) Divided UPLL Clock is selected */
-#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[7]) Master Clock is selected */
-#define PMC_PCK_PRES_Pos 4
-#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[7]) Programmable Clock Prescaler */
-#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
-/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
-#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
-#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
-#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
-#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */
-#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
-#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
-#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
-#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */
-#define PMC_IER_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable */
-#define PMC_IER_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable */
-#define PMC_IER_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable */
-#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
-#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
-#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
-#define PMC_IER_XT32KERR (0x1u << 21) /**< \brief (PMC_IER) Slow Crystal Oscillator Error Interrupt Enable */
-/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
-#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
-#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
-#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
-#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */
-#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
-#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
-#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
-#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */
-#define PMC_IDR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable */
-#define PMC_IDR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable */
-#define PMC_IDR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable */
-#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
-#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
-#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
-#define PMC_IDR_XT32KERR (0x1u << 21) /**< \brief (PMC_IDR) Slow Crystal Oscillator Error Interrupt Disable */
-/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
-#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main Crystal Oscillator Status */
-#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
-#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
-#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */
-#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
-#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
-#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
-#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
-#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
-#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
-#define PMC_SR_XT32KERR (0x1u << 21) /**< \brief (PMC_SR) Slow Crystal Oscillator Error */
-/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
-#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
-#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
-#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
-#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */
-#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
-#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
-#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
-#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
-#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
-#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
-#define PMC_IMR_XT32KERR (0x1u << 21) /**< \brief (PMC_IMR) Slow Crystal Oscillator Error Interrupt Mask */
-/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
-#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
-#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
-#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
-#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
-#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
-#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
-#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
-#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
-#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
-#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
-#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
-#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
-#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
-#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
-#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
-#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
-#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
-#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
-#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
-#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */
-#define PMC_FSMR_FLPM_Pos 21
-#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */
-#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos)))
-#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */
-#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */
-#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) Idle mode */
-#define PMC_FSMR_FFLPM (0x1u << 23) /**< \brief (PMC_FSMR) Force Flash Low-power Mode */
-/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
-#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */
-#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 1 */
-#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 2 */
-#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 3 */
-#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 4 */
-#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 5 */
-#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 6 */
-#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 7 */
-#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 8 */
-#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 9 */
-#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 10 */
-#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 11 */
-#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 12 */
-#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 13 */
-#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 14 */
-#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 15 */
-/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
-#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
-/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */
-#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */
-#define PMC_WPMR_WPKEY_Pos 8
-#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */
-#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
-#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
-/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */
-#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */
-#define PMC_WPSR_WPVSRC_Pos 8
-#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */
-/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
-#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
-#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
-#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
-#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */
-#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */
-#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */
-#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */
-#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */
-#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */
-#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */
-#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */
-#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */
-#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */
-#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */
-#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */
-#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */
-#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */
-#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */
-#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */
-#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */
-#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */
-#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */
-#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */
-#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */
-#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */
-/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
-#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
-#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
-#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
-#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */
-#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */
-#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */
-#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */
-#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */
-#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */
-#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */
-#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */
-#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */
-#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */
-#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */
-#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */
-#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */
-#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */
-#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */
-#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */
-#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */
-#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */
-#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */
-#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */
-#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */
-#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */
-/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
-#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
-#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
-#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
-#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */
-#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */
-#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */
-#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */
-#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */
-#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */
-#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */
-#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */
-#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */
-#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */
-#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */
-#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */
-#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */
-#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */
-#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */
-#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */
-#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */
-#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */
-#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */
-#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */
-#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */
-#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */
-/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */
-#define PMC_PCR_PID_Pos 0
-#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */
-#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))
-#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */
-#define PMC_PCR_DIV_Pos 16
-#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */
-#define PMC_PCR_DIV(value) ((PMC_PCR_DIV_Msk & ((value) << PMC_PCR_DIV_Pos)))
-#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */
-#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */
-#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */
-#define PMC_PCR_DIV_PERIPH_DIV8_MCK (0x3u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/8 */
-#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */
-/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
-#define PMC_OCR_CAL4_Pos 0
-#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */
-#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
-#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */
-#define PMC_OCR_CAL8_Pos 8
-#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */
-#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
-#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */
-#define PMC_OCR_CAL12_Pos 16
-#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */
-#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
-#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */
-/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */
-#define PMC_SLPWK_ER0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable */
-/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */
-#define PMC_SLPWK_DR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable */
-/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */
-#define PMC_SLPWK_SR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status */
-/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */
-#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR0) Peripheral 7 Activity Status */
-#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */
-#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */
-#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */
-#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */
-#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */
-#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */
-#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */
-#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */
-#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */
-#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */
-#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */
-#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */
-#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */
-#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */
-#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */
-#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */
-#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */
-#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */
-#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */
-#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */
-#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */
-#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */
-#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ASR0) Peripheral 30 Activity Status */
-#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ASR0) Peripheral 31 Activity Status */
-/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */
-#define PMC_SLPWK_ER1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable */
-/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */
-#define PMC_SLPWK_DR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable */
-/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */
-#define PMC_SLPWK_SR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status */
-/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */
-#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ASR1) Peripheral 32 Activity Status */
-#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ASR1) Peripheral 33 Activity Status */
-#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ASR1) Peripheral 34 Activity Status */
-#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ASR1) Peripheral 35 Activity Status */
-#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ASR1) Peripheral 37 Activity Status */
-#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR1) Peripheral 39 Activity Status */
-#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR1) Peripheral 40 Activity Status */
-#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR1) Peripheral 41 Activity Status */
-#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR1) Peripheral 42 Activity Status */
-#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR1) Peripheral 43 Activity Status */
-#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR1) Peripheral 44 Activity Status */
-#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR1) Peripheral 45 Activity Status */
-#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR1) Peripheral 46 Activity Status */
-#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR1) Peripheral 47 Activity Status */
-#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR1) Peripheral 48 Activity Status */
-#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR1) Peripheral 49 Activity Status */
-#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR1) Peripheral 50 Activity Status */
-#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR1) Peripheral 51 Activity Status */
-#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR1) Peripheral 52 Activity Status */
-#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR1) Peripheral 53 Activity Status */
-#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR1) Peripheral 56 Activity Status */
-#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR1) Peripheral 57 Activity Status */
-#define PMC_SLPWK_ASR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR1) Peripheral 58 Activity Status */
-#define PMC_SLPWK_ASR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR1) Peripheral 59 Activity Status */
-#define PMC_SLPWK_ASR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR1) Peripheral 60 Activity Status */
-/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */
-#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */
-
-/*@}*/
-
-
-#endif /* _SAMS70_PMC_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/pwm.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/pwm.h
deleted file mode 100644
index fb3c8fb..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/pwm.h
+++ /dev/null
@@ -1,715 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PWM_COMPONENT_
-#define _SAMS70_PWM_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_PWM Pulse Width Modulation Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief PwmCh_num hardware registers */
-typedef struct {
- __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
- __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
- __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
- __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
- __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
- __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
- __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
- __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
-} PwmCh_num;
-/** \brief PwmCmp hardware registers */
-typedef struct {
- __IO uint32_t PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
- __O uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
- __IO uint32_t PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
- __O uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
-} PwmCmp;
-/** \brief Pwm hardware registers */
-#define PWMCMP_NUMBER 8
-#define PWMCH_NUM_NUMBER 4
-typedef struct {
- __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
- __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
- __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
- __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
- __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
- __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
- __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
- __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
- __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
- __O uint32_t PWM_DMAR; /**< \brief (Pwm Offset: 0x24) PWM DMA Register */
- __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
- __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
- __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
- __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
- __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
- __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
- __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
- __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
- __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
- __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
- __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
- __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
- __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
- __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
- __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
- __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
- __IO uint32_t PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */
- __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
- __I uint32_t Reserved1[3];
- __IO uint32_t PWM_ELMR[8]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
- __I uint32_t Reserved2[1];
- __IO uint32_t PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */
- __O uint32_t PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */
- __I uint32_t Reserved3[2];
- __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
- __I uint32_t Reserved4[3];
- __IO uint32_t PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */
- __I uint32_t Reserved5[8];
- __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */
- __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */
- __I uint32_t Reserved6[17];
- PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
- __I uint32_t Reserved7[20];
- PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
- __I uint32_t Reserved8[96];
- __O uint32_t PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */
- __I uint32_t Reserved9[7];
- __O uint32_t PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */
- __I uint32_t Reserved10[2];
- __IO uint32_t PWM_ETRG1; /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */
- __IO uint32_t PWM_LEBR1; /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */
- __I uint32_t Reserved11[3];
- __O uint32_t PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */
- __I uint32_t Reserved12[2];
- __IO uint32_t PWM_ETRG2; /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */
- __IO uint32_t PWM_LEBR2; /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */
- __I uint32_t Reserved13[3];
- __O uint32_t PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */
- __I uint32_t Reserved14[2];
- __IO uint32_t PWM_ETRG3; /**< \brief (Pwm Offset: 0x46C) PWM External Trigger Register (trg_num = 3) */
- __IO uint32_t PWM_LEBR3; /**< \brief (Pwm Offset: 0x470) PWM Leading-Edge Blanking Register (trg_num = 3) */
- __I uint32_t Reserved15[6];
- __IO uint32_t PWM_ETRG4; /**< \brief (Pwm Offset: 0x48C) PWM External Trigger Register (trg_num = 4) */
- __IO uint32_t PWM_LEBR4; /**< \brief (Pwm Offset: 0x490) PWM Leading-Edge Blanking Register (trg_num = 4) */
-} Pwm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
-#define PWM_CLK_DIVA_Pos 0
-#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA Divide Factor */
-#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
-#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) /**< \brief (PWM_CLK) CLKA clock is turned off */
-#define PWM_CLK_DIVA_PREA (0x1u << 0) /**< \brief (PWM_CLK) CLKA clock is clock selected by PREA */
-#define PWM_CLK_PREA_Pos 8
-#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA Source Clock Selection */
-#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
-#define PWM_CLK_PREA_CLK (0x0u << 8) /**< \brief (PWM_CLK) Peripheral clock */
-#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) /**< \brief (PWM_CLK) Peripheral clock/2 */
-#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) /**< \brief (PWM_CLK) Peripheral clock/4 */
-#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) /**< \brief (PWM_CLK) Peripheral clock/8 */
-#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) /**< \brief (PWM_CLK) Peripheral clock/16 */
-#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) /**< \brief (PWM_CLK) Peripheral clock/32 */
-#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) /**< \brief (PWM_CLK) Peripheral clock/64 */
-#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) /**< \brief (PWM_CLK) Peripheral clock/128 */
-#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) /**< \brief (PWM_CLK) Peripheral clock/256 */
-#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) /**< \brief (PWM_CLK) Peripheral clock/512 */
-#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) /**< \brief (PWM_CLK) Peripheral clock/1024 */
-#define PWM_CLK_DIVB_Pos 16
-#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKB Divide Factor */
-#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
-#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) /**< \brief (PWM_CLK) CLKB clock is turned off */
-#define PWM_CLK_DIVB_PREB (0x1u << 16) /**< \brief (PWM_CLK) CLKB clock is clock selected by PREB */
-#define PWM_CLK_PREB_Pos 24
-#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKB Source Clock Selection */
-#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
-#define PWM_CLK_PREB_CLK (0x0u << 24) /**< \brief (PWM_CLK) Peripheral clock */
-#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) /**< \brief (PWM_CLK) Peripheral clock/2 */
-#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) /**< \brief (PWM_CLK) Peripheral clock/4 */
-#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) /**< \brief (PWM_CLK) Peripheral clock/8 */
-#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) /**< \brief (PWM_CLK) Peripheral clock/16 */
-#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) /**< \brief (PWM_CLK) Peripheral clock/32 */
-#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) /**< \brief (PWM_CLK) Peripheral clock/64 */
-#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) /**< \brief (PWM_CLK) Peripheral clock/128 */
-#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) /**< \brief (PWM_CLK) Peripheral clock/256 */
-#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) /**< \brief (PWM_CLK) Peripheral clock/512 */
-#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) /**< \brief (PWM_CLK) Peripheral clock/1024 */
-/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
-#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
-#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
-#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
-#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
-/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
-#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
-#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
-#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
-#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
-/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
-#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
-#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
-#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
-#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
-/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
-#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
-#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
-#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
-#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
-#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
-#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
-#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
-#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
-/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
-#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
-#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
-#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
-#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
-#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
-#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
-#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
-#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
-/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
-#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
-#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
-#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
-#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
-#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
-#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
-#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
-#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
-/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
-#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
-#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
-#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
-#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
-#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
-#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
-#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
-#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
-/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
-#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
-#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
-#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
-#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
-#define PWM_SCM_UPDM_Pos 16
-#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
-#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos)))
-#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
-#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
-#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA and automatic update of synchronous channels */
-#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Transfer Request Mode */
-#define PWM_SCM_PTRCS_Pos 21
-#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Transfer Request Comparison Selection */
-#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
-/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */
-#define PWM_DMAR_DMADUTY_Pos 0
-#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */
-#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos)))
-/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
-#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
-/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
-#define PWM_SCUP_UPR_Pos 0
-#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
-#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
-#define PWM_SCUP_UPRCNT_Pos 4
-#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
-#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
-/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
-#define PWM_SCUPUPD_UPRUPD_Pos 0
-#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
-#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
-/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
-#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
-#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
-#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
-#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
-#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
-#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
-#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
-#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
-#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
-#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
-#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
-#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
-#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
-#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
-#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
-#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
-#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
-#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
-/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
-#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
-#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
-#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
-#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
-#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
-#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
-#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
-#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
-#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
-#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
-#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
-#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
-#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
-#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
-#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
-#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
-#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
-#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
-/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
-#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
-#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
-#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
-#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
-#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
-#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
-#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
-#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
-#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
-#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
-#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
-#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
-#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
-#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
-#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
-#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
-#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
-#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
-/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
-#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
-#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
-#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
-#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
-#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
-#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
-#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
-#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
-#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
-#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
-#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
-#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
-#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
-#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
-#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
-#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
-#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
-#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
-/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
-#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
-#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
-#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
-#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
-#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
-#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
-#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
-#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
-/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
-#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
-#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
-#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
-#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
-#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
-#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
-#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
-#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
-/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
-#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
-#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
-#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
-#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
-#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
-#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
-#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
-#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
-/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
-#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
-#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
-#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
-#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
-#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
-#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
-#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
-#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
-/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
-#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
-#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
-#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
-#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
-#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
-#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
-#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
-#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
-/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
-#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
-#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
-#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
-#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
-#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
-#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
-#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
-#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
-/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
-#define PWM_FMR_FPOL_Pos 0
-#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */
-#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
-#define PWM_FMR_FMOD_Pos 8
-#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */
-#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
-#define PWM_FMR_FFIL_Pos 16
-#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */
-#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
-/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
-#define PWM_FSR_FIV_Pos 0
-#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */
-#define PWM_FSR_FS_Pos 8
-#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */
-/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
-#define PWM_FCR_FCLR_Pos 0
-#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */
-#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
-/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */
-#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */
-#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */
-#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */
-#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */
-#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */
-#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */
-#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */
-#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */
-/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
-#define PWM_FPE_FPE0_Pos 0
-#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */
-#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
-#define PWM_FPE_FPE1_Pos 8
-#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */
-#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
-#define PWM_FPE_FPE2_Pos 16
-#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */
-#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
-#define PWM_FPE_FPE3_Pos 24
-#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */
-#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
-/* -------- PWM_ELMR[8] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
-#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[8]) Comparison 0 Selection */
-#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[8]) Comparison 1 Selection */
-#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[8]) Comparison 2 Selection */
-#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[8]) Comparison 3 Selection */
-#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[8]) Comparison 4 Selection */
-#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[8]) Comparison 5 Selection */
-#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[8]) Comparison 6 Selection */
-#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[8]) Comparison 7 Selection */
-/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */
-#define PWM_SSPR_SPRD_Pos 0
-#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */
-#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos)))
-#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */
-/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */
-#define PWM_SSPUP_SPRDUP_Pos 0
-#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */
-#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos)))
-/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
-#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
-#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
-#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
-#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
-/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */
-#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */
-#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */
-#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */
-#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */
-#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */
-#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */
-#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */
-#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */
-/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */
-#define PWM_WPCR_WPCMD_Pos 0
-#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */
-#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
-#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */
-#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */
-#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */
-#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */
-#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */
-#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */
-#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */
-#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */
-#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */
-#define PWM_WPCR_WPKEY_Pos 8
-#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */
-#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
-#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */
-/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */
-#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
-#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPVSRC_Pos 16
-#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
-/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
-#define PWM_CMPV_CV_Pos 0
-#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
-#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
-#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
-/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
-#define PWM_CMPVUPD_CVUPD_Pos 0
-#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
-#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
-#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
-#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
-#define PWM_CMPM_CTR_Pos 4
-#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
-#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
-#define PWM_CMPM_CPR_Pos 8
-#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
-#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
-#define PWM_CMPM_CPRCNT_Pos 12
-#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
-#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
-#define PWM_CMPM_CUPR_Pos 16
-#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
-#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
-#define PWM_CMPM_CUPRCNT_Pos 20
-#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
-#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
-/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
-#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
-#define PWM_CMPMUPD_CTRUPD_Pos 4
-#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
-#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
-#define PWM_CMPMUPD_CPRUPD_Pos 8
-#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
-#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
-#define PWM_CMPMUPD_CUPRUPD_Pos 16
-#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
-#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
-/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
-#define PWM_CMR_CPRE_Pos 0
-#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
-#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos)))
-#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Peripheral clock */
-#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Peripheral clock/2 */
-#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Peripheral clock/4 */
-#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Peripheral clock/8 */
-#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Peripheral clock/16 */
-#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Peripheral clock/32 */
-#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Peripheral clock/64 */
-#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Peripheral clock/128 */
-#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Peripheral clock/256 */
-#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Peripheral clock/512 */
-#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Peripheral clock/1024 */
-#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
-#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
-#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
-#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
-#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
-#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */
-#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */
-#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */
-#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
-#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
-#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
-#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */
-/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
-#define PWM_CDTY_CDTY_Pos 0
-#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
-#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
-/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
-#define PWM_CDTYUPD_CDTYUPD_Pos 0
-#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
-#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
-/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
-#define PWM_CPRD_CPRD_Pos 0
-#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
-#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
-/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
-#define PWM_CPRDUPD_CPRDUPD_Pos 0
-#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
-#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
-/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
-#define PWM_CCNT_CNT_Pos 0
-#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
-/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
-#define PWM_DT_DTH_Pos 0
-#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
-#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
-#define PWM_DT_DTL_Pos 16
-#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
-#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
-/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
-#define PWM_DTUPD_DTHUPD_Pos 0
-#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
-#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
-#define PWM_DTUPD_DTLUPD_Pos 16
-#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
-#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
-/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */
-#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */
-#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */
-/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */
-#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */
-#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */
-/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */
-#define PWM_ETRG1_MAXCNT_Pos 0
-#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */
-#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos)))
-#define PWM_ETRG1_TRGMODE_Pos 24
-#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */
-#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos)))
-#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */
-#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */
-#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */
-#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */
-#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */
-#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */
-#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */
-#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */
-#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */
-#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */
-/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */
-#define PWM_LEBR1_LEBDELAY_Pos 0
-#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */
-#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos)))
-#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */
-#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */
-#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */
-#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */
-/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */
-#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */
-#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */
-/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */
-#define PWM_ETRG2_MAXCNT_Pos 0
-#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */
-#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos)))
-#define PWM_ETRG2_TRGMODE_Pos 24
-#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */
-#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos)))
-#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */
-#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */
-#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */
-#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */
-#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */
-#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */
-#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */
-#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */
-#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */
-#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */
-/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */
-#define PWM_LEBR2_LEBDELAY_Pos 0
-#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */
-#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos)))
-#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */
-#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */
-#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */
-#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */
-/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */
-#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */
-#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */
-/* -------- PWM_ETRG3 : (PWM Offset: 0x46C) PWM External Trigger Register (trg_num = 3) -------- */
-#define PWM_ETRG3_MAXCNT_Pos 0
-#define PWM_ETRG3_MAXCNT_Msk (0xffffffu << PWM_ETRG3_MAXCNT_Pos) /**< \brief (PWM_ETRG3) Maximum Counter value */
-#define PWM_ETRG3_MAXCNT(value) ((PWM_ETRG3_MAXCNT_Msk & ((value) << PWM_ETRG3_MAXCNT_Pos)))
-#define PWM_ETRG3_TRGMODE_Pos 24
-#define PWM_ETRG3_TRGMODE_Msk (0x3u << PWM_ETRG3_TRGMODE_Pos) /**< \brief (PWM_ETRG3) External Trigger Mode */
-#define PWM_ETRG3_TRGMODE(value) ((PWM_ETRG3_TRGMODE_Msk & ((value) << PWM_ETRG3_TRGMODE_Pos)))
-#define PWM_ETRG3_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG3) External trigger is not enabled. */
-#define PWM_ETRG3_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG3) External PWM Reset Mode */
-#define PWM_ETRG3_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG3) External PWM Start Mode */
-#define PWM_ETRG3_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG3) Cycle-by-cycle Duty Mode */
-#define PWM_ETRG3_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG3) Edge Selection */
-#define PWM_ETRG3_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG3) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */
-#define PWM_ETRG3_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG3) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */
-#define PWM_ETRG3_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG3) Filtered input */
-#define PWM_ETRG3_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG3) Trigger Source */
-#define PWM_ETRG3_RFEN (0x1u << 31) /**< \brief (PWM_ETRG3) Recoverable Fault Enable */
-/* -------- PWM_LEBR3 : (PWM Offset: 0x470) PWM Leading-Edge Blanking Register (trg_num = 3) -------- */
-#define PWM_LEBR3_LEBDELAY_Pos 0
-#define PWM_LEBR3_LEBDELAY_Msk (0x7fu << PWM_LEBR3_LEBDELAY_Pos) /**< \brief (PWM_LEBR3) Leading-Edge Blanking Delay for TRGINx */
-#define PWM_LEBR3_LEBDELAY(value) ((PWM_LEBR3_LEBDELAY_Msk & ((value) << PWM_LEBR3_LEBDELAY_Pos)))
-#define PWM_LEBR3_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR3) PWML Falling Edge Enable */
-#define PWM_LEBR3_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR3) PWML Rising Edge Enable */
-#define PWM_LEBR3_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR3) PWMH Falling Edge Enable */
-#define PWM_LEBR3_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR3) PWMH Rising Edge Enable */
-/* -------- PWM_ETRG4 : (PWM Offset: 0x48C) PWM External Trigger Register (trg_num = 4) -------- */
-#define PWM_ETRG4_MAXCNT_Pos 0
-#define PWM_ETRG4_MAXCNT_Msk (0xffffffu << PWM_ETRG4_MAXCNT_Pos) /**< \brief (PWM_ETRG4) Maximum Counter value */
-#define PWM_ETRG4_MAXCNT(value) ((PWM_ETRG4_MAXCNT_Msk & ((value) << PWM_ETRG4_MAXCNT_Pos)))
-#define PWM_ETRG4_TRGMODE_Pos 24
-#define PWM_ETRG4_TRGMODE_Msk (0x3u << PWM_ETRG4_TRGMODE_Pos) /**< \brief (PWM_ETRG4) External Trigger Mode */
-#define PWM_ETRG4_TRGMODE(value) ((PWM_ETRG4_TRGMODE_Msk & ((value) << PWM_ETRG4_TRGMODE_Pos)))
-#define PWM_ETRG4_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG4) External trigger is not enabled. */
-#define PWM_ETRG4_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG4) External PWM Reset Mode */
-#define PWM_ETRG4_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG4) External PWM Start Mode */
-#define PWM_ETRG4_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG4) Cycle-by-cycle Duty Mode */
-#define PWM_ETRG4_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG4) Edge Selection */
-#define PWM_ETRG4_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG4) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */
-#define PWM_ETRG4_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG4) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */
-#define PWM_ETRG4_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG4) Filtered input */
-#define PWM_ETRG4_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG4) Trigger Source */
-#define PWM_ETRG4_RFEN (0x1u << 31) /**< \brief (PWM_ETRG4) Recoverable Fault Enable */
-/* -------- PWM_LEBR4 : (PWM Offset: 0x490) PWM Leading-Edge Blanking Register (trg_num = 4) -------- */
-#define PWM_LEBR4_LEBDELAY_Pos 0
-#define PWM_LEBR4_LEBDELAY_Msk (0x7fu << PWM_LEBR4_LEBDELAY_Pos) /**< \brief (PWM_LEBR4) Leading-Edge Blanking Delay for TRGINx */
-#define PWM_LEBR4_LEBDELAY(value) ((PWM_LEBR4_LEBDELAY_Msk & ((value) << PWM_LEBR4_LEBDELAY_Pos)))
-#define PWM_LEBR4_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR4) PWML Falling Edge Enable */
-#define PWM_LEBR4_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR4) PWML Rising Edge Enable */
-#define PWM_LEBR4_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR4) PWMH Falling Edge Enable */
-#define PWM_LEBR4_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR4) PWMH Rising Edge Enable */
-
-/*@}*/
-
-
-#endif /* _SAMS70_PWM_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/qspi.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/qspi.h
deleted file mode 100644
index 6600ba3..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/qspi.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_QSPI_COMPONENT_
-#define _SAMS70_QSPI_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */
-/* ============================================================================= */
-/** \addtogroup SAMS70_QSPI Quad Serial Peripheral Interface */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Qspi hardware registers */
-typedef struct {
- __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */
- __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */
- __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */
- __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */
- __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */
- __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */
- __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */
- __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */
- __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */
- __I uint32_t Reserved1[3];
- __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */
- __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */
- __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */
- __I uint32_t Reserved2[1];
- __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */
- __O uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */
- __I uint32_t Reserved3[39];
- __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */
- __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */
-} Qspi;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */
-#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */
-#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */
-#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */
-#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */
-/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */
-#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */
-#define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */
-#define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */
-#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */
-#define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */
-#define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */
-#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */
-#define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */
-#define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */
-#define QSPI_MR_CSMODE_Pos 4
-#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */
-#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos)))
-#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */
-#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */
-#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */
-#define QSPI_MR_NBBITS_Pos 8
-#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */
-#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos)))
-#define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */
-#define QSPI_MR_NBBITS_9_BIT (0x1u << 8) /**< \brief (QSPI_MR) 9 bits for transfer */
-#define QSPI_MR_NBBITS_10_BIT (0x2u << 8) /**< \brief (QSPI_MR) 10 bits for transfer */
-#define QSPI_MR_NBBITS_11_BIT (0x3u << 8) /**< \brief (QSPI_MR) 11 bits for transfer */
-#define QSPI_MR_NBBITS_12_BIT (0x4u << 8) /**< \brief (QSPI_MR) 12 bits for transfer */
-#define QSPI_MR_NBBITS_13_BIT (0x5u << 8) /**< \brief (QSPI_MR) 13 bits for transfer */
-#define QSPI_MR_NBBITS_14_BIT (0x6u << 8) /**< \brief (QSPI_MR) 14 bits for transfer */
-#define QSPI_MR_NBBITS_15_BIT (0x7u << 8) /**< \brief (QSPI_MR) 15 bits for transfer */
-#define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */
-#define QSPI_MR_DLYBCT_Pos 16
-#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */
-#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos)))
-#define QSPI_MR_DLYCS_Pos 24
-#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */
-#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos)))
-/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */
-#define QSPI_RDR_RD_Pos 0
-#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */
-/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */
-#define QSPI_TDR_TD_Pos 0
-#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */
-#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos)))
-/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */
-#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full */
-#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty */
-#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty */
-#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status */
-#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */
-#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */
-#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */
-#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */
-/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */
-#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */
-#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */
-#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */
-#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */
-#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */
-#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */
-#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */
-/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */
-#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */
-#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */
-#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */
-#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */
-#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */
-#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */
-#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */
-/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */
-#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */
-#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */
-#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */
-#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */
-#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */
-#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */
-#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */
-/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */
-#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */
-#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */
-#define QSPI_SCR_SCBR_Pos 8
-#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */
-#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos)))
-#define QSPI_SCR_DLYBS_Pos 16
-#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */
-#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos)))
-/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */
-#define QSPI_IAR_ADDR_Pos 0
-#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */
-#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos)))
-/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */
-#define QSPI_ICR_INST_Pos 0
-#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */
-#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos)))
-#define QSPI_ICR_OPT_Pos 16
-#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */
-#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos)))
-/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */
-#define QSPI_IFR_WIDTH_Pos 0
-#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */
-#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos)))
-#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */
-#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */
-#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */
-#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */
-#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */
-#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */
-#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */
-#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */
-#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */
-#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */
-#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */
-#define QSPI_IFR_OPTL_Pos 8
-#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */
-#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos)))
-#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */
-#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */
-#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */
-#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */
-#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */
-#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */
-#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */
-#define QSPI_IFR_TFRTYP_Pos 12
-#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */
-#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos)))
-#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */
-#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */
-#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */
-#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */
-#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */
-#define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */
-#define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */
-#define QSPI_IFR_NBDUM_Pos 16
-#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */
-#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos)))
-/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */
-#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */
-#define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */
-#define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */
-#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */
-/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */
-#define QSPI_SKR_USRK_Pos 0
-#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */
-#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos)))
-/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */
-#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */
-#define QSPI_WPMR_WPKEY_Pos 8
-#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */
-#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos)))
-#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
-/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */
-#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */
-#define QSPI_WPSR_WPVSRC_Pos 8
-#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_QSPI_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/rstc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/rstc.h
deleted file mode 100644
index 592f50d..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/rstc.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RSTC_COMPONENT_
-#define _SAMS70_RSTC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Reset Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_RSTC Reset Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Rstc hardware registers */
-typedef struct {
- __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
- __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
- __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
-} Rstc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
-#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
-#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
-#define RSTC_CR_KEY_Pos 24
-#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */
-#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
-#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */
-/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
-#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
-#define RSTC_SR_RSTTYP_Pos 8
-#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
-#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */
-#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */
-#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */
-#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */
-#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */
-#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
-#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
-/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
-#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
-#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
-#define RSTC_MR_ERSTL_Pos 8
-#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
-#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
-#define RSTC_MR_KEY_Pos 24
-#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */
-#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
-#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */
-
-/*@}*/
-
-
-#endif /* _SAMS70_RSTC_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/rswdt.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/rswdt.h
deleted file mode 100644
index 09694f4..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/rswdt.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RSWDT_COMPONENT_
-#define _SAMS70_RSWDT_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */
-/* ============================================================================= */
-/** \addtogroup SAMS70_RSWDT Reinforced Safety Watchdog Timer */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Rswdt hardware registers */
-typedef struct {
- __O uint32_t RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */
- __IO uint32_t RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */
- __I uint32_t RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */
-} Rswdt;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */
-#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */
-#define RSWDT_CR_KEY_Pos 24
-#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */
-#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos)))
-#define RSWDT_CR_KEY_PASSWD (0xC4u << 24) /**< \brief (RSWDT_CR) Writing any other value in this field aborts the write operation. */
-/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */
-#define RSWDT_MR_WDV_Pos 0
-#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */
-#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos)))
-#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */
-#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */
-#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */
-#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */
-#define RSWDT_MR_ALLONES_Pos 16
-#define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) /**< \brief (RSWDT_MR) Must Always Be Written with 0xFFF */
-#define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos)))
-#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */
-#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */
-/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */
-#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */
-
-/*@}*/
-
-
-#endif /* _SAMS70_RSWDT_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/rtc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/rtc.h
deleted file mode 100644
index 2456bde..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/rtc.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RTC_COMPONENT_
-#define _SAMS70_RTC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Real-time Clock */
-/* ============================================================================= */
-/** \addtogroup SAMS70_RTC Real-time Clock */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Rtc hardware registers */
-typedef struct {
- __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */
- __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */
- __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */
- __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */
- __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
- __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
- __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */
- __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
- __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
- __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
- __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
- __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
-} Rtc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
-#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
-#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
-#define RTC_CR_TIMEVSEL_Pos 8
-#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
-#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos)))
-#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
-#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
-#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
-#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
-#define RTC_CR_CALEVSEL_Pos 16
-#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
-#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos)))
-#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
-#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
-#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
-/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
-#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
-#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */
-#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */
-#define RTC_MR_CORRECTION_Pos 8
-#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */
-#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))
-#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */
-#define RTC_MR_OUT0_Pos 16
-#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */
-#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos)))
-#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */
-#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */
-#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */
-#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */
-#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */
-#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) Output toggles when alarm flag rises */
-#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */
-#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) Duty cycle programmable pulse */
-#define RTC_MR_OUT1_Pos 20
-#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */
-#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos)))
-#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */
-#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */
-#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */
-#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */
-#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */
-#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) Output toggles when alarm flag rises */
-#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */
-#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) Duty cycle programmable pulse */
-#define RTC_MR_THIGH_Pos 24
-#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */
-#define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos)))
-#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */
-#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */
-#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */
-#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */
-#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */
-#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */
-#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */
-#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */
-#define RTC_MR_TPERIOD_Pos 28
-#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */
-#define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos)))
-#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */
-#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */
-#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */
-#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */
-/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
-#define RTC_TIMR_SEC_Pos 0
-#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
-#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
-#define RTC_TIMR_MIN_Pos 8
-#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
-#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
-#define RTC_TIMR_HOUR_Pos 16
-#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
-#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
-#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
-/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
-#define RTC_CALR_CENT_Pos 0
-#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
-#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
-#define RTC_CALR_YEAR_Pos 8
-#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
-#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
-#define RTC_CALR_MONTH_Pos 16
-#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
-#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
-#define RTC_CALR_DAY_Pos 21
-#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
-#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
-#define RTC_CALR_DATE_Pos 24
-#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
-#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
-/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
-#define RTC_TIMALR_SEC_Pos 0
-#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
-#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
-#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
-#define RTC_TIMALR_MIN_Pos 8
-#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
-#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
-#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
-#define RTC_TIMALR_HOUR_Pos 16
-#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
-#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
-#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
-#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
-/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
-#define RTC_CALALR_MONTH_Pos 16
-#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
-#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
-#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
-#define RTC_CALALR_DATE_Pos 24
-#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
-#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
-#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
-/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
-#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
-#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */
-#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */
-#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
-#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */
-#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */
-#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
-#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */
-#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */
-#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
-#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */
-#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */
-#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
-#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */
-#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */
-#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */
-#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */
-#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */
-/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
-#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
-#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
-#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
-#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
-#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
-#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */
-/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
-#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
-#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
-#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
-#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
-#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
-#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */
-/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
-#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
-#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
-#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
-#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
-#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
-#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */
-/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
-#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
-#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
-#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
-#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
-#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
-#define RTC_IMR_TDERR (0x1u << 5) /**< \brief (RTC_IMR) Time and/or Date Error Mask */
-/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
-#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
-#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
-#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
-#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
-
-/*@}*/
-
-
-#endif /* _SAMS70_RTC_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/rtt.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/rtt.h
deleted file mode 100644
index d9c76c5..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/rtt.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RTT_COMPONENT_
-#define _SAMS70_RTT_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Real-time Timer */
-/* ============================================================================= */
-/** \addtogroup SAMS70_RTT Real-time Timer */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Rtt hardware registers */
-typedef struct {
- __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
- __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
- __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
- __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
-} Rtt;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
-#define RTT_MR_RTPRES_Pos 0
-#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
-#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
-#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
-#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
-#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
-#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */
-#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */
-/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
-#define RTT_AR_ALMV_Pos 0
-#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
-#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
-/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
-#define RTT_VR_CRTV_Pos 0
-#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
-/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
-#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status (cleared on read) */
-#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status (cleared on read) */
-
-/*@}*/
-
-
-#endif /* _SAMS70_RTT_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/sdramc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/sdramc.h
deleted file mode 100644
index 126e9ca..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/sdramc.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SDRAMC_COMPONENT_
-#define _SAMS70_SDRAMC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR SDRAM Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_SDRAMC SDRAM Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Sdramc hardware registers */
-typedef struct {
- __IO uint32_t SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */
- __IO uint32_t SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */
- __IO uint32_t SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */
- __I uint32_t Reserved1[1];
- __IO uint32_t SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */
- __O uint32_t SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */
- __O uint32_t SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */
- __I uint32_t SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */
- __I uint32_t SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */
- __IO uint32_t SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */
- __IO uint32_t SDRAMC_CFR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */
- __IO uint32_t SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register */
- __O uint32_t SDRAMC_OCMS_KEY1; /**< \brief (Sdramc Offset: 0x30) SDRAMC OCMS KEY1 Register */
- __O uint32_t SDRAMC_OCMS_KEY2; /**< \brief (Sdramc Offset: 0x34) SDRAMC OCMS KEY2 Register */
-} Sdramc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */
-#define SDRAMC_MR_MODE_Pos 0
-#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */
-#define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos)))
-#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */
-#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
-#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
-#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
-#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */
-#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */
-#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */
-/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */
-#define SDRAMC_TR_COUNT_Pos 0
-#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */
-#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos)))
-/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */
-#define SDRAMC_CR_NC_Pos 0
-#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */
-#define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos)))
-#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */
-#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */
-#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */
-#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */
-#define SDRAMC_CR_NR_Pos 2
-#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */
-#define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos)))
-#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */
-#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */
-#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */
-#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */
-#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */
-#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */
-#define SDRAMC_CR_CAS_Pos 5
-#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */
-#define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos)))
-#define SDRAMC_CR_CAS_LATENCY1 (0x0u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */
-#define SDRAMC_CR_CAS_LATENCY2 (0x1u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */
-#define SDRAMC_CR_CAS_LATENCY3 (0x2u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */
-#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */
-#define SDRAMC_CR_TWR_Pos 8
-#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */
-#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos)))
-#define SDRAMC_CR_TRC_TRFC_Pos 12
-#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */
-#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos)))
-#define SDRAMC_CR_TRP_Pos 16
-#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */
-#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos)))
-#define SDRAMC_CR_TRCD_Pos 20
-#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */
-#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos)))
-#define SDRAMC_CR_TRAS_Pos 24
-#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */
-#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos)))
-#define SDRAMC_CR_TXSR_Pos 28
-#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */
-#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos)))
-/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */
-#define SDRAMC_LPR_LPCB_Pos 0
-#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */
-#define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos)))
-#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */
-#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */
-#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */
-#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */
-#define SDRAMC_LPR_PASR_Pos 4
-#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */
-#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos)))
-#define SDRAMC_LPR_TCSR_Pos 8
-#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */
-#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos)))
-#define SDRAMC_LPR_DS_Pos 10
-#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */
-#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos)))
-#define SDRAMC_LPR_TIMEOUT_Pos 12
-#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled */
-#define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos)))
-#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. */
-#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */
-#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */
-/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */
-#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */
-/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */
-#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */
-/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */
-#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */
-/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */
-#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status (cleared on read) */
-/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */
-#define SDRAMC_MDR_MD_Pos 0
-#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */
-#define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos)))
-#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */
-#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */
-/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */
-#define SDRAMC_CFR1_TMRD_Pos 0
-#define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos) /**< \brief (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command */
-#define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos)))
-#define SDRAMC_CFR1_UNAL (0x1u << 8) /**< \brief (SDRAMC_CFR1) Support Unaligned Access */
-#define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is not supported. */
-#define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is supported. */
-/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */
-#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */
-/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */
-#define SDRAMC_OCMS_KEY1_KEY1_Pos 0
-#define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< \brief (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 */
-#define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos)))
-/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */
-#define SDRAMC_OCMS_KEY2_KEY2_Pos 0
-#define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< \brief (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 */
-#define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos)))
-
-/*@}*/
-
-
-#endif /* _SAMS70_SDRAMC_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/smc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/smc.h
deleted file mode 100644
index 04954ec..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/smc.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SMC_COMPONENT_
-#define _SAMS70_SMC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Static Memory Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_SMC Static Memory Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief SmcCs_number hardware registers */
-typedef struct {
- __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
- __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
- __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
- __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC MODE Register */
-} SmcCs_number;
-/** \brief Smc hardware registers */
-#define SMCCS_NUMBER_NUMBER 4
-typedef struct {
- SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */
- __I uint32_t Reserved1[16];
- __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */
- __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */
- __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */
- __I uint32_t Reserved2[22];
- __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protection Mode Register */
- __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protection Status Register */
-} Smc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
-#define SMC_SETUP_NWE_SETUP_Pos 0
-#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
-#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
-#define SMC_SETUP_NCS_WR_SETUP_Pos 8
-#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */
-#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
-#define SMC_SETUP_NRD_SETUP_Pos 16
-#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
-#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
-#define SMC_SETUP_NCS_RD_SETUP_Pos 24
-#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */
-#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
-/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
-#define SMC_PULSE_NWE_PULSE_Pos 0
-#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
-#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
-#define SMC_PULSE_NCS_WR_PULSE_Pos 8
-#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
-#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
-#define SMC_PULSE_NRD_PULSE_Pos 16
-#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
-#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
-#define SMC_PULSE_NCS_RD_PULSE_Pos 24
-#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
-#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
-/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
-#define SMC_CYCLE_NWE_CYCLE_Pos 0
-#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
-#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
-#define SMC_CYCLE_NRD_CYCLE_Pos 16
-#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
-#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
-/* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */
-#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) Read Mode */
-#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) Write Mode */
-#define SMC_MODE_EXNW_MODE_Pos 4
-#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
-#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos)))
-#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
-#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
-#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
-#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */
-#define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8) /**< \brief (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */
-#define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8) /**< \brief (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */
-#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */
-#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit Data Bus */
-#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit Data Bus */
-#define SMC_MODE_TDF_CYCLES_Pos 16
-#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
-#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
-#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
-#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */
-#define SMC_MODE_PS_Pos 28
-#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */
-#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos)))
-#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */
-#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */
-#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */
-#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */
-/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */
-#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
-/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */
-#define SMC_KEY1_KEY1_Pos 0
-#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
-#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
-/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */
-#define SMC_KEY2_KEY2_Pos 0
-#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
-#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
-/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */
-#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */
-#define SMC_WPMR_WPKEY_Pos 8
-#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protection Key */
-#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))
-#define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8) /**< \brief (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
-/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */
-#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */
-#define SMC_WPSR_WPVSRC_Pos 8
-#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_SMC_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/spi.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/spi.h
deleted file mode 100644
index 0faef2c..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/spi.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SPI_COMPONENT_
-#define _SAMS70_SPI_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
-/* ============================================================================= */
-/** \addtogroup SAMS70_SPI Serial Peripheral Interface */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Spi hardware registers */
-typedef struct {
- __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */
- __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */
- __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */
- __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
- __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */
- __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
- __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
- __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
- __I uint32_t Reserved1[4];
- __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */
- __I uint32_t Reserved2[41];
- __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Mode Register */
- __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
-} Spi;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
-#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
-#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
-#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
-#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
-/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
-#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
-#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
-#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
-#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
-#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
-#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
-#define SPI_MR_PCS_Pos 16
-#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
-#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
-#define SPI_MR_DLYBCS_Pos 24
-#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
-#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
-/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
-#define SPI_RDR_RD_Pos 0
-#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
-#define SPI_RDR_PCS_Pos 16
-#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
-/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
-#define SPI_TDR_TD_Pos 0
-#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
-#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
-#define SPI_TDR_PCS_Pos 16
-#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
-#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
-#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */
-#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */
-#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */
-#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */
-#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */
-#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */
-#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) */
-#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
-#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
-#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
-#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
-#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
-#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
-#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
-#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
-#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
-#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
-#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
-#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
-#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
-#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
-/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
-#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
-#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
-#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
-#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
-#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
-#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
-#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
-/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
-#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
-#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
-#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
-#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */
-#define SPI_CSR_BITS_Pos 4
-#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
-#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos)))
-#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
-#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
-#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
-#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
-#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
-#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
-#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
-#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
-#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
-#define SPI_CSR_SCBR_Pos 8
-#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Bit Rate */
-#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
-#define SPI_CSR_DLYBS_Pos 16
-#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
-#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
-#define SPI_CSR_DLYBCT_Pos 24
-#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
-#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
-/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */
-#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */
-#define SPI_WPMR_WPKEY_Pos 8
-#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */
-#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
-#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
-/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
-#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */
-#define SPI_WPSR_WPVSRC_Pos 8
-#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_SPI_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/ssc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/ssc.h
deleted file mode 100644
index 904716c..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/ssc.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SSC_COMPONENT_
-#define _SAMS70_SSC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_SSC Synchronous Serial Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Ssc hardware registers */
-typedef struct {
- __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */
- __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
- __I uint32_t Reserved1[2];
- __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
- __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
- __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
- __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
- __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
- __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
- __I uint32_t Reserved2[2];
- __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
- __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
- __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
- __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
- __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */
- __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
- __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
- __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
- __I uint32_t Reserved3[37];
- __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protection Mode Register */
- __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protection Status Register */
-} Ssc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
-#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
-#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
-#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
-#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
-#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
-/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
-#define SSC_CMR_DIV_Pos 0
-#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
-#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
-/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
-#define SSC_RCMR_CKS_Pos 0
-#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
-#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos)))
-#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
-#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
-#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
-#define SSC_RCMR_CKO_Pos 2
-#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
-#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos)))
-#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */
-#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */
-#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */
-#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
-#define SSC_RCMR_CKG_Pos 6
-#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
-#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos)))
-#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */
-#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */
-#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */
-#define SSC_RCMR_START_Pos 8
-#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
-#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos)))
-#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
-#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
-#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
-#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
-#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
-#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
-#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
-#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
-#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
-#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
-#define SSC_RCMR_STTDLY_Pos 16
-#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
-#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
-#define SSC_RCMR_PERIOD_Pos 24
-#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
-#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
-/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
-#define SSC_RFMR_DATLEN_Pos 0
-#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
-#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
-#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
-#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
-#define SSC_RFMR_DATNB_Pos 8
-#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
-#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
-#define SSC_RFMR_FSLEN_Pos 16
-#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
-#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
-#define SSC_RFMR_FSOS_Pos 20
-#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
-#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos)))
-#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */
-#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */
-#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */
-#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */
-#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */
-#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */
-#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
-#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
-#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
-#define SSC_RFMR_FSLEN_EXT_Pos 28
-#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
-#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
-/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
-#define SSC_TCMR_CKS_Pos 0
-#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
-#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos)))
-#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
-#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */
-#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */
-#define SSC_TCMR_CKO_Pos 2
-#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
-#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos)))
-#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */
-#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */
-#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */
-#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
-#define SSC_TCMR_CKG_Pos 6
-#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
-#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos)))
-#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */
-#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
-#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
-#define SSC_TCMR_START_Pos 8
-#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
-#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos)))
-#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */
-#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
-#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
-#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
-#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
-#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
-#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
-#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
-#define SSC_TCMR_STTDLY_Pos 16
-#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
-#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
-#define SSC_TCMR_PERIOD_Pos 24
-#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
-#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
-/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
-#define SSC_TFMR_DATLEN_Pos 0
-#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
-#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
-#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
-#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
-#define SSC_TFMR_DATNB_Pos 8
-#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per Frame */
-#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
-#define SSC_TFMR_FSLEN_Pos 16
-#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
-#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
-#define SSC_TFMR_FSOS_Pos 20
-#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
-#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos)))
-#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, TF pin is an input */
-#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, TF pin is an output */
-#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, TF pin is an output */
-#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
-#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
-#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
-#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
-#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
-#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
-#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
-#define SSC_TFMR_FSLEN_EXT_Pos 28
-#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
-#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
-/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
-#define SSC_RHR_RDAT_Pos 0
-#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
-/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
-#define SSC_THR_TDAT_Pos 0
-#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
-#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
-/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
-#define SSC_RSHR_RSDAT_Pos 0
-#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
-/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
-#define SSC_TSHR_TSDAT_Pos 0
-#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
-#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
-/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
-#define SSC_RC0R_CP0_Pos 0
-#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
-#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
-/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
-#define SSC_RC1R_CP1_Pos 0
-#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
-#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
-/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
-#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
-#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
-#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
-#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
-#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
-#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
-#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
-#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
-#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
-#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
-/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
-#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
-#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
-#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
-#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
-#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
-#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
-#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
-#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
-/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
-#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
-#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
-#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
-#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
-#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
-#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
-#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
-#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
-/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
-#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
-#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
-#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
-#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
-#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
-#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
-#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
-#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
-/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */
-#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protection Enable */
-#define SSC_WPMR_WPKEY_Pos 8
-#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protection Key */
-#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
-#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
-/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */
-#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protection Violation Status */
-#define SSC_WPSR_WPVSRC_Pos 8
-#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_SSC_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/supc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/supc.h
deleted file mode 100644
index 6e10ef4..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/supc.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SUPC_COMPONENT_
-#define _SAMS70_SUPC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Supply Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_SUPC Supply Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Supc hardware registers */
-typedef struct {
- __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
- __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
- __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
- __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */
- __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */
- __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
-} Supc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
-#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
-#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */
-#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */
-#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
-#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */
-#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */
-#define SUPC_CR_KEY_Pos 24
-#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
-#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
-#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation. */
-/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
-#define SUPC_SMMR_SMTH_Pos 0
-#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
-#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos)))
-#define SUPC_SMMR_SMSMPL_Pos 8
-#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
-#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos)))
-#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
-#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
-#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
-#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
-#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
-#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
-#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */
-#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
-#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
-#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */
-#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */
-/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
-#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
-#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */
-#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
-#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
-#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */
-#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */
-#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator Enable */
-#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */
-#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is used. */
-#define SUPC_MR_BKUPRETON (0x1u << 17) /**< \brief (SUPC_MR) SRAM On In Backup Mode */
-#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
-#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */
-#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */
-#define SUPC_MR_KEY_Pos 24
-#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
-#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
-#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation. */
-/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */
-#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */
-#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */
-#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */
-#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */
-#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */
-#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */
-#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */
-#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */
-#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */
-#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP0 */
-#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */
-#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */
-#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP1 */
-#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */
-#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */
-#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low-power Debouncer Clear */
-#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */
-#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */
-#define SUPC_WUMR_WKUPDBC_Pos 12
-#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */
-#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos)))
-#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
-#define SUPC_WUMR_WKUPDBC_3_SLCK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_32_SLCK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_512_SLCK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_4096_SLCK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_32768_SLCK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
-#define SUPC_WUMR_LPDBC_Pos 16
-#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low-power Debouncer Period */
-#define SUPC_WUMR_LPDBC(value) ((SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos)))
-#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low-power debouncers. */
-#define SUPC_WUMR_LPDBC_2_RTCOUT (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */
-#define SUPC_WUMR_LPDBC_3_RTCOUT (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */
-#define SUPC_WUMR_LPDBC_4_RTCOUT (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */
-#define SUPC_WUMR_LPDBC_5_RTCOUT (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */
-#define SUPC_WUMR_LPDBC_6_RTCOUT (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */
-#define SUPC_WUMR_LPDBC_7_RTCOUT (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */
-#define SUPC_WUMR_LPDBC_8_RTCOUT (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */
-/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */
-#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 0 */
-#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 1 */
-#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 2 */
-#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 3 */
-#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 4 */
-#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 5 */
-#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 6 */
-#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 7 */
-#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 8 */
-#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 9 */
-#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 10 */
-#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 11 */
-#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 12 */
-#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 13 */
-#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 0 */
-#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 1 */
-#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 2 */
-#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 3 */
-#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 4 */
-#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 5 */
-#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 6 */
-#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 7 */
-#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 8 */
-#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 9 */
-#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 10 */
-#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 11 */
-#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 12 */
-#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 13 */
-#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
-#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status (cleared on read) */
-#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) */
-#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status (cleared on read) */
-#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */
-#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
-#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status (cleared on read) */
-#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
-#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
-#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status (cleared on read) */
-#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */
-#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */
-#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
-#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */
-#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */
-#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
-#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */
-#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */
-#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) */
-#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) */
-#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-
-/*@}*/
-
-
-#endif /* _SAMS70_SUPC_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/tc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/tc.h
deleted file mode 100644
index 5969e8a..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/tc.h
+++ /dev/null
@@ -1,361 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TC_COMPONENT_
-#define _SAMS70_TC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Timer Counter */
-/* ============================================================================= */
-/** \addtogroup SAMS70_TC Timer Counter */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief TcChannel hardware registers */
-typedef struct {
- __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
- __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
- __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
- __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */
- __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */
- __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */
- __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */
- __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */
- __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */
- __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
- __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
- __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
- __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */
- __I uint32_t Reserved1[3];
-} TcChannel;
-/** \brief Tc hardware registers */
-#define TCCHANNEL_NUMBER 3
-typedef struct {
- TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
- __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */
- __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */
- __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
- __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
- __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
- __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
- __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
- __I uint32_t Reserved1[2];
- __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */
-} Tc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
-#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
-#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
-#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
-/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
-#define TC_CMR_TCCLKS_Pos 0
-#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
-#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos)))
-#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */
-#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */
-#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */
-#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */
-#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */
-#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
-#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
-#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
-#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
-#define TC_CMR_BURST_Pos 4
-#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
-#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos)))
-#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
-#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
-#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
-#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
-#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
-#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
-#define TC_CMR_ETRGEDG_Pos 8
-#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
-#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos)))
-#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
-#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
-#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
-#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
-#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
-#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
-#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
-#define TC_CMR_LDRA_Pos 16
-#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
-#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos)))
-#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
-#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
-#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
-#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
-#define TC_CMR_LDRB_Pos 18
-#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
-#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos)))
-#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
-#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
-#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
-#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
-#define TC_CMR_SBSMPLR_Pos 20
-#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */
-#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos)))
-#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */
-#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */
-#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */
-#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */
-#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */
-#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
-#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
-#define TC_CMR_EEVTEDG_Pos 8
-#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
-#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos)))
-#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
-#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
-#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
-#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
-#define TC_CMR_EEVT_Pos 10
-#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
-#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos)))
-#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
-#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
-#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
-#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
-#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
-#define TC_CMR_WAVSEL_Pos 13
-#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
-#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos)))
-#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
-#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
-#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
-#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
-#define TC_CMR_ACPA_Pos 16
-#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
-#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos)))
-#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
-#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
-#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
-#define TC_CMR_ACPC_Pos 18
-#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
-#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos)))
-#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
-#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
-#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
-#define TC_CMR_AEEVT_Pos 20
-#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
-#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos)))
-#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
-#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
-#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
-#define TC_CMR_ASWTRG_Pos 22
-#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
-#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos)))
-#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
-#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
-#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
-#define TC_CMR_BCPB_Pos 24
-#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
-#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos)))
-#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
-#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
-#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
-#define TC_CMR_BCPC_Pos 26
-#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
-#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos)))
-#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
-#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
-#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
-#define TC_CMR_BEEVT_Pos 28
-#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
-#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos)))
-#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
-#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
-#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
-#define TC_CMR_BSWTRG_Pos 30
-#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
-#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos)))
-#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
-#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
-#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
-/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
-#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
-#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */
-/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */
-#define TC_RAB_RAB_Pos 0
-#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */
-/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
-#define TC_CV_CV_Pos 0
-#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
-/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
-#define TC_RA_RA_Pos 0
-#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
-#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
-/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
-#define TC_RB_RB_Pos 0
-#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
-#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
-/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
-#define TC_RC_RC_Pos 0
-#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
-#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
-/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
-#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */
-#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */
-#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */
-#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */
-#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */
-#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */
-#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */
-#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */
-#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
-#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
-#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
-/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
-#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
-#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
-#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
-#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
-#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
-#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
-#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
-#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
-/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
-#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
-#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
-#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
-#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
-#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
-#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
-#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
-#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
-/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
-#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
-#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
-#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
-#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
-#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
-#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
-#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
-#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
-/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */
-#define TC_EMR_TRIGSRCA_Pos 0
-#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */
-#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos)))
-#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */
-#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */
-#define TC_EMR_TRIGSRCB_Pos 4
-#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */
-#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos)))
-#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */
-#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven internally by PWMx */
-#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */
-/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
-#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
-/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
-#define TC_BMR_TC0XC0S_Pos 0
-#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
-#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos)))
-#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
-#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
-#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
-#define TC_BMR_TC1XC1S_Pos 2
-#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
-#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos)))
-#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
-#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
-#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
-#define TC_BMR_TC2XC2S_Pos 4
-#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
-#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos)))
-#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
-#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */
-#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
-#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */
-#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */
-#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */
-#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */
-#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */
-#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */
-#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */
-#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */
-#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */
-#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */
-#define TC_BMR_MAXFILT_Pos 20
-#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */
-#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
-/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
-#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */
-#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */
-#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */
-/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
-#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */
-#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */
-#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */
-/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
-#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */
-#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */
-#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */
-/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
-#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */
-#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */
-#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */
-#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
-/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
-#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */
-#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */
-/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */
-#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */
-#define TC_WPMR_WPKEY_Pos 8
-#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */
-#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
-#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
-
-/*@}*/
-
-
-#endif /* _SAMS70_TC_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/trng.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/trng.h
deleted file mode 100644
index 5b785aa..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/trng.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TRNG_COMPONENT_
-#define _SAMS70_TRNG_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR True Random Number Generator */
-/* ============================================================================= */
-/** \addtogroup SAMS70_TRNG True Random Number Generator */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Trng hardware registers */
-typedef struct {
- __O uint32_t TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */
- __I uint32_t Reserved1[3];
- __O uint32_t TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */
- __O uint32_t TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */
- __I uint32_t TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */
- __I uint32_t TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */
- __I uint32_t Reserved2[12];
- __I uint32_t TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */
-} Trng;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */
-#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */
-#define TRNG_CR_KEY_Pos 8
-#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key. */
-#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)))
-#define TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */
-/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */
-#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */
-/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */
-#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */
-/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */
-#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */
-/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */
-#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */
-/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */
-#define TRNG_ODATA_ODATA_Pos 0
-#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */
-
-/*@}*/
-
-
-#endif /* _SAMS70_TRNG_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/twihs.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/twihs.h
deleted file mode 100644
index 366650f..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/twihs.h
+++ /dev/null
@@ -1,265 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TWIHS_COMPONENT_
-#define _SAMS70_TWIHS_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */
-/* ============================================================================= */
-/** \addtogroup SAMS70_TWIHS Two-wire Interface High Speed */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Twihs hardware registers */
-typedef struct {
- __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */
- __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */
- __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */
- __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */
- __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */
- __I uint32_t Reserved1[3];
- __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */
- __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */
- __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */
- __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */
- __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */
- __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */
- __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */
- __I uint32_t Reserved2[2];
- __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */
- __I uint32_t Reserved3[1];
- __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */
- __I uint32_t Reserved4[37];
- __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */
- __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */
-} Twihs;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */
-#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */
-#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */
-#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */
-#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */
-#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */
-#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */
-#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */
-#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */
-#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */
-#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */
-#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */
-#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */
-#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */
-#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */
-#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */
-#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */
-/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */
-#define TWIHS_MMR_IADRSZ_Pos 8
-#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */
-#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos)))
-#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */
-#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */
-#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */
-#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */
-#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */
-#define TWIHS_MMR_DADR_Pos 16
-#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */
-#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos)))
-/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */
-#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */
-#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */
-#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */
-#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */
-#define TWIHS_SMR_MASK_Pos 8
-#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */
-#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos)))
-#define TWIHS_SMR_SADR_Pos 16
-#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */
-#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos)))
-#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */
-#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */
-#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */
-#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */
-/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */
-#define TWIHS_IADR_IADR_Pos 0
-#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */
-#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos)))
-/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */
-#define TWIHS_CWGR_CLDIV_Pos 0
-#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */
-#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos)))
-#define TWIHS_CWGR_CHDIV_Pos 8
-#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */
-#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos)))
-#define TWIHS_CWGR_CKDIV_Pos 16
-#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */
-#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos)))
-#define TWIHS_CWGR_HOLD_Pos 24
-#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */
-#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos)))
-/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */
-#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */
-#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */
-#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */
-#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */
-#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */
-#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */
-#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */
-#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */
-#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */
-#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */
-#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */
-#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */
-#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */
-#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */
-#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */
-#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */
-#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */
-#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL line value */
-#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA line value */
-/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */
-#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */
-#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */
-#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */
-#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */
-#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */
-#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */
-#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */
-#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */
-#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */
-#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */
-#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */
-#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */
-#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */
-#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */
-#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */
-#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */
-/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */
-#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */
-#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */
-#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */
-#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */
-#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */
-#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */
-#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */
-#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */
-#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */
-#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */
-#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */
-#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */
-#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */
-#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */
-#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */
-#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */
-/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */
-#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */
-#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */
-#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */
-#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */
-#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */
-#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */
-#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */
-#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */
-#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */
-#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */
-#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */
-#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */
-#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */
-#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */
-#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */
-#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */
-/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */
-#define TWIHS_RHR_RXDATA_Pos 0
-#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */
-/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */
-#define TWIHS_THR_TXDATA_Pos 0
-#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */
-#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos)))
-/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */
-#define TWIHS_SMBTR_PRESC_Pos 0
-#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */
-#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos)))
-#define TWIHS_SMBTR_TLOWS_Pos 8
-#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */
-#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos)))
-#define TWIHS_SMBTR_TLOWM_Pos 16
-#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */
-#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos)))
-#define TWIHS_SMBTR_THMAX_Pos 24
-#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */
-#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos)))
-/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */
-#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */
-#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */
-#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */
-#define TWIHS_FILTR_THRES_Pos 8
-#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */
-#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos)))
-/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */
-#define TWIHS_SWMR_SADR1_Pos 0
-#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */
-#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos)))
-#define TWIHS_SWMR_SADR2_Pos 8
-#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */
-#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos)))
-#define TWIHS_SWMR_SADR3_Pos 16
-#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */
-#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos)))
-#define TWIHS_SWMR_DATAM_Pos 24
-#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */
-#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos)))
-/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */
-#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */
-#define TWIHS_WPMR_WPKEY_Pos 8
-#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */
-#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos)))
-#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */
-/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */
-#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */
-#define TWIHS_WPSR_WPVSRC_Pos 8
-#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_TWIHS_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/uart.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/uart.h
deleted file mode 100644
index 0e54542..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/uart.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UART_COMPONENT_
-#define _SAMS70_UART_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
-/* ============================================================================= */
-/** \addtogroup SAMS70_UART Universal Asynchronous Receiver Transmitter */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Uart hardware registers */
-typedef struct {
- __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */
- __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */
- __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
- __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
- __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
- __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */
- __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
- __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
- __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
- __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */
- __I uint32_t Reserved1[47];
- __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */
-} Uart;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
-#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
-#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
-#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
-#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
-#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
-#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
-#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */
-#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */
-/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
-#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */
-#define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */
-#define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */
-#define UART_MR_PAR_Pos 9
-#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
-#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos)))
-#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */
-#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */
-#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
-#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
-#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
-#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */
-#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */
-#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */
-#define UART_MR_CHMODE_Pos 14
-#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
-#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos)))
-#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */
-#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */
-#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */
-#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */
-/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
-#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
-#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
-#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
-#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
-#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
-#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
-#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */
-/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
-#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
-#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
-#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
-#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
-#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
-#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
-#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */
-/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
-#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
-#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
-#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
-#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
-#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
-#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
-#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */
-/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
-#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
-#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
-#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
-#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
-#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
-#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
-#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */
-/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
-#define UART_RHR_RXCHR_Pos 0
-#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
-/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
-#define UART_THR_TXCHR_Pos 0
-#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
-#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
-/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
-#define UART_BRGR_CD_Pos 0
-#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
-#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
-/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */
-#define UART_CMPR_VAL1_Pos 0
-#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */
-#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos)))
-#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */
-#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */
-#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */
-#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */
-#define UART_CMPR_VAL2_Pos 16
-#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */
-#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos)))
-/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */
-#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */
-#define UART_WPMR_WPKEY_Pos 8
-#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */
-#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos)))
-#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */
-
-/*@}*/
-
-
-#endif /* _SAMS70_UART_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/usart.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/usart.h
deleted file mode 100644
index 9d4ce79..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/usart.h
+++ /dev/null
@@ -1,432 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_USART_COMPONENT_
-#define _SAMS70_USART_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
-/* ============================================================================= */
-/** \addtogroup SAMS70_USART Universal Synchronous Asynchronous Receiver Transmitter */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Usart hardware registers */
-typedef struct {
- __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */
- __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */
- __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
- __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
- __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
- __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */
- __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */
- __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */
- __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
- __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
- __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
- __I uint32_t Reserved1[9];
- __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */
- __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */
- __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */
- __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */
- __IO uint32_t US_LONMR; /**< \brief (Usart Offset: 0x0060) LON Mode Register */
- __IO uint32_t US_LONPR; /**< \brief (Usart Offset: 0x0064) LON Preamble Register */
- __IO uint32_t US_LONDL; /**< \brief (Usart Offset: 0x0068) LON Data Length Register */
- __IO uint32_t US_LONL2HDR; /**< \brief (Usart Offset: 0x006C) LON L2HDR Register */
- __I uint32_t US_LONBL; /**< \brief (Usart Offset: 0x0070) LON Backlog Register */
- __IO uint32_t US_LONB1TX; /**< \brief (Usart Offset: 0x0074) LON Beta1 Tx Register */
- __IO uint32_t US_LONB1RX; /**< \brief (Usart Offset: 0x0078) LON Beta1 Rx Register */
- __IO uint32_t US_LONPRIO; /**< \brief (Usart Offset: 0x007C) LON Priority Register */
- __IO uint32_t US_IDTTX; /**< \brief (Usart Offset: 0x0080) LON IDT Tx Register */
- __IO uint32_t US_IDTRX; /**< \brief (Usart Offset: 0x0084) LON IDT Rx Register */
- __IO uint32_t US_ICDIFF; /**< \brief (Usart Offset: 0x0088) IC DIFF Register */
- __I uint32_t Reserved2[22];
- __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */
- __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */
-} Usart;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
-#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
-#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
-#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
-#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
-#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
-#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
-#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
-#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
-#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
-#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received */
-#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
-#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Start Time-out Immediately */
-#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Pin Control */
-#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Pin Control */
-#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */
-#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */
-#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
-#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
-/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
-#define US_MR_USART_MODE_Pos 0
-#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */
-#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos)))
-#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
-#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
-#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
-#define US_MR_USART_MODE_LON (0x9u << 0) /**< \brief (US_MR) LON */
-#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master */
-#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
-#define US_MR_USCLKS_Pos 4
-#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
-#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos)))
-#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */
-#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock divided (DIV=DIV=8) is selected */
-#define US_MR_USCLKS_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */
-#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial clock (SCK) is selected */
-#define US_MR_CHRL_Pos 6
-#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */
-#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos)))
-#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
-#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
-#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
-#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
-#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
-#define US_MR_PAR_Pos 9
-#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
-#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos)))
-#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
-#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
-#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
-#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
-#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
-#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
-#define US_MR_NBSTOP_Pos 12
-#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
-#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos)))
-#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
-#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
-#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
-#define US_MR_CHMODE_Pos 14
-#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
-#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos)))
-#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */
-#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
-#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
-#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
-#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
-#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
-#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
-#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
-#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */
-#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
-#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
-#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
-#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
-#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
-#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */
-/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
-#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
-#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
-#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
-#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
-#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
-#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
-#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
-#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
-#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
-#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
-#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */
-#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */
-#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */
-#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */
-#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */
-#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */
-#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */
-#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */
-#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */
-#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */
-#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */
-#define US_IER_LSFE (0x1u << 6) /**< \brief (US_IER) LON Short Frame Error Interrupt Enable */
-#define US_IER_LCRCE (0x1u << 7) /**< \brief (US_IER) LON CRC Error Interrupt Enable */
-#define US_IER_LTXD (0x1u << 24) /**< \brief (US_IER) LON Transmission Done Interrupt Enable */
-#define US_IER_LCOL (0x1u << 25) /**< \brief (US_IER) LON Collision Interrupt Enable */
-#define US_IER_LFET (0x1u << 26) /**< \brief (US_IER) LON Frame Early Termination Interrupt Enable */
-#define US_IER_LRXD (0x1u << 27) /**< \brief (US_IER) LON Reception Done Interrupt Enable */
-#define US_IER_LBLOVFE (0x1u << 28) /**< \brief (US_IER) LON Backlog Overflow Error Interrupt Enable */
-/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
-#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
-#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
-#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
-#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */
-#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
-#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
-#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
-#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
-#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
-#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
-#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */
-#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */
-#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */
-#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */
-#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */
-#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */
-#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */
-#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */
-#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */
-#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */
-#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */
-#define US_IDR_LSFE (0x1u << 6) /**< \brief (US_IDR) LON Short Frame Error Interrupt Disable */
-#define US_IDR_LCRCE (0x1u << 7) /**< \brief (US_IDR) LON CRC Error Interrupt Disable */
-#define US_IDR_LTXD (0x1u << 24) /**< \brief (US_IDR) LON Transmission Done Interrupt Disable */
-#define US_IDR_LCOL (0x1u << 25) /**< \brief (US_IDR) LON Collision Interrupt Disable */
-#define US_IDR_LFET (0x1u << 26) /**< \brief (US_IDR) LON Frame Early Termination Interrupt Disable */
-#define US_IDR_LRXD (0x1u << 27) /**< \brief (US_IDR) LON Reception Done Interrupt Disable */
-#define US_IDR_LBLOVFE (0x1u << 28) /**< \brief (US_IDR) LON Backlog Overflow Error Interrupt Disable */
-/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
-#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
-#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
-#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
-#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
-#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
-#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
-#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
-#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
-#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
-#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
-#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */
-#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */
-#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */
-#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */
-#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */
-#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */
-#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */
-#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */
-#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */
-#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */
-#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */
-#define US_IMR_LSFE (0x1u << 6) /**< \brief (US_IMR) LON Short Frame Error Interrupt Mask */
-#define US_IMR_LCRCE (0x1u << 7) /**< \brief (US_IMR) LON CRC Error Interrupt Mask */
-#define US_IMR_LTXD (0x1u << 24) /**< \brief (US_IMR) LON Transmission Done Interrupt Mask */
-#define US_IMR_LCOL (0x1u << 25) /**< \brief (US_IMR) LON Collision Interrupt Mask */
-#define US_IMR_LFET (0x1u << 26) /**< \brief (US_IMR) LON Frame Early Termination Interrupt Mask */
-#define US_IMR_LRXD (0x1u << 27) /**< \brief (US_IMR) LON Reception Done Interrupt Mask */
-#define US_IMR_LBLOVFE (0x1u << 28) /**< \brief (US_IMR) LON Backlog Overflow Error Interrupt Mask */
-/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
-#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (cleared by reading US_RHR) */
-#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (cleared by writing US_THR) */
-#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) */
-#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (cleared by writing US_THR) */
-#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag (cleared on read) */
-#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
-#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) */
-#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */
-#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LSFE (0x1u << 6) /**< \brief (US_CSR) LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LCRCE (0x1u << 7) /**< \brief (US_CSR) LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LTXD (0x1u << 24) /**< \brief (US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LCOL (0x1u << 25) /**< \brief (US_CSR) LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LFET (0x1u << 26) /**< \brief (US_CSR) LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LRXD (0x1u << 27) /**< \brief (US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LBLOVFE (0x1u << 28) /**< \brief (US_CSR) LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) */
-/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */
-#define US_RHR_RXCHR_Pos 0
-#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
-#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
-/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */
-#define US_THR_TXCHR_Pos 0
-#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
-#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
-#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */
-/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
-#define US_BRGR_CD_Pos 0
-#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
-#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
-#define US_BRGR_FP_Pos 16
-#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
-#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
-/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
-#define US_RTOR_TO_Pos 0
-#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
-#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
-/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
-#define US_TTGR_TG_Pos 0
-#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
-#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
-#define US_TTGR_PCYCLE_Pos 0
-#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos) /**< \brief (US_TTGR) LON PCYCLE Length */
-#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos)))
-/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */
-#define US_MAN_TX_PL_Pos 0
-#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
-#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
-#define US_MAN_TX_PP_Pos 8
-#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
-#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos)))
-#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
-#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
-#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
-#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
-#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
-#define US_MAN_RX_PL_Pos 16
-#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
-#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
-#define US_MAN_RX_PP_Pos 24
-#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
-#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos)))
-#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
-#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
-#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
-#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
-#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
-#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */
-#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */
-#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) */
-/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */
-#define US_LINMR_NACT_Pos 0
-#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */
-#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos)))
-#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */
-#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */
-#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */
-#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */
-#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */
-#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */
-#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */
-#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */
-#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */
-#define US_LINMR_DLC_Pos 8
-#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */
-#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))
-#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */
-#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */
-/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */
-#define US_LINIR_IDCHR_Pos 0
-#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */
-#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))
-/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */
-#define US_LINBRR_LINCD_Pos 0
-#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */
-#define US_LINBRR_LINFP_Pos 16
-#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */
-/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */
-#define US_LONMR_COMMT (0x1u << 0) /**< \brief (US_LONMR) LON comm_type Parameter Value */
-#define US_LONMR_COLDET (0x1u << 1) /**< \brief (US_LONMR) LON Collision Detection Feature */
-#define US_LONMR_TCOL (0x1u << 2) /**< \brief (US_LONMR) Terminate Frame upon Collision Notification */
-#define US_LONMR_CDTAIL (0x1u << 3) /**< \brief (US_LONMR) LON Collision Detection on Frame Tail */
-#define US_LONMR_DMAM (0x1u << 4) /**< \brief (US_LONMR) LON DMA Mode */
-#define US_LONMR_LCDS (0x1u << 5) /**< \brief (US_LONMR) LON Collision Detection Source */
-#define US_LONMR_EOFS_Pos 16
-#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos) /**< \brief (US_LONMR) End of Frame Condition Size */
-#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos)))
-/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */
-#define US_LONPR_LONPL_Pos 0
-#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos) /**< \brief (US_LONPR) LON Preamble Length */
-#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos)))
-/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */
-#define US_LONDL_LONDL_Pos 0
-#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos) /**< \brief (US_LONDL) LON Data Length */
-#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos)))
-/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */
-#define US_LONL2HDR_BLI_Pos 0
-#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos) /**< \brief (US_LONL2HDR) LON Backlog Increment */
-#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos)))
-#define US_LONL2HDR_ALTP (0x1u << 6) /**< \brief (US_LONL2HDR) LON Alternate Path Bit */
-#define US_LONL2HDR_PB (0x1u << 7) /**< \brief (US_LONL2HDR) LON Priority Bit */
-/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */
-#define US_LONBL_LONBL_Pos 0
-#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos) /**< \brief (US_LONBL) LON Node Backlog Value */
-/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */
-#define US_LONB1TX_BETA1TX_Pos 0
-#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos) /**< \brief (US_LONB1TX) LON Beta1 Length after Transmission */
-#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos)))
-/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */
-#define US_LONB1RX_BETA1RX_Pos 0
-#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos) /**< \brief (US_LONB1RX) LON Beta1 Length after Reception */
-#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos)))
-/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */
-#define US_LONPRIO_PSNB_Pos 0
-#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos) /**< \brief (US_LONPRIO) LON Priority Slot Number */
-#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos)))
-#define US_LONPRIO_NPS_Pos 8
-#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos) /**< \brief (US_LONPRIO) LON Node Priority Slot */
-#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos)))
-/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */
-#define US_IDTTX_IDTTX_Pos 0
-#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos) /**< \brief (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) */
-#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos)))
-/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */
-#define US_IDTRX_IDTRX_Pos 0
-#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos) /**< \brief (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) */
-#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos)))
-/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */
-#define US_ICDIFF_ICDIFF_Pos 0
-#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos) /**< \brief (US_ICDIFF) IC Differentiator Number */
-#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos)))
-/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */
-#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */
-#define US_WPMR_WPKEY_Pos 8
-#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */
-#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
-#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
-/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */
-#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */
-#define US_WPSR_WPVSRC_Pos 8
-#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_USART_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/usbhs.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/usbhs.h
deleted file mode 100644
index 0391a17..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/usbhs.h
+++ /dev/null
@@ -1,975 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_USBHS_COMPONENT_
-#define _SAMS70_USBHS_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR USB High-Speed Interface */
-/* ============================================================================= */
-/** \addtogroup SAMS70_USBHS USB High-Speed Interface */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief UsbhsDevdma hardware registers */
-typedef struct {
- __IO uint32_t USBHS_DEVDMANXTDSC; /**< \brief (UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */
- __IO uint32_t USBHS_DEVDMAADDRESS; /**< \brief (UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register */
- __IO uint32_t USBHS_DEVDMACONTROL; /**< \brief (UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register */
- __IO uint32_t USBHS_DEVDMASTATUS; /**< \brief (UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register */
-} UsbhsDevdma;
-/** \brief UsbhsHstdma hardware registers */
-typedef struct {
- __IO uint32_t USBHS_HSTDMANXTDSC; /**< \brief (UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */
- __IO uint32_t USBHS_HSTDMAADDRESS; /**< \brief (UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register */
- __IO uint32_t USBHS_HSTDMACONTROL; /**< \brief (UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register */
- __IO uint32_t USBHS_HSTDMASTATUS; /**< \brief (UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register */
-} UsbhsHstdma;
-/** \brief Usbhs hardware registers */
-#define USBHSDEVDMA_NUMBER 7
-#define USBHSHSTDMA_NUMBER 7
-typedef struct {
- __IO uint32_t USBHS_DEVCTRL; /**< \brief (Usbhs Offset: 0x0000) Device General Control Register */
- __I uint32_t USBHS_DEVISR; /**< \brief (Usbhs Offset: 0x0004) Device Global Interrupt Status Register */
- __O uint32_t USBHS_DEVICR; /**< \brief (Usbhs Offset: 0x0008) Device Global Interrupt Clear Register */
- __O uint32_t USBHS_DEVIFR; /**< \brief (Usbhs Offset: 0x000C) Device Global Interrupt Set Register */
- __I uint32_t USBHS_DEVIMR; /**< \brief (Usbhs Offset: 0x0010) Device Global Interrupt Mask Register */
- __O uint32_t USBHS_DEVIDR; /**< \brief (Usbhs Offset: 0x0014) Device Global Interrupt Disable Register */
- __O uint32_t USBHS_DEVIER; /**< \brief (Usbhs Offset: 0x0018) Device Global Interrupt Enable Register */
- __IO uint32_t USBHS_DEVEPT; /**< \brief (Usbhs Offset: 0x001C) Device Endpoint Register */
- __I uint32_t USBHS_DEVFNUM; /**< \brief (Usbhs Offset: 0x0020) Device Frame Number Register */
- __I uint32_t Reserved1[55];
- __IO uint32_t USBHS_DEVEPTCFG[10]; /**< \brief (Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */
- __I uint32_t Reserved2[2];
- __I uint32_t USBHS_DEVEPTISR[10]; /**< \brief (Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0) */
- __I uint32_t Reserved3[2];
- __O uint32_t USBHS_DEVEPTICR[10]; /**< \brief (Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0) */
- __I uint32_t Reserved4[2];
- __O uint32_t USBHS_DEVEPTIFR[10]; /**< \brief (Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0) */
- __I uint32_t Reserved5[2];
- __I uint32_t USBHS_DEVEPTIMR[10]; /**< \brief (Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */
- __I uint32_t Reserved6[2];
- __O uint32_t USBHS_DEVEPTIER[10]; /**< \brief (Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */
- __I uint32_t Reserved7[2];
- __O uint32_t USBHS_DEVEPTIDR[10]; /**< \brief (Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0) */
- __I uint32_t Reserved8[50];
- UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x310) n = 1 .. 7 */
- __I uint32_t Reserved9[32];
- __IO uint32_t USBHS_HSTCTRL; /**< \brief (Usbhs Offset: 0x0400) Host General Control Register */
- __I uint32_t USBHS_HSTISR; /**< \brief (Usbhs Offset: 0x0404) Host Global Interrupt Status Register */
- __O uint32_t USBHS_HSTICR; /**< \brief (Usbhs Offset: 0x0408) Host Global Interrupt Clear Register */
- __O uint32_t USBHS_HSTIFR; /**< \brief (Usbhs Offset: 0x040C) Host Global Interrupt Set Register */
- __I uint32_t USBHS_HSTIMR; /**< \brief (Usbhs Offset: 0x0410) Host Global Interrupt Mask Register */
- __O uint32_t USBHS_HSTIDR; /**< \brief (Usbhs Offset: 0x0414) Host Global Interrupt Disable Register */
- __O uint32_t USBHS_HSTIER; /**< \brief (Usbhs Offset: 0x0418) Host Global Interrupt Enable Register */
- __IO uint32_t USBHS_HSTPIP; /**< \brief (Usbhs Offset: 0x0041C) Host Pipe Register */
- __IO uint32_t USBHS_HSTFNUM; /**< \brief (Usbhs Offset: 0x0420) Host Frame Number Register */
- __IO uint32_t USBHS_HSTADDR1; /**< \brief (Usbhs Offset: 0x0424) Host Address 1 Register */
- __IO uint32_t USBHS_HSTADDR2; /**< \brief (Usbhs Offset: 0x0428) Host Address 2 Register */
- __IO uint32_t USBHS_HSTADDR3; /**< \brief (Usbhs Offset: 0x042C) Host Address 3 Register */
- __I uint32_t Reserved10[52];
- __IO uint32_t USBHS_HSTPIPCFG[10]; /**< \brief (Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0) */
- __I uint32_t Reserved11[2];
- __I uint32_t USBHS_HSTPIPISR[10]; /**< \brief (Usbhs Offset: 0x530) Host Pipe Status Register (n = 0) */
- __I uint32_t Reserved12[2];
- __O uint32_t USBHS_HSTPIPICR[10]; /**< \brief (Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0) */
- __I uint32_t Reserved13[2];
- __O uint32_t USBHS_HSTPIPIFR[10]; /**< \brief (Usbhs Offset: 0x590) Host Pipe Set Register (n = 0) */
- __I uint32_t Reserved14[2];
- __I uint32_t USBHS_HSTPIPIMR[10]; /**< \brief (Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */
- __I uint32_t Reserved15[2];
- __O uint32_t USBHS_HSTPIPIER[10]; /**< \brief (Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */
- __I uint32_t Reserved16[2];
- __O uint32_t USBHS_HSTPIPIDR[10]; /**< \brief (Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0) */
- __I uint32_t Reserved17[2];
- __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< \brief (Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0) */
- __I uint32_t Reserved18[2];
- __IO uint32_t USBHS_HSTPIPERR[10]; /**< \brief (Usbhs Offset: 0x680) Host Pipe Error Register (n = 0) */
- __I uint32_t Reserved19[26];
- UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x710) n = 1 .. 7 */
- __I uint32_t Reserved20[32];
- __IO uint32_t USBHS_CTRL; /**< \brief (Usbhs Offset: 0x0800) General Control Register */
- __I uint32_t USBHS_SR; /**< \brief (Usbhs Offset: 0x0804) General Status Register */
- __O uint32_t USBHS_SCR; /**< \brief (Usbhs Offset: 0x0808) General Status Clear Register */
- __O uint32_t USBHS_SFR; /**< \brief (Usbhs Offset: 0x080C) General Status Set Register */
- __IO uint32_t USBHS_TSTA1; /**< \brief (Usbhs Offset: 0x0810) General Test A1 Register */
- __IO uint32_t USBHS_TSTA2; /**< \brief (Usbhs Offset: 0x0814) General Test A2 Register */
- __I uint32_t USBHS_VERSION; /**< \brief (Usbhs Offset: 0x0818) General Version Register */
- __I uint32_t Reserved21[4];
- __I uint32_t USBHS_FSM; /**< \brief (Usbhs Offset: 0x082C) General Finite State Machine Register */
-} Usbhs;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */
-#define USBHS_DEVCTRL_UADD_Pos 0
-#define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos) /**< \brief (USBHS_DEVCTRL) USB Address */
-#define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos)))
-#define USBHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (USBHS_DEVCTRL) Address Enable */
-#define USBHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (USBHS_DEVCTRL) Detach */
-#define USBHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (USBHS_DEVCTRL) Remote Wake-Up */
-#define USBHS_DEVCTRL_SPDCONF_Pos 10
-#define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos) /**< \brief (USBHS_DEVCTRL) Mode Configuration */
-#define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos)))
-#define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */
-#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */
-#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (USBHS_DEVCTRL) Forced high speed. */
-#define USBHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */
-#define USBHS_DEVCTRL_LS (0x1u << 12) /**< \brief (USBHS_DEVCTRL) Low-Speed Mode Force */
-#define USBHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (USBHS_DEVCTRL) Test mode J */
-#define USBHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (USBHS_DEVCTRL) Test mode K */
-#define USBHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (USBHS_DEVCTRL) Test packet mode */
-#define USBHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (USBHS_DEVCTRL) Specific Operational mode */
-/* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */
-#define USBHS_DEVISR_SUSP (0x1u << 0) /**< \brief (USBHS_DEVISR) Suspend Interrupt */
-#define USBHS_DEVISR_MSOF (0x1u << 1) /**< \brief (USBHS_DEVISR) Micro Start of Frame Interrupt */
-#define USBHS_DEVISR_SOF (0x1u << 2) /**< \brief (USBHS_DEVISR) Start of Frame Interrupt */
-#define USBHS_DEVISR_EORST (0x1u << 3) /**< \brief (USBHS_DEVISR) End of Reset Interrupt */
-#define USBHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (USBHS_DEVISR) Wake-Up Interrupt */
-#define USBHS_DEVISR_EORSM (0x1u << 5) /**< \brief (USBHS_DEVISR) End of Resume Interrupt */
-#define USBHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (USBHS_DEVISR) Upstream Resume Interrupt */
-#define USBHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVISR) Endpoint 0 Interrupt */
-#define USBHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVISR) Endpoint 1 Interrupt */
-#define USBHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVISR) Endpoint 2 Interrupt */
-#define USBHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVISR) Endpoint 3 Interrupt */
-#define USBHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVISR) Endpoint 4 Interrupt */
-#define USBHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVISR) Endpoint 5 Interrupt */
-#define USBHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVISR) Endpoint 6 Interrupt */
-#define USBHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVISR) Endpoint 7 Interrupt */
-#define USBHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVISR) Endpoint 8 Interrupt */
-#define USBHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVISR) Endpoint 9 Interrupt */
-#define USBHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVISR) Endpoint 10 Interrupt */
-#define USBHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVISR) Endpoint 11 Interrupt */
-#define USBHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVISR) DMA Channel 1 Interrupt */
-#define USBHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVISR) DMA Channel 2 Interrupt */
-#define USBHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVISR) DMA Channel 3 Interrupt */
-#define USBHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVISR) DMA Channel 4 Interrupt */
-#define USBHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVISR) DMA Channel 5 Interrupt */
-#define USBHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVISR) DMA Channel 6 Interrupt */
-#define USBHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVISR) DMA Channel 7 Interrupt */
-/* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */
-#define USBHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (USBHS_DEVICR) Suspend Interrupt Clear */
-#define USBHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (USBHS_DEVICR) Micro Start of Frame Interrupt Clear */
-#define USBHS_DEVICR_SOFC (0x1u << 2) /**< \brief (USBHS_DEVICR) Start of Frame Interrupt Clear */
-#define USBHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (USBHS_DEVICR) End of Reset Interrupt Clear */
-#define USBHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (USBHS_DEVICR) Wake-Up Interrupt Clear */
-#define USBHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (USBHS_DEVICR) End of Resume Interrupt Clear */
-#define USBHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (USBHS_DEVICR) Upstream Resume Interrupt Clear */
-/* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */
-#define USBHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (USBHS_DEVIFR) Suspend Interrupt Set */
-#define USBHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (USBHS_DEVIFR) Micro Start of Frame Interrupt Set */
-#define USBHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (USBHS_DEVIFR) Start of Frame Interrupt Set */
-#define USBHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (USBHS_DEVIFR) End of Reset Interrupt Set */
-#define USBHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (USBHS_DEVIFR) Wake-Up Interrupt Set */
-#define USBHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (USBHS_DEVIFR) End of Resume Interrupt Set */
-#define USBHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (USBHS_DEVIFR) Upstream Resume Interrupt Set */
-#define USBHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIFR) DMA Channel 1 Interrupt Set */
-#define USBHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIFR) DMA Channel 2 Interrupt Set */
-#define USBHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIFR) DMA Channel 3 Interrupt Set */
-#define USBHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIFR) DMA Channel 4 Interrupt Set */
-#define USBHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIFR) DMA Channel 5 Interrupt Set */
-#define USBHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIFR) DMA Channel 6 Interrupt Set */
-#define USBHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIFR) DMA Channel 7 Interrupt Set */
-/* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */
-#define USBHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (USBHS_DEVIMR) Suspend Interrupt Mask */
-#define USBHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask */
-#define USBHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (USBHS_DEVIMR) Start of Frame Interrupt Mask */
-#define USBHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (USBHS_DEVIMR) End of Reset Interrupt Mask */
-#define USBHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (USBHS_DEVIMR) Wake-Up Interrupt Mask */
-#define USBHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (USBHS_DEVIMR) End of Resume Interrupt Mask */
-#define USBHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (USBHS_DEVIMR) Upstream Resume Interrupt Mask */
-#define USBHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIMR) Endpoint 0 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIMR) Endpoint 1 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIMR) Endpoint 2 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIMR) Endpoint 3 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIMR) Endpoint 4 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIMR) Endpoint 5 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIMR) Endpoint 6 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIMR) Endpoint 7 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIMR) Endpoint 8 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIMR) Endpoint 9 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIMR) Endpoint 10 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIMR) Endpoint 11 Interrupt Mask */
-#define USBHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask */
-#define USBHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask */
-#define USBHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask */
-#define USBHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask */
-#define USBHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask */
-#define USBHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask */
-#define USBHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask */
-/* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */
-#define USBHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (USBHS_DEVIDR) Suspend Interrupt Disable */
-#define USBHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable */
-#define USBHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (USBHS_DEVIDR) Start of Frame Interrupt Disable */
-#define USBHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (USBHS_DEVIDR) End of Reset Interrupt Disable */
-#define USBHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (USBHS_DEVIDR) Wake-Up Interrupt Disable */
-#define USBHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (USBHS_DEVIDR) End of Resume Interrupt Disable */
-#define USBHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (USBHS_DEVIDR) Upstream Resume Interrupt Disable */
-#define USBHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIDR) Endpoint 0 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIDR) Endpoint 1 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIDR) Endpoint 2 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIDR) Endpoint 3 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIDR) Endpoint 4 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIDR) Endpoint 5 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIDR) Endpoint 6 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIDR) Endpoint 7 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIDR) Endpoint 8 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIDR) Endpoint 9 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIDR) Endpoint 10 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIDR) Endpoint 11 Interrupt Disable */
-#define USBHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable */
-#define USBHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable */
-#define USBHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable */
-#define USBHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable */
-#define USBHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable */
-#define USBHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable */
-#define USBHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable */
-/* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */
-#define USBHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (USBHS_DEVIER) Suspend Interrupt Enable */
-#define USBHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (USBHS_DEVIER) Micro Start of Frame Interrupt Enable */
-#define USBHS_DEVIER_SOFES (0x1u << 2) /**< \brief (USBHS_DEVIER) Start of Frame Interrupt Enable */
-#define USBHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (USBHS_DEVIER) End of Reset Interrupt Enable */
-#define USBHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (USBHS_DEVIER) Wake-Up Interrupt Enable */
-#define USBHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (USBHS_DEVIER) End of Resume Interrupt Enable */
-#define USBHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (USBHS_DEVIER) Upstream Resume Interrupt Enable */
-#define USBHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIER) Endpoint 0 Interrupt Enable */
-#define USBHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIER) Endpoint 1 Interrupt Enable */
-#define USBHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIER) Endpoint 2 Interrupt Enable */
-#define USBHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIER) Endpoint 3 Interrupt Enable */
-#define USBHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIER) Endpoint 4 Interrupt Enable */
-#define USBHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIER) Endpoint 5 Interrupt Enable */
-#define USBHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIER) Endpoint 6 Interrupt Enable */
-#define USBHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIER) Endpoint 7 Interrupt Enable */
-#define USBHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIER) Endpoint 8 Interrupt Enable */
-#define USBHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIER) Endpoint 9 Interrupt Enable */
-#define USBHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIER) Endpoint 10 Interrupt Enable */
-#define USBHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIER) Endpoint 11 Interrupt Enable */
-#define USBHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIER) DMA Channel 1 Interrupt Enable */
-#define USBHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIER) DMA Channel 2 Interrupt Enable */
-#define USBHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIER) DMA Channel 3 Interrupt Enable */
-#define USBHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIER) DMA Channel 4 Interrupt Enable */
-#define USBHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIER) DMA Channel 5 Interrupt Enable */
-#define USBHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIER) DMA Channel 6 Interrupt Enable */
-#define USBHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIER) DMA Channel 7 Interrupt Enable */
-/* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */
-#define USBHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (USBHS_DEVEPT) Endpoint 0 Enable */
-#define USBHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (USBHS_DEVEPT) Endpoint 1 Enable */
-#define USBHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (USBHS_DEVEPT) Endpoint 2 Enable */
-#define USBHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (USBHS_DEVEPT) Endpoint 3 Enable */
-#define USBHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (USBHS_DEVEPT) Endpoint 4 Enable */
-#define USBHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (USBHS_DEVEPT) Endpoint 5 Enable */
-#define USBHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (USBHS_DEVEPT) Endpoint 6 Enable */
-#define USBHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (USBHS_DEVEPT) Endpoint 7 Enable */
-#define USBHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (USBHS_DEVEPT) Endpoint 8 Enable */
-#define USBHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (USBHS_DEVEPT) Endpoint 0 Reset */
-#define USBHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (USBHS_DEVEPT) Endpoint 1 Reset */
-#define USBHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (USBHS_DEVEPT) Endpoint 2 Reset */
-#define USBHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (USBHS_DEVEPT) Endpoint 3 Reset */
-#define USBHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (USBHS_DEVEPT) Endpoint 4 Reset */
-#define USBHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (USBHS_DEVEPT) Endpoint 5 Reset */
-#define USBHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (USBHS_DEVEPT) Endpoint 6 Reset */
-#define USBHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (USBHS_DEVEPT) Endpoint 7 Reset */
-#define USBHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (USBHS_DEVEPT) Endpoint 8 Reset */
-/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */
-#define USBHS_DEVFNUM_MFNUM_Pos 0
-#define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos) /**< \brief (USBHS_DEVFNUM) Micro Frame Number */
-#define USBHS_DEVFNUM_FNUM_Pos 3
-#define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos) /**< \brief (USBHS_DEVFNUM) Frame Number */
-#define USBHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (USBHS_DEVFNUM) Frame Number CRC Error */
-/* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */
-#define USBHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate */
-#define USBHS_DEVEPTCFG_EPBK_Pos 2
-#define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Banks */
-#define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos)))
-#define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Single-bank endpoint */
-#define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Double-bank endpoint */
-#define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Triple-bank endpoint */
-#define USBHS_DEVEPTCFG_EPSIZE_Pos 4
-#define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Size */
-#define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos)))
-#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 8 bytes */
-#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 16 bytes */
-#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 32 bytes */
-#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 64 bytes */
-#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 128 bytes */
-#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 256 bytes */
-#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 512 bytes */
-#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 1024 bytes */
-#define USBHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Direction */
-#define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is OUT. */
-#define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */
-#define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (USBHS_DEVEPTCFG[10]) Automatic Switch */
-#define USBHS_DEVEPTCFG_EPTYPE_Pos 11
-#define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Type */
-#define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos)))
-#define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Control */
-#define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Isochronous */
-#define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Bulk */
-#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Interrupt */
-#define USBHS_DEVEPTCFG_NBTRANS_Pos 13
-#define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint */
-#define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos)))
-#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */
-#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe. */
-#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank. */
-#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank. */
-/* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */
-#define USBHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */
-#define USBHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (USBHS_DEVEPTISR[10]) Received OUT Data Interrupt */
-#define USBHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Received SETUP Interrupt */
-#define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) NAKed OUT Interrupt */
-#define USBHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) NAKed IN Interrupt */
-#define USBHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (USBHS_DEVEPTISR[10]) Overflow Interrupt */
-#define USBHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) STALLed Interrupt */
-#define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (USBHS_DEVEPTISR[10]) Short Packet Interrupt */
-#define USBHS_DEVEPTISR_DTSEQ_Pos 8
-#define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Data Toggle Sequence */
-#define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data0 toggle sequence */
-#define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data1 toggle sequence */
-#define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */
-#define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */
-#define USBHS_DEVEPTISR_NBUSYBK_Pos 12
-#define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Number of Busy Banks */
-#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 0 busy bank (all banks free) */
-#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 1 busy bank */
-#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 2 busy banks */
-#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 3 busy banks */
-#define USBHS_DEVEPTISR_CURRBK_Pos 14
-#define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Current Bank */
-#define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank0 */
-#define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank1 */
-#define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank2 */
-#define USBHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (USBHS_DEVEPTISR[10]) Read/Write Allowed */
-#define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (USBHS_DEVEPTISR[10]) Control Direction */
-#define USBHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (USBHS_DEVEPTISR[10]) Configuration OK Status */
-#define USBHS_DEVEPTISR_BYCT_Pos 20
-#define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Byte Count */
-#define USBHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Underflow Interrupt */
-#define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt */
-#define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */
-#define USBHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) CRC Error Interrupt */
-#define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */
-/* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */
-#define USBHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */
-#define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */
-#define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */
-#define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */
-#define USBHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */
-#define USBHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_DEVEPTICR[10]) Overflow Interrupt Clear */
-#define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) STALLed Interrupt Clear */
-#define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear */
-#define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Underflow Interrupt Clear */
-#define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear */
-#define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */
-#define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear */
-/* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */
-#define USBHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */
-#define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */
-#define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */
-#define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */
-#define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */
-#define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_DEVEPTIFR[10]) Overflow Interrupt Set */
-#define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) STALLed Interrupt Set */
-#define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set */
-#define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */
-#define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Underflow Interrupt Set */
-#define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set */
-#define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */
-#define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set */
-/* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */
-#define USBHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */
-#define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt */
-#define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Received SETUP Interrupt */
-#define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt */
-#define USBHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed IN Interrupt */
-#define USBHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (USBHS_DEVEPTIMR[10]) Overflow Interrupt */
-#define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) STALLed Interrupt */
-#define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (USBHS_DEVEPTIMR[10]) Short Packet Interrupt */
-#define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */
-#define USBHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (USBHS_DEVEPTIMR[10]) Kill IN Bank */
-#define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_DEVEPTIMR[10]) FIFO Control */
-#define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */
-#define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (USBHS_DEVEPTIMR[10]) NYET Token Disable */
-#define USBHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_DEVEPTIMR[10]) Reset Data Toggle */
-#define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (USBHS_DEVEPTIMR[10]) STALL Request */
-#define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Underflow Interrupt */
-#define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */
-#define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */
-#define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) CRC Error Interrupt */
-#define USBHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (USBHS_DEVEPTIMR[10]) MData Interrupt */
-#define USBHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (USBHS_DEVEPTIMR[10]) DataX Interrupt */
-#define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (USBHS_DEVEPTIMR[10]) Transaction Error Interrupt */
-/* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */
-#define USBHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */
-#define USBHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */
-#define USBHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */
-#define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */
-#define USBHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */
-#define USBHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (USBHS_DEVEPTIER[10]) Overflow Interrupt Enable */
-#define USBHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) STALLed Interrupt Enable */
-#define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable */
-#define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */
-#define USBHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (USBHS_DEVEPTIER[10]) Kill IN Bank */
-#define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (USBHS_DEVEPTIER[10]) FIFO Control */
-#define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */
-#define USBHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (USBHS_DEVEPTIER[10]) NYET Token Disable Enable */
-#define USBHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_DEVEPTIER[10]) Reset Data Toggle Enable */
-#define USBHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (USBHS_DEVEPTIER[10]) STALL Request Enable */
-#define USBHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Underflow Interrupt Enable */
-#define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */
-#define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */
-#define USBHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable */
-#define USBHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (USBHS_DEVEPTIER[10]) MData Interrupt Enable */
-#define USBHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (USBHS_DEVEPTIER[10]) DataX Interrupt Enable */
-#define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */
-/* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */
-#define USBHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */
-#define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */
-#define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */
-#define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */
-#define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */
-#define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear */
-#define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear */
-#define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */
-#define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */
-#define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_DEVEPTIDR[10]) FIFO Control Clear */
-#define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */
-#define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (USBHS_DEVEPTIDR[10]) NYET Token Disable Clear */
-#define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (USBHS_DEVEPTIDR[10]) STALL Request Clear */
-#define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear */
-#define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */
-#define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */
-#define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */
-#define USBHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (USBHS_DEVEPTIDR[10]) MData Interrupt Clear */
-#define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (USBHS_DEVEPTIDR[10]) DataX Interrupt Clear */
-#define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */
-/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */
-#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0
-#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_DEVDMANXTDSC) Next Descriptor Address */
-#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))
-/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */
-#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0
-#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_DEVDMAADDRESS) Buffer Address */
-#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)))
-/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */
-#define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMACONTROL) Channel Enable Command */
-#define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */
-#define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) */
-#define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Enable Control */
-#define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable */
-#define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable */
-#define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */
-#define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_DEVDMACONTROL) Burst Lock Enable */
-#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16
-#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */
-#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))
-/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */
-#define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMASTATUS) Channel Enable Status */
-#define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_DEVDMASTATUS) Channel Active Status */
-#define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Transfer Status */
-#define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Buffer Status */
-#define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_DEVDMASTATUS) Descriptor Loaded Status */
-#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16
-#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_DEVDMASTATUS) Buffer Byte Count */
-#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)))
-/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */
-#define USBHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (USBHS_HSTCTRL) Start of Frame Generation Enable */
-#define USBHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (USBHS_HSTCTRL) Send USB Reset */
-#define USBHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (USBHS_HSTCTRL) Send USB Resume */
-#define USBHS_HSTCTRL_SPDCONF_Pos 12
-#define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos) /**< \brief (USBHS_HSTCTRL) Mode Configuration */
-#define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos)))
-#define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */
-#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */
-#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (USBHS_HSTCTRL) Forced high speed. */
-#define USBHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */
-/* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */
-#define USBHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (USBHS_HSTISR) Device Connection Interrupt */
-#define USBHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (USBHS_HSTISR) Device Disconnection Interrupt */
-#define USBHS_HSTISR_RSTI (0x1u << 2) /**< \brief (USBHS_HSTISR) USB Reset Sent Interrupt */
-#define USBHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (USBHS_HSTISR) Downstream Resume Sent Interrupt */
-#define USBHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (USBHS_HSTISR) Upstream Resume Received Interrupt */
-#define USBHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (USBHS_HSTISR) Host Start of Frame Interrupt */
-#define USBHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (USBHS_HSTISR) Host Wake-Up Interrupt */
-#define USBHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTISR) Pipe 0 Interrupt */
-#define USBHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTISR) Pipe 1 Interrupt */
-#define USBHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTISR) Pipe 2 Interrupt */
-#define USBHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTISR) Pipe 3 Interrupt */
-#define USBHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTISR) Pipe 4 Interrupt */
-#define USBHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTISR) Pipe 5 Interrupt */
-#define USBHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTISR) Pipe 6 Interrupt */
-#define USBHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTISR) Pipe 7 Interrupt */
-#define USBHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTISR) Pipe 8 Interrupt */
-#define USBHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTISR) Pipe 9 Interrupt */
-#define USBHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTISR) Pipe 10 Interrupt */
-#define USBHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTISR) Pipe 11 Interrupt */
-#define USBHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTISR) DMA Channel 1 Interrupt */
-#define USBHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTISR) DMA Channel 2 Interrupt */
-#define USBHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTISR) DMA Channel 3 Interrupt */
-#define USBHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTISR) DMA Channel 4 Interrupt */
-#define USBHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTISR) DMA Channel 5 Interrupt */
-#define USBHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTISR) DMA Channel 6 Interrupt */
-#define USBHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTISR) DMA Channel 7 Interrupt */
-/* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */
-#define USBHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (USBHS_HSTICR) Device Connection Interrupt Clear */
-#define USBHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (USBHS_HSTICR) Device Disconnection Interrupt Clear */
-#define USBHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (USBHS_HSTICR) USB Reset Sent Interrupt Clear */
-#define USBHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear */
-#define USBHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (USBHS_HSTICR) Upstream Resume Received Interrupt Clear */
-#define USBHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (USBHS_HSTICR) Host Start of Frame Interrupt Clear */
-#define USBHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (USBHS_HSTICR) Host Wake-Up Interrupt Clear */
-/* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */
-#define USBHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (USBHS_HSTIFR) Device Connection Interrupt Set */
-#define USBHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (USBHS_HSTIFR) Device Disconnection Interrupt Set */
-#define USBHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (USBHS_HSTIFR) USB Reset Sent Interrupt Set */
-#define USBHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set */
-#define USBHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (USBHS_HSTIFR) Upstream Resume Received Interrupt Set */
-#define USBHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (USBHS_HSTIFR) Host Start of Frame Interrupt Set */
-#define USBHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (USBHS_HSTIFR) Host Wake-Up Interrupt Set */
-#define USBHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIFR) DMA Channel 1 Interrupt Set */
-#define USBHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIFR) DMA Channel 2 Interrupt Set */
-#define USBHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIFR) DMA Channel 3 Interrupt Set */
-#define USBHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIFR) DMA Channel 4 Interrupt Set */
-#define USBHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIFR) DMA Channel 5 Interrupt Set */
-#define USBHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIFR) DMA Channel 6 Interrupt Set */
-#define USBHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIFR) DMA Channel 7 Interrupt Set */
-/* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */
-#define USBHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (USBHS_HSTIMR) Device Connection Interrupt Enable */
-#define USBHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (USBHS_HSTIMR) Device Disconnection Interrupt Enable */
-#define USBHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (USBHS_HSTIMR) USB Reset Sent Interrupt Enable */
-#define USBHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable */
-#define USBHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable */
-#define USBHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (USBHS_HSTIMR) Host Start of Frame Interrupt Enable */
-#define USBHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (USBHS_HSTIMR) Host Wake-Up Interrupt Enable */
-#define USBHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIMR) Pipe 0 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIMR) Pipe 1 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIMR) Pipe 2 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIMR) Pipe 3 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIMR) Pipe 4 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIMR) Pipe 5 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIMR) Pipe 6 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIMR) Pipe 7 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIMR) Pipe 8 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIMR) Pipe 9 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIMR) Pipe 10 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIMR) Pipe 11 Interrupt Enable */
-#define USBHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable */
-#define USBHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable */
-#define USBHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable */
-#define USBHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable */
-#define USBHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable */
-#define USBHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable */
-#define USBHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable */
-/* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */
-#define USBHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (USBHS_HSTIDR) Device Connection Interrupt Disable */
-#define USBHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (USBHS_HSTIDR) Device Disconnection Interrupt Disable */
-#define USBHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (USBHS_HSTIDR) USB Reset Sent Interrupt Disable */
-#define USBHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable */
-#define USBHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable */
-#define USBHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (USBHS_HSTIDR) Host Start of Frame Interrupt Disable */
-#define USBHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (USBHS_HSTIDR) Host Wake-Up Interrupt Disable */
-#define USBHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIDR) Pipe 0 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIDR) Pipe 1 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIDR) Pipe 2 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIDR) Pipe 3 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIDR) Pipe 4 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIDR) Pipe 5 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIDR) Pipe 6 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIDR) Pipe 7 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIDR) Pipe 8 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIDR) Pipe 9 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIDR) Pipe 10 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIDR) Pipe 11 Interrupt Disable */
-#define USBHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable */
-#define USBHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable */
-#define USBHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable */
-#define USBHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable */
-#define USBHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable */
-#define USBHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable */
-#define USBHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable */
-/* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */
-#define USBHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (USBHS_HSTIER) Device Connection Interrupt Enable */
-#define USBHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (USBHS_HSTIER) Device Disconnection Interrupt Enable */
-#define USBHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (USBHS_HSTIER) USB Reset Sent Interrupt Enable */
-#define USBHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable */
-#define USBHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (USBHS_HSTIER) Upstream Resume Received Interrupt Enable */
-#define USBHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (USBHS_HSTIER) Host Start of Frame Interrupt Enable */
-#define USBHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (USBHS_HSTIER) Host Wake-Up Interrupt Enable */
-#define USBHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIER) Pipe 0 Interrupt Enable */
-#define USBHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIER) Pipe 1 Interrupt Enable */
-#define USBHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIER) Pipe 2 Interrupt Enable */
-#define USBHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIER) Pipe 3 Interrupt Enable */
-#define USBHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIER) Pipe 4 Interrupt Enable */
-#define USBHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIER) Pipe 5 Interrupt Enable */
-#define USBHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIER) Pipe 6 Interrupt Enable */
-#define USBHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIER) Pipe 7 Interrupt Enable */
-#define USBHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIER) Pipe 8 Interrupt Enable */
-#define USBHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIER) Pipe 9 Interrupt Enable */
-#define USBHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIER) Pipe 10 Interrupt Enable */
-#define USBHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIER) Pipe 11 Interrupt Enable */
-#define USBHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIER) DMA Channel 1 Interrupt Enable */
-#define USBHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIER) DMA Channel 2 Interrupt Enable */
-#define USBHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIER) DMA Channel 3 Interrupt Enable */
-#define USBHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIER) DMA Channel 4 Interrupt Enable */
-#define USBHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIER) DMA Channel 5 Interrupt Enable */
-#define USBHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIER) DMA Channel 6 Interrupt Enable */
-#define USBHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIER) DMA Channel 7 Interrupt Enable */
-/* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */
-#define USBHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (USBHS_HSTPIP) Pipe 0 Enable */
-#define USBHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (USBHS_HSTPIP) Pipe 1 Enable */
-#define USBHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (USBHS_HSTPIP) Pipe 2 Enable */
-#define USBHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (USBHS_HSTPIP) Pipe 3 Enable */
-#define USBHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (USBHS_HSTPIP) Pipe 4 Enable */
-#define USBHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (USBHS_HSTPIP) Pipe 5 Enable */
-#define USBHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (USBHS_HSTPIP) Pipe 6 Enable */
-#define USBHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (USBHS_HSTPIP) Pipe 7 Enable */
-#define USBHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (USBHS_HSTPIP) Pipe 8 Enable */
-#define USBHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (USBHS_HSTPIP) Pipe 0 Reset */
-#define USBHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (USBHS_HSTPIP) Pipe 1 Reset */
-#define USBHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (USBHS_HSTPIP) Pipe 2 Reset */
-#define USBHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (USBHS_HSTPIP) Pipe 3 Reset */
-#define USBHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (USBHS_HSTPIP) Pipe 4 Reset */
-#define USBHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (USBHS_HSTPIP) Pipe 5 Reset */
-#define USBHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (USBHS_HSTPIP) Pipe 6 Reset */
-#define USBHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (USBHS_HSTPIP) Pipe 7 Reset */
-#define USBHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (USBHS_HSTPIP) Pipe 8 Reset */
-/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */
-#define USBHS_HSTFNUM_MFNUM_Pos 0
-#define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos) /**< \brief (USBHS_HSTFNUM) Micro Frame Number */
-#define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos)))
-#define USBHS_HSTFNUM_FNUM_Pos 3
-#define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos) /**< \brief (USBHS_HSTFNUM) Frame Number */
-#define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos)))
-#define USBHS_HSTFNUM_FLENHIGH_Pos 16
-#define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (USBHS_HSTFNUM) Frame Length */
-#define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos)))
-/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */
-#define USBHS_HSTADDR1_HSTADDRP0_Pos 0
-#define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */
-#define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos)))
-#define USBHS_HSTADDR1_HSTADDRP1_Pos 8
-#define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */
-#define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos)))
-#define USBHS_HSTADDR1_HSTADDRP2_Pos 16
-#define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */
-#define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos)))
-#define USBHS_HSTADDR1_HSTADDRP3_Pos 24
-#define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */
-#define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos)))
-/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */
-#define USBHS_HSTADDR2_HSTADDRP4_Pos 0
-#define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */
-#define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos)))
-#define USBHS_HSTADDR2_HSTADDRP5_Pos 8
-#define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */
-#define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos)))
-#define USBHS_HSTADDR2_HSTADDRP6_Pos 16
-#define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */
-#define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos)))
-#define USBHS_HSTADDR2_HSTADDRP7_Pos 24
-#define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */
-#define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos)))
-/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */
-#define USBHS_HSTADDR3_HSTADDRP8_Pos 0
-#define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */
-#define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos)))
-#define USBHS_HSTADDR3_HSTADDRP9_Pos 8
-#define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */
-#define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos)))
-/* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */
-#define USBHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Memory Allocate */
-#define USBHS_HSTPIPCFG_PBK_Pos 2
-#define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Banks */
-#define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos)))
-#define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Single-bank pipe */
-#define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Double-bank pipe */
-#define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Triple-bank pipe */
-#define USBHS_HSTPIPCFG_PSIZE_Pos 4
-#define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Size */
-#define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos)))
-#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 8 bytes */
-#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 16 bytes */
-#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 32 bytes */
-#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 64 bytes */
-#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 128 bytes */
-#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 256 bytes */
-#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 512 bytes */
-#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 1024 bytes */
-#define USBHS_HSTPIPCFG_PTOKEN_Pos 8
-#define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Token */
-#define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos)))
-#define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) SETUP */
-#define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) IN */
-#define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) OUT */
-#define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (USBHS_HSTPIPCFG[10]) Automatic Switch */
-#define USBHS_HSTPIPCFG_PTYPE_Pos 12
-#define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Type */
-#define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos)))
-#define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Control */
-#define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Isochronous */
-#define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Bulk */
-#define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Interrupt */
-#define USBHS_HSTPIPCFG_PEPNUM_Pos 16
-#define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Endpoint Number */
-#define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos)))
-#define USBHS_HSTPIPCFG_INTFRQ_Pos 24
-#define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */
-#define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos)))
-#define USBHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (USBHS_HSTPIPCFG[10]) Ping Enable */
-#define USBHS_HSTPIPCFG_BINTERVAL_Pos 24
-#define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction */
-#define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos)))
-/* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */
-#define USBHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (USBHS_HSTPIPISR[10]) Received IN Data Interrupt */
-#define USBHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */
-#define USBHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */
-#define USBHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Error Interrupt */
-#define USBHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (USBHS_HSTPIPISR[10]) NAKed Interrupt */
-#define USBHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (USBHS_HSTPIPISR[10]) Overflow Interrupt */
-#define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) Received STALLed Interrupt */
-#define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (USBHS_HSTPIPISR[10]) Short Packet Interrupt */
-#define USBHS_HSTPIPISR_DTSEQ_Pos 8
-#define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Data Toggle Sequence */
-#define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data0 toggle sequence */
-#define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data1 toggle sequence */
-#define USBHS_HSTPIPISR_NBUSYBK_Pos 12
-#define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Number of Busy Banks */
-#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 0 busy bank (all banks free) */
-#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 1 busy bank */
-#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 2 busy banks */
-#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 3 busy banks */
-#define USBHS_HSTPIPISR_CURRBK_Pos 14
-#define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Current Bank */
-#define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank0 */
-#define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank1 */
-#define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank2 */
-#define USBHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (USBHS_HSTPIPISR[10]) Read/Write Allowed */
-#define USBHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (USBHS_HSTPIPISR[10]) Configuration OK Status */
-#define USBHS_HSTPIPISR_PBYCT_Pos 20
-#define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Byte Count */
-#define USBHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Underflow Interrupt */
-#define USBHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) CRC Error Interrupt */
-/* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */
-#define USBHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */
-#define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */
-#define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */
-#define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (USBHS_HSTPIPICR[10]) NAKed Interrupt Clear */
-#define USBHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_HSTPIPICR[10]) Overflow Interrupt Clear */
-#define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */
-#define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear */
-#define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Underflow Interrupt Clear */
-#define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear */
-/* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */
-#define USBHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */
-#define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */
-#define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */
-#define USBHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */
-#define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (USBHS_HSTPIPIFR[10]) NAKed Interrupt Set */
-#define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_HSTPIPIFR[10]) Overflow Interrupt Set */
-#define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */
-#define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set */
-#define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_HSTPIPIFR[10]) Number of Busy Banks Set */
-#define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Underflow Interrupt Set */
-#define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set */
-/* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */
-#define USBHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */
-#define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */
-#define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */
-#define USBHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */
-#define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable */
-#define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable */
-#define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */
-#define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */
-#define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */
-#define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_HSTPIPIMR[10]) FIFO Control */
-#define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */
-#define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Freeze */
-#define USBHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_HSTPIPIMR[10]) Reset Data Toggle */
-#define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable */
-#define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */
-/* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */
-#define USBHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */
-#define USBHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */
-#define USBHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */
-#define USBHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */
-#define USBHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (USBHS_HSTPIPIER[10]) NAKed Interrupt Enable */
-#define USBHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (USBHS_HSTPIPIER[10]) Overflow Interrupt Enable */
-#define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */
-#define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable */
-#define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_HSTPIPIER[10]) Number of Busy Banks Enable */
-#define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */
-#define USBHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Freeze Enable */
-#define USBHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_HSTPIPIER[10]) Reset Data Toggle Enable */
-#define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Underflow Interrupt Enable */
-#define USBHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable */
-/* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */
-#define USBHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */
-#define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */
-#define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */
-#define USBHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */
-#define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable */
-#define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable */
-#define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */
-#define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */
-#define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable */
-#define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_HSTPIPIDR[10]) FIFO Control Disable */
-#define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */
-#define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Freeze Disable */
-#define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable */
-#define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */
-/* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */
-#define USBHS_HSTPIPINRQ_INRQ_Pos 0
-#define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze */
-#define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos)))
-#define USBHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Mode */
-/* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */
-#define USBHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (USBHS_HSTPIPERR[10]) Data Toggle Error */
-#define USBHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */
-#define USBHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */
-#define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (USBHS_HSTPIPERR[10]) Time-Out Error */
-#define USBHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (USBHS_HSTPIPERR[10]) CRC16 Error */
-#define USBHS_HSTPIPERR_COUNTER_Pos 5
-#define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos) /**< \brief (USBHS_HSTPIPERR[10]) Error Counter */
-#define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos)))
-/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */
-#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0
-#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_HSTDMANXTDSC) Next Descriptor Address */
-#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))
-/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */
-#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0
-#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_HSTDMAADDRESS) Buffer Address */
-#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)))
-/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */
-#define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMACONTROL) Channel Enable Command */
-#define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */
-#define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) */
-#define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Enable Control */
-#define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable */
-#define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable */
-#define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */
-#define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_HSTDMACONTROL) Burst Lock Enable */
-#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16
-#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */
-#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))
-/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */
-#define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMASTATUS) Channel Enable Status */
-#define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_HSTDMASTATUS) Channel Active Status */
-#define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Transfer Status */
-#define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Buffer Status */
-#define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_HSTDMASTATUS) Descriptor Loaded Status */
-#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16
-#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_HSTDMASTATUS) Buffer Byte Count */
-#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)))
-/* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */
-#define USBHS_CTRL_RDERRE (0x1u << 4) /**< \brief (USBHS_CTRL) Remote Device Connection Error Interrupt Enable */
-#define USBHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (USBHS_CTRL) Freeze USB Clock */
-#define USBHS_CTRL_USBE (0x1u << 15) /**< \brief (USBHS_CTRL) USBHS Enable */
-#define USBHS_CTRL_UIMOD (0x1u << 25) /**< \brief (USBHS_CTRL) USBHS Mode */
-#define USBHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (USBHS_CTRL) The module is in USB Host mode. */
-#define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (USBHS_CTRL) The module is in USB Device mode. */
-/* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */
-#define USBHS_SR_RDERRI (0x1u << 4) /**< \brief (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) */
-#define USBHS_SR_VBUSRQ (0x1u << 9) /**< \brief (USBHS_SR) VBus Request (Host mode only) */
-#define USBHS_SR_SPEED_Pos 12
-#define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos) /**< \brief (USBHS_SR) Speed Status (Device mode only) */
-#define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (USBHS_SR) Full-Speed mode */
-#define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (USBHS_SR) High-Speed mode */
-#define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (USBHS_SR) Low-Speed mode */
-#define USBHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (USBHS_SR) UTMI Clock Usable */
-/* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */
-#define USBHS_SCR_RDERRIC (0x1u << 4) /**< \brief (USBHS_SCR) Remote Device Connection Error Interrupt Clear */
-#define USBHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (USBHS_SCR) VBus Request Clear */
-/* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */
-#define USBHS_SFR_RDERRIS (0x1u << 4) /**< \brief (USBHS_SFR) Remote Device Connection Error Interrupt Set */
-#define USBHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (USBHS_SFR) VBus Request Set */
-/* -------- USBHS_TSTA1 : (USBHS Offset: 0x0810) General Test A1 Register -------- */
-#define USBHS_TSTA1_CounterA_Pos 0
-#define USBHS_TSTA1_CounterA_Msk (0x7fffu << USBHS_TSTA1_CounterA_Pos) /**< \brief (USBHS_TSTA1) Counter A */
-#define USBHS_TSTA1_CounterA(value) ((USBHS_TSTA1_CounterA_Msk & ((value) << USBHS_TSTA1_CounterA_Pos)))
-#define USBHS_TSTA1_LoadCntA (0x1u << 15) /**< \brief (USBHS_TSTA1) Load CounterA */
-#define USBHS_TSTA1_CounterB_Pos 16
-#define USBHS_TSTA1_CounterB_Msk (0x3fu << USBHS_TSTA1_CounterB_Pos) /**< \brief (USBHS_TSTA1) Counter B */
-#define USBHS_TSTA1_CounterB(value) ((USBHS_TSTA1_CounterB_Msk & ((value) << USBHS_TSTA1_CounterB_Pos)))
-#define USBHS_TSTA1_LoadCntB (0x1u << 23) /**< \brief (USBHS_TSTA1) Load CounterB */
-#define USBHS_TSTA1_SOFCntMa1_Pos 24
-#define USBHS_TSTA1_SOFCntMa1_Msk (0x7fu << USBHS_TSTA1_SOFCntMa1_Pos) /**< \brief (USBHS_TSTA1) SOF Counter Max */
-#define USBHS_TSTA1_SOFCntMa1(value) ((USBHS_TSTA1_SOFCntMa1_Msk & ((value) << USBHS_TSTA1_SOFCntMa1_Pos)))
-#define USBHS_TSTA1_LoadSOFCnt (0x1u << 31) /**< \brief (USBHS_TSTA1) Load SOF Counter */
-/* -------- USBHS_TSTA2 : (USBHS Offset: 0x0814) General Test A2 Register -------- */
-#define USBHS_TSTA2_FullDetachEn (0x1u << 0) /**< \brief (USBHS_TSTA2) Full Detach Enable */
-#define USBHS_TSTA2_HSSerialMode (0x1u << 1) /**< \brief (USBHS_TSTA2) HS Serial Mode */
-#define USBHS_TSTA2_LoopBackMode (0x1u << 2) /**< \brief (USBHS_TSTA2) Loop-back Mode */
-#define USBHS_TSTA2_DisableGatedClock (0x1u << 3) /**< \brief (USBHS_TSTA2) Disable Gated Clock */
-#define USBHS_TSTA2_ForceSuspendMTo1 (0x1u << 4) /**< \brief (USBHS_TSTA2) Force SuspendM to 1 */
-#define USBHS_TSTA2_ByPassDpll (0x1u << 5) /**< \brief (USBHS_TSTA2) Bypass DPLL */
-#define USBHS_TSTA2_HostHSDisconnectDisable (0x1u << 6) /**< \brief (USBHS_TSTA2) Host HS Disconnect Disable */
-#define USBHS_TSTA2_ForceHSRst_50ms (0x1u << 7) /**< \brief (USBHS_TSTA2) Force HS Reset to 50 ms */
-#define USBHS_TSTA2_RemovePUWhenTX (0x1u << 9) /**< \brief (USBHS_TSTA2) Remove Pull-up When TX */
-/* -------- USBHS_VERSION : (USBHS Offset: 0x0818) General Version Register -------- */
-#define USBHS_VERSION_VERSION_Pos 0
-#define USBHS_VERSION_VERSION_Msk (0xfffu << USBHS_VERSION_VERSION_Pos) /**< \brief (USBHS_VERSION) Version Number */
-#define USBHS_VERSION_MFN_Pos 16
-#define USBHS_VERSION_MFN_Msk (0xfu << USBHS_VERSION_MFN_Pos) /**< \brief (USBHS_VERSION) Metal Fix Number */
-/* -------- USBHS_FSM : (USBHS Offset: 0x082C) General Finite State Machine Register -------- */
-#define USBHS_FSM_DRDSTATE_Pos 0
-#define USBHS_FSM_DRDSTATE_Msk (0xfu << USBHS_FSM_DRDSTATE_Pos) /**< \brief (USBHS_FSM) Dual Role Device State */
-#define USBHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (USBHS_FSM) This is the start state for A-devices (when the ID pin is 0) */
-#define USBHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */
-#define USBHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */
-#define USBHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (USBHS_FSM) In this state, the A-device that operates in Host mode is operational. */
-#define USBHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (USBHS_FSM) The A-device operating as a host is in the Suspend mode. */
-#define USBHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (USBHS_FSM) The A-device operates as a peripheral. */
-#define USBHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */
-#define USBHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */
-#define USBHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */
-#define USBHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (USBHS_FSM) This is the start state for B-device (when the ID pin is 1). */
-#define USBHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the peripheral. */
-#define USBHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (USBHS_FSM) In this state, the B-device is in Suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */
-#define USBHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us)) before becoming Host. */
-#define USBHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */
-#define USBHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the Host. */
-#define USBHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (USBHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */
-
-/*@}*/
-
-
-#endif /* _SAMS70_USBHS_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/utmi.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/utmi.h
deleted file mode 100644
index aa847f6..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/utmi.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UTMI_COMPONENT_
-#define _SAMS70_UTMI_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR USB Transmitter Interface Macrocell */
-/* ============================================================================= */
-/** \addtogroup SAMS70_UTMI USB Transmitter Interface Macrocell */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Utmi hardware registers */
-typedef struct {
- __I uint32_t Reserved1[4];
- __IO uint32_t UTMI_OHCIICR; /**< \brief (Utmi Offset: 0x10) OHCI Interrupt Configuration Register */
- __I uint32_t Reserved2[7];
- __IO uint32_t UTMI_CKTRIM; /**< \brief (Utmi Offset: 0x30) UTMI Clock Trimming Register */
-} Utmi;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) OHCI Interrupt Configuration Register -------- */
-#define UTMI_OHCIICR_RES0 (0x1u << 0) /**< \brief (UTMI_OHCIICR) USB PORTx Reset */
-#define UTMI_OHCIICR_ARIE (0x1u << 4) /**< \brief (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */
-#define UTMI_OHCIICR_APPSTART (0x1u << 5) /**< \brief (UTMI_OHCIICR) Reserved */
-#define UTMI_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (UTMI_OHCIICR) USB Device Pull-up Disable */
-/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) UTMI Clock Trimming Register -------- */
-#define UTMI_CKTRIM_FREQ_Pos 0
-#define UTMI_CKTRIM_FREQ_Msk (0x3u << UTMI_CKTRIM_FREQ_Pos) /**< \brief (UTMI_CKTRIM) UTMI Reference Clock Frequency */
-#define UTMI_CKTRIM_FREQ(value) ((UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos)))
-#define UTMI_CKTRIM_FREQ_XTAL12 (0x0u << 0) /**< \brief (UTMI_CKTRIM) 12 MHz reference clock */
-#define UTMI_CKTRIM_FREQ_XTAL16 (0x1u << 0) /**< \brief (UTMI_CKTRIM) 16 MHz reference clock */
-
-/*@}*/
-
-
-#endif /* _SAMS70_UTMI_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/wdt.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/wdt.h
deleted file mode 100644
index b8f749b..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/wdt.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_WDT_COMPONENT_
-#define _SAMS70_WDT_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Watchdog Timer */
-/* ============================================================================= */
-/** \addtogroup SAMS70_WDT Watchdog Timer */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Wdt hardware registers */
-typedef struct {
- __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
- __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
- __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
-} Wdt;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
-#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
-#define WDT_CR_KEY_Pos 24
-#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
-#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
-#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */
-/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
-#define WDT_MR_WDV_Pos 0
-#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
-#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
-#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
-#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
-#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
-#define WDT_MR_WDD_Pos 16
-#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
-#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
-#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
-#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
-/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
-#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */
-#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */
-
-/*@}*/
-
-
-#endif /* _SAMS70_WDT_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/xdmac.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/xdmac.h
deleted file mode 100644
index 942e270..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/component/xdmac.h
+++ /dev/null
@@ -1,634 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_XDMAC_COMPONENT_
-#define _SAMS70_XDMAC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Extensible DMA Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_XDMAC Extensible DMA Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief XdmacChid hardware registers */
-typedef struct {
- __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */
- __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */
- __O uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */
- __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */
- __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */
- __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */
- __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */
- __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */
- __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */
- __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */
- __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */
- __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */
- __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */
- __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */
- __I uint32_t Reserved1[2];
-} XdmacChid;
-/** \brief Xdmac hardware registers */
-#define XDMACCHID_NUMBER 24
-typedef struct {
- __IO uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */
- __I uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */
- __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */
- __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */
- __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */
- __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */
- __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */
- __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */
- __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */
- __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */
- __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */
- __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */
- __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */
- __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */
- __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */
- __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */
- __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */
- __I uint32_t Reserved1[3];
- XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 23 */
-} Xdmac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */
-#define XDMAC_GTYPE_NB_CH_Pos 0
-#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */
-#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos)))
-#define XDMAC_GTYPE_FIFO_SZ_Pos 5
-#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */
-#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos)))
-#define XDMAC_GTYPE_NB_REQ_Pos 16
-#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */
-#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos)))
-/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */
-#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */
-#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */
-#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */
-#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */
-#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilo byte Enable */
-/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */
-#define XDMAC_GWAC_PW0_Pos 0
-#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */
-#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos)))
-#define XDMAC_GWAC_PW1_Pos 4
-#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */
-#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos)))
-#define XDMAC_GWAC_PW2_Pos 8
-#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */
-#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos)))
-#define XDMAC_GWAC_PW3_Pos 12
-#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */
-#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos)))
-/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */
-#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */
-#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */
-#define XDMAC_GIE_IE2 (0x1u << 2) /**< \brief (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit */
-#define XDMAC_GIE_IE3 (0x1u << 3) /**< \brief (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit */
-#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */
-#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */
-#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */
-#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */
-#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */
-#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */
-#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */
-#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */
-#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */
-#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */
-#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */
-#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */
-#define XDMAC_GIE_IE16 (0x1u << 16) /**< \brief (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit */
-#define XDMAC_GIE_IE17 (0x1u << 17) /**< \brief (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit */
-#define XDMAC_GIE_IE18 (0x1u << 18) /**< \brief (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit */
-#define XDMAC_GIE_IE19 (0x1u << 19) /**< \brief (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit */
-#define XDMAC_GIE_IE20 (0x1u << 20) /**< \brief (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit */
-#define XDMAC_GIE_IE21 (0x1u << 21) /**< \brief (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit */
-#define XDMAC_GIE_IE22 (0x1u << 22) /**< \brief (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit */
-#define XDMAC_GIE_IE23 (0x1u << 23) /**< \brief (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit */
-/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */
-#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */
-#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */
-#define XDMAC_GID_ID2 (0x1u << 2) /**< \brief (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit */
-#define XDMAC_GID_ID3 (0x1u << 3) /**< \brief (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit */
-#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */
-#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */
-#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */
-#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */
-#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */
-#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */
-#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */
-#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */
-#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */
-#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */
-#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */
-#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */
-#define XDMAC_GID_ID16 (0x1u << 16) /**< \brief (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit */
-#define XDMAC_GID_ID17 (0x1u << 17) /**< \brief (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit */
-#define XDMAC_GID_ID18 (0x1u << 18) /**< \brief (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit */
-#define XDMAC_GID_ID19 (0x1u << 19) /**< \brief (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit */
-#define XDMAC_GID_ID20 (0x1u << 20) /**< \brief (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit */
-#define XDMAC_GID_ID21 (0x1u << 21) /**< \brief (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit */
-#define XDMAC_GID_ID22 (0x1u << 22) /**< \brief (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit */
-#define XDMAC_GID_ID23 (0x1u << 23) /**< \brief (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit */
-/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */
-#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */
-#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */
-#define XDMAC_GIM_IM2 (0x1u << 2) /**< \brief (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit */
-#define XDMAC_GIM_IM3 (0x1u << 3) /**< \brief (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit */
-#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */
-#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */
-#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */
-#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */
-#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */
-#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */
-#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */
-#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */
-#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */
-#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */
-#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */
-#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */
-#define XDMAC_GIM_IM16 (0x1u << 16) /**< \brief (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit */
-#define XDMAC_GIM_IM17 (0x1u << 17) /**< \brief (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit */
-#define XDMAC_GIM_IM18 (0x1u << 18) /**< \brief (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit */
-#define XDMAC_GIM_IM19 (0x1u << 19) /**< \brief (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit */
-#define XDMAC_GIM_IM20 (0x1u << 20) /**< \brief (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit */
-#define XDMAC_GIM_IM21 (0x1u << 21) /**< \brief (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit */
-#define XDMAC_GIM_IM22 (0x1u << 22) /**< \brief (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit */
-#define XDMAC_GIM_IM23 (0x1u << 23) /**< \brief (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit */
-/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */
-#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */
-#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */
-#define XDMAC_GIS_IS2 (0x1u << 2) /**< \brief (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit */
-#define XDMAC_GIS_IS3 (0x1u << 3) /**< \brief (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit */
-#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */
-#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */
-#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */
-#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */
-#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */
-#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */
-#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */
-#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */
-#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */
-#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */
-#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */
-#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */
-#define XDMAC_GIS_IS16 (0x1u << 16) /**< \brief (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit */
-#define XDMAC_GIS_IS17 (0x1u << 17) /**< \brief (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit */
-#define XDMAC_GIS_IS18 (0x1u << 18) /**< \brief (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit */
-#define XDMAC_GIS_IS19 (0x1u << 19) /**< \brief (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit */
-#define XDMAC_GIS_IS20 (0x1u << 20) /**< \brief (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit */
-#define XDMAC_GIS_IS21 (0x1u << 21) /**< \brief (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit */
-#define XDMAC_GIS_IS22 (0x1u << 22) /**< \brief (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit */
-#define XDMAC_GIS_IS23 (0x1u << 23) /**< \brief (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit */
-/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */
-#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */
-#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */
-#define XDMAC_GE_EN2 (0x1u << 2) /**< \brief (XDMAC_GE) XDMAC Channel 2 Enable Bit */
-#define XDMAC_GE_EN3 (0x1u << 3) /**< \brief (XDMAC_GE) XDMAC Channel 3 Enable Bit */
-#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */
-#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */
-#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */
-#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */
-#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */
-#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */
-#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */
-#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */
-#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */
-#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */
-#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */
-#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */
-#define XDMAC_GE_EN16 (0x1u << 16) /**< \brief (XDMAC_GE) XDMAC Channel 16 Enable Bit */
-#define XDMAC_GE_EN17 (0x1u << 17) /**< \brief (XDMAC_GE) XDMAC Channel 17 Enable Bit */
-#define XDMAC_GE_EN18 (0x1u << 18) /**< \brief (XDMAC_GE) XDMAC Channel 18 Enable Bit */
-#define XDMAC_GE_EN19 (0x1u << 19) /**< \brief (XDMAC_GE) XDMAC Channel 19 Enable Bit */
-#define XDMAC_GE_EN20 (0x1u << 20) /**< \brief (XDMAC_GE) XDMAC Channel 20 Enable Bit */
-#define XDMAC_GE_EN21 (0x1u << 21) /**< \brief (XDMAC_GE) XDMAC Channel 21 Enable Bit */
-#define XDMAC_GE_EN22 (0x1u << 22) /**< \brief (XDMAC_GE) XDMAC Channel 22 Enable Bit */
-#define XDMAC_GE_EN23 (0x1u << 23) /**< \brief (XDMAC_GE) XDMAC Channel 23 Enable Bit */
-/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */
-#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */
-#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */
-#define XDMAC_GD_DI2 (0x1u << 2) /**< \brief (XDMAC_GD) XDMAC Channel 2 Disable Bit */
-#define XDMAC_GD_DI3 (0x1u << 3) /**< \brief (XDMAC_GD) XDMAC Channel 3 Disable Bit */
-#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */
-#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */
-#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */
-#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */
-#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */
-#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */
-#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */
-#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */
-#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */
-#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */
-#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */
-#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */
-#define XDMAC_GD_DI16 (0x1u << 16) /**< \brief (XDMAC_GD) XDMAC Channel 16 Disable Bit */
-#define XDMAC_GD_DI17 (0x1u << 17) /**< \brief (XDMAC_GD) XDMAC Channel 17 Disable Bit */
-#define XDMAC_GD_DI18 (0x1u << 18) /**< \brief (XDMAC_GD) XDMAC Channel 18 Disable Bit */
-#define XDMAC_GD_DI19 (0x1u << 19) /**< \brief (XDMAC_GD) XDMAC Channel 19 Disable Bit */
-#define XDMAC_GD_DI20 (0x1u << 20) /**< \brief (XDMAC_GD) XDMAC Channel 20 Disable Bit */
-#define XDMAC_GD_DI21 (0x1u << 21) /**< \brief (XDMAC_GD) XDMAC Channel 21 Disable Bit */
-#define XDMAC_GD_DI22 (0x1u << 22) /**< \brief (XDMAC_GD) XDMAC Channel 22 Disable Bit */
-#define XDMAC_GD_DI23 (0x1u << 23) /**< \brief (XDMAC_GD) XDMAC Channel 23 Disable Bit */
-/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */
-#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */
-#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */
-#define XDMAC_GS_ST2 (0x1u << 2) /**< \brief (XDMAC_GS) XDMAC Channel 2 Status Bit */
-#define XDMAC_GS_ST3 (0x1u << 3) /**< \brief (XDMAC_GS) XDMAC Channel 3 Status Bit */
-#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */
-#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */
-#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */
-#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */
-#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */
-#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */
-#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */
-#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */
-#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */
-#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */
-#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */
-#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */
-#define XDMAC_GS_ST16 (0x1u << 16) /**< \brief (XDMAC_GS) XDMAC Channel 16 Status Bit */
-#define XDMAC_GS_ST17 (0x1u << 17) /**< \brief (XDMAC_GS) XDMAC Channel 17 Status Bit */
-#define XDMAC_GS_ST18 (0x1u << 18) /**< \brief (XDMAC_GS) XDMAC Channel 18 Status Bit */
-#define XDMAC_GS_ST19 (0x1u << 19) /**< \brief (XDMAC_GS) XDMAC Channel 19 Status Bit */
-#define XDMAC_GS_ST20 (0x1u << 20) /**< \brief (XDMAC_GS) XDMAC Channel 20 Status Bit */
-#define XDMAC_GS_ST21 (0x1u << 21) /**< \brief (XDMAC_GS) XDMAC Channel 21 Status Bit */
-#define XDMAC_GS_ST22 (0x1u << 22) /**< \brief (XDMAC_GS) XDMAC Channel 22 Status Bit */
-#define XDMAC_GS_ST23 (0x1u << 23) /**< \brief (XDMAC_GS) XDMAC Channel 23 Status Bit */
-/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */
-#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */
-#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */
-#define XDMAC_GRS_RS2 (0x1u << 2) /**< \brief (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit */
-#define XDMAC_GRS_RS3 (0x1u << 3) /**< \brief (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit */
-#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */
-#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */
-#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */
-#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */
-#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */
-#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */
-#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */
-#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */
-#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */
-#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */
-#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */
-#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */
-#define XDMAC_GRS_RS16 (0x1u << 16) /**< \brief (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit */
-#define XDMAC_GRS_RS17 (0x1u << 17) /**< \brief (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit */
-#define XDMAC_GRS_RS18 (0x1u << 18) /**< \brief (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit */
-#define XDMAC_GRS_RS19 (0x1u << 19) /**< \brief (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit */
-#define XDMAC_GRS_RS20 (0x1u << 20) /**< \brief (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit */
-#define XDMAC_GRS_RS21 (0x1u << 21) /**< \brief (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit */
-#define XDMAC_GRS_RS22 (0x1u << 22) /**< \brief (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit */
-#define XDMAC_GRS_RS23 (0x1u << 23) /**< \brief (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit */
-/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */
-#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */
-#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */
-#define XDMAC_GWS_WS2 (0x1u << 2) /**< \brief (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit */
-#define XDMAC_GWS_WS3 (0x1u << 3) /**< \brief (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit */
-#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */
-#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */
-#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */
-#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */
-#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */
-#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */
-#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */
-#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */
-#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */
-#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */
-#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */
-#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */
-#define XDMAC_GWS_WS16 (0x1u << 16) /**< \brief (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit */
-#define XDMAC_GWS_WS17 (0x1u << 17) /**< \brief (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit */
-#define XDMAC_GWS_WS18 (0x1u << 18) /**< \brief (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit */
-#define XDMAC_GWS_WS19 (0x1u << 19) /**< \brief (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit */
-#define XDMAC_GWS_WS20 (0x1u << 20) /**< \brief (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit */
-#define XDMAC_GWS_WS21 (0x1u << 21) /**< \brief (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit */
-#define XDMAC_GWS_WS22 (0x1u << 22) /**< \brief (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit */
-#define XDMAC_GWS_WS23 (0x1u << 23) /**< \brief (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit */
-/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */
-#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS2 (0x1u << 2) /**< \brief (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS3 (0x1u << 3) /**< \brief (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS16 (0x1u << 16) /**< \brief (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS17 (0x1u << 17) /**< \brief (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS18 (0x1u << 18) /**< \brief (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS19 (0x1u << 19) /**< \brief (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS20 (0x1u << 20) /**< \brief (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS21 (0x1u << 21) /**< \brief (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS22 (0x1u << 22) /**< \brief (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS23 (0x1u << 23) /**< \brief (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit */
-/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */
-#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR2 (0x1u << 2) /**< \brief (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR3 (0x1u << 3) /**< \brief (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR16 (0x1u << 16) /**< \brief (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR17 (0x1u << 17) /**< \brief (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR18 (0x1u << 18) /**< \brief (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR19 (0x1u << 19) /**< \brief (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR20 (0x1u << 20) /**< \brief (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR21 (0x1u << 21) /**< \brief (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR22 (0x1u << 22) /**< \brief (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR23 (0x1u << 23) /**< \brief (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit */
-/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */
-#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */
-#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */
-#define XDMAC_GSWR_SWREQ2 (0x1u << 2) /**< \brief (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit */
-#define XDMAC_GSWR_SWREQ3 (0x1u << 3) /**< \brief (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit */
-#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */
-#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */
-#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */
-#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */
-#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */
-#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */
-#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */
-#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */
-#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */
-#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */
-#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */
-#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */
-#define XDMAC_GSWR_SWREQ16 (0x1u << 16) /**< \brief (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit */
-#define XDMAC_GSWR_SWREQ17 (0x1u << 17) /**< \brief (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit */
-#define XDMAC_GSWR_SWREQ18 (0x1u << 18) /**< \brief (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit */
-#define XDMAC_GSWR_SWREQ19 (0x1u << 19) /**< \brief (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit */
-#define XDMAC_GSWR_SWREQ20 (0x1u << 20) /**< \brief (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit */
-#define XDMAC_GSWR_SWREQ21 (0x1u << 21) /**< \brief (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit */
-#define XDMAC_GSWR_SWREQ22 (0x1u << 22) /**< \brief (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit */
-#define XDMAC_GSWR_SWREQ23 (0x1u << 23) /**< \brief (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit */
-/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */
-#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS2 (0x1u << 2) /**< \brief (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS3 (0x1u << 3) /**< \brief (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS16 (0x1u << 16) /**< \brief (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS17 (0x1u << 17) /**< \brief (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS18 (0x1u << 18) /**< \brief (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS19 (0x1u << 19) /**< \brief (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS20 (0x1u << 20) /**< \brief (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS21 (0x1u << 21) /**< \brief (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS22 (0x1u << 22) /**< \brief (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS23 (0x1u << 23) /**< \brief (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit */
-/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */
-#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF2 (0x1u << 2) /**< \brief (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF3 (0x1u << 3) /**< \brief (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF16 (0x1u << 16) /**< \brief (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF17 (0x1u << 17) /**< \brief (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF18 (0x1u << 18) /**< \brief (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF19 (0x1u << 19) /**< \brief (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF20 (0x1u << 20) /**< \brief (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF21 (0x1u << 21) /**< \brief (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF22 (0x1u << 22) /**< \brief (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF23 (0x1u << 23) /**< \brief (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit */
-/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */
-#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */
-#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */
-#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */
-#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */
-#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */
-#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */
-#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */
-/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */
-#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */
-#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */
-#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */
-#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */
-#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */
-#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */
-#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */
-/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */
-#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */
-#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */
-#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */
-#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */
-#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */
-#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */
-#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */
-/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */
-#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */
-#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */
-#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */
-#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */
-#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */
-#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */
-#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */
-/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */
-#define XDMAC_CSA_SA_Pos 0
-#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */
-#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos)))
-/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */
-#define XDMAC_CDA_DA_Pos 0
-#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */
-#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos)))
-/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */
-#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */
-#define XDMAC_CNDA_NDA_Pos 2
-#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */
-#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos)))
-/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */
-#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */
-#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled */
-#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled */
-#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */
-#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */
-#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */
-#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */
-#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */
-#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */
-#define XDMAC_CNDC_NDVIEW_Pos 3
-#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */
-#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos)))
-#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */
-#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */
-#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */
-#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */
-/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */
-#define XDMAC_CUBC_UBLEN_Pos 0
-#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */
-#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos)))
-/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */
-#define XDMAC_CBC_BLEN_Pos 0
-#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */
-#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos)))
-/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */
-#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */
-#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */
-#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */
-#define XDMAC_CC_MBSIZE_Pos 1
-#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */
-#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos)))
-#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */
-#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */
-#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */
-#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */
-#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */
-#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer */
-#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer */
-#define XDMAC_CC_PROT (0x1u << 5) /**< \brief (XDMAC_CC) Channel x Protection */
-#define XDMAC_CC_PROT_SEC (0x0u << 5) /**< \brief (XDMAC_CC) Channel is secured */
-#define XDMAC_CC_PROT_UNSEC (0x1u << 5) /**< \brief (XDMAC_CC) Channel is unsecured */
-#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */
-#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */
-#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */
-#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */
-#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated */
-#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */
-#define XDMAC_CC_CSIZE_Pos 8
-#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */
-#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos)))
-#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */
-#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */
-#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */
-#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */
-#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */
-#define XDMAC_CC_DWIDTH_Pos 11
-#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */
-#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos)))
-#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */
-#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */
-#define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */
-#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */
-#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0 */
-#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1 */
-#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */
-#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0 */
-#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1 */
-#define XDMAC_CC_SAM_Pos 16
-#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */
-#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos)))
-#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */
-#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */
-#define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */
-#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */
-#define XDMAC_CC_DAM_Pos 18
-#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */
-#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos)))
-#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */
-#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */
-#define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */
-#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */
-#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */
-#define XDMAC_CC_INITD_TERMINATED (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */
-#define XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */
-#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */
-#define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */
-#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */
-#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */
-#define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */
-#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */
-#define XDMAC_CC_PERID_Pos 24
-#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Identifier */
-#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos)))
-/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */
-#define XDMAC_CDS_MSP_SDS_MSP_Pos 0
-#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */
-#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos)))
-#define XDMAC_CDS_MSP_DDS_MSP_Pos 16
-#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */
-#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos)))
-/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */
-#define XDMAC_CSUS_SUBS_Pos 0
-#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */
-#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos)))
-/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */
-#define XDMAC_CDUS_DUBS_Pos 0
-#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */
-#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos)))
-
-/*@}*/
-
-
-#endif /* _SAMS70_XDMAC_COMPONENT_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/acc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/acc.h
deleted file mode 100644
index 5fab150..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/acc.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_ACC_INSTANCE_
-#define _SAMS70_ACC_INSTANCE_
-
-/* ========== Register definition for ACC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_ACC_CR (0x40044000U) /**< \brief (ACC) Control Register */
- #define REG_ACC_MR (0x40044004U) /**< \brief (ACC) Mode Register */
- #define REG_ACC_IER (0x40044024U) /**< \brief (ACC) Interrupt Enable Register */
- #define REG_ACC_IDR (0x40044028U) /**< \brief (ACC) Interrupt Disable Register */
- #define REG_ACC_IMR (0x4004402CU) /**< \brief (ACC) Interrupt Mask Register */
- #define REG_ACC_ISR (0x40044030U) /**< \brief (ACC) Interrupt Status Register */
- #define REG_ACC_ACR (0x40044094U) /**< \brief (ACC) Analog Control Register */
- #define REG_ACC_WPMR (0x400440E4U) /**< \brief (ACC) Write Protection Mode Register */
- #define REG_ACC_WPSR (0x400440E8U) /**< \brief (ACC) Write Protection Status Register */
-#else
- #define REG_ACC_CR (*(__O uint32_t*)0x40044000U) /**< \brief (ACC) Control Register */
- #define REG_ACC_MR (*(__IO uint32_t*)0x40044004U) /**< \brief (ACC) Mode Register */
- #define REG_ACC_IER (*(__O uint32_t*)0x40044024U) /**< \brief (ACC) Interrupt Enable Register */
- #define REG_ACC_IDR (*(__O uint32_t*)0x40044028U) /**< \brief (ACC) Interrupt Disable Register */
- #define REG_ACC_IMR (*(__I uint32_t*)0x4004402CU) /**< \brief (ACC) Interrupt Mask Register */
- #define REG_ACC_ISR (*(__I uint32_t*)0x40044030U) /**< \brief (ACC) Interrupt Status Register */
- #define REG_ACC_ACR (*(__IO uint32_t*)0x40044094U) /**< \brief (ACC) Analog Control Register */
- #define REG_ACC_WPMR (*(__IO uint32_t*)0x400440E4U) /**< \brief (ACC) Write Protection Mode Register */
- #define REG_ACC_WPSR (*(__I uint32_t*)0x400440E8U) /**< \brief (ACC) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_ACC_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/aes.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/aes.h
deleted file mode 100644
index 5a9a067..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/aes.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_AES_INSTANCE_
-#define _SAMS70_AES_INSTANCE_
-
-/* ========== Register definition for AES peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_AES_CR (0x4006C000U) /**< \brief (AES) Control Register */
- #define REG_AES_MR (0x4006C004U) /**< \brief (AES) Mode Register */
- #define REG_AES_IER (0x4006C010U) /**< \brief (AES) Interrupt Enable Register */
- #define REG_AES_IDR (0x4006C014U) /**< \brief (AES) Interrupt Disable Register */
- #define REG_AES_IMR (0x4006C018U) /**< \brief (AES) Interrupt Mask Register */
- #define REG_AES_ISR (0x4006C01CU) /**< \brief (AES) Interrupt Status Register */
- #define REG_AES_KEYWR (0x4006C020U) /**< \brief (AES) Key Word Register */
- #define REG_AES_IDATAR (0x4006C040U) /**< \brief (AES) Input Data Register */
- #define REG_AES_ODATAR (0x4006C050U) /**< \brief (AES) Output Data Register */
- #define REG_AES_IVR (0x4006C060U) /**< \brief (AES) Initialization Vector Register */
- #define REG_AES_AADLENR (0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */
- #define REG_AES_CLENR (0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */
- #define REG_AES_GHASHR (0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */
- #define REG_AES_TAGR (0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */
- #define REG_AES_CTRR (0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */
- #define REG_AES_GCMHR (0x4006C09CU) /**< \brief (AES) GCM H Word Register */
-#else
- #define REG_AES_CR (*(__O uint32_t*)0x4006C000U) /**< \brief (AES) Control Register */
- #define REG_AES_MR (*(__IO uint32_t*)0x4006C004U) /**< \brief (AES) Mode Register */
- #define REG_AES_IER (*(__O uint32_t*)0x4006C010U) /**< \brief (AES) Interrupt Enable Register */
- #define REG_AES_IDR (*(__O uint32_t*)0x4006C014U) /**< \brief (AES) Interrupt Disable Register */
- #define REG_AES_IMR (*(__I uint32_t*)0x4006C018U) /**< \brief (AES) Interrupt Mask Register */
- #define REG_AES_ISR (*(__I uint32_t*)0x4006C01CU) /**< \brief (AES) Interrupt Status Register */
- #define REG_AES_KEYWR (*(__O uint32_t*)0x4006C020U) /**< \brief (AES) Key Word Register */
- #define REG_AES_IDATAR (*(__O uint32_t*)0x4006C040U) /**< \brief (AES) Input Data Register */
- #define REG_AES_ODATAR (*(__I uint32_t*)0x4006C050U) /**< \brief (AES) Output Data Register */
- #define REG_AES_IVR (*(__O uint32_t*)0x4006C060U) /**< \brief (AES) Initialization Vector Register */
- #define REG_AES_AADLENR (*(__IO uint32_t*)0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */
- #define REG_AES_CLENR (*(__IO uint32_t*)0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */
- #define REG_AES_GHASHR (*(__IO uint32_t*)0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */
- #define REG_AES_TAGR (*(__I uint32_t*)0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */
- #define REG_AES_CTRR (*(__I uint32_t*)0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */
- #define REG_AES_GCMHR (*(__IO uint32_t*)0x4006C09CU) /**< \brief (AES) GCM H Word Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_AES_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/afec0.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/afec0.h
deleted file mode 100644
index ac8498a..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/afec0.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_AFEC0_INSTANCE_
-#define _SAMS70_AFEC0_INSTANCE_
-
-/* ========== Register definition for AFEC0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_AFEC0_CR (0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */
- #define REG_AFEC0_MR (0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */
- #define REG_AFEC0_EMR (0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */
- #define REG_AFEC0_SEQ1R (0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */
- #define REG_AFEC0_SEQ2R (0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */
- #define REG_AFEC0_CHER (0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */
- #define REG_AFEC0_CHDR (0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */
- #define REG_AFEC0_CHSR (0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */
- #define REG_AFEC0_LCDR (0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */
- #define REG_AFEC0_IER (0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */
- #define REG_AFEC0_IDR (0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */
- #define REG_AFEC0_IMR (0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */
- #define REG_AFEC0_ISR (0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */
- #define REG_AFEC0_OVER (0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */
- #define REG_AFEC0_CWR (0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */
- #define REG_AFEC0_CGR (0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain Register */
- #define REG_AFEC0_DIFFR (0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */
- #define REG_AFEC0_CSELR (0x4003C064U) /**< \brief (AFEC0) AFEC Channel Selection Register */
- #define REG_AFEC0_CDR (0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */
- #define REG_AFEC0_COCR (0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */
- #define REG_AFEC0_TEMPMR (0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */
- #define REG_AFEC0_TEMPCWR (0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */
- #define REG_AFEC0_ACR (0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */
- #define REG_AFEC0_SHMR (0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */
- #define REG_AFEC0_COSR (0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */
- #define REG_AFEC0_CVR (0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */
- #define REG_AFEC0_CECR (0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */
- #define REG_AFEC0_WPMR (0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */
- #define REG_AFEC0_WPSR (0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */
-#else
- #define REG_AFEC0_CR (*(__O uint32_t*)0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */
- #define REG_AFEC0_MR (*(__IO uint32_t*)0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */
- #define REG_AFEC0_EMR (*(__IO uint32_t*)0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */
- #define REG_AFEC0_SEQ1R (*(__IO uint32_t*)0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */
- #define REG_AFEC0_SEQ2R (*(__IO uint32_t*)0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */
- #define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */
- #define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */
- #define REG_AFEC0_CHSR (*(__I uint32_t*)0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */
- #define REG_AFEC0_LCDR (*(__I uint32_t*)0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */
- #define REG_AFEC0_IER (*(__O uint32_t*)0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */
- #define REG_AFEC0_IDR (*(__O uint32_t*)0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */
- #define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */
- #define REG_AFEC0_ISR (*(__I uint32_t*)0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */
- #define REG_AFEC0_OVER (*(__I uint32_t*)0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */
- #define REG_AFEC0_CWR (*(__IO uint32_t*)0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */
- #define REG_AFEC0_CGR (*(__IO uint32_t*)0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain Register */
- #define REG_AFEC0_DIFFR (*(__IO uint32_t*)0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */
- #define REG_AFEC0_CSELR (*(__IO uint32_t*)0x4003C064U) /**< \brief (AFEC0) AFEC Channel Selection Register */
- #define REG_AFEC0_CDR (*(__I uint32_t*)0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */
- #define REG_AFEC0_COCR (*(__IO uint32_t*)0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */
- #define REG_AFEC0_TEMPMR (*(__IO uint32_t*)0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */
- #define REG_AFEC0_TEMPCWR (*(__IO uint32_t*)0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */
- #define REG_AFEC0_ACR (*(__IO uint32_t*)0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */
- #define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */
- #define REG_AFEC0_COSR (*(__IO uint32_t*)0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */
- #define REG_AFEC0_CVR (*(__IO uint32_t*)0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */
- #define REG_AFEC0_CECR (*(__IO uint32_t*)0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */
- #define REG_AFEC0_WPMR (*(__IO uint32_t*)0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */
- #define REG_AFEC0_WPSR (*(__I uint32_t*)0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_AFEC0_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/afec1.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/afec1.h
deleted file mode 100644
index 461f201..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/afec1.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_AFEC1_INSTANCE_
-#define _SAMS70_AFEC1_INSTANCE_
-
-/* ========== Register definition for AFEC1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_AFEC1_CR (0x40064000U) /**< \brief (AFEC1) AFEC Control Register */
- #define REG_AFEC1_MR (0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */
- #define REG_AFEC1_EMR (0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */
- #define REG_AFEC1_SEQ1R (0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */
- #define REG_AFEC1_SEQ2R (0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */
- #define REG_AFEC1_CHER (0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */
- #define REG_AFEC1_CHDR (0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */
- #define REG_AFEC1_CHSR (0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */
- #define REG_AFEC1_LCDR (0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */
- #define REG_AFEC1_IER (0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */
- #define REG_AFEC1_IDR (0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */
- #define REG_AFEC1_IMR (0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */
- #define REG_AFEC1_ISR (0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */
- #define REG_AFEC1_OVER (0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */
- #define REG_AFEC1_CWR (0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */
- #define REG_AFEC1_CGR (0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */
- #define REG_AFEC1_DIFFR (0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */
- #define REG_AFEC1_CSELR (0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */
- #define REG_AFEC1_CDR (0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */
- #define REG_AFEC1_COCR (0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */
- #define REG_AFEC1_TEMPMR (0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */
- #define REG_AFEC1_TEMPCWR (0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */
- #define REG_AFEC1_ACR (0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */
- #define REG_AFEC1_SHMR (0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */
- #define REG_AFEC1_COSR (0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */
- #define REG_AFEC1_CVR (0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */
- #define REG_AFEC1_CECR (0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */
- #define REG_AFEC1_WPMR (0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */
- #define REG_AFEC1_WPSR (0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */
-#else
- #define REG_AFEC1_CR (*(__O uint32_t*)0x40064000U) /**< \brief (AFEC1) AFEC Control Register */
- #define REG_AFEC1_MR (*(__IO uint32_t*)0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */
- #define REG_AFEC1_EMR (*(__IO uint32_t*)0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */
- #define REG_AFEC1_SEQ1R (*(__IO uint32_t*)0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */
- #define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */
- #define REG_AFEC1_CHER (*(__O uint32_t*)0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */
- #define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */
- #define REG_AFEC1_CHSR (*(__I uint32_t*)0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */
- #define REG_AFEC1_LCDR (*(__I uint32_t*)0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */
- #define REG_AFEC1_IER (*(__O uint32_t*)0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */
- #define REG_AFEC1_IDR (*(__O uint32_t*)0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */
- #define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */
- #define REG_AFEC1_ISR (*(__I uint32_t*)0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */
- #define REG_AFEC1_OVER (*(__I uint32_t*)0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */
- #define REG_AFEC1_CWR (*(__IO uint32_t*)0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */
- #define REG_AFEC1_CGR (*(__IO uint32_t*)0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */
- #define REG_AFEC1_DIFFR (*(__IO uint32_t*)0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */
- #define REG_AFEC1_CSELR (*(__IO uint32_t*)0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */
- #define REG_AFEC1_CDR (*(__I uint32_t*)0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */
- #define REG_AFEC1_COCR (*(__IO uint32_t*)0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */
- #define REG_AFEC1_TEMPMR (*(__IO uint32_t*)0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */
- #define REG_AFEC1_TEMPCWR (*(__IO uint32_t*)0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */
- #define REG_AFEC1_ACR (*(__IO uint32_t*)0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */
- #define REG_AFEC1_SHMR (*(__IO uint32_t*)0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */
- #define REG_AFEC1_COSR (*(__IO uint32_t*)0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */
- #define REG_AFEC1_CVR (*(__IO uint32_t*)0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */
- #define REG_AFEC1_CECR (*(__IO uint32_t*)0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */
- #define REG_AFEC1_WPMR (*(__IO uint32_t*)0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */
- #define REG_AFEC1_WPSR (*(__I uint32_t*)0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_AFEC1_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/chipid.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/chipid.h
deleted file mode 100644
index 722773b..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/chipid.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_CHIPID_INSTANCE_
-#define _SAMS70_CHIPID_INSTANCE_
-
-/* ========== Register definition for CHIPID peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_CHIPID_CIDR (0x400E0940U) /**< \brief (CHIPID) Chip ID Register */
- #define REG_CHIPID_EXID (0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */
-#else
- #define REG_CHIPID_CIDR (*(__I uint32_t*)0x400E0940U) /**< \brief (CHIPID) Chip ID Register */
- #define REG_CHIPID_EXID (*(__I uint32_t*)0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_CHIPID_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/dacc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/dacc.h
deleted file mode 100644
index f92fe6d..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/dacc.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_DACC_INSTANCE_
-#define _SAMS70_DACC_INSTANCE_
-
-/* ========== Register definition for DACC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_DACC_CR (0x40040000U) /**< \brief (DACC) Control Register */
- #define REG_DACC_MR (0x40040004U) /**< \brief (DACC) Mode Register */
- #define REG_DACC_TRIGR (0x40040008U) /**< \brief (DACC) Trigger Register */
- #define REG_DACC_CHER (0x40040010U) /**< \brief (DACC) Channel Enable Register */
- #define REG_DACC_CHDR (0x40040014U) /**< \brief (DACC) Channel Disable Register */
- #define REG_DACC_CHSR (0x40040018U) /**< \brief (DACC) Channel Status Register */
- #define REG_DACC_CDR (0x4004001CU) /**< \brief (DACC) Conversion Data Register */
- #define REG_DACC_IER (0x40040024U) /**< \brief (DACC) Interrupt Enable Register */
- #define REG_DACC_IDR (0x40040028U) /**< \brief (DACC) Interrupt Disable Register */
- #define REG_DACC_IMR (0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */
- #define REG_DACC_ISR (0x40040030U) /**< \brief (DACC) Interrupt Status Register */
- #define REG_DACC_ACR (0x40040094U) /**< \brief (DACC) Analog Current Register */
- #define REG_DACC_WPMR (0x400400E4U) /**< \brief (DACC) Write Protection Mode register */
- #define REG_DACC_WPSR (0x400400E8U) /**< \brief (DACC) Write Protection Status register */
-#else
- #define REG_DACC_CR (*(__O uint32_t*)0x40040000U) /**< \brief (DACC) Control Register */
- #define REG_DACC_MR (*(__IO uint32_t*)0x40040004U) /**< \brief (DACC) Mode Register */
- #define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) /**< \brief (DACC) Trigger Register */
- #define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) /**< \brief (DACC) Channel Enable Register */
- #define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) /**< \brief (DACC) Channel Disable Register */
- #define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) /**< \brief (DACC) Channel Status Register */
- #define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) /**< \brief (DACC) Conversion Data Register */
- #define REG_DACC_IER (*(__O uint32_t*)0x40040024U) /**< \brief (DACC) Interrupt Enable Register */
- #define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) /**< \brief (DACC) Interrupt Disable Register */
- #define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */
- #define REG_DACC_ISR (*(__I uint32_t*)0x40040030U) /**< \brief (DACC) Interrupt Status Register */
- #define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) /**< \brief (DACC) Analog Current Register */
- #define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< \brief (DACC) Write Protection Mode register */
- #define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< \brief (DACC) Write Protection Status register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_DACC_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/efc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/efc.h
deleted file mode 100644
index e86fafc..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/efc.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_EFC_INSTANCE_
-#define _SAMS70_EFC_INSTANCE_
-
-/* ========== Register definition for EFC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_EFC_FMR (0x400E0C00U) /**< \brief (EFC) EEFC Flash Mode Register */
- #define REG_EFC_FCR (0x400E0C04U) /**< \brief (EFC) EEFC Flash Command Register */
- #define REG_EFC_FSR (0x400E0C08U) /**< \brief (EFC) EEFC Flash Status Register */
- #define REG_EFC_FRR (0x400E0C0CU) /**< \brief (EFC) EEFC Flash Result Register */
- #define REG_EFC_VERSION (0x400E0C14U) /**< \brief (EFC) EEFC Version Register */
- #define REG_EFC_WPMR (0x400E0CE4U) /**< \brief (EFC) Write Protection Mode Register */
-#else
- #define REG_EFC_FMR (*(__IO uint32_t*)0x400E0C00U) /**< \brief (EFC) EEFC Flash Mode Register */
- #define REG_EFC_FCR (*(__O uint32_t*)0x400E0C04U) /**< \brief (EFC) EEFC Flash Command Register */
- #define REG_EFC_FSR (*(__I uint32_t*)0x400E0C08U) /**< \brief (EFC) EEFC Flash Status Register */
- #define REG_EFC_FRR (*(__I uint32_t*)0x400E0C0CU) /**< \brief (EFC) EEFC Flash Result Register */
- #define REG_EFC_VERSION (*(__I uint32_t*)0x400E0C14U) /**< \brief (EFC) EEFC Version Register */
- #define REG_EFC_WPMR (*(__IO uint32_t*)0x400E0CE4U) /**< \brief (EFC) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_EFC_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/gpbr.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/gpbr.h
deleted file mode 100644
index 49de2e9..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/gpbr.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_GPBR_INSTANCE_
-#define _SAMS70_GPBR_INSTANCE_
-
-/* ========== Register definition for GPBR peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_GPBR_GPBR (0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */
-#else
- #define REG_GPBR_GPBR (*(__IO uint32_t*)0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_GPBR_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/hsmci.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/hsmci.h
deleted file mode 100644
index 3fc54b7..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/hsmci.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_HSMCI_INSTANCE_
-#define _SAMS70_HSMCI_INSTANCE_
-
-/* ========== Register definition for HSMCI peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */
- #define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */
- #define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
- #define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
- #define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */
- #define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */
- #define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */
- #define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
- #define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */
- #define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */
- #define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
- #define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */
- #define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
- #define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
- #define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
- #define REG_HSMCI_DMA (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
- #define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */
- #define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
- #define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
- #define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
-#else
- #define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< \brief (HSMCI) Control Register */
- #define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< \brief (HSMCI) Mode Register */
- #define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
- #define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
- #define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< \brief (HSMCI) Argument Register */
- #define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< \brief (HSMCI) Command Register */
- #define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< \brief (HSMCI) Block Register */
- #define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
- #define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< \brief (HSMCI) Response Register */
- #define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */
- #define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
- #define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< \brief (HSMCI) Status Register */
- #define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
- #define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
- #define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
- #define REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
- #define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< \brief (HSMCI) Configuration Register */
- #define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
- #define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
- #define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_HSMCI_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/icm.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/icm.h
deleted file mode 100644
index d3f9fb7..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/icm.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_ICM_INSTANCE_
-#define _SAMS70_ICM_INSTANCE_
-
-/* ========== Register definition for ICM peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_ICM_CFG (0x40048000U) /**< \brief (ICM) Configuration Register */
- #define REG_ICM_CTRL (0x40048004U) /**< \brief (ICM) Control Register */
- #define REG_ICM_SR (0x40048008U) /**< \brief (ICM) Status Register */
- #define REG_ICM_IER (0x40048010U) /**< \brief (ICM) Interrupt Enable Register */
- #define REG_ICM_IDR (0x40048014U) /**< \brief (ICM) Interrupt Disable Register */
- #define REG_ICM_IMR (0x40048018U) /**< \brief (ICM) Interrupt Mask Register */
- #define REG_ICM_ISR (0x4004801CU) /**< \brief (ICM) Interrupt Status Register */
- #define REG_ICM_UASR (0x40048020U) /**< \brief (ICM) Undefined Access Status Register */
- #define REG_ICM_DSCR (0x40048030U) /**< \brief (ICM) Region Descriptor Area Start Address Register */
- #define REG_ICM_HASH (0x40048034U) /**< \brief (ICM) Region Hash Area Start Address Register */
- #define REG_ICM_UIHVAL (0x40048038U) /**< \brief (ICM) User Initial Hash Value 0 Register */
-#else
- #define REG_ICM_CFG (*(__IO uint32_t*)0x40048000U) /**< \brief (ICM) Configuration Register */
- #define REG_ICM_CTRL (*(__O uint32_t*)0x40048004U) /**< \brief (ICM) Control Register */
- #define REG_ICM_SR (*(__O uint32_t*)0x40048008U) /**< \brief (ICM) Status Register */
- #define REG_ICM_IER (*(__O uint32_t*)0x40048010U) /**< \brief (ICM) Interrupt Enable Register */
- #define REG_ICM_IDR (*(__O uint32_t*)0x40048014U) /**< \brief (ICM) Interrupt Disable Register */
- #define REG_ICM_IMR (*(__I uint32_t*)0x40048018U) /**< \brief (ICM) Interrupt Mask Register */
- #define REG_ICM_ISR (*(__I uint32_t*)0x4004801CU) /**< \brief (ICM) Interrupt Status Register */
- #define REG_ICM_UASR (*(__I uint32_t*)0x40048020U) /**< \brief (ICM) Undefined Access Status Register */
- #define REG_ICM_DSCR (*(__IO uint32_t*)0x40048030U) /**< \brief (ICM) Region Descriptor Area Start Address Register */
- #define REG_ICM_HASH (*(__IO uint32_t*)0x40048034U) /**< \brief (ICM) Region Hash Area Start Address Register */
- #define REG_ICM_UIHVAL (*(__O uint32_t*)0x40048038U) /**< \brief (ICM) User Initial Hash Value 0 Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_ICM_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/isi.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/isi.h
deleted file mode 100644
index 731415d..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/isi.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_ISI_INSTANCE_
-#define _SAMS70_ISI_INSTANCE_
-
-/* ========== Register definition for ISI peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_ISI_CFG1 (0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */
- #define REG_ISI_CFG2 (0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */
- #define REG_ISI_PSIZE (0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */
- #define REG_ISI_PDECF (0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */
- #define REG_ISI_Y2R_SET0 (0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */
- #define REG_ISI_Y2R_SET1 (0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */
- #define REG_ISI_R2Y_SET0 (0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */
- #define REG_ISI_R2Y_SET1 (0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */
- #define REG_ISI_R2Y_SET2 (0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */
- #define REG_ISI_CR (0x4004C024U) /**< \brief (ISI) ISI Control Register */
- #define REG_ISI_SR (0x4004C028U) /**< \brief (ISI) ISI Status Register */
- #define REG_ISI_IER (0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */
- #define REG_ISI_IDR (0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */
- #define REG_ISI_IMR (0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */
- #define REG_ISI_DMA_CHER (0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */
- #define REG_ISI_DMA_CHDR (0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */
- #define REG_ISI_DMA_CHSR (0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */
- #define REG_ISI_DMA_P_ADDR (0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */
- #define REG_ISI_DMA_P_CTRL (0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */
- #define REG_ISI_DMA_P_DSCR (0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */
- #define REG_ISI_DMA_C_ADDR (0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */
- #define REG_ISI_DMA_C_CTRL (0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */
- #define REG_ISI_DMA_C_DSCR (0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */
- #define REG_ISI_WPMR (0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */
- #define REG_ISI_WPSR (0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */
-#else
- #define REG_ISI_CFG1 (*(__IO uint32_t*)0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */
- #define REG_ISI_CFG2 (*(__IO uint32_t*)0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */
- #define REG_ISI_PSIZE (*(__IO uint32_t*)0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */
- #define REG_ISI_PDECF (*(__IO uint32_t*)0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */
- #define REG_ISI_Y2R_SET0 (*(__IO uint32_t*)0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */
- #define REG_ISI_Y2R_SET1 (*(__IO uint32_t*)0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */
- #define REG_ISI_R2Y_SET0 (*(__IO uint32_t*)0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */
- #define REG_ISI_R2Y_SET1 (*(__IO uint32_t*)0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */
- #define REG_ISI_R2Y_SET2 (*(__IO uint32_t*)0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */
- #define REG_ISI_CR (*(__O uint32_t*)0x4004C024U) /**< \brief (ISI) ISI Control Register */
- #define REG_ISI_SR (*(__I uint32_t*)0x4004C028U) /**< \brief (ISI) ISI Status Register */
- #define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */
- #define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */
- #define REG_ISI_IMR (*(__I uint32_t*)0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */
- #define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */
- #define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */
- #define REG_ISI_DMA_CHSR (*(__I uint32_t*)0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */
- #define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */
- #define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */
- #define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */
- #define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */
- #define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */
- #define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */
- #define REG_ISI_WPMR (*(__IO uint32_t*)0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */
- #define REG_ISI_WPSR (*(__I uint32_t*)0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_ISI_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/matrix.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/matrix.h
deleted file mode 100644
index 4e78d0f..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/matrix.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_MATRIX_INSTANCE_
-#define _SAMS70_MATRIX_INSTANCE_
-
-/* ========== Register definition for MATRIX peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_MATRIX_MCFG0 (0x40088000U) /**< \brief (MATRIX) Master Configuration Register 0 */
- #define REG_MATRIX_MCFG1 (0x40088004U) /**< \brief (MATRIX) Master Configuration Register 1 */
- #define REG_MATRIX_MCFG2 (0x40088008U) /**< \brief (MATRIX) Master Configuration Register 2 */
- #define REG_MATRIX_MCFG3 (0x4008800CU) /**< \brief (MATRIX) Master Configuration Register 3 */
- #define REG_MATRIX_MCFG4 (0x40088010U) /**< \brief (MATRIX) Master Configuration Register 4 */
- #define REG_MATRIX_MCFG5 (0x40088014U) /**< \brief (MATRIX) Master Configuration Register 5 */
- #define REG_MATRIX_MCFG6 (0x40088018U) /**< \brief (MATRIX) Master Configuration Register 6 */
- #define REG_MATRIX_MCFG8 (0x40088020U) /**< \brief (MATRIX) Master Configuration Register 8 */
- #define REG_MATRIX_SCFG (0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */
- #define REG_MATRIX_PRAS0 (0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
- #define REG_MATRIX_PRBS0 (0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
- #define REG_MATRIX_PRAS1 (0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
- #define REG_MATRIX_PRBS1 (0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
- #define REG_MATRIX_PRAS2 (0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
- #define REG_MATRIX_PRBS2 (0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
- #define REG_MATRIX_PRAS3 (0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
- #define REG_MATRIX_PRBS3 (0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
- #define REG_MATRIX_PRAS4 (0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
- #define REG_MATRIX_PRBS4 (0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
- #define REG_MATRIX_PRAS5 (0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
- #define REG_MATRIX_PRBS5 (0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
- #define REG_MATRIX_PRAS6 (0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
- #define REG_MATRIX_PRBS6 (0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
- #define REG_MATRIX_PRAS7 (0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
- #define REG_MATRIX_PRBS7 (0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
- #define REG_MATRIX_PRAS8 (0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
- #define REG_MATRIX_PRBS8 (0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
- #define REG_MATRIX_MRCR (0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */
- #define REG_CCFG_SYSIO (0x40088114U) /**< \brief (MATRIX) System I/O Configuration Register */
- #define REG_CCFG_SMCNFCS (0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */
- #define REG_MATRIX_WPMR (0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */
- #define REG_MATRIX_WPSR (0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */
-#else
- #define REG_MATRIX_MCFG0 (*(__IO uint32_t*)0x40088000U) /**< \brief (MATRIX) Master Configuration Register 0 */
- #define REG_MATRIX_MCFG1 (*(__IO uint32_t*)0x40088004U) /**< \brief (MATRIX) Master Configuration Register 1 */
- #define REG_MATRIX_MCFG2 (*(__IO uint32_t*)0x40088008U) /**< \brief (MATRIX) Master Configuration Register 2 */
- #define REG_MATRIX_MCFG3 (*(__IO uint32_t*)0x4008800CU) /**< \brief (MATRIX) Master Configuration Register 3 */
- #define REG_MATRIX_MCFG4 (*(__IO uint32_t*)0x40088010U) /**< \brief (MATRIX) Master Configuration Register 4 */
- #define REG_MATRIX_MCFG5 (*(__IO uint32_t*)0x40088014U) /**< \brief (MATRIX) Master Configuration Register 5 */
- #define REG_MATRIX_MCFG6 (*(__IO uint32_t*)0x40088018U) /**< \brief (MATRIX) Master Configuration Register 6 */
- #define REG_MATRIX_MCFG8 (*(__IO uint32_t*)0x40088020U) /**< \brief (MATRIX) Master Configuration Register 8 */
- #define REG_MATRIX_SCFG (*(__IO uint32_t*)0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */
- #define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
- #define REG_MATRIX_PRBS0 (*(__IO uint32_t*)0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
- #define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
- #define REG_MATRIX_PRBS1 (*(__IO uint32_t*)0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
- #define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
- #define REG_MATRIX_PRBS2 (*(__IO uint32_t*)0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
- #define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
- #define REG_MATRIX_PRBS3 (*(__IO uint32_t*)0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
- #define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
- #define REG_MATRIX_PRBS4 (*(__IO uint32_t*)0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
- #define REG_MATRIX_PRAS5 (*(__IO uint32_t*)0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
- #define REG_MATRIX_PRBS5 (*(__IO uint32_t*)0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
- #define REG_MATRIX_PRAS6 (*(__IO uint32_t*)0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
- #define REG_MATRIX_PRBS6 (*(__IO uint32_t*)0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
- #define REG_MATRIX_PRAS7 (*(__IO uint32_t*)0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
- #define REG_MATRIX_PRBS7 (*(__IO uint32_t*)0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
- #define REG_MATRIX_PRAS8 (*(__IO uint32_t*)0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
- #define REG_MATRIX_PRBS8 (*(__IO uint32_t*)0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
- #define REG_MATRIX_MRCR (*(__IO uint32_t*)0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */
- #define REG_CCFG_SYSIO (*(__IO uint32_t*)0x40088114U) /**< \brief (MATRIX) System I/O Configuration Register */
- #define REG_CCFG_SMCNFCS (*(__IO uint32_t*)0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */
- #define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */
- #define REG_MATRIX_WPSR (*(__I uint32_t*)0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_MATRIX_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pioa.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pioa.h
deleted file mode 100644
index edacbb8..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pioa.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PIOA_INSTANCE_
-#define _SAMS70_PIOA_INSTANCE_
-
-/* ========== Register definition for PIOA peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
- #define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
- #define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
- #define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
- #define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
- #define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
- #define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
- #define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
- #define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
- #define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
- #define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
- #define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
- #define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
- #define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
- #define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
- #define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
- #define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
- #define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
- #define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
- #define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
- #define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
- #define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
- #define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
- #define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
- #define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
- #define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
- #define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
- #define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
- #define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
- #define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
- #define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
- #define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
- #define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
- #define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
- #define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
- #define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */
- #define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
- #define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
- #define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
- #define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
- #define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */
- #define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */
- #define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
- #define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
- #define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */
- #define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */
- #define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
- #define REG_PIOA_DRIVER (0x400E0F18U) /**< \brief (PIOA) PIO I/O Drive Register */
- #define REG_PIOA_KER (0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */
- #define REG_PIOA_KRCR (0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */
- #define REG_PIOA_KDR (0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */
- #define REG_PIOA_KIER (0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */
- #define REG_PIOA_KIDR (0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */
- #define REG_PIOA_KIMR (0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */
- #define REG_PIOA_KSR (0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */
- #define REG_PIOA_KKPR (0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */
- #define REG_PIOA_KKRR (0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */
- #define REG_PIOA_PCMR (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
- #define REG_PIOA_PCIER (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
- #define REG_PIOA_PCIDR (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
- #define REG_PIOA_PCIMR (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
- #define REG_PIOA_PCISR (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
- #define REG_PIOA_PCRHR (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
-#else
- #define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
- #define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
- #define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
- #define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
- #define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
- #define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
- #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
- #define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
- #define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
- #define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
- #define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
- #define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
- #define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
- #define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
- #define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
- #define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
- #define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
- #define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
- #define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
- #define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
- #define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
- #define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
- #define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
- #define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
- #define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
- #define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
- #define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
- #define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
- #define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
- #define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
- #define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
- #define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
- #define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
- #define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
- #define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
- #define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */
- #define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
- #define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
- #define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
- #define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
- #define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */
- #define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */
- #define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
- #define REG_PIOA_LOCKSR (*(__I uint32_t*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
- #define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */
- #define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */
- #define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
- #define REG_PIOA_DRIVER (*(__IO uint32_t*)0x400E0F18U) /**< \brief (PIOA) PIO I/O Drive Register */
- #define REG_PIOA_KER (*(__IO uint32_t*)0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */
- #define REG_PIOA_KRCR (*(__IO uint32_t*)0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */
- #define REG_PIOA_KDR (*(__IO uint32_t*)0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */
- #define REG_PIOA_KIER (*(__O uint32_t*)0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */
- #define REG_PIOA_KIDR (*(__O uint32_t*)0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */
- #define REG_PIOA_KIMR (*(__I uint32_t*)0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */
- #define REG_PIOA_KSR (*(__I uint32_t*)0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */
- #define REG_PIOA_KKPR (*(__I uint32_t*)0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */
- #define REG_PIOA_KKRR (*(__I uint32_t*)0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */
- #define REG_PIOA_PCMR (*(__IO uint32_t*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
- #define REG_PIOA_PCIER (*(__O uint32_t*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
- #define REG_PIOA_PCIDR (*(__O uint32_t*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
- #define REG_PIOA_PCIMR (*(__I uint32_t*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
- #define REG_PIOA_PCISR (*(__I uint32_t*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
- #define REG_PIOA_PCRHR (*(__I uint32_t*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PIOA_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/piob.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/piob.h
deleted file mode 100644
index 11cd590..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/piob.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PIOB_INSTANCE_
-#define _SAMS70_PIOB_INSTANCE_
-
-/* ========== Register definition for PIOB peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
- #define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
- #define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
- #define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
- #define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
- #define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */
- #define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
- #define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
- #define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
- #define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
- #define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
- #define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
- #define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
- #define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
- #define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
- #define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
- #define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
- #define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
- #define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
- #define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
- #define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
- #define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
- #define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
- #define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
- #define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
- #define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
- #define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
- #define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
- #define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
- #define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
- #define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
- #define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
- #define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
- #define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
- #define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
- #define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */
- #define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
- #define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
- #define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
- #define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
- #define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */
- #define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */
- #define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
- #define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */
- #define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */
- #define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */
- #define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
- #define REG_PIOB_DRIVER (0x400E1118U) /**< \brief (PIOB) PIO I/O Drive Register */
- #define REG_PIOB_KER (0x400E1120U) /**< \brief (PIOB) Keypad Controller Enable Register */
- #define REG_PIOB_KRCR (0x400E1124U) /**< \brief (PIOB) Keypad Controller Row Column Register */
- #define REG_PIOB_KDR (0x400E1128U) /**< \brief (PIOB) Keypad Controller Debouncing Register */
- #define REG_PIOB_KIER (0x400E1130U) /**< \brief (PIOB) Keypad Controller Interrupt Enable Register */
- #define REG_PIOB_KIDR (0x400E1134U) /**< \brief (PIOB) Keypad Controller Interrupt Disable Register */
- #define REG_PIOB_KIMR (0x400E1138U) /**< \brief (PIOB) Keypad Controller Interrupt Mask Register */
- #define REG_PIOB_KSR (0x400E113CU) /**< \brief (PIOB) Keypad Controller Status Register */
- #define REG_PIOB_KKPR (0x400E1140U) /**< \brief (PIOB) Keypad Controller Key Press Register */
- #define REG_PIOB_KKRR (0x400E1144U) /**< \brief (PIOB) Keypad Controller Key Release Register */
- #define REG_PIOB_PCMR (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
- #define REG_PIOB_PCIER (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
- #define REG_PIOB_PCIDR (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
- #define REG_PIOB_PCIMR (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
- #define REG_PIOB_PCISR (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
- #define REG_PIOB_PCRHR (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
-#else
- #define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
- #define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
- #define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
- #define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
- #define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
- #define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
- #define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
- #define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
- #define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
- #define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
- #define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
- #define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
- #define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
- #define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
- #define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
- #define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
- #define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
- #define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
- #define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
- #define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
- #define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
- #define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
- #define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
- #define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
- #define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
- #define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
- #define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
- #define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
- #define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
- #define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
- #define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
- #define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
- #define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
- #define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
- #define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
- #define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */
- #define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
- #define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
- #define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
- #define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
- #define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */
- #define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */
- #define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
- #define REG_PIOB_LOCKSR (*(__I uint32_t*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
- #define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */
- #define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */
- #define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
- #define REG_PIOB_DRIVER (*(__IO uint32_t*)0x400E1118U) /**< \brief (PIOB) PIO I/O Drive Register */
- #define REG_PIOB_KER (*(__IO uint32_t*)0x400E1120U) /**< \brief (PIOB) Keypad Controller Enable Register */
- #define REG_PIOB_KRCR (*(__IO uint32_t*)0x400E1124U) /**< \brief (PIOB) Keypad Controller Row Column Register */
- #define REG_PIOB_KDR (*(__IO uint32_t*)0x400E1128U) /**< \brief (PIOB) Keypad Controller Debouncing Register */
- #define REG_PIOB_KIER (*(__O uint32_t*)0x400E1130U) /**< \brief (PIOB) Keypad Controller Interrupt Enable Register */
- #define REG_PIOB_KIDR (*(__O uint32_t*)0x400E1134U) /**< \brief (PIOB) Keypad Controller Interrupt Disable Register */
- #define REG_PIOB_KIMR (*(__I uint32_t*)0x400E1138U) /**< \brief (PIOB) Keypad Controller Interrupt Mask Register */
- #define REG_PIOB_KSR (*(__I uint32_t*)0x400E113CU) /**< \brief (PIOB) Keypad Controller Status Register */
- #define REG_PIOB_KKPR (*(__I uint32_t*)0x400E1140U) /**< \brief (PIOB) Keypad Controller Key Press Register */
- #define REG_PIOB_KKRR (*(__I uint32_t*)0x400E1144U) /**< \brief (PIOB) Keypad Controller Key Release Register */
- #define REG_PIOB_PCMR (*(__IO uint32_t*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
- #define REG_PIOB_PCIER (*(__O uint32_t*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
- #define REG_PIOB_PCIDR (*(__O uint32_t*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
- #define REG_PIOB_PCIMR (*(__I uint32_t*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
- #define REG_PIOB_PCISR (*(__I uint32_t*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
- #define REG_PIOB_PCRHR (*(__I uint32_t*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PIOB_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pioc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pioc.h
deleted file mode 100644
index 6d0d928..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pioc.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PIOC_INSTANCE_
-#define _SAMS70_PIOC_INSTANCE_
-
-/* ========== Register definition for PIOC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
- #define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
- #define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */
- #define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */
- #define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */
- #define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */
- #define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
- #define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
- #define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
- #define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
- #define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
- #define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
- #define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
- #define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
- #define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
- #define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
- #define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
- #define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
- #define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
- #define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
- #define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
- #define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
- #define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
- #define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
- #define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
- #define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
- #define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
- #define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
- #define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
- #define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
- #define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
- #define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
- #define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
- #define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
- #define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
- #define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disable Register */
- #define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
- #define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
- #define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */
- #define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
- #define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low-Level Select Register */
- #define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/High-Level Select Register */
- #define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
- #define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */
- #define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protection Mode Register */
- #define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protection Status Register */
- #define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
- #define REG_PIOC_DRIVER (0x400E1318U) /**< \brief (PIOC) PIO I/O Drive Register */
- #define REG_PIOC_KER (0x400E1320U) /**< \brief (PIOC) Keypad Controller Enable Register */
- #define REG_PIOC_KRCR (0x400E1324U) /**< \brief (PIOC) Keypad Controller Row Column Register */
- #define REG_PIOC_KDR (0x400E1328U) /**< \brief (PIOC) Keypad Controller Debouncing Register */
- #define REG_PIOC_KIER (0x400E1330U) /**< \brief (PIOC) Keypad Controller Interrupt Enable Register */
- #define REG_PIOC_KIDR (0x400E1334U) /**< \brief (PIOC) Keypad Controller Interrupt Disable Register */
- #define REG_PIOC_KIMR (0x400E1338U) /**< \brief (PIOC) Keypad Controller Interrupt Mask Register */
- #define REG_PIOC_KSR (0x400E133CU) /**< \brief (PIOC) Keypad Controller Status Register */
- #define REG_PIOC_KKPR (0x400E1340U) /**< \brief (PIOC) Keypad Controller Key Press Register */
- #define REG_PIOC_KKRR (0x400E1344U) /**< \brief (PIOC) Keypad Controller Key Release Register */
- #define REG_PIOC_PCMR (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
- #define REG_PIOC_PCIER (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
- #define REG_PIOC_PCIDR (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
- #define REG_PIOC_PCIMR (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
- #define REG_PIOC_PCISR (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
- #define REG_PIOC_PCRHR (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
-#else
- #define REG_PIOC_PER (*(__O uint32_t*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
- #define REG_PIOC_PDR (*(__O uint32_t*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
- #define REG_PIOC_PSR (*(__I uint32_t*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */
- #define REG_PIOC_OER (*(__O uint32_t*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */
- #define REG_PIOC_ODR (*(__O uint32_t*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */
- #define REG_PIOC_OSR (*(__I uint32_t*)0x400E1218U) /**< \brief (PIOC) Output Status Register */
- #define REG_PIOC_IFER (*(__O uint32_t*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
- #define REG_PIOC_IFDR (*(__O uint32_t*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
- #define REG_PIOC_IFSR (*(__I uint32_t*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
- #define REG_PIOC_SODR (*(__O uint32_t*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
- #define REG_PIOC_CODR (*(__O uint32_t*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
- #define REG_PIOC_ODSR (*(__IO uint32_t*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
- #define REG_PIOC_PDSR (*(__I uint32_t*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
- #define REG_PIOC_IER (*(__O uint32_t*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
- #define REG_PIOC_IDR (*(__O uint32_t*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
- #define REG_PIOC_IMR (*(__I uint32_t*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
- #define REG_PIOC_ISR (*(__I uint32_t*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
- #define REG_PIOC_MDER (*(__O uint32_t*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
- #define REG_PIOC_MDDR (*(__O uint32_t*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
- #define REG_PIOC_MDSR (*(__I uint32_t*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
- #define REG_PIOC_PUDR (*(__O uint32_t*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
- #define REG_PIOC_PUER (*(__O uint32_t*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
- #define REG_PIOC_PUSR (*(__I uint32_t*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
- #define REG_PIOC_ABCDSR (*(__IO uint32_t*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
- #define REG_PIOC_IFSCDR (*(__O uint32_t*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
- #define REG_PIOC_IFSCER (*(__O uint32_t*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
- #define REG_PIOC_IFSCSR (*(__I uint32_t*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
- #define REG_PIOC_SCDR (*(__IO uint32_t*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
- #define REG_PIOC_PPDDR (*(__O uint32_t*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
- #define REG_PIOC_PPDER (*(__O uint32_t*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
- #define REG_PIOC_PPDSR (*(__I uint32_t*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
- #define REG_PIOC_OWER (*(__O uint32_t*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
- #define REG_PIOC_OWDR (*(__O uint32_t*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
- #define REG_PIOC_OWSR (*(__I uint32_t*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
- #define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
- #define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disable Register */
- #define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
- #define REG_PIOC_ESR (*(__O uint32_t*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
- #define REG_PIOC_LSR (*(__O uint32_t*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */
- #define REG_PIOC_ELSR (*(__I uint32_t*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
- #define REG_PIOC_FELLSR (*(__O uint32_t*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low-Level Select Register */
- #define REG_PIOC_REHLSR (*(__O uint32_t*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/High-Level Select Register */
- #define REG_PIOC_FRLHSR (*(__I uint32_t*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
- #define REG_PIOC_LOCKSR (*(__I uint32_t*)0x400E12E0U) /**< \brief (PIOC) Lock Status */
- #define REG_PIOC_WPMR (*(__IO uint32_t*)0x400E12E4U) /**< \brief (PIOC) Write Protection Mode Register */
- #define REG_PIOC_WPSR (*(__I uint32_t*)0x400E12E8U) /**< \brief (PIOC) Write Protection Status Register */
- #define REG_PIOC_SCHMITT (*(__IO uint32_t*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
- #define REG_PIOC_DRIVER (*(__IO uint32_t*)0x400E1318U) /**< \brief (PIOC) PIO I/O Drive Register */
- #define REG_PIOC_KER (*(__IO uint32_t*)0x400E1320U) /**< \brief (PIOC) Keypad Controller Enable Register */
- #define REG_PIOC_KRCR (*(__IO uint32_t*)0x400E1324U) /**< \brief (PIOC) Keypad Controller Row Column Register */
- #define REG_PIOC_KDR (*(__IO uint32_t*)0x400E1328U) /**< \brief (PIOC) Keypad Controller Debouncing Register */
- #define REG_PIOC_KIER (*(__O uint32_t*)0x400E1330U) /**< \brief (PIOC) Keypad Controller Interrupt Enable Register */
- #define REG_PIOC_KIDR (*(__O uint32_t*)0x400E1334U) /**< \brief (PIOC) Keypad Controller Interrupt Disable Register */
- #define REG_PIOC_KIMR (*(__I uint32_t*)0x400E1338U) /**< \brief (PIOC) Keypad Controller Interrupt Mask Register */
- #define REG_PIOC_KSR (*(__I uint32_t*)0x400E133CU) /**< \brief (PIOC) Keypad Controller Status Register */
- #define REG_PIOC_KKPR (*(__I uint32_t*)0x400E1340U) /**< \brief (PIOC) Keypad Controller Key Press Register */
- #define REG_PIOC_KKRR (*(__I uint32_t*)0x400E1344U) /**< \brief (PIOC) Keypad Controller Key Release Register */
- #define REG_PIOC_PCMR (*(__IO uint32_t*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
- #define REG_PIOC_PCIER (*(__O uint32_t*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
- #define REG_PIOC_PCIDR (*(__O uint32_t*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
- #define REG_PIOC_PCIMR (*(__I uint32_t*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
- #define REG_PIOC_PCISR (*(__I uint32_t*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
- #define REG_PIOC_PCRHR (*(__I uint32_t*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PIOC_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/piod.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/piod.h
deleted file mode 100644
index 46d6f11..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/piod.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PIOD_INSTANCE_
-#define _SAMS70_PIOD_INSTANCE_
-
-/* ========== Register definition for PIOD peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PIOD_PER (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
- #define REG_PIOD_PDR (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
- #define REG_PIOD_PSR (0x400E1408U) /**< \brief (PIOD) PIO Status Register */
- #define REG_PIOD_OER (0x400E1410U) /**< \brief (PIOD) Output Enable Register */
- #define REG_PIOD_ODR (0x400E1414U) /**< \brief (PIOD) Output Disable Register */
- #define REG_PIOD_OSR (0x400E1418U) /**< \brief (PIOD) Output Status Register */
- #define REG_PIOD_IFER (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
- #define REG_PIOD_IFDR (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
- #define REG_PIOD_IFSR (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
- #define REG_PIOD_SODR (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
- #define REG_PIOD_CODR (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
- #define REG_PIOD_ODSR (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
- #define REG_PIOD_PDSR (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
- #define REG_PIOD_IER (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
- #define REG_PIOD_IDR (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
- #define REG_PIOD_IMR (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
- #define REG_PIOD_ISR (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
- #define REG_PIOD_MDER (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
- #define REG_PIOD_MDDR (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
- #define REG_PIOD_MDSR (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
- #define REG_PIOD_PUDR (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
- #define REG_PIOD_PUER (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
- #define REG_PIOD_PUSR (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
- #define REG_PIOD_ABCDSR (0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */
- #define REG_PIOD_IFSCDR (0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */
- #define REG_PIOD_IFSCER (0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */
- #define REG_PIOD_IFSCSR (0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */
- #define REG_PIOD_SCDR (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
- #define REG_PIOD_PPDDR (0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */
- #define REG_PIOD_PPDER (0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */
- #define REG_PIOD_PPDSR (0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */
- #define REG_PIOD_OWER (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
- #define REG_PIOD_OWDR (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
- #define REG_PIOD_OWSR (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
- #define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
- #define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disable Register */
- #define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
- #define REG_PIOD_ESR (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
- #define REG_PIOD_LSR (0x400E14C4U) /**< \brief (PIOD) Level Select Register */
- #define REG_PIOD_ELSR (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
- #define REG_PIOD_FELLSR (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low-Level Select Register */
- #define REG_PIOD_REHLSR (0x400E14D4U) /**< \brief (PIOD) Rising Edge/High-Level Select Register */
- #define REG_PIOD_FRLHSR (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
- #define REG_PIOD_LOCKSR (0x400E14E0U) /**< \brief (PIOD) Lock Status */
- #define REG_PIOD_WPMR (0x400E14E4U) /**< \brief (PIOD) Write Protection Mode Register */
- #define REG_PIOD_WPSR (0x400E14E8U) /**< \brief (PIOD) Write Protection Status Register */
- #define REG_PIOD_SCHMITT (0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */
- #define REG_PIOD_DRIVER (0x400E1518U) /**< \brief (PIOD) PIO I/O Drive Register */
- #define REG_PIOD_KER (0x400E1520U) /**< \brief (PIOD) Keypad Controller Enable Register */
- #define REG_PIOD_KRCR (0x400E1524U) /**< \brief (PIOD) Keypad Controller Row Column Register */
- #define REG_PIOD_KDR (0x400E1528U) /**< \brief (PIOD) Keypad Controller Debouncing Register */
- #define REG_PIOD_KIER (0x400E1530U) /**< \brief (PIOD) Keypad Controller Interrupt Enable Register */
- #define REG_PIOD_KIDR (0x400E1534U) /**< \brief (PIOD) Keypad Controller Interrupt Disable Register */
- #define REG_PIOD_KIMR (0x400E1538U) /**< \brief (PIOD) Keypad Controller Interrupt Mask Register */
- #define REG_PIOD_KSR (0x400E153CU) /**< \brief (PIOD) Keypad Controller Status Register */
- #define REG_PIOD_KKPR (0x400E1540U) /**< \brief (PIOD) Keypad Controller Key Press Register */
- #define REG_PIOD_KKRR (0x400E1544U) /**< \brief (PIOD) Keypad Controller Key Release Register */
- #define REG_PIOD_PCMR (0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */
- #define REG_PIOD_PCIER (0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */
- #define REG_PIOD_PCIDR (0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */
- #define REG_PIOD_PCIMR (0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */
- #define REG_PIOD_PCISR (0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */
- #define REG_PIOD_PCRHR (0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */
-#else
- #define REG_PIOD_PER (*(__O uint32_t*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
- #define REG_PIOD_PDR (*(__O uint32_t*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
- #define REG_PIOD_PSR (*(__I uint32_t*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */
- #define REG_PIOD_OER (*(__O uint32_t*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */
- #define REG_PIOD_ODR (*(__O uint32_t*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */
- #define REG_PIOD_OSR (*(__I uint32_t*)0x400E1418U) /**< \brief (PIOD) Output Status Register */
- #define REG_PIOD_IFER (*(__O uint32_t*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
- #define REG_PIOD_IFDR (*(__O uint32_t*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
- #define REG_PIOD_IFSR (*(__I uint32_t*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
- #define REG_PIOD_SODR (*(__O uint32_t*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
- #define REG_PIOD_CODR (*(__O uint32_t*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
- #define REG_PIOD_ODSR (*(__IO uint32_t*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
- #define REG_PIOD_PDSR (*(__I uint32_t*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
- #define REG_PIOD_IER (*(__O uint32_t*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
- #define REG_PIOD_IDR (*(__O uint32_t*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
- #define REG_PIOD_IMR (*(__I uint32_t*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
- #define REG_PIOD_ISR (*(__I uint32_t*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
- #define REG_PIOD_MDER (*(__O uint32_t*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
- #define REG_PIOD_MDDR (*(__O uint32_t*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
- #define REG_PIOD_MDSR (*(__I uint32_t*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
- #define REG_PIOD_PUDR (*(__O uint32_t*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
- #define REG_PIOD_PUER (*(__O uint32_t*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
- #define REG_PIOD_PUSR (*(__I uint32_t*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
- #define REG_PIOD_ABCDSR (*(__IO uint32_t*)0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */
- #define REG_PIOD_IFSCDR (*(__O uint32_t*)0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */
- #define REG_PIOD_IFSCER (*(__O uint32_t*)0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */
- #define REG_PIOD_IFSCSR (*(__I uint32_t*)0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */
- #define REG_PIOD_SCDR (*(__IO uint32_t*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
- #define REG_PIOD_PPDDR (*(__O uint32_t*)0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */
- #define REG_PIOD_PPDER (*(__O uint32_t*)0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */
- #define REG_PIOD_PPDSR (*(__I uint32_t*)0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */
- #define REG_PIOD_OWER (*(__O uint32_t*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
- #define REG_PIOD_OWDR (*(__O uint32_t*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
- #define REG_PIOD_OWSR (*(__I uint32_t*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
- #define REG_PIOD_AIMER (*(__O uint32_t*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
- #define REG_PIOD_AIMDR (*(__O uint32_t*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disable Register */
- #define REG_PIOD_AIMMR (*(__I uint32_t*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
- #define REG_PIOD_ESR (*(__O uint32_t*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
- #define REG_PIOD_LSR (*(__O uint32_t*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */
- #define REG_PIOD_ELSR (*(__I uint32_t*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
- #define REG_PIOD_FELLSR (*(__O uint32_t*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low-Level Select Register */
- #define REG_PIOD_REHLSR (*(__O uint32_t*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/High-Level Select Register */
- #define REG_PIOD_FRLHSR (*(__I uint32_t*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
- #define REG_PIOD_LOCKSR (*(__I uint32_t*)0x400E14E0U) /**< \brief (PIOD) Lock Status */
- #define REG_PIOD_WPMR (*(__IO uint32_t*)0x400E14E4U) /**< \brief (PIOD) Write Protection Mode Register */
- #define REG_PIOD_WPSR (*(__I uint32_t*)0x400E14E8U) /**< \brief (PIOD) Write Protection Status Register */
- #define REG_PIOD_SCHMITT (*(__IO uint32_t*)0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */
- #define REG_PIOD_DRIVER (*(__IO uint32_t*)0x400E1518U) /**< \brief (PIOD) PIO I/O Drive Register */
- #define REG_PIOD_KER (*(__IO uint32_t*)0x400E1520U) /**< \brief (PIOD) Keypad Controller Enable Register */
- #define REG_PIOD_KRCR (*(__IO uint32_t*)0x400E1524U) /**< \brief (PIOD) Keypad Controller Row Column Register */
- #define REG_PIOD_KDR (*(__IO uint32_t*)0x400E1528U) /**< \brief (PIOD) Keypad Controller Debouncing Register */
- #define REG_PIOD_KIER (*(__O uint32_t*)0x400E1530U) /**< \brief (PIOD) Keypad Controller Interrupt Enable Register */
- #define REG_PIOD_KIDR (*(__O uint32_t*)0x400E1534U) /**< \brief (PIOD) Keypad Controller Interrupt Disable Register */
- #define REG_PIOD_KIMR (*(__I uint32_t*)0x400E1538U) /**< \brief (PIOD) Keypad Controller Interrupt Mask Register */
- #define REG_PIOD_KSR (*(__I uint32_t*)0x400E153CU) /**< \brief (PIOD) Keypad Controller Status Register */
- #define REG_PIOD_KKPR (*(__I uint32_t*)0x400E1540U) /**< \brief (PIOD) Keypad Controller Key Press Register */
- #define REG_PIOD_KKRR (*(__I uint32_t*)0x400E1544U) /**< \brief (PIOD) Keypad Controller Key Release Register */
- #define REG_PIOD_PCMR (*(__IO uint32_t*)0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */
- #define REG_PIOD_PCIER (*(__O uint32_t*)0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */
- #define REG_PIOD_PCIDR (*(__O uint32_t*)0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */
- #define REG_PIOD_PCIMR (*(__I uint32_t*)0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */
- #define REG_PIOD_PCISR (*(__I uint32_t*)0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */
- #define REG_PIOD_PCRHR (*(__I uint32_t*)0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PIOD_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pioe.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pioe.h
deleted file mode 100644
index 4f44c5d..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pioe.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PIOE_INSTANCE_
-#define _SAMS70_PIOE_INSTANCE_
-
-/* ========== Register definition for PIOE peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PIOE_PER (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
- #define REG_PIOE_PDR (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
- #define REG_PIOE_PSR (0x400E1608U) /**< \brief (PIOE) PIO Status Register */
- #define REG_PIOE_OER (0x400E1610U) /**< \brief (PIOE) Output Enable Register */
- #define REG_PIOE_ODR (0x400E1614U) /**< \brief (PIOE) Output Disable Register */
- #define REG_PIOE_OSR (0x400E1618U) /**< \brief (PIOE) Output Status Register */
- #define REG_PIOE_IFER (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
- #define REG_PIOE_IFDR (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
- #define REG_PIOE_IFSR (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
- #define REG_PIOE_SODR (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
- #define REG_PIOE_CODR (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
- #define REG_PIOE_ODSR (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
- #define REG_PIOE_PDSR (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
- #define REG_PIOE_IER (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
- #define REG_PIOE_IDR (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
- #define REG_PIOE_IMR (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
- #define REG_PIOE_ISR (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
- #define REG_PIOE_MDER (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
- #define REG_PIOE_MDDR (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
- #define REG_PIOE_MDSR (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
- #define REG_PIOE_PUDR (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
- #define REG_PIOE_PUER (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
- #define REG_PIOE_PUSR (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
- #define REG_PIOE_ABCDSR (0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */
- #define REG_PIOE_IFSCDR (0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */
- #define REG_PIOE_IFSCER (0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */
- #define REG_PIOE_IFSCSR (0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */
- #define REG_PIOE_SCDR (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
- #define REG_PIOE_PPDDR (0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */
- #define REG_PIOE_PPDER (0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */
- #define REG_PIOE_PPDSR (0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */
- #define REG_PIOE_OWER (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
- #define REG_PIOE_OWDR (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
- #define REG_PIOE_OWSR (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
- #define REG_PIOE_AIMER (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
- #define REG_PIOE_AIMDR (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */
- #define REG_PIOE_AIMMR (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
- #define REG_PIOE_ESR (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
- #define REG_PIOE_LSR (0x400E16C4U) /**< \brief (PIOE) Level Select Register */
- #define REG_PIOE_ELSR (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
- #define REG_PIOE_FELLSR (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */
- #define REG_PIOE_REHLSR (0x400E16D4U) /**< \brief (PIOE) Rising Edge/High-Level Select Register */
- #define REG_PIOE_FRLHSR (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
- #define REG_PIOE_LOCKSR (0x400E16E0U) /**< \brief (PIOE) Lock Status */
- #define REG_PIOE_WPMR (0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */
- #define REG_PIOE_WPSR (0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */
- #define REG_PIOE_SCHMITT (0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */
- #define REG_PIOE_DRIVER (0x400E1718U) /**< \brief (PIOE) PIO I/O Drive Register */
- #define REG_PIOE_KER (0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */
- #define REG_PIOE_KRCR (0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */
- #define REG_PIOE_KDR (0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */
- #define REG_PIOE_KIER (0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */
- #define REG_PIOE_KIDR (0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */
- #define REG_PIOE_KIMR (0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */
- #define REG_PIOE_KSR (0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */
- #define REG_PIOE_KKPR (0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */
- #define REG_PIOE_KKRR (0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */
- #define REG_PIOE_PCMR (0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */
- #define REG_PIOE_PCIER (0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */
- #define REG_PIOE_PCIDR (0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */
- #define REG_PIOE_PCIMR (0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */
- #define REG_PIOE_PCISR (0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */
- #define REG_PIOE_PCRHR (0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */
-#else
- #define REG_PIOE_PER (*(__O uint32_t*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
- #define REG_PIOE_PDR (*(__O uint32_t*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
- #define REG_PIOE_PSR (*(__I uint32_t*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */
- #define REG_PIOE_OER (*(__O uint32_t*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */
- #define REG_PIOE_ODR (*(__O uint32_t*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */
- #define REG_PIOE_OSR (*(__I uint32_t*)0x400E1618U) /**< \brief (PIOE) Output Status Register */
- #define REG_PIOE_IFER (*(__O uint32_t*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
- #define REG_PIOE_IFDR (*(__O uint32_t*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
- #define REG_PIOE_IFSR (*(__I uint32_t*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
- #define REG_PIOE_SODR (*(__O uint32_t*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
- #define REG_PIOE_CODR (*(__O uint32_t*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
- #define REG_PIOE_ODSR (*(__IO uint32_t*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
- #define REG_PIOE_PDSR (*(__I uint32_t*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
- #define REG_PIOE_IER (*(__O uint32_t*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
- #define REG_PIOE_IDR (*(__O uint32_t*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
- #define REG_PIOE_IMR (*(__I uint32_t*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
- #define REG_PIOE_ISR (*(__I uint32_t*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
- #define REG_PIOE_MDER (*(__O uint32_t*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
- #define REG_PIOE_MDDR (*(__O uint32_t*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
- #define REG_PIOE_MDSR (*(__I uint32_t*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
- #define REG_PIOE_PUDR (*(__O uint32_t*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
- #define REG_PIOE_PUER (*(__O uint32_t*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
- #define REG_PIOE_PUSR (*(__I uint32_t*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
- #define REG_PIOE_ABCDSR (*(__IO uint32_t*)0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */
- #define REG_PIOE_IFSCDR (*(__O uint32_t*)0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */
- #define REG_PIOE_IFSCER (*(__O uint32_t*)0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */
- #define REG_PIOE_IFSCSR (*(__I uint32_t*)0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */
- #define REG_PIOE_SCDR (*(__IO uint32_t*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
- #define REG_PIOE_PPDDR (*(__O uint32_t*)0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */
- #define REG_PIOE_PPDER (*(__O uint32_t*)0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */
- #define REG_PIOE_PPDSR (*(__I uint32_t*)0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */
- #define REG_PIOE_OWER (*(__O uint32_t*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
- #define REG_PIOE_OWDR (*(__O uint32_t*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
- #define REG_PIOE_OWSR (*(__I uint32_t*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
- #define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
- #define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */
- #define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
- #define REG_PIOE_ESR (*(__O uint32_t*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
- #define REG_PIOE_LSR (*(__O uint32_t*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */
- #define REG_PIOE_ELSR (*(__I uint32_t*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
- #define REG_PIOE_FELLSR (*(__O uint32_t*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */
- #define REG_PIOE_REHLSR (*(__O uint32_t*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/High-Level Select Register */
- #define REG_PIOE_FRLHSR (*(__I uint32_t*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
- #define REG_PIOE_LOCKSR (*(__I uint32_t*)0x400E16E0U) /**< \brief (PIOE) Lock Status */
- #define REG_PIOE_WPMR (*(__IO uint32_t*)0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */
- #define REG_PIOE_WPSR (*(__I uint32_t*)0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */
- #define REG_PIOE_SCHMITT (*(__IO uint32_t*)0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */
- #define REG_PIOE_DRIVER (*(__IO uint32_t*)0x400E1718U) /**< \brief (PIOE) PIO I/O Drive Register */
- #define REG_PIOE_KER (*(__IO uint32_t*)0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */
- #define REG_PIOE_KRCR (*(__IO uint32_t*)0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */
- #define REG_PIOE_KDR (*(__IO uint32_t*)0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */
- #define REG_PIOE_KIER (*(__O uint32_t*)0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */
- #define REG_PIOE_KIDR (*(__O uint32_t*)0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */
- #define REG_PIOE_KIMR (*(__I uint32_t*)0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */
- #define REG_PIOE_KSR (*(__I uint32_t*)0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */
- #define REG_PIOE_KKPR (*(__I uint32_t*)0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */
- #define REG_PIOE_KKRR (*(__I uint32_t*)0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */
- #define REG_PIOE_PCMR (*(__IO uint32_t*)0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */
- #define REG_PIOE_PCIER (*(__O uint32_t*)0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */
- #define REG_PIOE_PCIDR (*(__O uint32_t*)0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */
- #define REG_PIOE_PCIMR (*(__I uint32_t*)0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */
- #define REG_PIOE_PCISR (*(__I uint32_t*)0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */
- #define REG_PIOE_PCRHR (*(__I uint32_t*)0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PIOE_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pmc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pmc.h
deleted file mode 100644
index 2a2ade3..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pmc.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PMC_INSTANCE_
-#define _SAMS70_PMC_INSTANCE_
-
-/* ========== Register definition for PMC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PMC_SCER (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */
- #define REG_PMC_SCDR (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */
- #define REG_PMC_SCSR (0x400E0608U) /**< \brief (PMC) System Clock Status Register */
- #define REG_PMC_PCER0 (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
- #define REG_PMC_PCDR0 (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
- #define REG_PMC_PCSR0 (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
- #define REG_CKGR_UCKR (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */
- #define REG_CKGR_MOR (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */
- #define REG_CKGR_MCFR (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */
- #define REG_CKGR_PLLAR (0x400E0628U) /**< \brief (PMC) PLLA Register */
- #define REG_PMC_MCKR (0x400E0630U) /**< \brief (PMC) Master Clock Register */
- #define REG_PMC_USB (0x400E0638U) /**< \brief (PMC) USB Clock Register */
- #define REG_PMC_PCK (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */
- #define REG_PMC_IER (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */
- #define REG_PMC_IDR (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */
- #define REG_PMC_SR (0x400E0668U) /**< \brief (PMC) Status Register */
- #define REG_PMC_IMR (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */
- #define REG_PMC_FSMR (0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */
- #define REG_PMC_FSPR (0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */
- #define REG_PMC_FOCR (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */
- #define REG_PMC_WPMR (0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */
- #define REG_PMC_WPSR (0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */
- #define REG_PMC_PCER1 (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
- #define REG_PMC_PCDR1 (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
- #define REG_PMC_PCSR1 (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
- #define REG_PMC_PCR (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */
- #define REG_PMC_OCR (0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */
- #define REG_PMC_SLPWK_ER0 (0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */
- #define REG_PMC_SLPWK_DR0 (0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */
- #define REG_PMC_SLPWK_SR0 (0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */
- #define REG_PMC_SLPWK_ASR0 (0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */
- #define REG_PMC_SLPWK_ER1 (0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */
- #define REG_PMC_SLPWK_DR1 (0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */
- #define REG_PMC_SLPWK_SR1 (0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */
- #define REG_PMC_SLPWK_ASR1 (0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */
- #define REG_PMC_SLPWK_AIPR (0x400E0744U) /**< \brief (PMC) SleepWalking Activity In Progress Register */
-#else
- #define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */
- #define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */
- #define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */
- #define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
- #define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
- #define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
- #define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */
- #define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */
- #define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */
- #define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U) /**< \brief (PMC) PLLA Register */
- #define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U) /**< \brief (PMC) Master Clock Register */
- #define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U) /**< \brief (PMC) USB Clock Register */
- #define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */
- #define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */
- #define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */
- #define REG_PMC_SR (*(__I uint32_t*)0x400E0668U) /**< \brief (PMC) Status Register */
- #define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */
- #define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */
- #define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */
- #define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */
- #define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */
- #define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */
- #define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
- #define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
- #define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
- #define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */
- #define REG_PMC_OCR (*(__IO uint32_t*)0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */
- #define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */
- #define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */
- #define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */
- #define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */
- #define REG_PMC_SLPWK_ER1 (*(__O uint32_t*)0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */
- #define REG_PMC_SLPWK_DR1 (*(__O uint32_t*)0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */
- #define REG_PMC_SLPWK_SR1 (*(__I uint32_t*)0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */
- #define REG_PMC_SLPWK_ASR1 (*(__I uint32_t*)0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */
- #define REG_PMC_SLPWK_AIPR (*(__I uint32_t*)0x400E0744U) /**< \brief (PMC) SleepWalking Activity In Progress Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PMC_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pwm0.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pwm0.h
deleted file mode 100644
index 908e462..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pwm0.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PWM0_INSTANCE_
-#define _SAMS70_PWM0_INSTANCE_
-
-/* ========== Register definition for PWM0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PWM0_CLK (0x40020000U) /**< \brief (PWM0) PWM Clock Register */
- #define REG_PWM0_ENA (0x40020004U) /**< \brief (PWM0) PWM Enable Register */
- #define REG_PWM0_DIS (0x40020008U) /**< \brief (PWM0) PWM Disable Register */
- #define REG_PWM0_SR (0x4002000CU) /**< \brief (PWM0) PWM Status Register */
- #define REG_PWM0_IER1 (0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */
- #define REG_PWM0_IDR1 (0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */
- #define REG_PWM0_IMR1 (0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */
- #define REG_PWM0_ISR1 (0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */
- #define REG_PWM0_SCM (0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */
- #define REG_PWM0_DMAR (0x40020024U) /**< \brief (PWM0) PWM DMA Register */
- #define REG_PWM0_SCUC (0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */
- #define REG_PWM0_SCUP (0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */
- #define REG_PWM0_SCUPUPD (0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */
- #define REG_PWM0_IER2 (0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */
- #define REG_PWM0_IDR2 (0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */
- #define REG_PWM0_IMR2 (0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */
- #define REG_PWM0_ISR2 (0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */
- #define REG_PWM0_OOV (0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */
- #define REG_PWM0_OS (0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */
- #define REG_PWM0_OSS (0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */
- #define REG_PWM0_OSC (0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */
- #define REG_PWM0_OSSUPD (0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */
- #define REG_PWM0_OSCUPD (0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */
- #define REG_PWM0_FMR (0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */
- #define REG_PWM0_FSR (0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */
- #define REG_PWM0_FCR (0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */
- #define REG_PWM0_FPV1 (0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */
- #define REG_PWM0_FPE (0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */
- #define REG_PWM0_ELMR (0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */
- #define REG_PWM0_SSPR (0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */
- #define REG_PWM0_SSPUP (0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */
- #define REG_PWM0_SMMR (0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */
- #define REG_PWM0_FPV2 (0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */
- #define REG_PWM0_WPCR (0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */
- #define REG_PWM0_WPSR (0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */
- #define REG_PWM0_CMPV0 (0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */
- #define REG_PWM0_CMPVUPD0 (0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */
- #define REG_PWM0_CMPM0 (0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */
- #define REG_PWM0_CMPMUPD0 (0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */
- #define REG_PWM0_CMPV1 (0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */
- #define REG_PWM0_CMPVUPD1 (0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */
- #define REG_PWM0_CMPM1 (0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */
- #define REG_PWM0_CMPMUPD1 (0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */
- #define REG_PWM0_CMPV2 (0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */
- #define REG_PWM0_CMPVUPD2 (0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */
- #define REG_PWM0_CMPM2 (0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */
- #define REG_PWM0_CMPMUPD2 (0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */
- #define REG_PWM0_CMPV3 (0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */
- #define REG_PWM0_CMPVUPD3 (0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */
- #define REG_PWM0_CMPM3 (0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */
- #define REG_PWM0_CMPMUPD3 (0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */
- #define REG_PWM0_CMPV4 (0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */
- #define REG_PWM0_CMPVUPD4 (0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */
- #define REG_PWM0_CMPM4 (0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */
- #define REG_PWM0_CMPMUPD4 (0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */
- #define REG_PWM0_CMPV5 (0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */
- #define REG_PWM0_CMPVUPD5 (0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */
- #define REG_PWM0_CMPM5 (0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */
- #define REG_PWM0_CMPMUPD5 (0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */
- #define REG_PWM0_CMPV6 (0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */
- #define REG_PWM0_CMPVUPD6 (0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */
- #define REG_PWM0_CMPM6 (0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */
- #define REG_PWM0_CMPMUPD6 (0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */
- #define REG_PWM0_CMPV7 (0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */
- #define REG_PWM0_CMPVUPD7 (0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */
- #define REG_PWM0_CMPM7 (0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */
- #define REG_PWM0_CMPMUPD7 (0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */
- #define REG_PWM0_CMR0 (0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */
- #define REG_PWM0_CDTY0 (0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */
- #define REG_PWM0_CDTYUPD0 (0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */
- #define REG_PWM0_CPRD0 (0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */
- #define REG_PWM0_CPRDUPD0 (0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */
- #define REG_PWM0_CCNT0 (0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */
- #define REG_PWM0_DT0 (0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */
- #define REG_PWM0_DTUPD0 (0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */
- #define REG_PWM0_CMR1 (0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */
- #define REG_PWM0_CDTY1 (0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */
- #define REG_PWM0_CDTYUPD1 (0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */
- #define REG_PWM0_CPRD1 (0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */
- #define REG_PWM0_CPRDUPD1 (0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */
- #define REG_PWM0_CCNT1 (0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */
- #define REG_PWM0_DT1 (0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */
- #define REG_PWM0_DTUPD1 (0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */
- #define REG_PWM0_CMR2 (0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */
- #define REG_PWM0_CDTY2 (0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */
- #define REG_PWM0_CDTYUPD2 (0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */
- #define REG_PWM0_CPRD2 (0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */
- #define REG_PWM0_CPRDUPD2 (0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */
- #define REG_PWM0_CCNT2 (0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */
- #define REG_PWM0_DT2 (0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */
- #define REG_PWM0_DTUPD2 (0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */
- #define REG_PWM0_CMR3 (0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */
- #define REG_PWM0_CDTY3 (0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */
- #define REG_PWM0_CDTYUPD3 (0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */
- #define REG_PWM0_CPRD3 (0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */
- #define REG_PWM0_CPRDUPD3 (0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */
- #define REG_PWM0_CCNT3 (0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */
- #define REG_PWM0_DT3 (0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */
- #define REG_PWM0_DTUPD3 (0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */
- #define REG_PWM0_CMUPD0 (0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */
- #define REG_PWM0_CMUPD1 (0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */
- #define REG_PWM0_ETRG1 (0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */
- #define REG_PWM0_LEBR1 (0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */
- #define REG_PWM0_CMUPD2 (0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */
- #define REG_PWM0_ETRG2 (0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */
- #define REG_PWM0_LEBR2 (0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */
- #define REG_PWM0_CMUPD3 (0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */
- #define REG_PWM0_ETRG3 (0x4002046CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 3) */
- #define REG_PWM0_LEBR3 (0x40020470U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 3) */
- #define REG_PWM0_ETRG4 (0x4002048CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 4) */
- #define REG_PWM0_LEBR4 (0x40020490U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 4) */
-#else
- #define REG_PWM0_CLK (*(__IO uint32_t*)0x40020000U) /**< \brief (PWM0) PWM Clock Register */
- #define REG_PWM0_ENA (*(__O uint32_t*)0x40020004U) /**< \brief (PWM0) PWM Enable Register */
- #define REG_PWM0_DIS (*(__O uint32_t*)0x40020008U) /**< \brief (PWM0) PWM Disable Register */
- #define REG_PWM0_SR (*(__I uint32_t*)0x4002000CU) /**< \brief (PWM0) PWM Status Register */
- #define REG_PWM0_IER1 (*(__O uint32_t*)0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */
- #define REG_PWM0_IDR1 (*(__O uint32_t*)0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */
- #define REG_PWM0_IMR1 (*(__I uint32_t*)0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */
- #define REG_PWM0_ISR1 (*(__I uint32_t*)0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */
- #define REG_PWM0_SCM (*(__IO uint32_t*)0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */
- #define REG_PWM0_DMAR (*(__O uint32_t*)0x40020024U) /**< \brief (PWM0) PWM DMA Register */
- #define REG_PWM0_SCUC (*(__IO uint32_t*)0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */
- #define REG_PWM0_SCUP (*(__IO uint32_t*)0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */
- #define REG_PWM0_SCUPUPD (*(__O uint32_t*)0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */
- #define REG_PWM0_IER2 (*(__O uint32_t*)0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */
- #define REG_PWM0_IDR2 (*(__O uint32_t*)0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */
- #define REG_PWM0_IMR2 (*(__I uint32_t*)0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */
- #define REG_PWM0_ISR2 (*(__I uint32_t*)0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */
- #define REG_PWM0_OOV (*(__IO uint32_t*)0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */
- #define REG_PWM0_OS (*(__IO uint32_t*)0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */
- #define REG_PWM0_OSS (*(__O uint32_t*)0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */
- #define REG_PWM0_OSC (*(__O uint32_t*)0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */
- #define REG_PWM0_OSSUPD (*(__O uint32_t*)0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */
- #define REG_PWM0_OSCUPD (*(__O uint32_t*)0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */
- #define REG_PWM0_FMR (*(__IO uint32_t*)0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */
- #define REG_PWM0_FSR (*(__I uint32_t*)0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */
- #define REG_PWM0_FCR (*(__O uint32_t*)0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */
- #define REG_PWM0_FPV1 (*(__IO uint32_t*)0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */
- #define REG_PWM0_FPE (*(__IO uint32_t*)0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */
- #define REG_PWM0_ELMR (*(__IO uint32_t*)0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */
- #define REG_PWM0_SSPR (*(__IO uint32_t*)0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */
- #define REG_PWM0_SSPUP (*(__O uint32_t*)0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */
- #define REG_PWM0_SMMR (*(__IO uint32_t*)0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */
- #define REG_PWM0_FPV2 (*(__IO uint32_t*)0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */
- #define REG_PWM0_WPCR (*(__O uint32_t*)0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */
- #define REG_PWM0_WPSR (*(__I uint32_t*)0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */
- #define REG_PWM0_CMPV0 (*(__IO uint32_t*)0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */
- #define REG_PWM0_CMPVUPD0 (*(__O uint32_t*)0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */
- #define REG_PWM0_CMPM0 (*(__IO uint32_t*)0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */
- #define REG_PWM0_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */
- #define REG_PWM0_CMPV1 (*(__IO uint32_t*)0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */
- #define REG_PWM0_CMPVUPD1 (*(__O uint32_t*)0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */
- #define REG_PWM0_CMPM1 (*(__IO uint32_t*)0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */
- #define REG_PWM0_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */
- #define REG_PWM0_CMPV2 (*(__IO uint32_t*)0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */
- #define REG_PWM0_CMPVUPD2 (*(__O uint32_t*)0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */
- #define REG_PWM0_CMPM2 (*(__IO uint32_t*)0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */
- #define REG_PWM0_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */
- #define REG_PWM0_CMPV3 (*(__IO uint32_t*)0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */
- #define REG_PWM0_CMPVUPD3 (*(__O uint32_t*)0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */
- #define REG_PWM0_CMPM3 (*(__IO uint32_t*)0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */
- #define REG_PWM0_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */
- #define REG_PWM0_CMPV4 (*(__IO uint32_t*)0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */
- #define REG_PWM0_CMPVUPD4 (*(__O uint32_t*)0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */
- #define REG_PWM0_CMPM4 (*(__IO uint32_t*)0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */
- #define REG_PWM0_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */
- #define REG_PWM0_CMPV5 (*(__IO uint32_t*)0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */
- #define REG_PWM0_CMPVUPD5 (*(__O uint32_t*)0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */
- #define REG_PWM0_CMPM5 (*(__IO uint32_t*)0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */
- #define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */
- #define REG_PWM0_CMPV6 (*(__IO uint32_t*)0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */
- #define REG_PWM0_CMPVUPD6 (*(__O uint32_t*)0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */
- #define REG_PWM0_CMPM6 (*(__IO uint32_t*)0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */
- #define REG_PWM0_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */
- #define REG_PWM0_CMPV7 (*(__IO uint32_t*)0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */
- #define REG_PWM0_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */
- #define REG_PWM0_CMPM7 (*(__IO uint32_t*)0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */
- #define REG_PWM0_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */
- #define REG_PWM0_CMR0 (*(__IO uint32_t*)0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */
- #define REG_PWM0_CDTY0 (*(__IO uint32_t*)0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */
- #define REG_PWM0_CDTYUPD0 (*(__O uint32_t*)0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */
- #define REG_PWM0_CPRD0 (*(__IO uint32_t*)0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */
- #define REG_PWM0_CPRDUPD0 (*(__O uint32_t*)0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */
- #define REG_PWM0_CCNT0 (*(__I uint32_t*)0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */
- #define REG_PWM0_DT0 (*(__IO uint32_t*)0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */
- #define REG_PWM0_DTUPD0 (*(__O uint32_t*)0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */
- #define REG_PWM0_CMR1 (*(__IO uint32_t*)0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */
- #define REG_PWM0_CDTY1 (*(__IO uint32_t*)0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */
- #define REG_PWM0_CDTYUPD1 (*(__O uint32_t*)0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */
- #define REG_PWM0_CPRD1 (*(__IO uint32_t*)0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */
- #define REG_PWM0_CPRDUPD1 (*(__O uint32_t*)0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */
- #define REG_PWM0_CCNT1 (*(__I uint32_t*)0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */
- #define REG_PWM0_DT1 (*(__IO uint32_t*)0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */
- #define REG_PWM0_DTUPD1 (*(__O uint32_t*)0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */
- #define REG_PWM0_CMR2 (*(__IO uint32_t*)0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */
- #define REG_PWM0_CDTY2 (*(__IO uint32_t*)0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */
- #define REG_PWM0_CDTYUPD2 (*(__O uint32_t*)0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */
- #define REG_PWM0_CPRD2 (*(__IO uint32_t*)0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */
- #define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */
- #define REG_PWM0_CCNT2 (*(__I uint32_t*)0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */
- #define REG_PWM0_DT2 (*(__IO uint32_t*)0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */
- #define REG_PWM0_DTUPD2 (*(__O uint32_t*)0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */
- #define REG_PWM0_CMR3 (*(__IO uint32_t*)0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */
- #define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */
- #define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */
- #define REG_PWM0_CPRD3 (*(__IO uint32_t*)0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */
- #define REG_PWM0_CPRDUPD3 (*(__O uint32_t*)0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */
- #define REG_PWM0_CCNT3 (*(__I uint32_t*)0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */
- #define REG_PWM0_DT3 (*(__IO uint32_t*)0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */
- #define REG_PWM0_DTUPD3 (*(__O uint32_t*)0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */
- #define REG_PWM0_CMUPD0 (*(__O uint32_t*)0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */
- #define REG_PWM0_CMUPD1 (*(__O uint32_t*)0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */
- #define REG_PWM0_ETRG1 (*(__IO uint32_t*)0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */
- #define REG_PWM0_LEBR1 (*(__IO uint32_t*)0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */
- #define REG_PWM0_CMUPD2 (*(__O uint32_t*)0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */
- #define REG_PWM0_ETRG2 (*(__IO uint32_t*)0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */
- #define REG_PWM0_LEBR2 (*(__IO uint32_t*)0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */
- #define REG_PWM0_CMUPD3 (*(__O uint32_t*)0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */
- #define REG_PWM0_ETRG3 (*(__IO uint32_t*)0x4002046CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 3) */
- #define REG_PWM0_LEBR3 (*(__IO uint32_t*)0x40020470U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 3) */
- #define REG_PWM0_ETRG4 (*(__IO uint32_t*)0x4002048CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 4) */
- #define REG_PWM0_LEBR4 (*(__IO uint32_t*)0x40020490U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 4) */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PWM0_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pwm1.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pwm1.h
deleted file mode 100644
index 0f4dcf7..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/pwm1.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PWM1_INSTANCE_
-#define _SAMS70_PWM1_INSTANCE_
-
-/* ========== Register definition for PWM1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PWM1_CLK (0x4005C000U) /**< \brief (PWM1) PWM Clock Register */
- #define REG_PWM1_ENA (0x4005C004U) /**< \brief (PWM1) PWM Enable Register */
- #define REG_PWM1_DIS (0x4005C008U) /**< \brief (PWM1) PWM Disable Register */
- #define REG_PWM1_SR (0x4005C00CU) /**< \brief (PWM1) PWM Status Register */
- #define REG_PWM1_IER1 (0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */
- #define REG_PWM1_IDR1 (0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */
- #define REG_PWM1_IMR1 (0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */
- #define REG_PWM1_ISR1 (0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */
- #define REG_PWM1_SCM (0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */
- #define REG_PWM1_DMAR (0x4005C024U) /**< \brief (PWM1) PWM DMA Register */
- #define REG_PWM1_SCUC (0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */
- #define REG_PWM1_SCUP (0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */
- #define REG_PWM1_SCUPUPD (0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */
- #define REG_PWM1_IER2 (0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */
- #define REG_PWM1_IDR2 (0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */
- #define REG_PWM1_IMR2 (0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */
- #define REG_PWM1_ISR2 (0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */
- #define REG_PWM1_OOV (0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */
- #define REG_PWM1_OS (0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */
- #define REG_PWM1_OSS (0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */
- #define REG_PWM1_OSC (0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */
- #define REG_PWM1_OSSUPD (0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */
- #define REG_PWM1_OSCUPD (0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */
- #define REG_PWM1_FMR (0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */
- #define REG_PWM1_FSR (0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */
- #define REG_PWM1_FCR (0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */
- #define REG_PWM1_FPV1 (0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */
- #define REG_PWM1_FPE (0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */
- #define REG_PWM1_ELMR (0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */
- #define REG_PWM1_SSPR (0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */
- #define REG_PWM1_SSPUP (0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */
- #define REG_PWM1_SMMR (0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */
- #define REG_PWM1_FPV2 (0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */
- #define REG_PWM1_WPCR (0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */
- #define REG_PWM1_WPSR (0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */
- #define REG_PWM1_CMPV0 (0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */
- #define REG_PWM1_CMPVUPD0 (0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */
- #define REG_PWM1_CMPM0 (0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */
- #define REG_PWM1_CMPMUPD0 (0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */
- #define REG_PWM1_CMPV1 (0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */
- #define REG_PWM1_CMPVUPD1 (0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */
- #define REG_PWM1_CMPM1 (0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */
- #define REG_PWM1_CMPMUPD1 (0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */
- #define REG_PWM1_CMPV2 (0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */
- #define REG_PWM1_CMPVUPD2 (0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */
- #define REG_PWM1_CMPM2 (0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */
- #define REG_PWM1_CMPMUPD2 (0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */
- #define REG_PWM1_CMPV3 (0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */
- #define REG_PWM1_CMPVUPD3 (0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */
- #define REG_PWM1_CMPM3 (0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */
- #define REG_PWM1_CMPMUPD3 (0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */
- #define REG_PWM1_CMPV4 (0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */
- #define REG_PWM1_CMPVUPD4 (0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */
- #define REG_PWM1_CMPM4 (0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */
- #define REG_PWM1_CMPMUPD4 (0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */
- #define REG_PWM1_CMPV5 (0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */
- #define REG_PWM1_CMPVUPD5 (0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */
- #define REG_PWM1_CMPM5 (0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */
- #define REG_PWM1_CMPMUPD5 (0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */
- #define REG_PWM1_CMPV6 (0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */
- #define REG_PWM1_CMPVUPD6 (0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */
- #define REG_PWM1_CMPM6 (0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */
- #define REG_PWM1_CMPMUPD6 (0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */
- #define REG_PWM1_CMPV7 (0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */
- #define REG_PWM1_CMPVUPD7 (0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */
- #define REG_PWM1_CMPM7 (0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */
- #define REG_PWM1_CMPMUPD7 (0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */
- #define REG_PWM1_CMR0 (0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */
- #define REG_PWM1_CDTY0 (0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */
- #define REG_PWM1_CDTYUPD0 (0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */
- #define REG_PWM1_CPRD0 (0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */
- #define REG_PWM1_CPRDUPD0 (0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */
- #define REG_PWM1_CCNT0 (0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */
- #define REG_PWM1_DT0 (0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */
- #define REG_PWM1_DTUPD0 (0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */
- #define REG_PWM1_CMR1 (0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */
- #define REG_PWM1_CDTY1 (0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */
- #define REG_PWM1_CDTYUPD1 (0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */
- #define REG_PWM1_CPRD1 (0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */
- #define REG_PWM1_CPRDUPD1 (0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */
- #define REG_PWM1_CCNT1 (0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */
- #define REG_PWM1_DT1 (0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */
- #define REG_PWM1_DTUPD1 (0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */
- #define REG_PWM1_CMR2 (0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */
- #define REG_PWM1_CDTY2 (0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */
- #define REG_PWM1_CDTYUPD2 (0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */
- #define REG_PWM1_CPRD2 (0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */
- #define REG_PWM1_CPRDUPD2 (0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */
- #define REG_PWM1_CCNT2 (0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */
- #define REG_PWM1_DT2 (0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */
- #define REG_PWM1_DTUPD2 (0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */
- #define REG_PWM1_CMR3 (0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */
- #define REG_PWM1_CDTY3 (0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */
- #define REG_PWM1_CDTYUPD3 (0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */
- #define REG_PWM1_CPRD3 (0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */
- #define REG_PWM1_CPRDUPD3 (0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */
- #define REG_PWM1_CCNT3 (0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */
- #define REG_PWM1_DT3 (0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */
- #define REG_PWM1_DTUPD3 (0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */
- #define REG_PWM1_CMUPD0 (0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */
- #define REG_PWM1_CMUPD1 (0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */
- #define REG_PWM1_ETRG1 (0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */
- #define REG_PWM1_LEBR1 (0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */
- #define REG_PWM1_CMUPD2 (0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */
- #define REG_PWM1_ETRG2 (0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */
- #define REG_PWM1_LEBR2 (0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */
- #define REG_PWM1_CMUPD3 (0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */
- #define REG_PWM1_ETRG3 (0x4005C46CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 3) */
- #define REG_PWM1_LEBR3 (0x4005C470U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 3) */
- #define REG_PWM1_ETRG4 (0x4005C48CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 4) */
- #define REG_PWM1_LEBR4 (0x4005C490U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 4) */
-#else
- #define REG_PWM1_CLK (*(__IO uint32_t*)0x4005C000U) /**< \brief (PWM1) PWM Clock Register */
- #define REG_PWM1_ENA (*(__O uint32_t*)0x4005C004U) /**< \brief (PWM1) PWM Enable Register */
- #define REG_PWM1_DIS (*(__O uint32_t*)0x4005C008U) /**< \brief (PWM1) PWM Disable Register */
- #define REG_PWM1_SR (*(__I uint32_t*)0x4005C00CU) /**< \brief (PWM1) PWM Status Register */
- #define REG_PWM1_IER1 (*(__O uint32_t*)0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */
- #define REG_PWM1_IDR1 (*(__O uint32_t*)0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */
- #define REG_PWM1_IMR1 (*(__I uint32_t*)0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */
- #define REG_PWM1_ISR1 (*(__I uint32_t*)0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */
- #define REG_PWM1_SCM (*(__IO uint32_t*)0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */
- #define REG_PWM1_DMAR (*(__O uint32_t*)0x4005C024U) /**< \brief (PWM1) PWM DMA Register */
- #define REG_PWM1_SCUC (*(__IO uint32_t*)0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */
- #define REG_PWM1_SCUP (*(__IO uint32_t*)0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */
- #define REG_PWM1_SCUPUPD (*(__O uint32_t*)0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */
- #define REG_PWM1_IER2 (*(__O uint32_t*)0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */
- #define REG_PWM1_IDR2 (*(__O uint32_t*)0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */
- #define REG_PWM1_IMR2 (*(__I uint32_t*)0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */
- #define REG_PWM1_ISR2 (*(__I uint32_t*)0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */
- #define REG_PWM1_OOV (*(__IO uint32_t*)0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */
- #define REG_PWM1_OS (*(__IO uint32_t*)0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */
- #define REG_PWM1_OSS (*(__O uint32_t*)0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */
- #define REG_PWM1_OSC (*(__O uint32_t*)0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */
- #define REG_PWM1_OSSUPD (*(__O uint32_t*)0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */
- #define REG_PWM1_OSCUPD (*(__O uint32_t*)0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */
- #define REG_PWM1_FMR (*(__IO uint32_t*)0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */
- #define REG_PWM1_FSR (*(__I uint32_t*)0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */
- #define REG_PWM1_FCR (*(__O uint32_t*)0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */
- #define REG_PWM1_FPV1 (*(__IO uint32_t*)0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */
- #define REG_PWM1_FPE (*(__IO uint32_t*)0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */
- #define REG_PWM1_ELMR (*(__IO uint32_t*)0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */
- #define REG_PWM1_SSPR (*(__IO uint32_t*)0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */
- #define REG_PWM1_SSPUP (*(__O uint32_t*)0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */
- #define REG_PWM1_SMMR (*(__IO uint32_t*)0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */
- #define REG_PWM1_FPV2 (*(__IO uint32_t*)0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */
- #define REG_PWM1_WPCR (*(__O uint32_t*)0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */
- #define REG_PWM1_WPSR (*(__I uint32_t*)0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */
- #define REG_PWM1_CMPV0 (*(__IO uint32_t*)0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */
- #define REG_PWM1_CMPVUPD0 (*(__O uint32_t*)0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */
- #define REG_PWM1_CMPM0 (*(__IO uint32_t*)0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */
- #define REG_PWM1_CMPMUPD0 (*(__O uint32_t*)0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */
- #define REG_PWM1_CMPV1 (*(__IO uint32_t*)0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */
- #define REG_PWM1_CMPVUPD1 (*(__O uint32_t*)0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */
- #define REG_PWM1_CMPM1 (*(__IO uint32_t*)0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */
- #define REG_PWM1_CMPMUPD1 (*(__O uint32_t*)0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */
- #define REG_PWM1_CMPV2 (*(__IO uint32_t*)0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */
- #define REG_PWM1_CMPVUPD2 (*(__O uint32_t*)0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */
- #define REG_PWM1_CMPM2 (*(__IO uint32_t*)0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */
- #define REG_PWM1_CMPMUPD2 (*(__O uint32_t*)0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */
- #define REG_PWM1_CMPV3 (*(__IO uint32_t*)0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */
- #define REG_PWM1_CMPVUPD3 (*(__O uint32_t*)0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */
- #define REG_PWM1_CMPM3 (*(__IO uint32_t*)0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */
- #define REG_PWM1_CMPMUPD3 (*(__O uint32_t*)0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */
- #define REG_PWM1_CMPV4 (*(__IO uint32_t*)0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */
- #define REG_PWM1_CMPVUPD4 (*(__O uint32_t*)0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */
- #define REG_PWM1_CMPM4 (*(__IO uint32_t*)0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */
- #define REG_PWM1_CMPMUPD4 (*(__O uint32_t*)0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */
- #define REG_PWM1_CMPV5 (*(__IO uint32_t*)0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */
- #define REG_PWM1_CMPVUPD5 (*(__O uint32_t*)0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */
- #define REG_PWM1_CMPM5 (*(__IO uint32_t*)0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */
- #define REG_PWM1_CMPMUPD5 (*(__O uint32_t*)0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */
- #define REG_PWM1_CMPV6 (*(__IO uint32_t*)0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */
- #define REG_PWM1_CMPVUPD6 (*(__O uint32_t*)0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */
- #define REG_PWM1_CMPM6 (*(__IO uint32_t*)0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */
- #define REG_PWM1_CMPMUPD6 (*(__O uint32_t*)0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */
- #define REG_PWM1_CMPV7 (*(__IO uint32_t*)0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */
- #define REG_PWM1_CMPVUPD7 (*(__O uint32_t*)0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */
- #define REG_PWM1_CMPM7 (*(__IO uint32_t*)0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */
- #define REG_PWM1_CMPMUPD7 (*(__O uint32_t*)0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */
- #define REG_PWM1_CMR0 (*(__IO uint32_t*)0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */
- #define REG_PWM1_CDTY0 (*(__IO uint32_t*)0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */
- #define REG_PWM1_CDTYUPD0 (*(__O uint32_t*)0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */
- #define REG_PWM1_CPRD0 (*(__IO uint32_t*)0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */
- #define REG_PWM1_CPRDUPD0 (*(__O uint32_t*)0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */
- #define REG_PWM1_CCNT0 (*(__I uint32_t*)0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */
- #define REG_PWM1_DT0 (*(__IO uint32_t*)0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */
- #define REG_PWM1_DTUPD0 (*(__O uint32_t*)0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */
- #define REG_PWM1_CMR1 (*(__IO uint32_t*)0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */
- #define REG_PWM1_CDTY1 (*(__IO uint32_t*)0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */
- #define REG_PWM1_CDTYUPD1 (*(__O uint32_t*)0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */
- #define REG_PWM1_CPRD1 (*(__IO uint32_t*)0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */
- #define REG_PWM1_CPRDUPD1 (*(__O uint32_t*)0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */
- #define REG_PWM1_CCNT1 (*(__I uint32_t*)0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */
- #define REG_PWM1_DT1 (*(__IO uint32_t*)0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */
- #define REG_PWM1_DTUPD1 (*(__O uint32_t*)0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */
- #define REG_PWM1_CMR2 (*(__IO uint32_t*)0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */
- #define REG_PWM1_CDTY2 (*(__IO uint32_t*)0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */
- #define REG_PWM1_CDTYUPD2 (*(__O uint32_t*)0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */
- #define REG_PWM1_CPRD2 (*(__IO uint32_t*)0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */
- #define REG_PWM1_CPRDUPD2 (*(__O uint32_t*)0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */
- #define REG_PWM1_CCNT2 (*(__I uint32_t*)0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */
- #define REG_PWM1_DT2 (*(__IO uint32_t*)0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */
- #define REG_PWM1_DTUPD2 (*(__O uint32_t*)0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */
- #define REG_PWM1_CMR3 (*(__IO uint32_t*)0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */
- #define REG_PWM1_CDTY3 (*(__IO uint32_t*)0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */
- #define REG_PWM1_CDTYUPD3 (*(__O uint32_t*)0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */
- #define REG_PWM1_CPRD3 (*(__IO uint32_t*)0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */
- #define REG_PWM1_CPRDUPD3 (*(__O uint32_t*)0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */
- #define REG_PWM1_CCNT3 (*(__I uint32_t*)0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */
- #define REG_PWM1_DT3 (*(__IO uint32_t*)0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */
- #define REG_PWM1_DTUPD3 (*(__O uint32_t*)0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */
- #define REG_PWM1_CMUPD0 (*(__O uint32_t*)0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */
- #define REG_PWM1_CMUPD1 (*(__O uint32_t*)0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */
- #define REG_PWM1_ETRG1 (*(__IO uint32_t*)0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */
- #define REG_PWM1_LEBR1 (*(__IO uint32_t*)0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */
- #define REG_PWM1_CMUPD2 (*(__O uint32_t*)0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */
- #define REG_PWM1_ETRG2 (*(__IO uint32_t*)0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */
- #define REG_PWM1_LEBR2 (*(__IO uint32_t*)0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */
- #define REG_PWM1_CMUPD3 (*(__O uint32_t*)0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */
- #define REG_PWM1_ETRG3 (*(__IO uint32_t*)0x4005C46CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 3) */
- #define REG_PWM1_LEBR3 (*(__IO uint32_t*)0x4005C470U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 3) */
- #define REG_PWM1_ETRG4 (*(__IO uint32_t*)0x4005C48CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 4) */
- #define REG_PWM1_LEBR4 (*(__IO uint32_t*)0x4005C490U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 4) */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PWM1_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/qspi.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/qspi.h
deleted file mode 100644
index 2009f77..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/qspi.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_QSPI_INSTANCE_
-#define _SAMS70_QSPI_INSTANCE_
-
-/* ========== Register definition for QSPI peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_QSPI_CR (0x4007C000U) /**< \brief (QSPI) Control Register */
- #define REG_QSPI_MR (0x4007C004U) /**< \brief (QSPI) Mode Register */
- #define REG_QSPI_RDR (0x4007C008U) /**< \brief (QSPI) Receive Data Register */
- #define REG_QSPI_TDR (0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */
- #define REG_QSPI_SR (0x4007C010U) /**< \brief (QSPI) Status Register */
- #define REG_QSPI_IER (0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */
- #define REG_QSPI_IDR (0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */
- #define REG_QSPI_IMR (0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */
- #define REG_QSPI_SCR (0x4007C020U) /**< \brief (QSPI) Serial Clock Register */
- #define REG_QSPI_IAR (0x4007C030U) /**< \brief (QSPI) Instruction Address Register */
- #define REG_QSPI_ICR (0x4007C034U) /**< \brief (QSPI) Instruction Code Register */
- #define REG_QSPI_IFR (0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */
- #define REG_QSPI_SMR (0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */
- #define REG_QSPI_SKR (0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */
- #define REG_QSPI_WPMR (0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */
- #define REG_QSPI_WPSR (0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */
-#else
- #define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< \brief (QSPI) Control Register */
- #define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U) /**< \brief (QSPI) Mode Register */
- #define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U) /**< \brief (QSPI) Receive Data Register */
- #define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */
- #define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U) /**< \brief (QSPI) Status Register */
- #define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */
- #define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */
- #define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */
- #define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U) /**< \brief (QSPI) Serial Clock Register */
- #define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U) /**< \brief (QSPI) Instruction Address Register */
- #define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U) /**< \brief (QSPI) Instruction Code Register */
- #define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */
- #define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */
- #define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */
- #define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */
- #define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_QSPI_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/rstc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/rstc.h
deleted file mode 100644
index 8278615..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/rstc.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RSTC_INSTANCE_
-#define _SAMS70_RSTC_INSTANCE_
-
-/* ========== Register definition for RSTC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_RSTC_CR (0x400E1800U) /**< \brief (RSTC) Control Register */
- #define REG_RSTC_SR (0x400E1804U) /**< \brief (RSTC) Status Register */
- #define REG_RSTC_MR (0x400E1808U) /**< \brief (RSTC) Mode Register */
-#else
- #define REG_RSTC_CR (*(__O uint32_t*)0x400E1800U) /**< \brief (RSTC) Control Register */
- #define REG_RSTC_SR (*(__I uint32_t*)0x400E1804U) /**< \brief (RSTC) Status Register */
- #define REG_RSTC_MR (*(__IO uint32_t*)0x400E1808U) /**< \brief (RSTC) Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_RSTC_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/rswdt.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/rswdt.h
deleted file mode 100644
index 903cd16..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/rswdt.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RSWDT_INSTANCE_
-#define _SAMS70_RSWDT_INSTANCE_
-
-/* ========== Register definition for RSWDT peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_RSWDT_CR (0x400E1900U) /**< \brief (RSWDT) Control Register */
- #define REG_RSWDT_MR (0x400E1904U) /**< \brief (RSWDT) Mode Register */
- #define REG_RSWDT_SR (0x400E1908U) /**< \brief (RSWDT) Status Register */
-#else
- #define REG_RSWDT_CR (*(__O uint32_t*)0x400E1900U) /**< \brief (RSWDT) Control Register */
- #define REG_RSWDT_MR (*(__IO uint32_t*)0x400E1904U) /**< \brief (RSWDT) Mode Register */
- #define REG_RSWDT_SR (*(__I uint32_t*)0x400E1908U) /**< \brief (RSWDT) Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_RSWDT_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/rtc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/rtc.h
deleted file mode 100644
index c44c036..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/rtc.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RTC_INSTANCE_
-#define _SAMS70_RTC_INSTANCE_
-
-/* ========== Register definition for RTC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_RTC_CR (0x400E1860U) /**< \brief (RTC) Control Register */
- #define REG_RTC_MR (0x400E1864U) /**< \brief (RTC) Mode Register */
- #define REG_RTC_TIMR (0x400E1868U) /**< \brief (RTC) Time Register */
- #define REG_RTC_CALR (0x400E186CU) /**< \brief (RTC) Calendar Register */
- #define REG_RTC_TIMALR (0x400E1870U) /**< \brief (RTC) Time Alarm Register */
- #define REG_RTC_CALALR (0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */
- #define REG_RTC_SR (0x400E1878U) /**< \brief (RTC) Status Register */
- #define REG_RTC_SCCR (0x400E187CU) /**< \brief (RTC) Status Clear Command Register */
- #define REG_RTC_IER (0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */
- #define REG_RTC_IDR (0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */
- #define REG_RTC_IMR (0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */
- #define REG_RTC_VER (0x400E188CU) /**< \brief (RTC) Valid Entry Register */
-#else
- #define REG_RTC_CR (*(__IO uint32_t*)0x400E1860U) /**< \brief (RTC) Control Register */
- #define REG_RTC_MR (*(__IO uint32_t*)0x400E1864U) /**< \brief (RTC) Mode Register */
- #define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1868U) /**< \brief (RTC) Time Register */
- #define REG_RTC_CALR (*(__IO uint32_t*)0x400E186CU) /**< \brief (RTC) Calendar Register */
- #define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1870U) /**< \brief (RTC) Time Alarm Register */
- #define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */
- #define REG_RTC_SR (*(__I uint32_t*)0x400E1878U) /**< \brief (RTC) Status Register */
- #define REG_RTC_SCCR (*(__O uint32_t*)0x400E187CU) /**< \brief (RTC) Status Clear Command Register */
- #define REG_RTC_IER (*(__O uint32_t*)0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */
- #define REG_RTC_IDR (*(__O uint32_t*)0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */
- #define REG_RTC_IMR (*(__I uint32_t*)0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */
- #define REG_RTC_VER (*(__I uint32_t*)0x400E188CU) /**< \brief (RTC) Valid Entry Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_RTC_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/rtt.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/rtt.h
deleted file mode 100644
index 79b313d..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/rtt.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RTT_INSTANCE_
-#define _SAMS70_RTT_INSTANCE_
-
-/* ========== Register definition for RTT peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_RTT_MR (0x400E1830U) /**< \brief (RTT) Mode Register */
- #define REG_RTT_AR (0x400E1834U) /**< \brief (RTT) Alarm Register */
- #define REG_RTT_VR (0x400E1838U) /**< \brief (RTT) Value Register */
- #define REG_RTT_SR (0x400E183CU) /**< \brief (RTT) Status Register */
-#else
- #define REG_RTT_MR (*(__IO uint32_t*)0x400E1830U) /**< \brief (RTT) Mode Register */
- #define REG_RTT_AR (*(__IO uint32_t*)0x400E1834U) /**< \brief (RTT) Alarm Register */
- #define REG_RTT_VR (*(__I uint32_t*)0x400E1838U) /**< \brief (RTT) Value Register */
- #define REG_RTT_SR (*(__I uint32_t*)0x400E183CU) /**< \brief (RTT) Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_RTT_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/sdramc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/sdramc.h
deleted file mode 100644
index 7febe8d..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/sdramc.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SDRAMC_INSTANCE_
-#define _SAMS70_SDRAMC_INSTANCE_
-
-/* ========== Register definition for SDRAMC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_SDRAMC_MR (0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */
- #define REG_SDRAMC_TR (0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
- #define REG_SDRAMC_CR (0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
- #define REG_SDRAMC_LPR (0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
- #define REG_SDRAMC_IER (0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
- #define REG_SDRAMC_IDR (0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
- #define REG_SDRAMC_IMR (0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
- #define REG_SDRAMC_ISR (0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
- #define REG_SDRAMC_MDR (0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
- #define REG_SDRAMC_CFR1 (0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
- #define REG_SDRAMC_OCMS (0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */
- #define REG_SDRAMC_OCMS_KEY1 (0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */
- #define REG_SDRAMC_OCMS_KEY2 (0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */
-#else
- #define REG_SDRAMC_MR (*(__IO uint32_t*)0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */
- #define REG_SDRAMC_TR (*(__IO uint32_t*)0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
- #define REG_SDRAMC_CR (*(__IO uint32_t*)0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
- #define REG_SDRAMC_LPR (*(__IO uint32_t*)0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
- #define REG_SDRAMC_IER (*(__O uint32_t*)0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
- #define REG_SDRAMC_IDR (*(__O uint32_t*)0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
- #define REG_SDRAMC_IMR (*(__I uint32_t*)0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
- #define REG_SDRAMC_ISR (*(__I uint32_t*)0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
- #define REG_SDRAMC_MDR (*(__IO uint32_t*)0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
- #define REG_SDRAMC_CFR1 (*(__IO uint32_t*)0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
- #define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */
- #define REG_SDRAMC_OCMS_KEY1 (*(__O uint32_t*)0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */
- #define REG_SDRAMC_OCMS_KEY2 (*(__O uint32_t*)0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_SDRAMC_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/smc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/smc.h
deleted file mode 100644
index e4cde22..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/smc.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SMC_INSTANCE_
-#define _SAMS70_SMC_INSTANCE_
-
-/* ========== Register definition for SMC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_SMC_SETUP0 (0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
- #define REG_SMC_PULSE0 (0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
- #define REG_SMC_CYCLE0 (0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
- #define REG_SMC_MODE0 (0x4008000CU) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */
- #define REG_SMC_SETUP1 (0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
- #define REG_SMC_PULSE1 (0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
- #define REG_SMC_CYCLE1 (0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
- #define REG_SMC_MODE1 (0x4008001CU) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */
- #define REG_SMC_SETUP2 (0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
- #define REG_SMC_PULSE2 (0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
- #define REG_SMC_CYCLE2 (0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
- #define REG_SMC_MODE2 (0x4008002CU) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */
- #define REG_SMC_SETUP3 (0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
- #define REG_SMC_PULSE3 (0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
- #define REG_SMC_CYCLE3 (0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
- #define REG_SMC_MODE3 (0x4008003CU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */
- #define REG_SMC_OCMS (0x40080080U) /**< \brief (SMC) SMC OCMS MODE Register */
- #define REG_SMC_KEY1 (0x40080084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
- #define REG_SMC_KEY2 (0x40080088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
- #define REG_SMC_WPMR (0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */
- #define REG_SMC_WPSR (0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */
-#else
- #define REG_SMC_SETUP0 (*(__IO uint32_t*)0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
- #define REG_SMC_PULSE0 (*(__IO uint32_t*)0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
- #define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
- #define REG_SMC_MODE0 (*(__IO uint32_t*)0x4008000CU) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */
- #define REG_SMC_SETUP1 (*(__IO uint32_t*)0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
- #define REG_SMC_PULSE1 (*(__IO uint32_t*)0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
- #define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
- #define REG_SMC_MODE1 (*(__IO uint32_t*)0x4008001CU) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */
- #define REG_SMC_SETUP2 (*(__IO uint32_t*)0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
- #define REG_SMC_PULSE2 (*(__IO uint32_t*)0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
- #define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
- #define REG_SMC_MODE2 (*(__IO uint32_t*)0x4008002CU) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */
- #define REG_SMC_SETUP3 (*(__IO uint32_t*)0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
- #define REG_SMC_PULSE3 (*(__IO uint32_t*)0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
- #define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
- #define REG_SMC_MODE3 (*(__IO uint32_t*)0x4008003CU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */
- #define REG_SMC_OCMS (*(__IO uint32_t*)0x40080080U) /**< \brief (SMC) SMC OCMS MODE Register */
- #define REG_SMC_KEY1 (*(__O uint32_t*)0x40080084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
- #define REG_SMC_KEY2 (*(__O uint32_t*)0x40080088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
- #define REG_SMC_WPMR (*(__IO uint32_t*)0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */
- #define REG_SMC_WPSR (*(__I uint32_t*)0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_SMC_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/spi0.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/spi0.h
deleted file mode 100644
index 5e7a8cc..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/spi0.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SPI0_INSTANCE_
-#define _SAMS70_SPI0_INSTANCE_
-
-/* ========== Register definition for SPI0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_SPI0_CR (0x40008000U) /**< \brief (SPI0) Control Register */
- #define REG_SPI0_MR (0x40008004U) /**< \brief (SPI0) Mode Register */
- #define REG_SPI0_RDR (0x40008008U) /**< \brief (SPI0) Receive Data Register */
- #define REG_SPI0_TDR (0x4000800CU) /**< \brief (SPI0) Transmit Data Register */
- #define REG_SPI0_SR (0x40008010U) /**< \brief (SPI0) Status Register */
- #define REG_SPI0_IER (0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */
- #define REG_SPI0_IDR (0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */
- #define REG_SPI0_IMR (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */
- #define REG_SPI0_CSR (0x40008030U) /**< \brief (SPI0) Chip Select Register */
- #define REG_SPI0_WPMR (0x400080E4U) /**< \brief (SPI0) Write Protection Mode Register */
- #define REG_SPI0_WPSR (0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */
-#else
- #define REG_SPI0_CR (*(__O uint32_t*)0x40008000U) /**< \brief (SPI0) Control Register */
- #define REG_SPI0_MR (*(__IO uint32_t*)0x40008004U) /**< \brief (SPI0) Mode Register */
- #define REG_SPI0_RDR (*(__I uint32_t*)0x40008008U) /**< \brief (SPI0) Receive Data Register */
- #define REG_SPI0_TDR (*(__O uint32_t*)0x4000800CU) /**< \brief (SPI0) Transmit Data Register */
- #define REG_SPI0_SR (*(__I uint32_t*)0x40008010U) /**< \brief (SPI0) Status Register */
- #define REG_SPI0_IER (*(__O uint32_t*)0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */
- #define REG_SPI0_IDR (*(__O uint32_t*)0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */
- #define REG_SPI0_IMR (*(__I uint32_t*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */
- #define REG_SPI0_CSR (*(__IO uint32_t*)0x40008030U) /**< \brief (SPI0) Chip Select Register */
- #define REG_SPI0_WPMR (*(__IO uint32_t*)0x400080E4U) /**< \brief (SPI0) Write Protection Mode Register */
- #define REG_SPI0_WPSR (*(__I uint32_t*)0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_SPI0_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/spi1.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/spi1.h
deleted file mode 100644
index dbd26f0..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/spi1.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SPI1_INSTANCE_
-#define _SAMS70_SPI1_INSTANCE_
-
-/* ========== Register definition for SPI1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_SPI1_CR (0x40058000U) /**< \brief (SPI1) Control Register */
- #define REG_SPI1_MR (0x40058004U) /**< \brief (SPI1) Mode Register */
- #define REG_SPI1_RDR (0x40058008U) /**< \brief (SPI1) Receive Data Register */
- #define REG_SPI1_TDR (0x4005800CU) /**< \brief (SPI1) Transmit Data Register */
- #define REG_SPI1_SR (0x40058010U) /**< \brief (SPI1) Status Register */
- #define REG_SPI1_IER (0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */
- #define REG_SPI1_IDR (0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */
- #define REG_SPI1_IMR (0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */
- #define REG_SPI1_CSR (0x40058030U) /**< \brief (SPI1) Chip Select Register */
- #define REG_SPI1_WPMR (0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */
- #define REG_SPI1_WPSR (0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */
-#else
- #define REG_SPI1_CR (*(__O uint32_t*)0x40058000U) /**< \brief (SPI1) Control Register */
- #define REG_SPI1_MR (*(__IO uint32_t*)0x40058004U) /**< \brief (SPI1) Mode Register */
- #define REG_SPI1_RDR (*(__I uint32_t*)0x40058008U) /**< \brief (SPI1) Receive Data Register */
- #define REG_SPI1_TDR (*(__O uint32_t*)0x4005800CU) /**< \brief (SPI1) Transmit Data Register */
- #define REG_SPI1_SR (*(__I uint32_t*)0x40058010U) /**< \brief (SPI1) Status Register */
- #define REG_SPI1_IER (*(__O uint32_t*)0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */
- #define REG_SPI1_IDR (*(__O uint32_t*)0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */
- #define REG_SPI1_IMR (*(__I uint32_t*)0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */
- #define REG_SPI1_CSR (*(__IO uint32_t*)0x40058030U) /**< \brief (SPI1) Chip Select Register */
- #define REG_SPI1_WPMR (*(__IO uint32_t*)0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */
- #define REG_SPI1_WPSR (*(__I uint32_t*)0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_SPI1_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/ssc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/ssc.h
deleted file mode 100644
index 3d55362..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/ssc.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SSC_INSTANCE_
-#define _SAMS70_SSC_INSTANCE_
-
-/* ========== Register definition for SSC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */
- #define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */
- #define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
- #define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
- #define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
- #define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
- #define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */
- #define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
- #define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
- #define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
- #define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
- #define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
- #define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */
- #define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
- #define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
- #define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
- #define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */
- #define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protection Status Register */
-#else
- #define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< \brief (SSC) Control Register */
- #define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
- #define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
- #define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
- #define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
- #define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
- #define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
- #define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
- #define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
- #define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
- #define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
- #define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
- #define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< \brief (SSC) Status Register */
- #define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
- #define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
- #define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
- #define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */
- #define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< \brief (SSC) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_SSC_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/supc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/supc.h
deleted file mode 100644
index 3a8ccae..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/supc.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SUPC_INSTANCE_
-#define _SAMS70_SUPC_INSTANCE_
-
-/* ========== Register definition for SUPC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_SUPC_CR (0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */
- #define REG_SUPC_SMMR (0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
- #define REG_SUPC_MR (0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */
- #define REG_SUPC_WUMR (0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */
- #define REG_SUPC_WUIR (0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */
- #define REG_SUPC_SR (0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */
-#else
- #define REG_SUPC_CR (*(__O uint32_t*)0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */
- #define REG_SUPC_SMMR (*(__IO uint32_t*)0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
- #define REG_SUPC_MR (*(__IO uint32_t*)0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */
- #define REG_SUPC_WUMR (*(__IO uint32_t*)0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */
- #define REG_SUPC_WUIR (*(__IO uint32_t*)0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */
- #define REG_SUPC_SR (*(__I uint32_t*)0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_SUPC_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/tc0.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/tc0.h
deleted file mode 100644
index 35b9687..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/tc0.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TC0_INSTANCE_
-#define _SAMS70_TC0_INSTANCE_
-
-/* ========== Register definition for TC0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TC0_CCR0 (0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
- #define REG_TC0_CMR0 (0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
- #define REG_TC0_SMMR0 (0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC0_RAB0 (0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */
- #define REG_TC0_CV0 (0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */
- #define REG_TC0_RA0 (0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */
- #define REG_TC0_RB0 (0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */
- #define REG_TC0_RC0 (0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */
- #define REG_TC0_SR0 (0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */
- #define REG_TC0_IER0 (0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
- #define REG_TC0_IDR0 (0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
- #define REG_TC0_IMR0 (0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
- #define REG_TC0_EMR0 (0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */
- #define REG_TC0_CCR1 (0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
- #define REG_TC0_CMR1 (0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
- #define REG_TC0_SMMR1 (0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC0_RAB1 (0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */
- #define REG_TC0_CV1 (0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */
- #define REG_TC0_RA1 (0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */
- #define REG_TC0_RB1 (0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */
- #define REG_TC0_RC1 (0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */
- #define REG_TC0_SR1 (0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */
- #define REG_TC0_IER1 (0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
- #define REG_TC0_IDR1 (0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
- #define REG_TC0_IMR1 (0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
- #define REG_TC0_EMR1 (0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */
- #define REG_TC0_CCR2 (0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
- #define REG_TC0_CMR2 (0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
- #define REG_TC0_SMMR2 (0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC0_RAB2 (0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */
- #define REG_TC0_CV2 (0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */
- #define REG_TC0_RA2 (0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */
- #define REG_TC0_RB2 (0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */
- #define REG_TC0_RC2 (0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */
- #define REG_TC0_SR2 (0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */
- #define REG_TC0_IER2 (0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
- #define REG_TC0_IDR2 (0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
- #define REG_TC0_IMR2 (0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
- #define REG_TC0_EMR2 (0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */
- #define REG_TC0_BCR (0x4000C0C0U) /**< \brief (TC0) Block Control Register */
- #define REG_TC0_BMR (0x4000C0C4U) /**< \brief (TC0) Block Mode Register */
- #define REG_TC0_QIER (0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
- #define REG_TC0_QIDR (0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
- #define REG_TC0_QIMR (0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
- #define REG_TC0_QISR (0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
- #define REG_TC0_FMR (0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */
- #define REG_TC0_WPMR (0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */
-#else
- #define REG_TC0_CCR0 (*(__O uint32_t*)0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
- #define REG_TC0_CMR0 (*(__IO uint32_t*)0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
- #define REG_TC0_SMMR0 (*(__IO uint32_t*)0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC0_RAB0 (*(__I uint32_t*)0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */
- #define REG_TC0_CV0 (*(__I uint32_t*)0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */
- #define REG_TC0_RA0 (*(__IO uint32_t*)0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */
- #define REG_TC0_RB0 (*(__IO uint32_t*)0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */
- #define REG_TC0_RC0 (*(__IO uint32_t*)0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */
- #define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */
- #define REG_TC0_IER0 (*(__O uint32_t*)0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
- #define REG_TC0_IDR0 (*(__O uint32_t*)0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
- #define REG_TC0_IMR0 (*(__I uint32_t*)0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
- #define REG_TC0_EMR0 (*(__IO uint32_t*)0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */
- #define REG_TC0_CCR1 (*(__O uint32_t*)0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
- #define REG_TC0_CMR1 (*(__IO uint32_t*)0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
- #define REG_TC0_SMMR1 (*(__IO uint32_t*)0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC0_RAB1 (*(__I uint32_t*)0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */
- #define REG_TC0_CV1 (*(__I uint32_t*)0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */
- #define REG_TC0_RA1 (*(__IO uint32_t*)0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */
- #define REG_TC0_RB1 (*(__IO uint32_t*)0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */
- #define REG_TC0_RC1 (*(__IO uint32_t*)0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */
- #define REG_TC0_SR1 (*(__I uint32_t*)0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */
- #define REG_TC0_IER1 (*(__O uint32_t*)0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
- #define REG_TC0_IDR1 (*(__O uint32_t*)0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
- #define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
- #define REG_TC0_EMR1 (*(__IO uint32_t*)0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */
- #define REG_TC0_CCR2 (*(__O uint32_t*)0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
- #define REG_TC0_CMR2 (*(__IO uint32_t*)0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
- #define REG_TC0_SMMR2 (*(__IO uint32_t*)0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC0_RAB2 (*(__I uint32_t*)0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */
- #define REG_TC0_CV2 (*(__I uint32_t*)0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */
- #define REG_TC0_RA2 (*(__IO uint32_t*)0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */
- #define REG_TC0_RB2 (*(__IO uint32_t*)0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */
- #define REG_TC0_RC2 (*(__IO uint32_t*)0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */
- #define REG_TC0_SR2 (*(__I uint32_t*)0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */
- #define REG_TC0_IER2 (*(__O uint32_t*)0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
- #define REG_TC0_IDR2 (*(__O uint32_t*)0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
- #define REG_TC0_IMR2 (*(__I uint32_t*)0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
- #define REG_TC0_EMR2 (*(__IO uint32_t*)0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */
- #define REG_TC0_BCR (*(__O uint32_t*)0x4000C0C0U) /**< \brief (TC0) Block Control Register */
- #define REG_TC0_BMR (*(__IO uint32_t*)0x4000C0C4U) /**< \brief (TC0) Block Mode Register */
- #define REG_TC0_QIER (*(__O uint32_t*)0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
- #define REG_TC0_QIDR (*(__O uint32_t*)0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
- #define REG_TC0_QIMR (*(__I uint32_t*)0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
- #define REG_TC0_QISR (*(__I uint32_t*)0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
- #define REG_TC0_FMR (*(__IO uint32_t*)0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */
- #define REG_TC0_WPMR (*(__IO uint32_t*)0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TC0_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/tc1.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/tc1.h
deleted file mode 100644
index 0f1bc18..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/tc1.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TC1_INSTANCE_
-#define _SAMS70_TC1_INSTANCE_
-
-/* ========== Register definition for TC1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TC1_CCR0 (0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
- #define REG_TC1_CMR0 (0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
- #define REG_TC1_SMMR0 (0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC1_RAB0 (0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */
- #define REG_TC1_CV0 (0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */
- #define REG_TC1_RA0 (0x40010014U) /**< \brief (TC1) Register A (channel = 0) */
- #define REG_TC1_RB0 (0x40010018U) /**< \brief (TC1) Register B (channel = 0) */
- #define REG_TC1_RC0 (0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */
- #define REG_TC1_SR0 (0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */
- #define REG_TC1_IER0 (0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
- #define REG_TC1_IDR0 (0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
- #define REG_TC1_IMR0 (0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
- #define REG_TC1_EMR0 (0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */
- #define REG_TC1_CCR1 (0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
- #define REG_TC1_CMR1 (0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
- #define REG_TC1_SMMR1 (0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC1_RAB1 (0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */
- #define REG_TC1_CV1 (0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */
- #define REG_TC1_RA1 (0x40010054U) /**< \brief (TC1) Register A (channel = 1) */
- #define REG_TC1_RB1 (0x40010058U) /**< \brief (TC1) Register B (channel = 1) */
- #define REG_TC1_RC1 (0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */
- #define REG_TC1_SR1 (0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */
- #define REG_TC1_IER1 (0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
- #define REG_TC1_IDR1 (0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
- #define REG_TC1_IMR1 (0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
- #define REG_TC1_EMR1 (0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */
- #define REG_TC1_CCR2 (0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
- #define REG_TC1_CMR2 (0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
- #define REG_TC1_SMMR2 (0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC1_RAB2 (0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */
- #define REG_TC1_CV2 (0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */
- #define REG_TC1_RA2 (0x40010094U) /**< \brief (TC1) Register A (channel = 2) */
- #define REG_TC1_RB2 (0x40010098U) /**< \brief (TC1) Register B (channel = 2) */
- #define REG_TC1_RC2 (0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */
- #define REG_TC1_SR2 (0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */
- #define REG_TC1_IER2 (0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
- #define REG_TC1_IDR2 (0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
- #define REG_TC1_IMR2 (0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
- #define REG_TC1_EMR2 (0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */
- #define REG_TC1_BCR (0x400100C0U) /**< \brief (TC1) Block Control Register */
- #define REG_TC1_BMR (0x400100C4U) /**< \brief (TC1) Block Mode Register */
- #define REG_TC1_QIER (0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
- #define REG_TC1_QIDR (0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
- #define REG_TC1_QIMR (0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
- #define REG_TC1_QISR (0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
- #define REG_TC1_FMR (0x400100D8U) /**< \brief (TC1) Fault Mode Register */
- #define REG_TC1_WPMR (0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */
-#else
- #define REG_TC1_CCR0 (*(__O uint32_t*)0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
- #define REG_TC1_CMR0 (*(__IO uint32_t*)0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
- #define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC1_RAB0 (*(__I uint32_t*)0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */
- #define REG_TC1_CV0 (*(__I uint32_t*)0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */
- #define REG_TC1_RA0 (*(__IO uint32_t*)0x40010014U) /**< \brief (TC1) Register A (channel = 0) */
- #define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< \brief (TC1) Register B (channel = 0) */
- #define REG_TC1_RC0 (*(__IO uint32_t*)0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */
- #define REG_TC1_SR0 (*(__I uint32_t*)0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */
- #define REG_TC1_IER0 (*(__O uint32_t*)0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
- #define REG_TC1_IDR0 (*(__O uint32_t*)0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
- #define REG_TC1_IMR0 (*(__I uint32_t*)0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
- #define REG_TC1_EMR0 (*(__IO uint32_t*)0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */
- #define REG_TC1_CCR1 (*(__O uint32_t*)0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
- #define REG_TC1_CMR1 (*(__IO uint32_t*)0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
- #define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC1_RAB1 (*(__I uint32_t*)0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */
- #define REG_TC1_CV1 (*(__I uint32_t*)0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */
- #define REG_TC1_RA1 (*(__IO uint32_t*)0x40010054U) /**< \brief (TC1) Register A (channel = 1) */
- #define REG_TC1_RB1 (*(__IO uint32_t*)0x40010058U) /**< \brief (TC1) Register B (channel = 1) */
- #define REG_TC1_RC1 (*(__IO uint32_t*)0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */
- #define REG_TC1_SR1 (*(__I uint32_t*)0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */
- #define REG_TC1_IER1 (*(__O uint32_t*)0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
- #define REG_TC1_IDR1 (*(__O uint32_t*)0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
- #define REG_TC1_IMR1 (*(__I uint32_t*)0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
- #define REG_TC1_EMR1 (*(__IO uint32_t*)0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */
- #define REG_TC1_CCR2 (*(__O uint32_t*)0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
- #define REG_TC1_CMR2 (*(__IO uint32_t*)0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
- #define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC1_RAB2 (*(__I uint32_t*)0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */
- #define REG_TC1_CV2 (*(__I uint32_t*)0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */
- #define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< \brief (TC1) Register A (channel = 2) */
- #define REG_TC1_RB2 (*(__IO uint32_t*)0x40010098U) /**< \brief (TC1) Register B (channel = 2) */
- #define REG_TC1_RC2 (*(__IO uint32_t*)0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */
- #define REG_TC1_SR2 (*(__I uint32_t*)0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */
- #define REG_TC1_IER2 (*(__O uint32_t*)0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
- #define REG_TC1_IDR2 (*(__O uint32_t*)0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
- #define REG_TC1_IMR2 (*(__I uint32_t*)0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
- #define REG_TC1_EMR2 (*(__IO uint32_t*)0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */
- #define REG_TC1_BCR (*(__O uint32_t*)0x400100C0U) /**< \brief (TC1) Block Control Register */
- #define REG_TC1_BMR (*(__IO uint32_t*)0x400100C4U) /**< \brief (TC1) Block Mode Register */
- #define REG_TC1_QIER (*(__O uint32_t*)0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
- #define REG_TC1_QIDR (*(__O uint32_t*)0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
- #define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
- #define REG_TC1_QISR (*(__I uint32_t*)0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
- #define REG_TC1_FMR (*(__IO uint32_t*)0x400100D8U) /**< \brief (TC1) Fault Mode Register */
- #define REG_TC1_WPMR (*(__IO uint32_t*)0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TC1_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/tc2.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/tc2.h
deleted file mode 100644
index 6a7e0b9..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/tc2.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TC2_INSTANCE_
-#define _SAMS70_TC2_INSTANCE_
-
-/* ========== Register definition for TC2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TC2_CCR0 (0x40014000U) /**< \brief (TC2) Channel Control Register (channel = 0) */
- #define REG_TC2_CMR0 (0x40014004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */
- #define REG_TC2_SMMR0 (0x40014008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC2_RAB0 (0x4001400CU) /**< \brief (TC2) Register AB (channel = 0) */
- #define REG_TC2_CV0 (0x40014010U) /**< \brief (TC2) Counter Value (channel = 0) */
- #define REG_TC2_RA0 (0x40014014U) /**< \brief (TC2) Register A (channel = 0) */
- #define REG_TC2_RB0 (0x40014018U) /**< \brief (TC2) Register B (channel = 0) */
- #define REG_TC2_RC0 (0x4001401CU) /**< \brief (TC2) Register C (channel = 0) */
- #define REG_TC2_SR0 (0x40014020U) /**< \brief (TC2) Status Register (channel = 0) */
- #define REG_TC2_IER0 (0x40014024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */
- #define REG_TC2_IDR0 (0x40014028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */
- #define REG_TC2_IMR0 (0x4001402CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */
- #define REG_TC2_EMR0 (0x40014030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */
- #define REG_TC2_CCR1 (0x40014040U) /**< \brief (TC2) Channel Control Register (channel = 1) */
- #define REG_TC2_CMR1 (0x40014044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */
- #define REG_TC2_SMMR1 (0x40014048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC2_RAB1 (0x4001404CU) /**< \brief (TC2) Register AB (channel = 1) */
- #define REG_TC2_CV1 (0x40014050U) /**< \brief (TC2) Counter Value (channel = 1) */
- #define REG_TC2_RA1 (0x40014054U) /**< \brief (TC2) Register A (channel = 1) */
- #define REG_TC2_RB1 (0x40014058U) /**< \brief (TC2) Register B (channel = 1) */
- #define REG_TC2_RC1 (0x4001405CU) /**< \brief (TC2) Register C (channel = 1) */
- #define REG_TC2_SR1 (0x40014060U) /**< \brief (TC2) Status Register (channel = 1) */
- #define REG_TC2_IER1 (0x40014064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */
- #define REG_TC2_IDR1 (0x40014068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */
- #define REG_TC2_IMR1 (0x4001406CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */
- #define REG_TC2_EMR1 (0x40014070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */
- #define REG_TC2_CCR2 (0x40014080U) /**< \brief (TC2) Channel Control Register (channel = 2) */
- #define REG_TC2_CMR2 (0x40014084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */
- #define REG_TC2_SMMR2 (0x40014088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC2_RAB2 (0x4001408CU) /**< \brief (TC2) Register AB (channel = 2) */
- #define REG_TC2_CV2 (0x40014090U) /**< \brief (TC2) Counter Value (channel = 2) */
- #define REG_TC2_RA2 (0x40014094U) /**< \brief (TC2) Register A (channel = 2) */
- #define REG_TC2_RB2 (0x40014098U) /**< \brief (TC2) Register B (channel = 2) */
- #define REG_TC2_RC2 (0x4001409CU) /**< \brief (TC2) Register C (channel = 2) */
- #define REG_TC2_SR2 (0x400140A0U) /**< \brief (TC2) Status Register (channel = 2) */
- #define REG_TC2_IER2 (0x400140A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */
- #define REG_TC2_IDR2 (0x400140A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */
- #define REG_TC2_IMR2 (0x400140ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */
- #define REG_TC2_EMR2 (0x400140B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */
- #define REG_TC2_BCR (0x400140C0U) /**< \brief (TC2) Block Control Register */
- #define REG_TC2_BMR (0x400140C4U) /**< \brief (TC2) Block Mode Register */
- #define REG_TC2_QIER (0x400140C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */
- #define REG_TC2_QIDR (0x400140CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */
- #define REG_TC2_QIMR (0x400140D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */
- #define REG_TC2_QISR (0x400140D4U) /**< \brief (TC2) QDEC Interrupt Status Register */
- #define REG_TC2_FMR (0x400140D8U) /**< \brief (TC2) Fault Mode Register */
- #define REG_TC2_WPMR (0x400140E4U) /**< \brief (TC2) Write Protection Mode Register */
-#else
- #define REG_TC2_CCR0 (*(__O uint32_t*)0x40014000U) /**< \brief (TC2) Channel Control Register (channel = 0) */
- #define REG_TC2_CMR0 (*(__IO uint32_t*)0x40014004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */
- #define REG_TC2_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC2_RAB0 (*(__I uint32_t*)0x4001400CU) /**< \brief (TC2) Register AB (channel = 0) */
- #define REG_TC2_CV0 (*(__I uint32_t*)0x40014010U) /**< \brief (TC2) Counter Value (channel = 0) */
- #define REG_TC2_RA0 (*(__IO uint32_t*)0x40014014U) /**< \brief (TC2) Register A (channel = 0) */
- #define REG_TC2_RB0 (*(__IO uint32_t*)0x40014018U) /**< \brief (TC2) Register B (channel = 0) */
- #define REG_TC2_RC0 (*(__IO uint32_t*)0x4001401CU) /**< \brief (TC2) Register C (channel = 0) */
- #define REG_TC2_SR0 (*(__I uint32_t*)0x40014020U) /**< \brief (TC2) Status Register (channel = 0) */
- #define REG_TC2_IER0 (*(__O uint32_t*)0x40014024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */
- #define REG_TC2_IDR0 (*(__O uint32_t*)0x40014028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */
- #define REG_TC2_IMR0 (*(__I uint32_t*)0x4001402CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */
- #define REG_TC2_EMR0 (*(__IO uint32_t*)0x40014030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */
- #define REG_TC2_CCR1 (*(__O uint32_t*)0x40014040U) /**< \brief (TC2) Channel Control Register (channel = 1) */
- #define REG_TC2_CMR1 (*(__IO uint32_t*)0x40014044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */
- #define REG_TC2_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC2_RAB1 (*(__I uint32_t*)0x4001404CU) /**< \brief (TC2) Register AB (channel = 1) */
- #define REG_TC2_CV1 (*(__I uint32_t*)0x40014050U) /**< \brief (TC2) Counter Value (channel = 1) */
- #define REG_TC2_RA1 (*(__IO uint32_t*)0x40014054U) /**< \brief (TC2) Register A (channel = 1) */
- #define REG_TC2_RB1 (*(__IO uint32_t*)0x40014058U) /**< \brief (TC2) Register B (channel = 1) */
- #define REG_TC2_RC1 (*(__IO uint32_t*)0x4001405CU) /**< \brief (TC2) Register C (channel = 1) */
- #define REG_TC2_SR1 (*(__I uint32_t*)0x40014060U) /**< \brief (TC2) Status Register (channel = 1) */
- #define REG_TC2_IER1 (*(__O uint32_t*)0x40014064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */
- #define REG_TC2_IDR1 (*(__O uint32_t*)0x40014068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */
- #define REG_TC2_IMR1 (*(__I uint32_t*)0x4001406CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */
- #define REG_TC2_EMR1 (*(__IO uint32_t*)0x40014070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */
- #define REG_TC2_CCR2 (*(__O uint32_t*)0x40014080U) /**< \brief (TC2) Channel Control Register (channel = 2) */
- #define REG_TC2_CMR2 (*(__IO uint32_t*)0x40014084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */
- #define REG_TC2_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC2_RAB2 (*(__I uint32_t*)0x4001408CU) /**< \brief (TC2) Register AB (channel = 2) */
- #define REG_TC2_CV2 (*(__I uint32_t*)0x40014090U) /**< \brief (TC2) Counter Value (channel = 2) */
- #define REG_TC2_RA2 (*(__IO uint32_t*)0x40014094U) /**< \brief (TC2) Register A (channel = 2) */
- #define REG_TC2_RB2 (*(__IO uint32_t*)0x40014098U) /**< \brief (TC2) Register B (channel = 2) */
- #define REG_TC2_RC2 (*(__IO uint32_t*)0x4001409CU) /**< \brief (TC2) Register C (channel = 2) */
- #define REG_TC2_SR2 (*(__I uint32_t*)0x400140A0U) /**< \brief (TC2) Status Register (channel = 2) */
- #define REG_TC2_IER2 (*(__O uint32_t*)0x400140A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */
- #define REG_TC2_IDR2 (*(__O uint32_t*)0x400140A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */
- #define REG_TC2_IMR2 (*(__I uint32_t*)0x400140ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */
- #define REG_TC2_EMR2 (*(__IO uint32_t*)0x400140B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */
- #define REG_TC2_BCR (*(__O uint32_t*)0x400140C0U) /**< \brief (TC2) Block Control Register */
- #define REG_TC2_BMR (*(__IO uint32_t*)0x400140C4U) /**< \brief (TC2) Block Mode Register */
- #define REG_TC2_QIER (*(__O uint32_t*)0x400140C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */
- #define REG_TC2_QIDR (*(__O uint32_t*)0x400140CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */
- #define REG_TC2_QIMR (*(__I uint32_t*)0x400140D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */
- #define REG_TC2_QISR (*(__I uint32_t*)0x400140D4U) /**< \brief (TC2) QDEC Interrupt Status Register */
- #define REG_TC2_FMR (*(__IO uint32_t*)0x400140D8U) /**< \brief (TC2) Fault Mode Register */
- #define REG_TC2_WPMR (*(__IO uint32_t*)0x400140E4U) /**< \brief (TC2) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TC2_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/tc3.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/tc3.h
deleted file mode 100644
index 2921bd4..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/tc3.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TC3_INSTANCE_
-#define _SAMS70_TC3_INSTANCE_
-
-/* ========== Register definition for TC3 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TC3_CCR0 (0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */
- #define REG_TC3_CMR0 (0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */
- #define REG_TC3_SMMR0 (0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC3_RAB0 (0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */
- #define REG_TC3_CV0 (0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */
- #define REG_TC3_RA0 (0x40054014U) /**< \brief (TC3) Register A (channel = 0) */
- #define REG_TC3_RB0 (0x40054018U) /**< \brief (TC3) Register B (channel = 0) */
- #define REG_TC3_RC0 (0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */
- #define REG_TC3_SR0 (0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */
- #define REG_TC3_IER0 (0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */
- #define REG_TC3_IDR0 (0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */
- #define REG_TC3_IMR0 (0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */
- #define REG_TC3_EMR0 (0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */
- #define REG_TC3_CCR1 (0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */
- #define REG_TC3_CMR1 (0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */
- #define REG_TC3_SMMR1 (0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC3_RAB1 (0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */
- #define REG_TC3_CV1 (0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */
- #define REG_TC3_RA1 (0x40054054U) /**< \brief (TC3) Register A (channel = 1) */
- #define REG_TC3_RB1 (0x40054058U) /**< \brief (TC3) Register B (channel = 1) */
- #define REG_TC3_RC1 (0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */
- #define REG_TC3_SR1 (0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */
- #define REG_TC3_IER1 (0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */
- #define REG_TC3_IDR1 (0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */
- #define REG_TC3_IMR1 (0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */
- #define REG_TC3_EMR1 (0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */
- #define REG_TC3_CCR2 (0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */
- #define REG_TC3_CMR2 (0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */
- #define REG_TC3_SMMR2 (0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC3_RAB2 (0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */
- #define REG_TC3_CV2 (0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */
- #define REG_TC3_RA2 (0x40054094U) /**< \brief (TC3) Register A (channel = 2) */
- #define REG_TC3_RB2 (0x40054098U) /**< \brief (TC3) Register B (channel = 2) */
- #define REG_TC3_RC2 (0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */
- #define REG_TC3_SR2 (0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */
- #define REG_TC3_IER2 (0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */
- #define REG_TC3_IDR2 (0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */
- #define REG_TC3_IMR2 (0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */
- #define REG_TC3_EMR2 (0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */
- #define REG_TC3_BCR (0x400540C0U) /**< \brief (TC3) Block Control Register */
- #define REG_TC3_BMR (0x400540C4U) /**< \brief (TC3) Block Mode Register */
- #define REG_TC3_QIER (0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */
- #define REG_TC3_QIDR (0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */
- #define REG_TC3_QIMR (0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */
- #define REG_TC3_QISR (0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */
- #define REG_TC3_FMR (0x400540D8U) /**< \brief (TC3) Fault Mode Register */
- #define REG_TC3_WPMR (0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */
-#else
- #define REG_TC3_CCR0 (*(__O uint32_t*)0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */
- #define REG_TC3_CMR0 (*(__IO uint32_t*)0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */
- #define REG_TC3_SMMR0 (*(__IO uint32_t*)0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC3_RAB0 (*(__I uint32_t*)0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */
- #define REG_TC3_CV0 (*(__I uint32_t*)0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */
- #define REG_TC3_RA0 (*(__IO uint32_t*)0x40054014U) /**< \brief (TC3) Register A (channel = 0) */
- #define REG_TC3_RB0 (*(__IO uint32_t*)0x40054018U) /**< \brief (TC3) Register B (channel = 0) */
- #define REG_TC3_RC0 (*(__IO uint32_t*)0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */
- #define REG_TC3_SR0 (*(__I uint32_t*)0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */
- #define REG_TC3_IER0 (*(__O uint32_t*)0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */
- #define REG_TC3_IDR0 (*(__O uint32_t*)0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */
- #define REG_TC3_IMR0 (*(__I uint32_t*)0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */
- #define REG_TC3_EMR0 (*(__IO uint32_t*)0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */
- #define REG_TC3_CCR1 (*(__O uint32_t*)0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */
- #define REG_TC3_CMR1 (*(__IO uint32_t*)0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */
- #define REG_TC3_SMMR1 (*(__IO uint32_t*)0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC3_RAB1 (*(__I uint32_t*)0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */
- #define REG_TC3_CV1 (*(__I uint32_t*)0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */
- #define REG_TC3_RA1 (*(__IO uint32_t*)0x40054054U) /**< \brief (TC3) Register A (channel = 1) */
- #define REG_TC3_RB1 (*(__IO uint32_t*)0x40054058U) /**< \brief (TC3) Register B (channel = 1) */
- #define REG_TC3_RC1 (*(__IO uint32_t*)0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */
- #define REG_TC3_SR1 (*(__I uint32_t*)0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */
- #define REG_TC3_IER1 (*(__O uint32_t*)0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */
- #define REG_TC3_IDR1 (*(__O uint32_t*)0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */
- #define REG_TC3_IMR1 (*(__I uint32_t*)0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */
- #define REG_TC3_EMR1 (*(__IO uint32_t*)0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */
- #define REG_TC3_CCR2 (*(__O uint32_t*)0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */
- #define REG_TC3_CMR2 (*(__IO uint32_t*)0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */
- #define REG_TC3_SMMR2 (*(__IO uint32_t*)0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC3_RAB2 (*(__I uint32_t*)0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */
- #define REG_TC3_CV2 (*(__I uint32_t*)0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */
- #define REG_TC3_RA2 (*(__IO uint32_t*)0x40054094U) /**< \brief (TC3) Register A (channel = 2) */
- #define REG_TC3_RB2 (*(__IO uint32_t*)0x40054098U) /**< \brief (TC3) Register B (channel = 2) */
- #define REG_TC3_RC2 (*(__IO uint32_t*)0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */
- #define REG_TC3_SR2 (*(__I uint32_t*)0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */
- #define REG_TC3_IER2 (*(__O uint32_t*)0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */
- #define REG_TC3_IDR2 (*(__O uint32_t*)0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */
- #define REG_TC3_IMR2 (*(__I uint32_t*)0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */
- #define REG_TC3_EMR2 (*(__IO uint32_t*)0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */
- #define REG_TC3_BCR (*(__O uint32_t*)0x400540C0U) /**< \brief (TC3) Block Control Register */
- #define REG_TC3_BMR (*(__IO uint32_t*)0x400540C4U) /**< \brief (TC3) Block Mode Register */
- #define REG_TC3_QIER (*(__O uint32_t*)0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */
- #define REG_TC3_QIDR (*(__O uint32_t*)0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */
- #define REG_TC3_QIMR (*(__I uint32_t*)0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */
- #define REG_TC3_QISR (*(__I uint32_t*)0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */
- #define REG_TC3_FMR (*(__IO uint32_t*)0x400540D8U) /**< \brief (TC3) Fault Mode Register */
- #define REG_TC3_WPMR (*(__IO uint32_t*)0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TC3_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/trng.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/trng.h
deleted file mode 100644
index aa70ee0..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/trng.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TRNG_INSTANCE_
-#define _SAMS70_TRNG_INSTANCE_
-
-/* ========== Register definition for TRNG peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TRNG_CR (0x40070000U) /**< \brief (TRNG) Control Register */
- #define REG_TRNG_IER (0x40070010U) /**< \brief (TRNG) Interrupt Enable Register */
- #define REG_TRNG_IDR (0x40070014U) /**< \brief (TRNG) Interrupt Disable Register */
- #define REG_TRNG_IMR (0x40070018U) /**< \brief (TRNG) Interrupt Mask Register */
- #define REG_TRNG_ISR (0x4007001CU) /**< \brief (TRNG) Interrupt Status Register */
- #define REG_TRNG_ODATA (0x40070050U) /**< \brief (TRNG) Output Data Register */
-#else
- #define REG_TRNG_CR (*(__O uint32_t*)0x40070000U) /**< \brief (TRNG) Control Register */
- #define REG_TRNG_IER (*(__O uint32_t*)0x40070010U) /**< \brief (TRNG) Interrupt Enable Register */
- #define REG_TRNG_IDR (*(__O uint32_t*)0x40070014U) /**< \brief (TRNG) Interrupt Disable Register */
- #define REG_TRNG_IMR (*(__I uint32_t*)0x40070018U) /**< \brief (TRNG) Interrupt Mask Register */
- #define REG_TRNG_ISR (*(__I uint32_t*)0x4007001CU) /**< \brief (TRNG) Interrupt Status Register */
- #define REG_TRNG_ODATA (*(__I uint32_t*)0x40070050U) /**< \brief (TRNG) Output Data Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TRNG_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs0.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs0.h
deleted file mode 100644
index 8fc2286..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs0.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TWIHS0_INSTANCE_
-#define _SAMS70_TWIHS0_INSTANCE_
-
-/* ========== Register definition for TWIHS0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TWIHS0_CR (0x40018000U) /**< \brief (TWIHS0) Control Register */
- #define REG_TWIHS0_MMR (0x40018004U) /**< \brief (TWIHS0) Master Mode Register */
- #define REG_TWIHS0_SMR (0x40018008U) /**< \brief (TWIHS0) Slave Mode Register */
- #define REG_TWIHS0_IADR (0x4001800CU) /**< \brief (TWIHS0) Internal Address Register */
- #define REG_TWIHS0_CWGR (0x40018010U) /**< \brief (TWIHS0) Clock Waveform Generator Register */
- #define REG_TWIHS0_SR (0x40018020U) /**< \brief (TWIHS0) Status Register */
- #define REG_TWIHS0_IER (0x40018024U) /**< \brief (TWIHS0) Interrupt Enable Register */
- #define REG_TWIHS0_IDR (0x40018028U) /**< \brief (TWIHS0) Interrupt Disable Register */
- #define REG_TWIHS0_IMR (0x4001802CU) /**< \brief (TWIHS0) Interrupt Mask Register */
- #define REG_TWIHS0_RHR (0x40018030U) /**< \brief (TWIHS0) Receive Holding Register */
- #define REG_TWIHS0_THR (0x40018034U) /**< \brief (TWIHS0) Transmit Holding Register */
- #define REG_TWIHS0_SMBTR (0x40018038U) /**< \brief (TWIHS0) SMBus Timing Register */
- #define REG_TWIHS0_FILTR (0x40018044U) /**< \brief (TWIHS0) Filter Register */
- #define REG_TWIHS0_SWMR (0x4001804CU) /**< \brief (TWIHS0) SleepWalking Matching Register */
- #define REG_TWIHS0_WPMR (0x400180E4U) /**< \brief (TWIHS0) Write Protection Mode Register */
- #define REG_TWIHS0_WPSR (0x400180E8U) /**< \brief (TWIHS0) Write Protection Status Register */
-#else
- #define REG_TWIHS0_CR (*(__O uint32_t*)0x40018000U) /**< \brief (TWIHS0) Control Register */
- #define REG_TWIHS0_MMR (*(__IO uint32_t*)0x40018004U) /**< \brief (TWIHS0) Master Mode Register */
- #define REG_TWIHS0_SMR (*(__IO uint32_t*)0x40018008U) /**< \brief (TWIHS0) Slave Mode Register */
- #define REG_TWIHS0_IADR (*(__IO uint32_t*)0x4001800CU) /**< \brief (TWIHS0) Internal Address Register */
- #define REG_TWIHS0_CWGR (*(__IO uint32_t*)0x40018010U) /**< \brief (TWIHS0) Clock Waveform Generator Register */
- #define REG_TWIHS0_SR (*(__I uint32_t*)0x40018020U) /**< \brief (TWIHS0) Status Register */
- #define REG_TWIHS0_IER (*(__O uint32_t*)0x40018024U) /**< \brief (TWIHS0) Interrupt Enable Register */
- #define REG_TWIHS0_IDR (*(__O uint32_t*)0x40018028U) /**< \brief (TWIHS0) Interrupt Disable Register */
- #define REG_TWIHS0_IMR (*(__I uint32_t*)0x4001802CU) /**< \brief (TWIHS0) Interrupt Mask Register */
- #define REG_TWIHS0_RHR (*(__I uint32_t*)0x40018030U) /**< \brief (TWIHS0) Receive Holding Register */
- #define REG_TWIHS0_THR (*(__O uint32_t*)0x40018034U) /**< \brief (TWIHS0) Transmit Holding Register */
- #define REG_TWIHS0_SMBTR (*(__IO uint32_t*)0x40018038U) /**< \brief (TWIHS0) SMBus Timing Register */
- #define REG_TWIHS0_FILTR (*(__IO uint32_t*)0x40018044U) /**< \brief (TWIHS0) Filter Register */
- #define REG_TWIHS0_SWMR (*(__IO uint32_t*)0x4001804CU) /**< \brief (TWIHS0) SleepWalking Matching Register */
- #define REG_TWIHS0_WPMR (*(__IO uint32_t*)0x400180E4U) /**< \brief (TWIHS0) Write Protection Mode Register */
- #define REG_TWIHS0_WPSR (*(__I uint32_t*)0x400180E8U) /**< \brief (TWIHS0) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TWIHS0_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs1.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs1.h
deleted file mode 100644
index ca179cc..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs1.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TWIHS1_INSTANCE_
-#define _SAMS70_TWIHS1_INSTANCE_
-
-/* ========== Register definition for TWIHS1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TWIHS1_CR (0x4001C000U) /**< \brief (TWIHS1) Control Register */
- #define REG_TWIHS1_MMR (0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */
- #define REG_TWIHS1_SMR (0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */
- #define REG_TWIHS1_IADR (0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */
- #define REG_TWIHS1_CWGR (0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */
- #define REG_TWIHS1_SR (0x4001C020U) /**< \brief (TWIHS1) Status Register */
- #define REG_TWIHS1_IER (0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */
- #define REG_TWIHS1_IDR (0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */
- #define REG_TWIHS1_IMR (0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */
- #define REG_TWIHS1_RHR (0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */
- #define REG_TWIHS1_THR (0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */
- #define REG_TWIHS1_SMBTR (0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */
- #define REG_TWIHS1_FILTR (0x4001C044U) /**< \brief (TWIHS1) Filter Register */
- #define REG_TWIHS1_SWMR (0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */
- #define REG_TWIHS1_WPMR (0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */
- #define REG_TWIHS1_WPSR (0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */
-#else
- #define REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) /**< \brief (TWIHS1) Control Register */
- #define REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */
- #define REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */
- #define REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */
- #define REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */
- #define REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) /**< \brief (TWIHS1) Status Register */
- #define REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */
- #define REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */
- #define REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */
- #define REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */
- #define REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */
- #define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */
- #define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) /**< \brief (TWIHS1) Filter Register */
- #define REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */
- #define REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */
- #define REG_TWIHS1_WPSR (*(__I uint32_t*)0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TWIHS1_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs2.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs2.h
deleted file mode 100644
index d67cbf3..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs2.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TWIHS2_INSTANCE_
-#define _SAMS70_TWIHS2_INSTANCE_
-
-/* ========== Register definition for TWIHS2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TWIHS2_CR (0x40060000U) /**< \brief (TWIHS2) Control Register */
- #define REG_TWIHS2_MMR (0x40060004U) /**< \brief (TWIHS2) Master Mode Register */
- #define REG_TWIHS2_SMR (0x40060008U) /**< \brief (TWIHS2) Slave Mode Register */
- #define REG_TWIHS2_IADR (0x4006000CU) /**< \brief (TWIHS2) Internal Address Register */
- #define REG_TWIHS2_CWGR (0x40060010U) /**< \brief (TWIHS2) Clock Waveform Generator Register */
- #define REG_TWIHS2_SR (0x40060020U) /**< \brief (TWIHS2) Status Register */
- #define REG_TWIHS2_IER (0x40060024U) /**< \brief (TWIHS2) Interrupt Enable Register */
- #define REG_TWIHS2_IDR (0x40060028U) /**< \brief (TWIHS2) Interrupt Disable Register */
- #define REG_TWIHS2_IMR (0x4006002CU) /**< \brief (TWIHS2) Interrupt Mask Register */
- #define REG_TWIHS2_RHR (0x40060030U) /**< \brief (TWIHS2) Receive Holding Register */
- #define REG_TWIHS2_THR (0x40060034U) /**< \brief (TWIHS2) Transmit Holding Register */
- #define REG_TWIHS2_SMBTR (0x40060038U) /**< \brief (TWIHS2) SMBus Timing Register */
- #define REG_TWIHS2_FILTR (0x40060044U) /**< \brief (TWIHS2) Filter Register */
- #define REG_TWIHS2_SWMR (0x4006004CU) /**< \brief (TWIHS2) SleepWalking Matching Register */
- #define REG_TWIHS2_WPMR (0x400600E4U) /**< \brief (TWIHS2) Write Protection Mode Register */
- #define REG_TWIHS2_WPSR (0x400600E8U) /**< \brief (TWIHS2) Write Protection Status Register */
-#else
- #define REG_TWIHS2_CR (*(__O uint32_t*)0x40060000U) /**< \brief (TWIHS2) Control Register */
- #define REG_TWIHS2_MMR (*(__IO uint32_t*)0x40060004U) /**< \brief (TWIHS2) Master Mode Register */
- #define REG_TWIHS2_SMR (*(__IO uint32_t*)0x40060008U) /**< \brief (TWIHS2) Slave Mode Register */
- #define REG_TWIHS2_IADR (*(__IO uint32_t*)0x4006000CU) /**< \brief (TWIHS2) Internal Address Register */
- #define REG_TWIHS2_CWGR (*(__IO uint32_t*)0x40060010U) /**< \brief (TWIHS2) Clock Waveform Generator Register */
- #define REG_TWIHS2_SR (*(__I uint32_t*)0x40060020U) /**< \brief (TWIHS2) Status Register */
- #define REG_TWIHS2_IER (*(__O uint32_t*)0x40060024U) /**< \brief (TWIHS2) Interrupt Enable Register */
- #define REG_TWIHS2_IDR (*(__O uint32_t*)0x40060028U) /**< \brief (TWIHS2) Interrupt Disable Register */
- #define REG_TWIHS2_IMR (*(__I uint32_t*)0x4006002CU) /**< \brief (TWIHS2) Interrupt Mask Register */
- #define REG_TWIHS2_RHR (*(__I uint32_t*)0x40060030U) /**< \brief (TWIHS2) Receive Holding Register */
- #define REG_TWIHS2_THR (*(__O uint32_t*)0x40060034U) /**< \brief (TWIHS2) Transmit Holding Register */
- #define REG_TWIHS2_SMBTR (*(__IO uint32_t*)0x40060038U) /**< \brief (TWIHS2) SMBus Timing Register */
- #define REG_TWIHS2_FILTR (*(__IO uint32_t*)0x40060044U) /**< \brief (TWIHS2) Filter Register */
- #define REG_TWIHS2_SWMR (*(__IO uint32_t*)0x4006004CU) /**< \brief (TWIHS2) SleepWalking Matching Register */
- #define REG_TWIHS2_WPMR (*(__IO uint32_t*)0x400600E4U) /**< \brief (TWIHS2) Write Protection Mode Register */
- #define REG_TWIHS2_WPSR (*(__I uint32_t*)0x400600E8U) /**< \brief (TWIHS2) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TWIHS2_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart0.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart0.h
deleted file mode 100644
index f03845e..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart0.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UART0_INSTANCE_
-#define _SAMS70_UART0_INSTANCE_
-
-/* ========== Register definition for UART0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_UART0_CR (0x400E0800U) /**< \brief (UART0) Control Register */
- #define REG_UART0_MR (0x400E0804U) /**< \brief (UART0) Mode Register */
- #define REG_UART0_IER (0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */
- #define REG_UART0_IDR (0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */
- #define REG_UART0_IMR (0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */
- #define REG_UART0_SR (0x400E0814U) /**< \brief (UART0) Status Register */
- #define REG_UART0_RHR (0x400E0818U) /**< \brief (UART0) Receive Holding Register */
- #define REG_UART0_THR (0x400E081CU) /**< \brief (UART0) Transmit Holding Register */
- #define REG_UART0_BRGR (0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */
- #define REG_UART0_CMPR (0x400E0824U) /**< \brief (UART0) Comparison Register */
- #define REG_UART0_WPMR (0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */
-#else
- #define REG_UART0_CR (*(__O uint32_t*)0x400E0800U) /**< \brief (UART0) Control Register */
- #define REG_UART0_MR (*(__IO uint32_t*)0x400E0804U) /**< \brief (UART0) Mode Register */
- #define REG_UART0_IER (*(__O uint32_t*)0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */
- #define REG_UART0_IDR (*(__O uint32_t*)0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */
- #define REG_UART0_IMR (*(__I uint32_t*)0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */
- #define REG_UART0_SR (*(__I uint32_t*)0x400E0814U) /**< \brief (UART0) Status Register */
- #define REG_UART0_RHR (*(__I uint32_t*)0x400E0818U) /**< \brief (UART0) Receive Holding Register */
- #define REG_UART0_THR (*(__O uint32_t*)0x400E081CU) /**< \brief (UART0) Transmit Holding Register */
- #define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */
- #define REG_UART0_CMPR (*(__IO uint32_t*)0x400E0824U) /**< \brief (UART0) Comparison Register */
- #define REG_UART0_WPMR (*(__IO uint32_t*)0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_UART0_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart1.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart1.h
deleted file mode 100644
index f88ca7f..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart1.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UART1_INSTANCE_
-#define _SAMS70_UART1_INSTANCE_
-
-/* ========== Register definition for UART1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_UART1_CR (0x400E0A00U) /**< \brief (UART1) Control Register */
- #define REG_UART1_MR (0x400E0A04U) /**< \brief (UART1) Mode Register */
- #define REG_UART1_IER (0x400E0A08U) /**< \brief (UART1) Interrupt Enable Register */
- #define REG_UART1_IDR (0x400E0A0CU) /**< \brief (UART1) Interrupt Disable Register */
- #define REG_UART1_IMR (0x400E0A10U) /**< \brief (UART1) Interrupt Mask Register */
- #define REG_UART1_SR (0x400E0A14U) /**< \brief (UART1) Status Register */
- #define REG_UART1_RHR (0x400E0A18U) /**< \brief (UART1) Receive Holding Register */
- #define REG_UART1_THR (0x400E0A1CU) /**< \brief (UART1) Transmit Holding Register */
- #define REG_UART1_BRGR (0x400E0A20U) /**< \brief (UART1) Baud Rate Generator Register */
- #define REG_UART1_CMPR (0x400E0A24U) /**< \brief (UART1) Comparison Register */
- #define REG_UART1_WPMR (0x400E0AE4U) /**< \brief (UART1) Write Protection Mode Register */
-#else
- #define REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) /**< \brief (UART1) Control Register */
- #define REG_UART1_MR (*(__IO uint32_t*)0x400E0A04U) /**< \brief (UART1) Mode Register */
- #define REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) /**< \brief (UART1) Interrupt Enable Register */
- #define REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) /**< \brief (UART1) Interrupt Disable Register */
- #define REG_UART1_IMR (*(__I uint32_t*)0x400E0A10U) /**< \brief (UART1) Interrupt Mask Register */
- #define REG_UART1_SR (*(__I uint32_t*)0x400E0A14U) /**< \brief (UART1) Status Register */
- #define REG_UART1_RHR (*(__I uint32_t*)0x400E0A18U) /**< \brief (UART1) Receive Holding Register */
- #define REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) /**< \brief (UART1) Transmit Holding Register */
- #define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0A20U) /**< \brief (UART1) Baud Rate Generator Register */
- #define REG_UART1_CMPR (*(__IO uint32_t*)0x400E0A24U) /**< \brief (UART1) Comparison Register */
- #define REG_UART1_WPMR (*(__IO uint32_t*)0x400E0AE4U) /**< \brief (UART1) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_UART1_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart2.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart2.h
deleted file mode 100644
index 68d5c0e..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart2.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UART2_INSTANCE_
-#define _SAMS70_UART2_INSTANCE_
-
-/* ========== Register definition for UART2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_UART2_CR (0x400E1A00U) /**< \brief (UART2) Control Register */
- #define REG_UART2_MR (0x400E1A04U) /**< \brief (UART2) Mode Register */
- #define REG_UART2_IER (0x400E1A08U) /**< \brief (UART2) Interrupt Enable Register */
- #define REG_UART2_IDR (0x400E1A0CU) /**< \brief (UART2) Interrupt Disable Register */
- #define REG_UART2_IMR (0x400E1A10U) /**< \brief (UART2) Interrupt Mask Register */
- #define REG_UART2_SR (0x400E1A14U) /**< \brief (UART2) Status Register */
- #define REG_UART2_RHR (0x400E1A18U) /**< \brief (UART2) Receive Holding Register */
- #define REG_UART2_THR (0x400E1A1CU) /**< \brief (UART2) Transmit Holding Register */
- #define REG_UART2_BRGR (0x400E1A20U) /**< \brief (UART2) Baud Rate Generator Register */
- #define REG_UART2_CMPR (0x400E1A24U) /**< \brief (UART2) Comparison Register */
- #define REG_UART2_WPMR (0x400E1AE4U) /**< \brief (UART2) Write Protection Mode Register */
-#else
- #define REG_UART2_CR (*(__O uint32_t*)0x400E1A00U) /**< \brief (UART2) Control Register */
- #define REG_UART2_MR (*(__IO uint32_t*)0x400E1A04U) /**< \brief (UART2) Mode Register */
- #define REG_UART2_IER (*(__O uint32_t*)0x400E1A08U) /**< \brief (UART2) Interrupt Enable Register */
- #define REG_UART2_IDR (*(__O uint32_t*)0x400E1A0CU) /**< \brief (UART2) Interrupt Disable Register */
- #define REG_UART2_IMR (*(__I uint32_t*)0x400E1A10U) /**< \brief (UART2) Interrupt Mask Register */
- #define REG_UART2_SR (*(__I uint32_t*)0x400E1A14U) /**< \brief (UART2) Status Register */
- #define REG_UART2_RHR (*(__I uint32_t*)0x400E1A18U) /**< \brief (UART2) Receive Holding Register */
- #define REG_UART2_THR (*(__O uint32_t*)0x400E1A1CU) /**< \brief (UART2) Transmit Holding Register */
- #define REG_UART2_BRGR (*(__IO uint32_t*)0x400E1A20U) /**< \brief (UART2) Baud Rate Generator Register */
- #define REG_UART2_CMPR (*(__IO uint32_t*)0x400E1A24U) /**< \brief (UART2) Comparison Register */
- #define REG_UART2_WPMR (*(__IO uint32_t*)0x400E1AE4U) /**< \brief (UART2) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_UART2_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart3.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart3.h
deleted file mode 100644
index b519395..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart3.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UART3_INSTANCE_
-#define _SAMS70_UART3_INSTANCE_
-
-/* ========== Register definition for UART3 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_UART3_CR (0x400E1C00U) /**< \brief (UART3) Control Register */
- #define REG_UART3_MR (0x400E1C04U) /**< \brief (UART3) Mode Register */
- #define REG_UART3_IER (0x400E1C08U) /**< \brief (UART3) Interrupt Enable Register */
- #define REG_UART3_IDR (0x400E1C0CU) /**< \brief (UART3) Interrupt Disable Register */
- #define REG_UART3_IMR (0x400E1C10U) /**< \brief (UART3) Interrupt Mask Register */
- #define REG_UART3_SR (0x400E1C14U) /**< \brief (UART3) Status Register */
- #define REG_UART3_RHR (0x400E1C18U) /**< \brief (UART3) Receive Holding Register */
- #define REG_UART3_THR (0x400E1C1CU) /**< \brief (UART3) Transmit Holding Register */
- #define REG_UART3_BRGR (0x400E1C20U) /**< \brief (UART3) Baud Rate Generator Register */
- #define REG_UART3_CMPR (0x400E1C24U) /**< \brief (UART3) Comparison Register */
- #define REG_UART3_WPMR (0x400E1CE4U) /**< \brief (UART3) Write Protection Mode Register */
-#else
- #define REG_UART3_CR (*(__O uint32_t*)0x400E1C00U) /**< \brief (UART3) Control Register */
- #define REG_UART3_MR (*(__IO uint32_t*)0x400E1C04U) /**< \brief (UART3) Mode Register */
- #define REG_UART3_IER (*(__O uint32_t*)0x400E1C08U) /**< \brief (UART3) Interrupt Enable Register */
- #define REG_UART3_IDR (*(__O uint32_t*)0x400E1C0CU) /**< \brief (UART3) Interrupt Disable Register */
- #define REG_UART3_IMR (*(__I uint32_t*)0x400E1C10U) /**< \brief (UART3) Interrupt Mask Register */
- #define REG_UART3_SR (*(__I uint32_t*)0x400E1C14U) /**< \brief (UART3) Status Register */
- #define REG_UART3_RHR (*(__I uint32_t*)0x400E1C18U) /**< \brief (UART3) Receive Holding Register */
- #define REG_UART3_THR (*(__O uint32_t*)0x400E1C1CU) /**< \brief (UART3) Transmit Holding Register */
- #define REG_UART3_BRGR (*(__IO uint32_t*)0x400E1C20U) /**< \brief (UART3) Baud Rate Generator Register */
- #define REG_UART3_CMPR (*(__IO uint32_t*)0x400E1C24U) /**< \brief (UART3) Comparison Register */
- #define REG_UART3_WPMR (*(__IO uint32_t*)0x400E1CE4U) /**< \brief (UART3) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_UART3_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart4.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart4.h
deleted file mode 100644
index c96331c..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/uart4.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UART4_INSTANCE_
-#define _SAMS70_UART4_INSTANCE_
-
-/* ========== Register definition for UART4 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_UART4_CR (0x400E1E00U) /**< \brief (UART4) Control Register */
- #define REG_UART4_MR (0x400E1E04U) /**< \brief (UART4) Mode Register */
- #define REG_UART4_IER (0x400E1E08U) /**< \brief (UART4) Interrupt Enable Register */
- #define REG_UART4_IDR (0x400E1E0CU) /**< \brief (UART4) Interrupt Disable Register */
- #define REG_UART4_IMR (0x400E1E10U) /**< \brief (UART4) Interrupt Mask Register */
- #define REG_UART4_SR (0x400E1E14U) /**< \brief (UART4) Status Register */
- #define REG_UART4_RHR (0x400E1E18U) /**< \brief (UART4) Receive Holding Register */
- #define REG_UART4_THR (0x400E1E1CU) /**< \brief (UART4) Transmit Holding Register */
- #define REG_UART4_BRGR (0x400E1E20U) /**< \brief (UART4) Baud Rate Generator Register */
- #define REG_UART4_CMPR (0x400E1E24U) /**< \brief (UART4) Comparison Register */
- #define REG_UART4_WPMR (0x400E1EE4U) /**< \brief (UART4) Write Protection Mode Register */
-#else
- #define REG_UART4_CR (*(__O uint32_t*)0x400E1E00U) /**< \brief (UART4) Control Register */
- #define REG_UART4_MR (*(__IO uint32_t*)0x400E1E04U) /**< \brief (UART4) Mode Register */
- #define REG_UART4_IER (*(__O uint32_t*)0x400E1E08U) /**< \brief (UART4) Interrupt Enable Register */
- #define REG_UART4_IDR (*(__O uint32_t*)0x400E1E0CU) /**< \brief (UART4) Interrupt Disable Register */
- #define REG_UART4_IMR (*(__I uint32_t*)0x400E1E10U) /**< \brief (UART4) Interrupt Mask Register */
- #define REG_UART4_SR (*(__I uint32_t*)0x400E1E14U) /**< \brief (UART4) Status Register */
- #define REG_UART4_RHR (*(__I uint32_t*)0x400E1E18U) /**< \brief (UART4) Receive Holding Register */
- #define REG_UART4_THR (*(__O uint32_t*)0x400E1E1CU) /**< \brief (UART4) Transmit Holding Register */
- #define REG_UART4_BRGR (*(__IO uint32_t*)0x400E1E20U) /**< \brief (UART4) Baud Rate Generator Register */
- #define REG_UART4_CMPR (*(__IO uint32_t*)0x400E1E24U) /**< \brief (UART4) Comparison Register */
- #define REG_UART4_WPMR (*(__IO uint32_t*)0x400E1EE4U) /**< \brief (UART4) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_UART4_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/usart0.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/usart0.h
deleted file mode 100644
index 2715694..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/usart0.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_USART0_INSTANCE_
-#define _SAMS70_USART0_INSTANCE_
-
-/* ========== Register definition for USART0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */
- #define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */
- #define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
- #define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
- #define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
- #define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */
- #define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receive Holding Register */
- #define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmit Holding Register */
- #define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
- #define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
- #define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
- #define REG_USART0_MAN (0x40024050U) /**< \brief (USART0) Manchester Configuration Register */
- #define REG_USART0_LINMR (0x40024054U) /**< \brief (USART0) LIN Mode Register */
- #define REG_USART0_LINIR (0x40024058U) /**< \brief (USART0) LIN Identifier Register */
- #define REG_USART0_LINBRR (0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */
- #define REG_USART0_LONMR (0x40024060U) /**< \brief (USART0) LON Mode Register */
- #define REG_USART0_LONPR (0x40024064U) /**< \brief (USART0) LON Preamble Register */
- #define REG_USART0_LONDL (0x40024068U) /**< \brief (USART0) LON Data Length Register */
- #define REG_USART0_LONL2HDR (0x4002406CU) /**< \brief (USART0) LON L2HDR Register */
- #define REG_USART0_LONBL (0x40024070U) /**< \brief (USART0) LON Backlog Register */
- #define REG_USART0_LONB1TX (0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */
- #define REG_USART0_LONB1RX (0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */
- #define REG_USART0_LONPRIO (0x4002407CU) /**< \brief (USART0) LON Priority Register */
- #define REG_USART0_IDTTX (0x40024080U) /**< \brief (USART0) LON IDT Tx Register */
- #define REG_USART0_IDTRX (0x40024084U) /**< \brief (USART0) LON IDT Rx Register */
- #define REG_USART0_ICDIFF (0x40024088U) /**< \brief (USART0) IC DIFF Register */
- #define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */
- #define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protection Status Register */
-#else
- #define REG_USART0_CR (*(__O uint32_t*)0x40024000U) /**< \brief (USART0) Control Register */
- #define REG_USART0_MR (*(__IO uint32_t*)0x40024004U) /**< \brief (USART0) Mode Register */
- #define REG_USART0_IER (*(__O uint32_t*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
- #define REG_USART0_IDR (*(__O uint32_t*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
- #define REG_USART0_IMR (*(__I uint32_t*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
- #define REG_USART0_CSR (*(__I uint32_t*)0x40024014U) /**< \brief (USART0) Channel Status Register */
- #define REG_USART0_RHR (*(__I uint32_t*)0x40024018U) /**< \brief (USART0) Receive Holding Register */
- #define REG_USART0_THR (*(__O uint32_t*)0x4002401CU) /**< \brief (USART0) Transmit Holding Register */
- #define REG_USART0_BRGR (*(__IO uint32_t*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
- #define REG_USART0_RTOR (*(__IO uint32_t*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
- #define REG_USART0_TTGR (*(__IO uint32_t*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
- #define REG_USART0_MAN (*(__IO uint32_t*)0x40024050U) /**< \brief (USART0) Manchester Configuration Register */
- #define REG_USART0_LINMR (*(__IO uint32_t*)0x40024054U) /**< \brief (USART0) LIN Mode Register */
- #define REG_USART0_LINIR (*(__IO uint32_t*)0x40024058U) /**< \brief (USART0) LIN Identifier Register */
- #define REG_USART0_LINBRR (*(__I uint32_t*)0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */
- #define REG_USART0_LONMR (*(__IO uint32_t*)0x40024060U) /**< \brief (USART0) LON Mode Register */
- #define REG_USART0_LONPR (*(__IO uint32_t*)0x40024064U) /**< \brief (USART0) LON Preamble Register */
- #define REG_USART0_LONDL (*(__IO uint32_t*)0x40024068U) /**< \brief (USART0) LON Data Length Register */
- #define REG_USART0_LONL2HDR (*(__IO uint32_t*)0x4002406CU) /**< \brief (USART0) LON L2HDR Register */
- #define REG_USART0_LONBL (*(__I uint32_t*)0x40024070U) /**< \brief (USART0) LON Backlog Register */
- #define REG_USART0_LONB1TX (*(__IO uint32_t*)0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */
- #define REG_USART0_LONB1RX (*(__IO uint32_t*)0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */
- #define REG_USART0_LONPRIO (*(__IO uint32_t*)0x4002407CU) /**< \brief (USART0) LON Priority Register */
- #define REG_USART0_IDTTX (*(__IO uint32_t*)0x40024080U) /**< \brief (USART0) LON IDT Tx Register */
- #define REG_USART0_IDTRX (*(__IO uint32_t*)0x40024084U) /**< \brief (USART0) LON IDT Rx Register */
- #define REG_USART0_ICDIFF (*(__IO uint32_t*)0x40024088U) /**< \brief (USART0) IC DIFF Register */
- #define REG_USART0_WPMR (*(__IO uint32_t*)0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */
- #define REG_USART0_WPSR (*(__I uint32_t*)0x400240E8U) /**< \brief (USART0) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_USART0_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/usart1.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/usart1.h
deleted file mode 100644
index 067f32e..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/usart1.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_USART1_INSTANCE_
-#define _SAMS70_USART1_INSTANCE_
-
-/* ========== Register definition for USART1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_USART1_CR (0x40028000U) /**< \brief (USART1) Control Register */
- #define REG_USART1_MR (0x40028004U) /**< \brief (USART1) Mode Register */
- #define REG_USART1_IER (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
- #define REG_USART1_IDR (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
- #define REG_USART1_IMR (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
- #define REG_USART1_CSR (0x40028014U) /**< \brief (USART1) Channel Status Register */
- #define REG_USART1_RHR (0x40028018U) /**< \brief (USART1) Receive Holding Register */
- #define REG_USART1_THR (0x4002801CU) /**< \brief (USART1) Transmit Holding Register */
- #define REG_USART1_BRGR (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
- #define REG_USART1_RTOR (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
- #define REG_USART1_TTGR (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
- #define REG_USART1_MAN (0x40028050U) /**< \brief (USART1) Manchester Configuration Register */
- #define REG_USART1_LINMR (0x40028054U) /**< \brief (USART1) LIN Mode Register */
- #define REG_USART1_LINIR (0x40028058U) /**< \brief (USART1) LIN Identifier Register */
- #define REG_USART1_LINBRR (0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */
- #define REG_USART1_LONMR (0x40028060U) /**< \brief (USART1) LON Mode Register */
- #define REG_USART1_LONPR (0x40028064U) /**< \brief (USART1) LON Preamble Register */
- #define REG_USART1_LONDL (0x40028068U) /**< \brief (USART1) LON Data Length Register */
- #define REG_USART1_LONL2HDR (0x4002806CU) /**< \brief (USART1) LON L2HDR Register */
- #define REG_USART1_LONBL (0x40028070U) /**< \brief (USART1) LON Backlog Register */
- #define REG_USART1_LONB1TX (0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */
- #define REG_USART1_LONB1RX (0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */
- #define REG_USART1_LONPRIO (0x4002807CU) /**< \brief (USART1) LON Priority Register */
- #define REG_USART1_IDTTX (0x40028080U) /**< \brief (USART1) LON IDT Tx Register */
- #define REG_USART1_IDTRX (0x40028084U) /**< \brief (USART1) LON IDT Rx Register */
- #define REG_USART1_ICDIFF (0x40028088U) /**< \brief (USART1) IC DIFF Register */
- #define REG_USART1_WPMR (0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */
- #define REG_USART1_WPSR (0x400280E8U) /**< \brief (USART1) Write Protection Status Register */
-#else
- #define REG_USART1_CR (*(__O uint32_t*)0x40028000U) /**< \brief (USART1) Control Register */
- #define REG_USART1_MR (*(__IO uint32_t*)0x40028004U) /**< \brief (USART1) Mode Register */
- #define REG_USART1_IER (*(__O uint32_t*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
- #define REG_USART1_IDR (*(__O uint32_t*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
- #define REG_USART1_IMR (*(__I uint32_t*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
- #define REG_USART1_CSR (*(__I uint32_t*)0x40028014U) /**< \brief (USART1) Channel Status Register */
- #define REG_USART1_RHR (*(__I uint32_t*)0x40028018U) /**< \brief (USART1) Receive Holding Register */
- #define REG_USART1_THR (*(__O uint32_t*)0x4002801CU) /**< \brief (USART1) Transmit Holding Register */
- #define REG_USART1_BRGR (*(__IO uint32_t*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
- #define REG_USART1_RTOR (*(__IO uint32_t*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
- #define REG_USART1_TTGR (*(__IO uint32_t*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
- #define REG_USART1_MAN (*(__IO uint32_t*)0x40028050U) /**< \brief (USART1) Manchester Configuration Register */
- #define REG_USART1_LINMR (*(__IO uint32_t*)0x40028054U) /**< \brief (USART1) LIN Mode Register */
- #define REG_USART1_LINIR (*(__IO uint32_t*)0x40028058U) /**< \brief (USART1) LIN Identifier Register */
- #define REG_USART1_LINBRR (*(__I uint32_t*)0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */
- #define REG_USART1_LONMR (*(__IO uint32_t*)0x40028060U) /**< \brief (USART1) LON Mode Register */
- #define REG_USART1_LONPR (*(__IO uint32_t*)0x40028064U) /**< \brief (USART1) LON Preamble Register */
- #define REG_USART1_LONDL (*(__IO uint32_t*)0x40028068U) /**< \brief (USART1) LON Data Length Register */
- #define REG_USART1_LONL2HDR (*(__IO uint32_t*)0x4002806CU) /**< \brief (USART1) LON L2HDR Register */
- #define REG_USART1_LONBL (*(__I uint32_t*)0x40028070U) /**< \brief (USART1) LON Backlog Register */
- #define REG_USART1_LONB1TX (*(__IO uint32_t*)0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */
- #define REG_USART1_LONB1RX (*(__IO uint32_t*)0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */
- #define REG_USART1_LONPRIO (*(__IO uint32_t*)0x4002807CU) /**< \brief (USART1) LON Priority Register */
- #define REG_USART1_IDTTX (*(__IO uint32_t*)0x40028080U) /**< \brief (USART1) LON IDT Tx Register */
- #define REG_USART1_IDTRX (*(__IO uint32_t*)0x40028084U) /**< \brief (USART1) LON IDT Rx Register */
- #define REG_USART1_ICDIFF (*(__IO uint32_t*)0x40028088U) /**< \brief (USART1) IC DIFF Register */
- #define REG_USART1_WPMR (*(__IO uint32_t*)0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */
- #define REG_USART1_WPSR (*(__I uint32_t*)0x400280E8U) /**< \brief (USART1) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_USART1_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/usart2.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/usart2.h
deleted file mode 100644
index 88c8ce8..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/usart2.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_USART2_INSTANCE_
-#define _SAMS70_USART2_INSTANCE_
-
-/* ========== Register definition for USART2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_USART2_CR (0x4002C000U) /**< \brief (USART2) Control Register */
- #define REG_USART2_MR (0x4002C004U) /**< \brief (USART2) Mode Register */
- #define REG_USART2_IER (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
- #define REG_USART2_IDR (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
- #define REG_USART2_IMR (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
- #define REG_USART2_CSR (0x4002C014U) /**< \brief (USART2) Channel Status Register */
- #define REG_USART2_RHR (0x4002C018U) /**< \brief (USART2) Receive Holding Register */
- #define REG_USART2_THR (0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */
- #define REG_USART2_BRGR (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
- #define REG_USART2_RTOR (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
- #define REG_USART2_TTGR (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
- #define REG_USART2_MAN (0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */
- #define REG_USART2_LINMR (0x4002C054U) /**< \brief (USART2) LIN Mode Register */
- #define REG_USART2_LINIR (0x4002C058U) /**< \brief (USART2) LIN Identifier Register */
- #define REG_USART2_LINBRR (0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */
- #define REG_USART2_LONMR (0x4002C060U) /**< \brief (USART2) LON Mode Register */
- #define REG_USART2_LONPR (0x4002C064U) /**< \brief (USART2) LON Preamble Register */
- #define REG_USART2_LONDL (0x4002C068U) /**< \brief (USART2) LON Data Length Register */
- #define REG_USART2_LONL2HDR (0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */
- #define REG_USART2_LONBL (0x4002C070U) /**< \brief (USART2) LON Backlog Register */
- #define REG_USART2_LONB1TX (0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */
- #define REG_USART2_LONB1RX (0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */
- #define REG_USART2_LONPRIO (0x4002C07CU) /**< \brief (USART2) LON Priority Register */
- #define REG_USART2_IDTTX (0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */
- #define REG_USART2_IDTRX (0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */
- #define REG_USART2_ICDIFF (0x4002C088U) /**< \brief (USART2) IC DIFF Register */
- #define REG_USART2_WPMR (0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */
- #define REG_USART2_WPSR (0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */
-#else
- #define REG_USART2_CR (*(__O uint32_t*)0x4002C000U) /**< \brief (USART2) Control Register */
- #define REG_USART2_MR (*(__IO uint32_t*)0x4002C004U) /**< \brief (USART2) Mode Register */
- #define REG_USART2_IER (*(__O uint32_t*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
- #define REG_USART2_IDR (*(__O uint32_t*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
- #define REG_USART2_IMR (*(__I uint32_t*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
- #define REG_USART2_CSR (*(__I uint32_t*)0x4002C014U) /**< \brief (USART2) Channel Status Register */
- #define REG_USART2_RHR (*(__I uint32_t*)0x4002C018U) /**< \brief (USART2) Receive Holding Register */
- #define REG_USART2_THR (*(__O uint32_t*)0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */
- #define REG_USART2_BRGR (*(__IO uint32_t*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
- #define REG_USART2_RTOR (*(__IO uint32_t*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
- #define REG_USART2_TTGR (*(__IO uint32_t*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
- #define REG_USART2_MAN (*(__IO uint32_t*)0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */
- #define REG_USART2_LINMR (*(__IO uint32_t*)0x4002C054U) /**< \brief (USART2) LIN Mode Register */
- #define REG_USART2_LINIR (*(__IO uint32_t*)0x4002C058U) /**< \brief (USART2) LIN Identifier Register */
- #define REG_USART2_LINBRR (*(__I uint32_t*)0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */
- #define REG_USART2_LONMR (*(__IO uint32_t*)0x4002C060U) /**< \brief (USART2) LON Mode Register */
- #define REG_USART2_LONPR (*(__IO uint32_t*)0x4002C064U) /**< \brief (USART2) LON Preamble Register */
- #define REG_USART2_LONDL (*(__IO uint32_t*)0x4002C068U) /**< \brief (USART2) LON Data Length Register */
- #define REG_USART2_LONL2HDR (*(__IO uint32_t*)0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */
- #define REG_USART2_LONBL (*(__I uint32_t*)0x4002C070U) /**< \brief (USART2) LON Backlog Register */
- #define REG_USART2_LONB1TX (*(__IO uint32_t*)0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */
- #define REG_USART2_LONB1RX (*(__IO uint32_t*)0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */
- #define REG_USART2_LONPRIO (*(__IO uint32_t*)0x4002C07CU) /**< \brief (USART2) LON Priority Register */
- #define REG_USART2_IDTTX (*(__IO uint32_t*)0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */
- #define REG_USART2_IDTRX (*(__IO uint32_t*)0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */
- #define REG_USART2_ICDIFF (*(__IO uint32_t*)0x4002C088U) /**< \brief (USART2) IC DIFF Register */
- #define REG_USART2_WPMR (*(__IO uint32_t*)0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */
- #define REG_USART2_WPSR (*(__I uint32_t*)0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_USART2_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/usbhs.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/usbhs.h
deleted file mode 100644
index 39b7629..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/usbhs.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_USBHS_INSTANCE_
-#define _SAMS70_USBHS_INSTANCE_
-
-/* ========== Register definition for USBHS peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_USBHS_DEVCTRL (0x40038000U) /**< \brief (USBHS) Device General Control Register */
- #define REG_USBHS_DEVISR (0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */
- #define REG_USBHS_DEVICR (0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */
- #define REG_USBHS_DEVIFR (0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */
- #define REG_USBHS_DEVIMR (0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */
- #define REG_USBHS_DEVIDR (0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */
- #define REG_USBHS_DEVIER (0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */
- #define REG_USBHS_DEVEPT (0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */
- #define REG_USBHS_DEVFNUM (0x40038020U) /**< \brief (USBHS) Device Frame Number Register */
- #define REG_USBHS_DEVEPTCFG (0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */
- #define REG_USBHS_DEVEPTISR (0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */
- #define REG_USBHS_DEVEPTICR (0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */
- #define REG_USBHS_DEVEPTIFR (0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */
- #define REG_USBHS_DEVEPTIMR (0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */
- #define REG_USBHS_DEVEPTIER (0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */
- #define REG_USBHS_DEVEPTIDR (0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */
- #define REG_USBHS_DEVDMANXTDSC1 (0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */
- #define REG_USBHS_DEVDMAADDRESS1 (0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */
- #define REG_USBHS_DEVDMACONTROL1 (0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */
- #define REG_USBHS_DEVDMASTATUS1 (0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */
- #define REG_USBHS_DEVDMANXTDSC2 (0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */
- #define REG_USBHS_DEVDMAADDRESS2 (0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */
- #define REG_USBHS_DEVDMACONTROL2 (0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */
- #define REG_USBHS_DEVDMASTATUS2 (0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */
- #define REG_USBHS_DEVDMANXTDSC3 (0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */
- #define REG_USBHS_DEVDMAADDRESS3 (0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */
- #define REG_USBHS_DEVDMACONTROL3 (0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */
- #define REG_USBHS_DEVDMASTATUS3 (0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */
- #define REG_USBHS_DEVDMANXTDSC4 (0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */
- #define REG_USBHS_DEVDMAADDRESS4 (0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */
- #define REG_USBHS_DEVDMACONTROL4 (0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */
- #define REG_USBHS_DEVDMASTATUS4 (0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */
- #define REG_USBHS_DEVDMANXTDSC5 (0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */
- #define REG_USBHS_DEVDMAADDRESS5 (0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */
- #define REG_USBHS_DEVDMACONTROL5 (0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */
- #define REG_USBHS_DEVDMASTATUS5 (0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */
- #define REG_USBHS_DEVDMANXTDSC6 (0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */
- #define REG_USBHS_DEVDMAADDRESS6 (0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */
- #define REG_USBHS_DEVDMACONTROL6 (0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */
- #define REG_USBHS_DEVDMASTATUS6 (0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */
- #define REG_USBHS_DEVDMANXTDSC7 (0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */
- #define REG_USBHS_DEVDMAADDRESS7 (0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */
- #define REG_USBHS_DEVDMACONTROL7 (0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */
- #define REG_USBHS_DEVDMASTATUS7 (0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */
- #define REG_USBHS_HSTCTRL (0x40038400U) /**< \brief (USBHS) Host General Control Register */
- #define REG_USBHS_HSTISR (0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */
- #define REG_USBHS_HSTICR (0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */
- #define REG_USBHS_HSTIFR (0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */
- #define REG_USBHS_HSTIMR (0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */
- #define REG_USBHS_HSTIDR (0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */
- #define REG_USBHS_HSTIER (0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */
- #define REG_USBHS_HSTPIP (0x4003841CU) /**< \brief (USBHS) Host Pipe Register */
- #define REG_USBHS_HSTFNUM (0x40038420U) /**< \brief (USBHS) Host Frame Number Register */
- #define REG_USBHS_HSTADDR1 (0x40038424U) /**< \brief (USBHS) Host Address 1 Register */
- #define REG_USBHS_HSTADDR2 (0x40038428U) /**< \brief (USBHS) Host Address 2 Register */
- #define REG_USBHS_HSTADDR3 (0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */
- #define REG_USBHS_HSTPIPCFG (0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */
- #define REG_USBHS_HSTPIPISR (0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */
- #define REG_USBHS_HSTPIPICR (0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */
- #define REG_USBHS_HSTPIPIFR (0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */
- #define REG_USBHS_HSTPIPIMR (0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */
- #define REG_USBHS_HSTPIPIER (0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */
- #define REG_USBHS_HSTPIPIDR (0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */
- #define REG_USBHS_HSTPIPINRQ (0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */
- #define REG_USBHS_HSTPIPERR (0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */
- #define REG_USBHS_HSTDMANXTDSC1 (0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */
- #define REG_USBHS_HSTDMAADDRESS1 (0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */
- #define REG_USBHS_HSTDMACONTROL1 (0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */
- #define REG_USBHS_HSTDMASTATUS1 (0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */
- #define REG_USBHS_HSTDMANXTDSC2 (0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */
- #define REG_USBHS_HSTDMAADDRESS2 (0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */
- #define REG_USBHS_HSTDMACONTROL2 (0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */
- #define REG_USBHS_HSTDMASTATUS2 (0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */
- #define REG_USBHS_HSTDMANXTDSC3 (0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */
- #define REG_USBHS_HSTDMAADDRESS3 (0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */
- #define REG_USBHS_HSTDMACONTROL3 (0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */
- #define REG_USBHS_HSTDMASTATUS3 (0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */
- #define REG_USBHS_HSTDMANXTDSC4 (0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */
- #define REG_USBHS_HSTDMAADDRESS4 (0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */
- #define REG_USBHS_HSTDMACONTROL4 (0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */
- #define REG_USBHS_HSTDMASTATUS4 (0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */
- #define REG_USBHS_HSTDMANXTDSC5 (0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */
- #define REG_USBHS_HSTDMAADDRESS5 (0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */
- #define REG_USBHS_HSTDMACONTROL5 (0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */
- #define REG_USBHS_HSTDMASTATUS5 (0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */
- #define REG_USBHS_HSTDMANXTDSC6 (0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */
- #define REG_USBHS_HSTDMAADDRESS6 (0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */
- #define REG_USBHS_HSTDMACONTROL6 (0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */
- #define REG_USBHS_HSTDMASTATUS6 (0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */
- #define REG_USBHS_HSTDMANXTDSC7 (0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */
- #define REG_USBHS_HSTDMAADDRESS7 (0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */
- #define REG_USBHS_HSTDMACONTROL7 (0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */
- #define REG_USBHS_HSTDMASTATUS7 (0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */
- #define REG_USBHS_CTRL (0x40038800U) /**< \brief (USBHS) General Control Register */
- #define REG_USBHS_SR (0x40038804U) /**< \brief (USBHS) General Status Register */
- #define REG_USBHS_SCR (0x40038808U) /**< \brief (USBHS) General Status Clear Register */
- #define REG_USBHS_SFR (0x4003880CU) /**< \brief (USBHS) General Status Set Register */
- #define REG_USBHS_TSTA1 (0x40038810U) /**< \brief (USBHS) General Test A1 Register */
- #define REG_USBHS_TSTA2 (0x40038814U) /**< \brief (USBHS) General Test A2 Register */
- #define REG_USBHS_VERSION (0x40038818U) /**< \brief (USBHS) General Version Register */
- #define REG_USBHS_FSM (0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */
-#else
- #define REG_USBHS_DEVCTRL (*(__IO uint32_t*)0x40038000U) /**< \brief (USBHS) Device General Control Register */
- #define REG_USBHS_DEVISR (*(__I uint32_t*)0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */
- #define REG_USBHS_DEVICR (*(__O uint32_t*)0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */
- #define REG_USBHS_DEVIFR (*(__O uint32_t*)0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */
- #define REG_USBHS_DEVIMR (*(__I uint32_t*)0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */
- #define REG_USBHS_DEVIDR (*(__O uint32_t*)0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */
- #define REG_USBHS_DEVIER (*(__O uint32_t*)0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */
- #define REG_USBHS_DEVEPT (*(__IO uint32_t*)0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */
- #define REG_USBHS_DEVFNUM (*(__I uint32_t*)0x40038020U) /**< \brief (USBHS) Device Frame Number Register */
- #define REG_USBHS_DEVEPTCFG (*(__IO uint32_t*)0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */
- #define REG_USBHS_DEVEPTISR (*(__I uint32_t*)0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */
- #define REG_USBHS_DEVEPTICR (*(__O uint32_t*)0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */
- #define REG_USBHS_DEVEPTIFR (*(__O uint32_t*)0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */
- #define REG_USBHS_DEVEPTIMR (*(__I uint32_t*)0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */
- #define REG_USBHS_DEVEPTIER (*(__O uint32_t*)0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */
- #define REG_USBHS_DEVEPTIDR (*(__O uint32_t*)0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */
- #define REG_USBHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */
- #define REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */
- #define REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */
- #define REG_USBHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */
- #define REG_USBHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */
- #define REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */
- #define REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */
- #define REG_USBHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */
- #define REG_USBHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */
- #define REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */
- #define REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */
- #define REG_USBHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */
- #define REG_USBHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */
- #define REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */
- #define REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */
- #define REG_USBHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */
- #define REG_USBHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */
- #define REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */
- #define REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */
- #define REG_USBHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */
- #define REG_USBHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */
- #define REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */
- #define REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */
- #define REG_USBHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */
- #define REG_USBHS_DEVDMANXTDSC7 (*(__IO uint32_t*)0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */
- #define REG_USBHS_DEVDMAADDRESS7 (*(__IO uint32_t*)0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */
- #define REG_USBHS_DEVDMACONTROL7 (*(__IO uint32_t*)0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */
- #define REG_USBHS_DEVDMASTATUS7 (*(__IO uint32_t*)0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */
- #define REG_USBHS_HSTCTRL (*(__IO uint32_t*)0x40038400U) /**< \brief (USBHS) Host General Control Register */
- #define REG_USBHS_HSTISR (*(__I uint32_t*)0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */
- #define REG_USBHS_HSTICR (*(__O uint32_t*)0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */
- #define REG_USBHS_HSTIFR (*(__O uint32_t*)0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */
- #define REG_USBHS_HSTIMR (*(__I uint32_t*)0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */
- #define REG_USBHS_HSTIDR (*(__O uint32_t*)0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */
- #define REG_USBHS_HSTIER (*(__O uint32_t*)0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */
- #define REG_USBHS_HSTPIP (*(__IO uint32_t*)0x4003841CU) /**< \brief (USBHS) Host Pipe Register */
- #define REG_USBHS_HSTFNUM (*(__IO uint32_t*)0x40038420U) /**< \brief (USBHS) Host Frame Number Register */
- #define REG_USBHS_HSTADDR1 (*(__IO uint32_t*)0x40038424U) /**< \brief (USBHS) Host Address 1 Register */
- #define REG_USBHS_HSTADDR2 (*(__IO uint32_t*)0x40038428U) /**< \brief (USBHS) Host Address 2 Register */
- #define REG_USBHS_HSTADDR3 (*(__IO uint32_t*)0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */
- #define REG_USBHS_HSTPIPCFG (*(__IO uint32_t*)0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */
- #define REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */
- #define REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */
- #define REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */
- #define REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */
- #define REG_USBHS_HSTPIPIER (*(__O uint32_t*)0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */
- #define REG_USBHS_HSTPIPIDR (*(__O uint32_t*)0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */
- #define REG_USBHS_HSTPIPINRQ (*(__IO uint32_t*)0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */
- #define REG_USBHS_HSTPIPERR (*(__IO uint32_t*)0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */
- #define REG_USBHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */
- #define REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */
- #define REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */
- #define REG_USBHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */
- #define REG_USBHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */
- #define REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */
- #define REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */
- #define REG_USBHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */
- #define REG_USBHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */
- #define REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */
- #define REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */
- #define REG_USBHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */
- #define REG_USBHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */
- #define REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */
- #define REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */
- #define REG_USBHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */
- #define REG_USBHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */
- #define REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */
- #define REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */
- #define REG_USBHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */
- #define REG_USBHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */
- #define REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */
- #define REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */
- #define REG_USBHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */
- #define REG_USBHS_HSTDMANXTDSC7 (*(__IO uint32_t*)0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */
- #define REG_USBHS_HSTDMAADDRESS7 (*(__IO uint32_t*)0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */
- #define REG_USBHS_HSTDMACONTROL7 (*(__IO uint32_t*)0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */
- #define REG_USBHS_HSTDMASTATUS7 (*(__IO uint32_t*)0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */
- #define REG_USBHS_CTRL (*(__IO uint32_t*)0x40038800U) /**< \brief (USBHS) General Control Register */
- #define REG_USBHS_SR (*(__I uint32_t*)0x40038804U) /**< \brief (USBHS) General Status Register */
- #define REG_USBHS_SCR (*(__O uint32_t*)0x40038808U) /**< \brief (USBHS) General Status Clear Register */
- #define REG_USBHS_SFR (*(__O uint32_t*)0x4003880CU) /**< \brief (USBHS) General Status Set Register */
- #define REG_USBHS_TSTA1 (*(__IO uint32_t*)0x40038810U) /**< \brief (USBHS) General Test A1 Register */
- #define REG_USBHS_TSTA2 (*(__IO uint32_t*)0x40038814U) /**< \brief (USBHS) General Test A2 Register */
- #define REG_USBHS_VERSION (*(__I uint32_t*)0x40038818U) /**< \brief (USBHS) General Version Register */
- #define REG_USBHS_FSM (*(__I uint32_t*)0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_USBHS_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/utmi.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/utmi.h
deleted file mode 100644
index daf3766..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/utmi.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UTMI_INSTANCE_
-#define _SAMS70_UTMI_INSTANCE_
-
-/* ========== Register definition for UTMI peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_UTMI_OHCIICR (0x400E0410U) /**< \brief (UTMI) OHCI Interrupt Configuration Register */
- #define REG_UTMI_CKTRIM (0x400E0430U) /**< \brief (UTMI) UTMI Clock Trimming Register */
-#else
- #define REG_UTMI_OHCIICR (*(__IO uint32_t*)0x400E0410U) /**< \brief (UTMI) OHCI Interrupt Configuration Register */
- #define REG_UTMI_CKTRIM (*(__IO uint32_t*)0x400E0430U) /**< \brief (UTMI) UTMI Clock Trimming Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_UTMI_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/wdt.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/wdt.h
deleted file mode 100644
index 963c644..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/wdt.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_WDT_INSTANCE_
-#define _SAMS70_WDT_INSTANCE_
-
-/* ========== Register definition for WDT peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_WDT_CR (0x400E1850U) /**< \brief (WDT) Control Register */
- #define REG_WDT_MR (0x400E1854U) /**< \brief (WDT) Mode Register */
- #define REG_WDT_SR (0x400E1858U) /**< \brief (WDT) Status Register */
-#else
- #define REG_WDT_CR (*(__O uint32_t*)0x400E1850U) /**< \brief (WDT) Control Register */
- #define REG_WDT_MR (*(__IO uint32_t*)0x400E1854U) /**< \brief (WDT) Mode Register */
- #define REG_WDT_SR (*(__I uint32_t*)0x400E1858U) /**< \brief (WDT) Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_WDT_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/xdmac.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/xdmac.h
deleted file mode 100644
index b6a043b..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/instance/xdmac.h
+++ /dev/null
@@ -1,759 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_XDMAC_INSTANCE_
-#define _SAMS70_XDMAC_INSTANCE_
-
-/* ========== Register definition for XDMAC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_XDMAC_GTYPE (0x40078000U) /**< \brief (XDMAC) Global Type Register */
- #define REG_XDMAC_GCFG (0x40078004U) /**< \brief (XDMAC) Global Configuration Register */
- #define REG_XDMAC_GWAC (0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */
- #define REG_XDMAC_GIE (0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */
- #define REG_XDMAC_GID (0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */
- #define REG_XDMAC_GIM (0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */
- #define REG_XDMAC_GIS (0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */
- #define REG_XDMAC_GE (0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */
- #define REG_XDMAC_GD (0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */
- #define REG_XDMAC_GS (0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */
- #define REG_XDMAC_GRS (0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */
- #define REG_XDMAC_GWS (0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */
- #define REG_XDMAC_GRWS (0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */
- #define REG_XDMAC_GRWR (0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */
- #define REG_XDMAC_GSWR (0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */
- #define REG_XDMAC_GSWS (0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */
- #define REG_XDMAC_GSWF (0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */
- #define REG_XDMAC_CIE0 (0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */
- #define REG_XDMAC_CID0 (0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */
- #define REG_XDMAC_CIM0 (0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */
- #define REG_XDMAC_CIS0 (0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */
- #define REG_XDMAC_CSA0 (0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */
- #define REG_XDMAC_CDA0 (0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */
- #define REG_XDMAC_CNDA0 (0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */
- #define REG_XDMAC_CNDC0 (0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */
- #define REG_XDMAC_CUBC0 (0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */
- #define REG_XDMAC_CBC0 (0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */
- #define REG_XDMAC_CC0 (0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */
- #define REG_XDMAC_CDS_MSP0 (0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */
- #define REG_XDMAC_CSUS0 (0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */
- #define REG_XDMAC_CDUS0 (0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */
- #define REG_XDMAC_CIE1 (0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */
- #define REG_XDMAC_CID1 (0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */
- #define REG_XDMAC_CIM1 (0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */
- #define REG_XDMAC_CIS1 (0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */
- #define REG_XDMAC_CSA1 (0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */
- #define REG_XDMAC_CDA1 (0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */
- #define REG_XDMAC_CNDA1 (0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */
- #define REG_XDMAC_CNDC1 (0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */
- #define REG_XDMAC_CUBC1 (0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */
- #define REG_XDMAC_CBC1 (0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */
- #define REG_XDMAC_CC1 (0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */
- #define REG_XDMAC_CDS_MSP1 (0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */
- #define REG_XDMAC_CSUS1 (0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */
- #define REG_XDMAC_CDUS1 (0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */
- #define REG_XDMAC_CIE2 (0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */
- #define REG_XDMAC_CID2 (0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */
- #define REG_XDMAC_CIM2 (0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */
- #define REG_XDMAC_CIS2 (0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */
- #define REG_XDMAC_CSA2 (0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */
- #define REG_XDMAC_CDA2 (0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */
- #define REG_XDMAC_CNDA2 (0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */
- #define REG_XDMAC_CNDC2 (0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */
- #define REG_XDMAC_CUBC2 (0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */
- #define REG_XDMAC_CBC2 (0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */
- #define REG_XDMAC_CC2 (0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */
- #define REG_XDMAC_CDS_MSP2 (0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */
- #define REG_XDMAC_CSUS2 (0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */
- #define REG_XDMAC_CDUS2 (0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */
- #define REG_XDMAC_CIE3 (0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */
- #define REG_XDMAC_CID3 (0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */
- #define REG_XDMAC_CIM3 (0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */
- #define REG_XDMAC_CIS3 (0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */
- #define REG_XDMAC_CSA3 (0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */
- #define REG_XDMAC_CDA3 (0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */
- #define REG_XDMAC_CNDA3 (0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */
- #define REG_XDMAC_CNDC3 (0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */
- #define REG_XDMAC_CUBC3 (0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */
- #define REG_XDMAC_CBC3 (0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */
- #define REG_XDMAC_CC3 (0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */
- #define REG_XDMAC_CDS_MSP3 (0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */
- #define REG_XDMAC_CSUS3 (0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */
- #define REG_XDMAC_CDUS3 (0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */
- #define REG_XDMAC_CIE4 (0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */
- #define REG_XDMAC_CID4 (0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */
- #define REG_XDMAC_CIM4 (0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */
- #define REG_XDMAC_CIS4 (0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */
- #define REG_XDMAC_CSA4 (0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */
- #define REG_XDMAC_CDA4 (0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */
- #define REG_XDMAC_CNDA4 (0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */
- #define REG_XDMAC_CNDC4 (0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */
- #define REG_XDMAC_CUBC4 (0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */
- #define REG_XDMAC_CBC4 (0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */
- #define REG_XDMAC_CC4 (0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */
- #define REG_XDMAC_CDS_MSP4 (0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */
- #define REG_XDMAC_CSUS4 (0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */
- #define REG_XDMAC_CDUS4 (0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */
- #define REG_XDMAC_CIE5 (0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */
- #define REG_XDMAC_CID5 (0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */
- #define REG_XDMAC_CIM5 (0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */
- #define REG_XDMAC_CIS5 (0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */
- #define REG_XDMAC_CSA5 (0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */
- #define REG_XDMAC_CDA5 (0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */
- #define REG_XDMAC_CNDA5 (0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */
- #define REG_XDMAC_CNDC5 (0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */
- #define REG_XDMAC_CUBC5 (0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */
- #define REG_XDMAC_CBC5 (0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */
- #define REG_XDMAC_CC5 (0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */
- #define REG_XDMAC_CDS_MSP5 (0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */
- #define REG_XDMAC_CSUS5 (0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */
- #define REG_XDMAC_CDUS5 (0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */
- #define REG_XDMAC_CIE6 (0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */
- #define REG_XDMAC_CID6 (0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */
- #define REG_XDMAC_CIM6 (0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */
- #define REG_XDMAC_CIS6 (0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */
- #define REG_XDMAC_CSA6 (0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */
- #define REG_XDMAC_CDA6 (0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */
- #define REG_XDMAC_CNDA6 (0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */
- #define REG_XDMAC_CNDC6 (0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */
- #define REG_XDMAC_CUBC6 (0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */
- #define REG_XDMAC_CBC6 (0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */
- #define REG_XDMAC_CC6 (0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */
- #define REG_XDMAC_CDS_MSP6 (0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */
- #define REG_XDMAC_CSUS6 (0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */
- #define REG_XDMAC_CDUS6 (0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */
- #define REG_XDMAC_CIE7 (0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */
- #define REG_XDMAC_CID7 (0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */
- #define REG_XDMAC_CIM7 (0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */
- #define REG_XDMAC_CIS7 (0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */
- #define REG_XDMAC_CSA7 (0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */
- #define REG_XDMAC_CDA7 (0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */
- #define REG_XDMAC_CNDA7 (0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */
- #define REG_XDMAC_CNDC7 (0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */
- #define REG_XDMAC_CUBC7 (0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */
- #define REG_XDMAC_CBC7 (0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */
- #define REG_XDMAC_CC7 (0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */
- #define REG_XDMAC_CDS_MSP7 (0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */
- #define REG_XDMAC_CSUS7 (0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */
- #define REG_XDMAC_CDUS7 (0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */
- #define REG_XDMAC_CIE8 (0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */
- #define REG_XDMAC_CID8 (0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */
- #define REG_XDMAC_CIM8 (0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */
- #define REG_XDMAC_CIS8 (0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */
- #define REG_XDMAC_CSA8 (0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */
- #define REG_XDMAC_CDA8 (0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */
- #define REG_XDMAC_CNDA8 (0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */
- #define REG_XDMAC_CNDC8 (0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */
- #define REG_XDMAC_CUBC8 (0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */
- #define REG_XDMAC_CBC8 (0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */
- #define REG_XDMAC_CC8 (0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */
- #define REG_XDMAC_CDS_MSP8 (0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */
- #define REG_XDMAC_CSUS8 (0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */
- #define REG_XDMAC_CDUS8 (0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */
- #define REG_XDMAC_CIE9 (0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */
- #define REG_XDMAC_CID9 (0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */
- #define REG_XDMAC_CIM9 (0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */
- #define REG_XDMAC_CIS9 (0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */
- #define REG_XDMAC_CSA9 (0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */
- #define REG_XDMAC_CDA9 (0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */
- #define REG_XDMAC_CNDA9 (0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */
- #define REG_XDMAC_CNDC9 (0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */
- #define REG_XDMAC_CUBC9 (0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */
- #define REG_XDMAC_CBC9 (0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */
- #define REG_XDMAC_CC9 (0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */
- #define REG_XDMAC_CDS_MSP9 (0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */
- #define REG_XDMAC_CSUS9 (0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */
- #define REG_XDMAC_CDUS9 (0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */
- #define REG_XDMAC_CIE10 (0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */
- #define REG_XDMAC_CID10 (0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */
- #define REG_XDMAC_CIM10 (0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */
- #define REG_XDMAC_CIS10 (0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */
- #define REG_XDMAC_CSA10 (0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */
- #define REG_XDMAC_CDA10 (0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */
- #define REG_XDMAC_CNDA10 (0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */
- #define REG_XDMAC_CNDC10 (0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */
- #define REG_XDMAC_CUBC10 (0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */
- #define REG_XDMAC_CBC10 (0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */
- #define REG_XDMAC_CC10 (0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */
- #define REG_XDMAC_CDS_MSP10 (0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */
- #define REG_XDMAC_CSUS10 (0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */
- #define REG_XDMAC_CDUS10 (0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */
- #define REG_XDMAC_CIE11 (0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */
- #define REG_XDMAC_CID11 (0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */
- #define REG_XDMAC_CIM11 (0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */
- #define REG_XDMAC_CIS11 (0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */
- #define REG_XDMAC_CSA11 (0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */
- #define REG_XDMAC_CDA11 (0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */
- #define REG_XDMAC_CNDA11 (0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */
- #define REG_XDMAC_CNDC11 (0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */
- #define REG_XDMAC_CUBC11 (0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */
- #define REG_XDMAC_CBC11 (0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */
- #define REG_XDMAC_CC11 (0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */
- #define REG_XDMAC_CDS_MSP11 (0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */
- #define REG_XDMAC_CSUS11 (0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */
- #define REG_XDMAC_CDUS11 (0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */
- #define REG_XDMAC_CIE12 (0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */
- #define REG_XDMAC_CID12 (0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */
- #define REG_XDMAC_CIM12 (0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */
- #define REG_XDMAC_CIS12 (0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */
- #define REG_XDMAC_CSA12 (0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */
- #define REG_XDMAC_CDA12 (0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */
- #define REG_XDMAC_CNDA12 (0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */
- #define REG_XDMAC_CNDC12 (0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */
- #define REG_XDMAC_CUBC12 (0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */
- #define REG_XDMAC_CBC12 (0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */
- #define REG_XDMAC_CC12 (0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */
- #define REG_XDMAC_CDS_MSP12 (0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */
- #define REG_XDMAC_CSUS12 (0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */
- #define REG_XDMAC_CDUS12 (0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */
- #define REG_XDMAC_CIE13 (0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */
- #define REG_XDMAC_CID13 (0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */
- #define REG_XDMAC_CIM13 (0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */
- #define REG_XDMAC_CIS13 (0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */
- #define REG_XDMAC_CSA13 (0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */
- #define REG_XDMAC_CDA13 (0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */
- #define REG_XDMAC_CNDA13 (0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */
- #define REG_XDMAC_CNDC13 (0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */
- #define REG_XDMAC_CUBC13 (0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */
- #define REG_XDMAC_CBC13 (0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */
- #define REG_XDMAC_CC13 (0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */
- #define REG_XDMAC_CDS_MSP13 (0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */
- #define REG_XDMAC_CSUS13 (0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */
- #define REG_XDMAC_CDUS13 (0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */
- #define REG_XDMAC_CIE14 (0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */
- #define REG_XDMAC_CID14 (0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */
- #define REG_XDMAC_CIM14 (0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */
- #define REG_XDMAC_CIS14 (0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */
- #define REG_XDMAC_CSA14 (0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */
- #define REG_XDMAC_CDA14 (0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */
- #define REG_XDMAC_CNDA14 (0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */
- #define REG_XDMAC_CNDC14 (0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */
- #define REG_XDMAC_CUBC14 (0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */
- #define REG_XDMAC_CBC14 (0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */
- #define REG_XDMAC_CC14 (0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */
- #define REG_XDMAC_CDS_MSP14 (0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */
- #define REG_XDMAC_CSUS14 (0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */
- #define REG_XDMAC_CDUS14 (0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */
- #define REG_XDMAC_CIE15 (0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */
- #define REG_XDMAC_CID15 (0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */
- #define REG_XDMAC_CIM15 (0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */
- #define REG_XDMAC_CIS15 (0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */
- #define REG_XDMAC_CSA15 (0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */
- #define REG_XDMAC_CDA15 (0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */
- #define REG_XDMAC_CNDA15 (0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */
- #define REG_XDMAC_CNDC15 (0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */
- #define REG_XDMAC_CUBC15 (0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */
- #define REG_XDMAC_CBC15 (0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */
- #define REG_XDMAC_CC15 (0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */
- #define REG_XDMAC_CDS_MSP15 (0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */
- #define REG_XDMAC_CSUS15 (0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */
- #define REG_XDMAC_CDUS15 (0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */
- #define REG_XDMAC_CIE16 (0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */
- #define REG_XDMAC_CID16 (0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */
- #define REG_XDMAC_CIM16 (0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */
- #define REG_XDMAC_CIS16 (0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */
- #define REG_XDMAC_CSA16 (0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */
- #define REG_XDMAC_CDA16 (0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */
- #define REG_XDMAC_CNDA16 (0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */
- #define REG_XDMAC_CNDC16 (0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */
- #define REG_XDMAC_CUBC16 (0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */
- #define REG_XDMAC_CBC16 (0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */
- #define REG_XDMAC_CC16 (0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */
- #define REG_XDMAC_CDS_MSP16 (0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */
- #define REG_XDMAC_CSUS16 (0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */
- #define REG_XDMAC_CDUS16 (0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */
- #define REG_XDMAC_CIE17 (0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */
- #define REG_XDMAC_CID17 (0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */
- #define REG_XDMAC_CIM17 (0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */
- #define REG_XDMAC_CIS17 (0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */
- #define REG_XDMAC_CSA17 (0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */
- #define REG_XDMAC_CDA17 (0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */
- #define REG_XDMAC_CNDA17 (0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */
- #define REG_XDMAC_CNDC17 (0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */
- #define REG_XDMAC_CUBC17 (0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */
- #define REG_XDMAC_CBC17 (0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */
- #define REG_XDMAC_CC17 (0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */
- #define REG_XDMAC_CDS_MSP17 (0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */
- #define REG_XDMAC_CSUS17 (0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */
- #define REG_XDMAC_CDUS17 (0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */
- #define REG_XDMAC_CIE18 (0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */
- #define REG_XDMAC_CID18 (0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */
- #define REG_XDMAC_CIM18 (0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */
- #define REG_XDMAC_CIS18 (0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */
- #define REG_XDMAC_CSA18 (0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */
- #define REG_XDMAC_CDA18 (0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */
- #define REG_XDMAC_CNDA18 (0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */
- #define REG_XDMAC_CNDC18 (0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */
- #define REG_XDMAC_CUBC18 (0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */
- #define REG_XDMAC_CBC18 (0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */
- #define REG_XDMAC_CC18 (0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */
- #define REG_XDMAC_CDS_MSP18 (0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */
- #define REG_XDMAC_CSUS18 (0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */
- #define REG_XDMAC_CDUS18 (0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */
- #define REG_XDMAC_CIE19 (0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */
- #define REG_XDMAC_CID19 (0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */
- #define REG_XDMAC_CIM19 (0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */
- #define REG_XDMAC_CIS19 (0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */
- #define REG_XDMAC_CSA19 (0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */
- #define REG_XDMAC_CDA19 (0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */
- #define REG_XDMAC_CNDA19 (0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */
- #define REG_XDMAC_CNDC19 (0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */
- #define REG_XDMAC_CUBC19 (0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */
- #define REG_XDMAC_CBC19 (0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */
- #define REG_XDMAC_CC19 (0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */
- #define REG_XDMAC_CDS_MSP19 (0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */
- #define REG_XDMAC_CSUS19 (0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */
- #define REG_XDMAC_CDUS19 (0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */
- #define REG_XDMAC_CIE20 (0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */
- #define REG_XDMAC_CID20 (0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */
- #define REG_XDMAC_CIM20 (0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */
- #define REG_XDMAC_CIS20 (0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */
- #define REG_XDMAC_CSA20 (0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */
- #define REG_XDMAC_CDA20 (0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */
- #define REG_XDMAC_CNDA20 (0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */
- #define REG_XDMAC_CNDC20 (0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */
- #define REG_XDMAC_CUBC20 (0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */
- #define REG_XDMAC_CBC20 (0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */
- #define REG_XDMAC_CC20 (0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */
- #define REG_XDMAC_CDS_MSP20 (0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */
- #define REG_XDMAC_CSUS20 (0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */
- #define REG_XDMAC_CDUS20 (0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */
- #define REG_XDMAC_CIE21 (0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */
- #define REG_XDMAC_CID21 (0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */
- #define REG_XDMAC_CIM21 (0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */
- #define REG_XDMAC_CIS21 (0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */
- #define REG_XDMAC_CSA21 (0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */
- #define REG_XDMAC_CDA21 (0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */
- #define REG_XDMAC_CNDA21 (0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */
- #define REG_XDMAC_CNDC21 (0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */
- #define REG_XDMAC_CUBC21 (0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */
- #define REG_XDMAC_CBC21 (0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */
- #define REG_XDMAC_CC21 (0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */
- #define REG_XDMAC_CDS_MSP21 (0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */
- #define REG_XDMAC_CSUS21 (0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */
- #define REG_XDMAC_CDUS21 (0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */
- #define REG_XDMAC_CIE22 (0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */
- #define REG_XDMAC_CID22 (0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */
- #define REG_XDMAC_CIM22 (0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */
- #define REG_XDMAC_CIS22 (0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */
- #define REG_XDMAC_CSA22 (0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */
- #define REG_XDMAC_CDA22 (0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */
- #define REG_XDMAC_CNDA22 (0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */
- #define REG_XDMAC_CNDC22 (0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */
- #define REG_XDMAC_CUBC22 (0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */
- #define REG_XDMAC_CBC22 (0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */
- #define REG_XDMAC_CC22 (0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */
- #define REG_XDMAC_CDS_MSP22 (0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */
- #define REG_XDMAC_CSUS22 (0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */
- #define REG_XDMAC_CDUS22 (0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */
- #define REG_XDMAC_CIE23 (0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */
- #define REG_XDMAC_CID23 (0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */
- #define REG_XDMAC_CIM23 (0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */
- #define REG_XDMAC_CIS23 (0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */
- #define REG_XDMAC_CSA23 (0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */
- #define REG_XDMAC_CDA23 (0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */
- #define REG_XDMAC_CNDA23 (0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */
- #define REG_XDMAC_CNDC23 (0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */
- #define REG_XDMAC_CUBC23 (0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */
- #define REG_XDMAC_CBC23 (0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */
- #define REG_XDMAC_CC23 (0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */
- #define REG_XDMAC_CDS_MSP23 (0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */
- #define REG_XDMAC_CSUS23 (0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */
- #define REG_XDMAC_CDUS23 (0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */
-#else
- #define REG_XDMAC_GTYPE (*(__IO uint32_t*)0x40078000U) /**< \brief (XDMAC) Global Type Register */
- #define REG_XDMAC_GCFG (*(__I uint32_t*)0x40078004U) /**< \brief (XDMAC) Global Configuration Register */
- #define REG_XDMAC_GWAC (*(__IO uint32_t*)0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */
- #define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */
- #define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */
- #define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */
- #define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */
- #define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */
- #define REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */
- #define REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */
- #define REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */
- #define REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */
- #define REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */
- #define REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */
- #define REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */
- #define REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */
- #define REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */
- #define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */
- #define REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */
- #define REG_XDMAC_CIM0 (*(__O uint32_t*)0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */
- #define REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */
- #define REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */
- #define REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */
- #define REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */
- #define REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */
- #define REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */
- #define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */
- #define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */
- #define REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */
- #define REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */
- #define REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */
- #define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */
- #define REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */
- #define REG_XDMAC_CIM1 (*(__O uint32_t*)0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */
- #define REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */
- #define REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */
- #define REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */
- #define REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */
- #define REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */
- #define REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */
- #define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */
- #define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */
- #define REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */
- #define REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */
- #define REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */
- #define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */
- #define REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */
- #define REG_XDMAC_CIM2 (*(__O uint32_t*)0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */
- #define REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */
- #define REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */
- #define REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */
- #define REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */
- #define REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */
- #define REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */
- #define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */
- #define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */
- #define REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */
- #define REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */
- #define REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */
- #define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */
- #define REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */
- #define REG_XDMAC_CIM3 (*(__O uint32_t*)0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */
- #define REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */
- #define REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */
- #define REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */
- #define REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */
- #define REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */
- #define REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */
- #define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */
- #define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */
- #define REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */
- #define REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */
- #define REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */
- #define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */
- #define REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */
- #define REG_XDMAC_CIM4 (*(__O uint32_t*)0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */
- #define REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */
- #define REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */
- #define REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */
- #define REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */
- #define REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */
- #define REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */
- #define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */
- #define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */
- #define REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */
- #define REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */
- #define REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */
- #define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */
- #define REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */
- #define REG_XDMAC_CIM5 (*(__O uint32_t*)0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */
- #define REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */
- #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */
- #define REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */
- #define REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */
- #define REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */
- #define REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */
- #define REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */
- #define REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */
- #define REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */
- #define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */
- #define REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */
- #define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */
- #define REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */
- #define REG_XDMAC_CIM6 (*(__O uint32_t*)0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */
- #define REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */
- #define REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */
- #define REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */
- #define REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */
- #define REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */
- #define REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */
- #define REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */
- #define REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */
- #define REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */
- #define REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */
- #define REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */
- #define REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */
- #define REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */
- #define REG_XDMAC_CIM7 (*(__O uint32_t*)0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */
- #define REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */
- #define REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */
- #define REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */
- #define REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */
- #define REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */
- #define REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */
- #define REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */
- #define REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */
- #define REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */
- #define REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */
- #define REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */
- #define REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */
- #define REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */
- #define REG_XDMAC_CIM8 (*(__O uint32_t*)0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */
- #define REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */
- #define REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */
- #define REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */
- #define REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */
- #define REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */
- #define REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */
- #define REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */
- #define REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */
- #define REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */
- #define REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */
- #define REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */
- #define REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */
- #define REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */
- #define REG_XDMAC_CIM9 (*(__O uint32_t*)0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */
- #define REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */
- #define REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */
- #define REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */
- #define REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */
- #define REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */
- #define REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */
- #define REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */
- #define REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */
- #define REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */
- #define REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */
- #define REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */
- #define REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */
- #define REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */
- #define REG_XDMAC_CIM10 (*(__O uint32_t*)0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */
- #define REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */
- #define REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */
- #define REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */
- #define REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */
- #define REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */
- #define REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */
- #define REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */
- #define REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */
- #define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */
- #define REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */
- #define REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */
- #define REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */
- #define REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */
- #define REG_XDMAC_CIM11 (*(__O uint32_t*)0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */
- #define REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */
- #define REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */
- #define REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */
- #define REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */
- #define REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */
- #define REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */
- #define REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */
- #define REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */
- #define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */
- #define REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */
- #define REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */
- #define REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */
- #define REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */
- #define REG_XDMAC_CIM12 (*(__O uint32_t*)0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */
- #define REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */
- #define REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */
- #define REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */
- #define REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */
- #define REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */
- #define REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */
- #define REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */
- #define REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */
- #define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */
- #define REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */
- #define REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */
- #define REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */
- #define REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */
- #define REG_XDMAC_CIM13 (*(__O uint32_t*)0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */
- #define REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */
- #define REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */
- #define REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */
- #define REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */
- #define REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */
- #define REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */
- #define REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */
- #define REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */
- #define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */
- #define REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */
- #define REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */
- #define REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */
- #define REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */
- #define REG_XDMAC_CIM14 (*(__O uint32_t*)0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */
- #define REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */
- #define REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */
- #define REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */
- #define REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */
- #define REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */
- #define REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */
- #define REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */
- #define REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */
- #define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */
- #define REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */
- #define REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */
- #define REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */
- #define REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */
- #define REG_XDMAC_CIM15 (*(__O uint32_t*)0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */
- #define REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */
- #define REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */
- #define REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */
- #define REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */
- #define REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */
- #define REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */
- #define REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */
- #define REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */
- #define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */
- #define REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */
- #define REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */
- #define REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */
- #define REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */
- #define REG_XDMAC_CIM16 (*(__O uint32_t*)0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */
- #define REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */
- #define REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */
- #define REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */
- #define REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */
- #define REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */
- #define REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */
- #define REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */
- #define REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */
- #define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */
- #define REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */
- #define REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */
- #define REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */
- #define REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */
- #define REG_XDMAC_CIM17 (*(__O uint32_t*)0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */
- #define REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */
- #define REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */
- #define REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */
- #define REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */
- #define REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */
- #define REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */
- #define REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */
- #define REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */
- #define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */
- #define REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */
- #define REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */
- #define REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */
- #define REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */
- #define REG_XDMAC_CIM18 (*(__O uint32_t*)0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */
- #define REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */
- #define REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */
- #define REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */
- #define REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */
- #define REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */
- #define REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */
- #define REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */
- #define REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */
- #define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */
- #define REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */
- #define REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */
- #define REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */
- #define REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */
- #define REG_XDMAC_CIM19 (*(__O uint32_t*)0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */
- #define REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */
- #define REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */
- #define REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */
- #define REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */
- #define REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */
- #define REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */
- #define REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */
- #define REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */
- #define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */
- #define REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */
- #define REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */
- #define REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */
- #define REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */
- #define REG_XDMAC_CIM20 (*(__O uint32_t*)0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */
- #define REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */
- #define REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */
- #define REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */
- #define REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */
- #define REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */
- #define REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */
- #define REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */
- #define REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */
- #define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */
- #define REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */
- #define REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */
- #define REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */
- #define REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */
- #define REG_XDMAC_CIM21 (*(__O uint32_t*)0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */
- #define REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */
- #define REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */
- #define REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */
- #define REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */
- #define REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */
- #define REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */
- #define REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */
- #define REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */
- #define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */
- #define REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */
- #define REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */
- #define REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */
- #define REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */
- #define REG_XDMAC_CIM22 (*(__O uint32_t*)0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */
- #define REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */
- #define REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */
- #define REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */
- #define REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */
- #define REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */
- #define REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */
- #define REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */
- #define REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */
- #define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */
- #define REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */
- #define REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */
- #define REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */
- #define REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */
- #define REG_XDMAC_CIM23 (*(__O uint32_t*)0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */
- #define REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */
- #define REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */
- #define REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */
- #define REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */
- #define REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */
- #define REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */
- #define REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */
- #define REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */
- #define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */
- #define REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */
- #define REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_XDMAC_INSTANCE_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j19.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j19.h
deleted file mode 100644
index 786bdc6..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j19.h
+++ /dev/null
@@ -1,418 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70J19_PIO_
-#define _SAMS70J19_PIO_
-
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA24_IDX 24
-#define PIO_PA27_IDX 27
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD31_IDX 127
-
-#endif /* _SAMS70J19_PIO_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j20.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j20.h
deleted file mode 100644
index 77b1fb3..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j20.h
+++ /dev/null
@@ -1,422 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70J20_PIO_
-#define _SAMS70J20_PIO_
-
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for DACC peripheral ========== */
-#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
-#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */
-#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA24_IDX 24
-#define PIO_PA27_IDX 27
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD31_IDX 127
-
-#endif /* _SAMS70J20_PIO_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j21.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j21.h
deleted file mode 100644
index eac07be..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j21.h
+++ /dev/null
@@ -1,422 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70J21_PIO_
-#define _SAMS70J21_PIO_
-
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for DACC peripheral ========== */
-#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
-#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */
-#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA24_IDX 24
-#define PIO_PA27_IDX 27
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD31_IDX 127
-
-#endif /* _SAMS70J21_PIO_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n19.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n19.h
deleted file mode 100644
index fc6b03a..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n19.h
+++ /dev/null
@@ -1,479 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70N19_PIO_
-#define _SAMS70N19_PIO_
-
-#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
-#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
-#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
-#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
-#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
-#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
-#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
-#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
-#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
-#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
-#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */
-#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */
-#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */
-#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */
-#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */
-#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */
-#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */
-#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */
-#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */
-#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for DACC peripheral ========== */
-#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
-#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */
-#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for TWIHS2 peripheral ========== */
-#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */
-#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA0_IDX 0
-#define PIO_PA1_IDX 1
-#define PIO_PA2_IDX 2
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA15_IDX 15
-#define PIO_PA16_IDX 16
-#define PIO_PA17_IDX 17
-#define PIO_PA18_IDX 18
-#define PIO_PA19_IDX 19
-#define PIO_PA20_IDX 20
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA23_IDX 23
-#define PIO_PA24_IDX 24
-#define PIO_PA25_IDX 25
-#define PIO_PA26_IDX 26
-#define PIO_PA27_IDX 27
-#define PIO_PA28_IDX 28
-#define PIO_PA30_IDX 30
-#define PIO_PA31_IDX 31
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PB13_IDX 45
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD13_IDX 109
-#define PIO_PD14_IDX 110
-#define PIO_PD15_IDX 111
-#define PIO_PD16_IDX 112
-#define PIO_PD17_IDX 113
-#define PIO_PD18_IDX 114
-#define PIO_PD19_IDX 115
-#define PIO_PD20_IDX 116
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD27_IDX 123
-#define PIO_PD28_IDX 124
-#define PIO_PD30_IDX 126
-#define PIO_PD31_IDX 127
-
-#endif /* _SAMS70N19_PIO_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n20.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n20.h
deleted file mode 100644
index 844f1f7..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n20.h
+++ /dev/null
@@ -1,475 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70N20_PIO_
-#define _SAMS70N20_PIO_
-
-#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
-#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
-#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
-#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
-#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
-#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
-#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
-#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
-#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
-#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
-#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */
-#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */
-#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */
-#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */
-#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */
-#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */
-#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */
-#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */
-#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */
-#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for TWIHS2 peripheral ========== */
-#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */
-#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA0_IDX 0
-#define PIO_PA1_IDX 1
-#define PIO_PA2_IDX 2
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA15_IDX 15
-#define PIO_PA16_IDX 16
-#define PIO_PA17_IDX 17
-#define PIO_PA18_IDX 18
-#define PIO_PA19_IDX 19
-#define PIO_PA20_IDX 20
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA23_IDX 23
-#define PIO_PA24_IDX 24
-#define PIO_PA25_IDX 25
-#define PIO_PA26_IDX 26
-#define PIO_PA27_IDX 27
-#define PIO_PA28_IDX 28
-#define PIO_PA30_IDX 30
-#define PIO_PA31_IDX 31
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PB13_IDX 45
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD13_IDX 109
-#define PIO_PD14_IDX 110
-#define PIO_PD15_IDX 111
-#define PIO_PD16_IDX 112
-#define PIO_PD17_IDX 113
-#define PIO_PD18_IDX 114
-#define PIO_PD19_IDX 115
-#define PIO_PD20_IDX 116
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD27_IDX 123
-#define PIO_PD28_IDX 124
-#define PIO_PD30_IDX 126
-#define PIO_PD31_IDX 127
-
-#endif /* _SAMS70N20_PIO_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n21.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n21.h
deleted file mode 100644
index 1e1d83c..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n21.h
+++ /dev/null
@@ -1,475 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70N21_PIO_
-#define _SAMS70N21_PIO_
-
-#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
-#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
-#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
-#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
-#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
-#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
-#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
-#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
-#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
-#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
-#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */
-#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */
-#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */
-#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */
-#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */
-#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */
-#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */
-#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */
-#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */
-#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for TWIHS2 peripheral ========== */
-#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */
-#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA0_IDX 0
-#define PIO_PA1_IDX 1
-#define PIO_PA2_IDX 2
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA15_IDX 15
-#define PIO_PA16_IDX 16
-#define PIO_PA17_IDX 17
-#define PIO_PA18_IDX 18
-#define PIO_PA19_IDX 19
-#define PIO_PA20_IDX 20
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA23_IDX 23
-#define PIO_PA24_IDX 24
-#define PIO_PA25_IDX 25
-#define PIO_PA26_IDX 26
-#define PIO_PA27_IDX 27
-#define PIO_PA28_IDX 28
-#define PIO_PA30_IDX 30
-#define PIO_PA31_IDX 31
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PB13_IDX 45
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD13_IDX 109
-#define PIO_PD14_IDX 110
-#define PIO_PD15_IDX 111
-#define PIO_PD16_IDX 112
-#define PIO_PD17_IDX 113
-#define PIO_PD18_IDX 114
-#define PIO_PD19_IDX 115
-#define PIO_PD20_IDX 116
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD27_IDX 123
-#define PIO_PD28_IDX 124
-#define PIO_PD30_IDX 126
-#define PIO_PD31_IDX 127
-
-#endif /* _SAMS70N21_PIO_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q19.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q19.h
deleted file mode 100644
index d59cbc3..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q19.h
+++ /dev/null
@@ -1,652 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70Q19_PIO_
-#define _SAMS70Q19_PIO_
-
-#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
-#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
-#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
-#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
-#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
-#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
-#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
-#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
-#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
-#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
-#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
-#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
-#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */
-#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */
-#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */
-#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */
-#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */
-#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */
-#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */
-#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */
-#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */
-#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */
-#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */
-#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */
-#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */
-#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */
-#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */
-#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */
-#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */
-#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */
-#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */
-#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */
-#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */
-#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */
-#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */
-#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */
-#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */
-#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */
-#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */
-#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */
-#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */
-#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */
-#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */
-#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */
-#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */
-#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */
-#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */
-#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */
-#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */
-#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */
-#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */
-#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */
-#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */
-#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */
-#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */
-#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */
-#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */
-#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */
-#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for DACC peripheral ========== */
-#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
-#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */
-#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
-/* ========== Pio definition for EBI peripheral ========== */
-#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */
-#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */
-#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */
-#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */
-#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */
-#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */
-#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */
-#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */
-#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */
-#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */
-#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */
-#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */
-#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */
-#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */
-#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */
-#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */
-#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */
-#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
-#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
-#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
-#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
-#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */
-#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */
-#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */
-#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */
-#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */
-#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */
-#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */
-#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */
-#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */
-#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */
-#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */
-#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */
-#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */
-#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */
-#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */
-#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */
-#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */
-#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */
-#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */
-#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */
-#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */
-#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */
-#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */
-#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */
-#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */
-#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */
-#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */
-#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */
-#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */
-#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */
-#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */
-#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */
-#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */
-#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */
-#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */
-#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
-#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
-#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */
-#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */
-#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */
-#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */
-#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */
-#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC1 peripheral ========== */
-#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */
-#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */
-#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */
-#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */
-#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */
-#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */
-#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */
-#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */
-#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */
-/* ========== Pio definition for TC2 peripheral ========== */
-#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */
-#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */
-#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */
-#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */
-#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */
-#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */
-#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */
-#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */
-#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for TWIHS2 peripheral ========== */
-#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */
-#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA0_IDX 0
-#define PIO_PA1_IDX 1
-#define PIO_PA2_IDX 2
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA6_IDX 6
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA15_IDX 15
-#define PIO_PA16_IDX 16
-#define PIO_PA17_IDX 17
-#define PIO_PA18_IDX 18
-#define PIO_PA19_IDX 19
-#define PIO_PA20_IDX 20
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA23_IDX 23
-#define PIO_PA24_IDX 24
-#define PIO_PA25_IDX 25
-#define PIO_PA26_IDX 26
-#define PIO_PA27_IDX 27
-#define PIO_PA28_IDX 28
-#define PIO_PA29_IDX 29
-#define PIO_PA30_IDX 30
-#define PIO_PA31_IDX 31
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PB13_IDX 45
-#define PIO_PC0_IDX 64
-#define PIO_PC1_IDX 65
-#define PIO_PC2_IDX 66
-#define PIO_PC3_IDX 67
-#define PIO_PC4_IDX 68
-#define PIO_PC5_IDX 69
-#define PIO_PC6_IDX 70
-#define PIO_PC7_IDX 71
-#define PIO_PC8_IDX 72
-#define PIO_PC9_IDX 73
-#define PIO_PC10_IDX 74
-#define PIO_PC11_IDX 75
-#define PIO_PC12_IDX 76
-#define PIO_PC13_IDX 77
-#define PIO_PC14_IDX 78
-#define PIO_PC15_IDX 79
-#define PIO_PC16_IDX 80
-#define PIO_PC17_IDX 81
-#define PIO_PC18_IDX 82
-#define PIO_PC19_IDX 83
-#define PIO_PC20_IDX 84
-#define PIO_PC21_IDX 85
-#define PIO_PC22_IDX 86
-#define PIO_PC23_IDX 87
-#define PIO_PC24_IDX 88
-#define PIO_PC25_IDX 89
-#define PIO_PC26_IDX 90
-#define PIO_PC27_IDX 91
-#define PIO_PC28_IDX 92
-#define PIO_PC29_IDX 93
-#define PIO_PC30_IDX 94
-#define PIO_PC31_IDX 95
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD13_IDX 109
-#define PIO_PD14_IDX 110
-#define PIO_PD15_IDX 111
-#define PIO_PD16_IDX 112
-#define PIO_PD17_IDX 113
-#define PIO_PD18_IDX 114
-#define PIO_PD19_IDX 115
-#define PIO_PD20_IDX 116
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD23_IDX 119
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD27_IDX 123
-#define PIO_PD28_IDX 124
-#define PIO_PD29_IDX 125
-#define PIO_PD30_IDX 126
-#define PIO_PD31_IDX 127
-#define PIO_PE0_IDX 128
-#define PIO_PE1_IDX 129
-#define PIO_PE2_IDX 130
-#define PIO_PE3_IDX 131
-#define PIO_PE4_IDX 132
-#define PIO_PE5_IDX 133
-
-#endif /* _SAMS70Q19_PIO_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q20.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q20.h
deleted file mode 100644
index 38e6038..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q20.h
+++ /dev/null
@@ -1,652 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70Q20_PIO_
-#define _SAMS70Q20_PIO_
-
-#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
-#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
-#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
-#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
-#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
-#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
-#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
-#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
-#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
-#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
-#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
-#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
-#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */
-#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */
-#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */
-#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */
-#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */
-#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */
-#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */
-#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */
-#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */
-#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */
-#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */
-#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */
-#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */
-#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */
-#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */
-#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */
-#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */
-#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */
-#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */
-#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */
-#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */
-#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */
-#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */
-#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */
-#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */
-#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */
-#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */
-#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */
-#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */
-#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */
-#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */
-#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */
-#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */
-#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */
-#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */
-#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */
-#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */
-#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */
-#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */
-#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */
-#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */
-#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */
-#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */
-#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */
-#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */
-#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */
-#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for DACC peripheral ========== */
-#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
-#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */
-#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
-/* ========== Pio definition for EBI peripheral ========== */
-#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */
-#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */
-#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */
-#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */
-#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */
-#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */
-#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */
-#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */
-#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */
-#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */
-#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */
-#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */
-#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */
-#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */
-#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */
-#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */
-#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */
-#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
-#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
-#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
-#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
-#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */
-#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */
-#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */
-#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */
-#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */
-#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */
-#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */
-#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */
-#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */
-#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */
-#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */
-#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */
-#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */
-#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */
-#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */
-#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */
-#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */
-#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */
-#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */
-#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */
-#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */
-#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */
-#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */
-#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */
-#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */
-#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */
-#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */
-#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */
-#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */
-#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */
-#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */
-#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */
-#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */
-#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */
-#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */
-#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
-#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
-#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */
-#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */
-#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */
-#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */
-#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */
-#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC1 peripheral ========== */
-#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */
-#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */
-#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */
-#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */
-#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */
-#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */
-#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */
-#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */
-#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */
-/* ========== Pio definition for TC2 peripheral ========== */
-#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */
-#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */
-#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */
-#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */
-#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */
-#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */
-#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */
-#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */
-#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for TWIHS2 peripheral ========== */
-#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */
-#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA0_IDX 0
-#define PIO_PA1_IDX 1
-#define PIO_PA2_IDX 2
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA6_IDX 6
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA15_IDX 15
-#define PIO_PA16_IDX 16
-#define PIO_PA17_IDX 17
-#define PIO_PA18_IDX 18
-#define PIO_PA19_IDX 19
-#define PIO_PA20_IDX 20
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA23_IDX 23
-#define PIO_PA24_IDX 24
-#define PIO_PA25_IDX 25
-#define PIO_PA26_IDX 26
-#define PIO_PA27_IDX 27
-#define PIO_PA28_IDX 28
-#define PIO_PA29_IDX 29
-#define PIO_PA30_IDX 30
-#define PIO_PA31_IDX 31
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PB13_IDX 45
-#define PIO_PC0_IDX 64
-#define PIO_PC1_IDX 65
-#define PIO_PC2_IDX 66
-#define PIO_PC3_IDX 67
-#define PIO_PC4_IDX 68
-#define PIO_PC5_IDX 69
-#define PIO_PC6_IDX 70
-#define PIO_PC7_IDX 71
-#define PIO_PC8_IDX 72
-#define PIO_PC9_IDX 73
-#define PIO_PC10_IDX 74
-#define PIO_PC11_IDX 75
-#define PIO_PC12_IDX 76
-#define PIO_PC13_IDX 77
-#define PIO_PC14_IDX 78
-#define PIO_PC15_IDX 79
-#define PIO_PC16_IDX 80
-#define PIO_PC17_IDX 81
-#define PIO_PC18_IDX 82
-#define PIO_PC19_IDX 83
-#define PIO_PC20_IDX 84
-#define PIO_PC21_IDX 85
-#define PIO_PC22_IDX 86
-#define PIO_PC23_IDX 87
-#define PIO_PC24_IDX 88
-#define PIO_PC25_IDX 89
-#define PIO_PC26_IDX 90
-#define PIO_PC27_IDX 91
-#define PIO_PC28_IDX 92
-#define PIO_PC29_IDX 93
-#define PIO_PC30_IDX 94
-#define PIO_PC31_IDX 95
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD13_IDX 109
-#define PIO_PD14_IDX 110
-#define PIO_PD15_IDX 111
-#define PIO_PD16_IDX 112
-#define PIO_PD17_IDX 113
-#define PIO_PD18_IDX 114
-#define PIO_PD19_IDX 115
-#define PIO_PD20_IDX 116
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD23_IDX 119
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD27_IDX 123
-#define PIO_PD28_IDX 124
-#define PIO_PD29_IDX 125
-#define PIO_PD30_IDX 126
-#define PIO_PD31_IDX 127
-#define PIO_PE0_IDX 128
-#define PIO_PE1_IDX 129
-#define PIO_PE2_IDX 130
-#define PIO_PE3_IDX 131
-#define PIO_PE4_IDX 132
-#define PIO_PE5_IDX 133
-
-#endif /* _SAMS70Q20_PIO_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q21.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q21.h
deleted file mode 100644
index 25cb978..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q21.h
+++ /dev/null
@@ -1,652 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70Q21_PIO_
-#define _SAMS70Q21_PIO_
-
-#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
-#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
-#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
-#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
-#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
-#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
-#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
-#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
-#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
-#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
-#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
-#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
-#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */
-#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */
-#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */
-#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */
-#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */
-#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */
-#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */
-#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */
-#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */
-#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */
-#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */
-#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */
-#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */
-#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */
-#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */
-#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */
-#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */
-#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */
-#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */
-#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */
-#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */
-#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */
-#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */
-#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */
-#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */
-#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */
-#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */
-#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */
-#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */
-#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */
-#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */
-#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */
-#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */
-#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */
-#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */
-#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */
-#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */
-#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */
-#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */
-#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */
-#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */
-#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */
-#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */
-#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */
-#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */
-#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */
-#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for DACC peripheral ========== */
-#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
-#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */
-#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
-/* ========== Pio definition for EBI peripheral ========== */
-#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */
-#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */
-#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */
-#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */
-#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */
-#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */
-#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */
-#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */
-#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */
-#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */
-#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */
-#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */
-#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */
-#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */
-#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */
-#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */
-#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */
-#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
-#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
-#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
-#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
-#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */
-#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */
-#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */
-#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */
-#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */
-#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */
-#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */
-#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */
-#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */
-#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */
-#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */
-#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */
-#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */
-#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */
-#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */
-#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */
-#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */
-#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */
-#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */
-#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */
-#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */
-#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */
-#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */
-#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */
-#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */
-#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */
-#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */
-#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */
-#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */
-#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */
-#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */
-#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */
-#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */
-#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */
-#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */
-#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
-#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
-#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */
-#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */
-#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */
-#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */
-#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */
-#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC1 peripheral ========== */
-#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */
-#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */
-#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */
-#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */
-#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */
-#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */
-#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */
-#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */
-#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */
-/* ========== Pio definition for TC2 peripheral ========== */
-#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */
-#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */
-#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */
-#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */
-#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */
-#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */
-#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */
-#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */
-#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for TWIHS2 peripheral ========== */
-#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */
-#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA0_IDX 0
-#define PIO_PA1_IDX 1
-#define PIO_PA2_IDX 2
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA6_IDX 6
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA15_IDX 15
-#define PIO_PA16_IDX 16
-#define PIO_PA17_IDX 17
-#define PIO_PA18_IDX 18
-#define PIO_PA19_IDX 19
-#define PIO_PA20_IDX 20
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA23_IDX 23
-#define PIO_PA24_IDX 24
-#define PIO_PA25_IDX 25
-#define PIO_PA26_IDX 26
-#define PIO_PA27_IDX 27
-#define PIO_PA28_IDX 28
-#define PIO_PA29_IDX 29
-#define PIO_PA30_IDX 30
-#define PIO_PA31_IDX 31
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PB13_IDX 45
-#define PIO_PC0_IDX 64
-#define PIO_PC1_IDX 65
-#define PIO_PC2_IDX 66
-#define PIO_PC3_IDX 67
-#define PIO_PC4_IDX 68
-#define PIO_PC5_IDX 69
-#define PIO_PC6_IDX 70
-#define PIO_PC7_IDX 71
-#define PIO_PC8_IDX 72
-#define PIO_PC9_IDX 73
-#define PIO_PC10_IDX 74
-#define PIO_PC11_IDX 75
-#define PIO_PC12_IDX 76
-#define PIO_PC13_IDX 77
-#define PIO_PC14_IDX 78
-#define PIO_PC15_IDX 79
-#define PIO_PC16_IDX 80
-#define PIO_PC17_IDX 81
-#define PIO_PC18_IDX 82
-#define PIO_PC19_IDX 83
-#define PIO_PC20_IDX 84
-#define PIO_PC21_IDX 85
-#define PIO_PC22_IDX 86
-#define PIO_PC23_IDX 87
-#define PIO_PC24_IDX 88
-#define PIO_PC25_IDX 89
-#define PIO_PC26_IDX 90
-#define PIO_PC27_IDX 91
-#define PIO_PC28_IDX 92
-#define PIO_PC29_IDX 93
-#define PIO_PC30_IDX 94
-#define PIO_PC31_IDX 95
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD13_IDX 109
-#define PIO_PD14_IDX 110
-#define PIO_PD15_IDX 111
-#define PIO_PD16_IDX 112
-#define PIO_PD17_IDX 113
-#define PIO_PD18_IDX 114
-#define PIO_PD19_IDX 115
-#define PIO_PD20_IDX 116
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD23_IDX 119
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD27_IDX 123
-#define PIO_PD28_IDX 124
-#define PIO_PD29_IDX 125
-#define PIO_PD30_IDX 126
-#define PIO_PD31_IDX 127
-#define PIO_PE0_IDX 128
-#define PIO_PE1_IDX 129
-#define PIO_PE2_IDX 130
-#define PIO_PE3_IDX 131
-#define PIO_PE4_IDX 132
-#define PIO_PE5_IDX 133
-
-#endif /* _SAMS70Q21_PIO_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70.h
deleted file mode 100644
index aca1034..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef _SAMS70_
-#define _SAMS70_
-
-#if defined (__SAMS70J19__)
-#include "sams70j19.h"
-#elif defined (__SAMS70J20__)
-#include "sams70j20.h"
-#elif defined (__SAMS70J21__)
-#include "sams70j21.h"
-#elif defined (__SAMS70N19__)
-#include "sams70n19.h"
-#elif defined (__SAMS70N20__)
-#include "sams70n20.h"
-#elif defined (__SAMS70N21__)
-#include "sams70n21.h"
-#elif defined (__SAMS70Q19__)
-#include "sams70q19.h"
-#elif defined (__SAMS70Q20__)
-#include "sams70q20.h"
-#elif defined (__SAMS70Q21__)
-#include "sams70q21.h"
-#else
- #error Library does not support the specified device.
-#endif
-
-#endif /* _SAMS70_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70j19.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70j19.h
deleted file mode 100644
index f4edaa2..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70j19.h
+++ /dev/null
@@ -1,618 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70J19_
-#define _SAMS70J19_
-
-/** \addtogroup SAMS70J19_definitions SAMS70J19 definitions
- This file defines all structures and symbols for SAMS70J19:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J19_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70J19 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70J19 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70J19 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70J19 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70J19 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70J19 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70J19 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70J19 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70J19 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70J19 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70J19 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70J19 Parallel I/O Controller B (PIOB) */
- USART0_IRQn = 13, /**< 13 SAMS70J19 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70J19 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70J19 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70J19 Parallel I/O Controller D (PIOD) */
- HSMCI_IRQn = 18, /**< 18 SAMS70J19 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70J19 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70J19 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70J19 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70J19 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70J19 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70J19 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70J19 Timer/Counter 2 (TC2) */
- AFEC0_IRQn = 29, /**< 29 SAMS70J19 Analog Front End 0 (AFEC0) */
- PWM0_IRQn = 31, /**< 31 SAMS70J19 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70J19 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70J19 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70J19 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70J19 Analog Front End 1 (AFEC1) */
- SPI1_IRQn = 42, /**< 42 SAMS70J19 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70J19 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70J19 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70J19 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70J19 UART 4 (UART4) */
- TC9_IRQn = 50, /**< 50 SAMS70J19 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70J19 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70J19 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70J19 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70J19 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70J19 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70J19 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70J19 Pulse Width Modulation 1 (PWM1) */
- RSWDT_IRQn = 63, /**< 63 SAMS70J19 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pvReserved12;
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pvReserved17;
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pvReserved26;
- void* pvReserved27;
- void* pvReserved28;
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pvReserved30;
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pvReserved41;
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pvReserved47;
- void* pvReserved48;
- void* pvReserved49;
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pvReserved62;
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOD_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70J19 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70J19 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70J19 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70J19 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70J19 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70J19 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70J19 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70J19 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70J19 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70J19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J19_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J19_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/piod.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J19_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J19_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J19_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70j19.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x80000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (1024u)
-#define IFLASH_NB_OF_LOCK_BITS (32u)
-#define IRAM_SIZE (0x40000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA11D0A00UL)
-#define CHIP_EXID (0x00000000UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70J19_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70j20.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70j20.h
deleted file mode 100644
index e2fd998..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70j20.h
+++ /dev/null
@@ -1,625 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70J20_
-#define _SAMS70J20_
-
-/** \addtogroup SAMS70J20_definitions SAMS70J20 definitions
- This file defines all structures and symbols for SAMS70J20:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J20_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70J20 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70J20 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70J20 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70J20 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70J20 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70J20 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70J20 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70J20 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70J20 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70J20 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70J20 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70J20 Parallel I/O Controller B (PIOB) */
- USART0_IRQn = 13, /**< 13 SAMS70J20 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70J20 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70J20 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70J20 Parallel I/O Controller D (PIOD) */
- HSMCI_IRQn = 18, /**< 18 SAMS70J20 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70J20 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70J20 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70J20 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70J20 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70J20 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70J20 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70J20 Timer/Counter 2 (TC2) */
- AFEC0_IRQn = 29, /**< 29 SAMS70J20 Analog Front End 0 (AFEC0) */
- DACC_IRQn = 30, /**< 30 SAMS70J20 Digital To Analog Converter (DACC) */
- PWM0_IRQn = 31, /**< 31 SAMS70J20 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70J20 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70J20 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70J20 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70J20 Analog Front End 1 (AFEC1) */
- SPI1_IRQn = 42, /**< 42 SAMS70J20 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70J20 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70J20 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70J20 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70J20 UART 4 (UART4) */
- TC9_IRQn = 50, /**< 50 SAMS70J20 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70J20 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70J20 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70J20 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70J20 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70J20 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70J20 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70J20 Pulse Width Modulation 1 (PWM1) */
- RSWDT_IRQn = 63, /**< 63 SAMS70J20 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pvReserved12;
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pvReserved17;
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pvReserved26;
- void* pvReserved27;
- void* pvReserved28;
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pvReserved41;
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pvReserved47;
- void* pvReserved48;
- void* pvReserved49;
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pvReserved62;
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void DACC_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOD_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70J20 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70J20 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70J20 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70J20 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70J20 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70J20 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70J20 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70J20 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70J20 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70J20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J20_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/dacc.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J20_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/dacc.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/piod.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J20_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J20_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J20_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70j20.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x100000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (2048u)
-#define IFLASH_NB_OF_LOCK_BITS (64u)
-#define IRAM_SIZE (0x60000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA1120C00UL)
-#define CHIP_EXID (0x00000000UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70J20_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70j21.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70j21.h
deleted file mode 100644
index b554f03..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70j21.h
+++ /dev/null
@@ -1,625 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70J21_
-#define _SAMS70J21_
-
-/** \addtogroup SAMS70J21_definitions SAMS70J21 definitions
- This file defines all structures and symbols for SAMS70J21:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J21_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70J21 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70J21 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70J21 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70J21 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70J21 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70J21 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70J21 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70J21 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70J21 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70J21 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70J21 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70J21 Parallel I/O Controller B (PIOB) */
- USART0_IRQn = 13, /**< 13 SAMS70J21 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70J21 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70J21 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70J21 Parallel I/O Controller D (PIOD) */
- HSMCI_IRQn = 18, /**< 18 SAMS70J21 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70J21 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70J21 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70J21 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70J21 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70J21 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70J21 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70J21 Timer/Counter 2 (TC2) */
- AFEC0_IRQn = 29, /**< 29 SAMS70J21 Analog Front End 0 (AFEC0) */
- DACC_IRQn = 30, /**< 30 SAMS70J21 Digital To Analog Converter (DACC) */
- PWM0_IRQn = 31, /**< 31 SAMS70J21 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70J21 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70J21 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70J21 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70J21 Analog Front End 1 (AFEC1) */
- SPI1_IRQn = 42, /**< 42 SAMS70J21 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70J21 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70J21 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70J21 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70J21 UART 4 (UART4) */
- TC9_IRQn = 50, /**< 50 SAMS70J21 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70J21 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70J21 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70J21 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70J21 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70J21 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70J21 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70J21 Pulse Width Modulation 1 (PWM1) */
- RSWDT_IRQn = 63, /**< 63 SAMS70J21 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pvReserved12;
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pvReserved17;
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pvReserved26;
- void* pvReserved27;
- void* pvReserved28;
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pvReserved41;
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pvReserved47;
- void* pvReserved48;
- void* pvReserved49;
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pvReserved62;
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void DACC_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOD_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70J21 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70J21 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70J21 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70J21 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70J21 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70J21 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70J21 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70J21 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70J21 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70J21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J21_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/dacc.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J21_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/dacc.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/piod.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J21_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J21_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J21_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70j21.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x200000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (4096u)
-#define IFLASH_NB_OF_LOCK_BITS (128u)
-#define IRAM_SIZE (0x60000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA1120E00UL)
-#define CHIP_EXID (0x00000000UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70J21_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70n19.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70n19.h
deleted file mode 100644
index 1957933..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70n19.h
+++ /dev/null
@@ -1,631 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70N19_
-#define _SAMS70N19_
-
-/** \addtogroup SAMS70N19_definitions SAMS70N19 definitions
- This file defines all structures and symbols for SAMS70N19:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N19_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70N19 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70N19 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70N19 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70N19 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70N19 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70N19 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70N19 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70N19 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70N19 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70N19 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70N19 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70N19 Parallel I/O Controller B (PIOB) */
- USART0_IRQn = 13, /**< 13 SAMS70N19 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70N19 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70N19 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70N19 Parallel I/O Controller D (PIOD) */
- HSMCI_IRQn = 18, /**< 18 SAMS70N19 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70N19 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70N19 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70N19 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70N19 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70N19 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70N19 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70N19 Timer/Counter 2 (TC2) */
- AFEC0_IRQn = 29, /**< 29 SAMS70N19 Analog Front End 0 (AFEC0) */
- DACC_IRQn = 30, /**< 30 SAMS70N19 Digital To Analog Converter (DACC) */
- PWM0_IRQn = 31, /**< 31 SAMS70N19 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70N19 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70N19 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70N19 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70N19 Analog Front End 1 (AFEC1) */
- TWIHS2_IRQn = 41, /**< 41 SAMS70N19 Two Wire Interface 2 HS (TWIHS2) */
- SPI1_IRQn = 42, /**< 42 SAMS70N19 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70N19 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70N19 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70N19 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70N19 UART 4 (UART4) */
- TC9_IRQn = 50, /**< 50 SAMS70N19 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70N19 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70N19 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70N19 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70N19 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70N19 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70N19 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70N19 Pulse Width Modulation 1 (PWM1) */
- RSWDT_IRQn = 63, /**< 63 SAMS70N19 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pvReserved12;
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pvReserved17;
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pvReserved26;
- void* pvReserved27;
- void* pvReserved28;
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pvReserved47;
- void* pvReserved48;
- void* pvReserved49;
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pvReserved62;
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void DACC_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOD_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void TWIHS2_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70N19 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70N19 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70N19 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70N19 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70N19 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70N19 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70N19 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70N19 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70N19 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70N19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N19_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/dacc.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N19_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/dacc.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/twihs2.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/piod.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N19_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N19_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N19_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70n19.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x80000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (1024u)
-#define IFLASH_NB_OF_LOCK_BITS (32u)
-#define IRAM_SIZE (0x40000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA11D0A00UL)
-#define CHIP_EXID (0x00000001UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70N19_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70n20.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70n20.h
deleted file mode 100644
index fabfc0c..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70n20.h
+++ /dev/null
@@ -1,624 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70N20_
-#define _SAMS70N20_
-
-/** \addtogroup SAMS70N20_definitions SAMS70N20 definitions
- This file defines all structures and symbols for SAMS70N20:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N20_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70N20 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70N20 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70N20 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70N20 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70N20 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70N20 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70N20 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70N20 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70N20 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70N20 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70N20 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70N20 Parallel I/O Controller B (PIOB) */
- USART0_IRQn = 13, /**< 13 SAMS70N20 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70N20 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70N20 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70N20 Parallel I/O Controller D (PIOD) */
- HSMCI_IRQn = 18, /**< 18 SAMS70N20 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70N20 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70N20 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70N20 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70N20 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70N20 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70N20 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70N20 Timer/Counter 2 (TC2) */
- AFEC0_IRQn = 29, /**< 29 SAMS70N20 Analog Front End 0 (AFEC0) */
- PWM0_IRQn = 31, /**< 31 SAMS70N20 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70N20 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70N20 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70N20 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70N20 Analog Front End 1 (AFEC1) */
- TWIHS2_IRQn = 41, /**< 41 SAMS70N20 Two Wire Interface 2 HS (TWIHS2) */
- SPI1_IRQn = 42, /**< 42 SAMS70N20 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70N20 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70N20 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70N20 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70N20 UART 4 (UART4) */
- TC9_IRQn = 50, /**< 50 SAMS70N20 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70N20 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70N20 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70N20 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70N20 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70N20 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70N20 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70N20 Pulse Width Modulation 1 (PWM1) */
- RSWDT_IRQn = 63, /**< 63 SAMS70N20 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pvReserved12;
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pvReserved17;
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pvReserved26;
- void* pvReserved27;
- void* pvReserved28;
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pvReserved30;
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pvReserved47;
- void* pvReserved48;
- void* pvReserved49;
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pvReserved62;
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOD_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void TWIHS2_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70N20 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70N20 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70N20 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70N20 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70N20 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70N20 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70N20 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70N20 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70N20 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70N20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N20_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N20_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/twihs2.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/piod.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N20_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N20_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N20_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70n20.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x100000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (2048u)
-#define IFLASH_NB_OF_LOCK_BITS (64u)
-#define IRAM_SIZE (0x60000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA1120C00UL)
-#define CHIP_EXID (0x00000001UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70N20_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70n21.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70n21.h
deleted file mode 100644
index 2e98fd9..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70n21.h
+++ /dev/null
@@ -1,624 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70N21_
-#define _SAMS70N21_
-
-/** \addtogroup SAMS70N21_definitions SAMS70N21 definitions
- This file defines all structures and symbols for SAMS70N21:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N21_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70N21 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70N21 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70N21 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70N21 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70N21 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70N21 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70N21 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70N21 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70N21 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70N21 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70N21 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70N21 Parallel I/O Controller B (PIOB) */
- USART0_IRQn = 13, /**< 13 SAMS70N21 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70N21 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70N21 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70N21 Parallel I/O Controller D (PIOD) */
- HSMCI_IRQn = 18, /**< 18 SAMS70N21 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70N21 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70N21 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70N21 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70N21 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70N21 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70N21 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70N21 Timer/Counter 2 (TC2) */
- AFEC0_IRQn = 29, /**< 29 SAMS70N21 Analog Front End 0 (AFEC0) */
- PWM0_IRQn = 31, /**< 31 SAMS70N21 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70N21 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70N21 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70N21 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70N21 Analog Front End 1 (AFEC1) */
- TWIHS2_IRQn = 41, /**< 41 SAMS70N21 Two Wire Interface 2 HS (TWIHS2) */
- SPI1_IRQn = 42, /**< 42 SAMS70N21 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70N21 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70N21 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70N21 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70N21 UART 4 (UART4) */
- TC9_IRQn = 50, /**< 50 SAMS70N21 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70N21 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70N21 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70N21 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70N21 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70N21 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70N21 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70N21 Pulse Width Modulation 1 (PWM1) */
- RSWDT_IRQn = 63, /**< 63 SAMS70N21 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pvReserved12;
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pvReserved17;
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pvReserved26;
- void* pvReserved27;
- void* pvReserved28;
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pvReserved30;
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pvReserved47;
- void* pvReserved48;
- void* pvReserved49;
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pvReserved62;
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOD_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void TWIHS2_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70N21 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70N21 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70N21 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70N21 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70N21 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70N21 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70N21 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70N21 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70N21 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70N21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N21_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N21_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/twihs2.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/piod.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N21_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N21_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N21_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70n21.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x200000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (4096u)
-#define IFLASH_NB_OF_LOCK_BITS (128u)
-#define IRAM_SIZE (0x60000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA1120E00UL)
-#define CHIP_EXID (0x00000001UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70N21_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70q19.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70q19.h
deleted file mode 100644
index ef33389..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70q19.h
+++ /dev/null
@@ -1,679 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70Q19_
-#define _SAMS70Q19_
-
-/** \addtogroup SAMS70Q19_definitions SAMS70Q19 definitions
- This file defines all structures and symbols for SAMS70Q19:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q19_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70Q19 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70Q19 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70Q19 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70Q19 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70Q19 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70Q19 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70Q19 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70Q19 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70Q19 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70Q19 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70Q19 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70Q19 Parallel I/O Controller B (PIOB) */
- PIOC_IRQn = 12, /**< 12 SAMS70Q19 Parallel I/O Controller C (PIOC) */
- USART0_IRQn = 13, /**< 13 SAMS70Q19 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70Q19 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70Q19 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70Q19 Parallel I/O Controller D (PIOD) */
- PIOE_IRQn = 17, /**< 17 SAMS70Q19 Parallel I/O Controller E (PIOE) */
- HSMCI_IRQn = 18, /**< 18 SAMS70Q19 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70Q19 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70Q19 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70Q19 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70Q19 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70Q19 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70Q19 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70Q19 Timer/Counter 2 (TC2) */
- TC3_IRQn = 26, /**< 26 SAMS70Q19 Timer/Counter 3 (TC3) */
- TC4_IRQn = 27, /**< 27 SAMS70Q19 Timer/Counter 4 (TC4) */
- TC5_IRQn = 28, /**< 28 SAMS70Q19 Timer/Counter 5 (TC5) */
- AFEC0_IRQn = 29, /**< 29 SAMS70Q19 Analog Front End 0 (AFEC0) */
- DACC_IRQn = 30, /**< 30 SAMS70Q19 Digital To Analog Converter (DACC) */
- PWM0_IRQn = 31, /**< 31 SAMS70Q19 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70Q19 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70Q19 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70Q19 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70Q19 Analog Front End 1 (AFEC1) */
- TWIHS2_IRQn = 41, /**< 41 SAMS70Q19 Two Wire Interface 2 HS (TWIHS2) */
- SPI1_IRQn = 42, /**< 42 SAMS70Q19 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70Q19 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70Q19 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70Q19 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70Q19 UART 4 (UART4) */
- TC6_IRQn = 47, /**< 47 SAMS70Q19 Timer/Counter 6 (TC6) */
- TC7_IRQn = 48, /**< 48 SAMS70Q19 Timer/Counter 7 (TC7) */
- TC8_IRQn = 49, /**< 49 SAMS70Q19 Timer/Counter 8 (TC8) */
- TC9_IRQn = 50, /**< 50 SAMS70Q19 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70Q19 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70Q19 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70Q19 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70Q19 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70Q19 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70Q19 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70Q19 Pulse Width Modulation 1 (PWM1) */
- SDRAMC_IRQn = 62, /**< 62 SAMS70Q19 SDRAM Controller (SDRAMC) */
- RSWDT_IRQn = 63, /**< 63 SAMS70Q19 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
- void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
- void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pfnTC6_Handler; /* 47 Timer/Counter 6 */
- void* pfnTC7_Handler; /* 48 Timer/Counter 7 */
- void* pfnTC8_Handler; /* 49 Timer/Counter 8 */
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void DACC_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOC_Handler ( void );
-void PIOD_Handler ( void );
-void PIOE_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SDRAMC_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC3_Handler ( void );
-void TC4_Handler ( void );
-void TC5_Handler ( void );
-void TC6_Handler ( void );
-void TC7_Handler ( void );
-void TC8_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void TWIHS2_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70Q19 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70Q19 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70Q19 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70Q19 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70Q19 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70Q19 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70Q19 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70Q19 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70Q19 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70Q19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q19_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/dacc.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/sdramc.h"
-#include "component/smc.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q19_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/tc1.h"
-#include "instance/tc2.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/dacc.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/twihs2.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/smc.h"
-#include "instance/sdramc.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/pioc.h"
-#include "instance/piod.h"
-#include "instance/pioe.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q19_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
-#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
-#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */
-#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */
-#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q19_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */
-#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */
-#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */
-#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */
-#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q19_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70q19.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x80000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (1024u)
-#define IFLASH_NB_OF_LOCK_BITS (32u)
-#define IRAM_SIZE (0x40000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA11D0A00UL)
-#define CHIP_EXID (0x00000002UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70Q19_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70q20.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70q20.h
deleted file mode 100644
index bfadf15..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70q20.h
+++ /dev/null
@@ -1,679 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70Q20_
-#define _SAMS70Q20_
-
-/** \addtogroup SAMS70Q20_definitions SAMS70Q20 definitions
- This file defines all structures and symbols for SAMS70Q20:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q20_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70Q20 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70Q20 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70Q20 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70Q20 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70Q20 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70Q20 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70Q20 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70Q20 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70Q20 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70Q20 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70Q20 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70Q20 Parallel I/O Controller B (PIOB) */
- PIOC_IRQn = 12, /**< 12 SAMS70Q20 Parallel I/O Controller C (PIOC) */
- USART0_IRQn = 13, /**< 13 SAMS70Q20 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70Q20 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70Q20 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70Q20 Parallel I/O Controller D (PIOD) */
- PIOE_IRQn = 17, /**< 17 SAMS70Q20 Parallel I/O Controller E (PIOE) */
- HSMCI_IRQn = 18, /**< 18 SAMS70Q20 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70Q20 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70Q20 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70Q20 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70Q20 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70Q20 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70Q20 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70Q20 Timer/Counter 2 (TC2) */
- TC3_IRQn = 26, /**< 26 SAMS70Q20 Timer/Counter 3 (TC3) */
- TC4_IRQn = 27, /**< 27 SAMS70Q20 Timer/Counter 4 (TC4) */
- TC5_IRQn = 28, /**< 28 SAMS70Q20 Timer/Counter 5 (TC5) */
- AFEC0_IRQn = 29, /**< 29 SAMS70Q20 Analog Front End 0 (AFEC0) */
- DACC_IRQn = 30, /**< 30 SAMS70Q20 Digital To Analog Converter (DACC) */
- PWM0_IRQn = 31, /**< 31 SAMS70Q20 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70Q20 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70Q20 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70Q20 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70Q20 Analog Front End 1 (AFEC1) */
- TWIHS2_IRQn = 41, /**< 41 SAMS70Q20 Two Wire Interface 2 HS (TWIHS2) */
- SPI1_IRQn = 42, /**< 42 SAMS70Q20 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70Q20 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70Q20 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70Q20 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70Q20 UART 4 (UART4) */
- TC6_IRQn = 47, /**< 47 SAMS70Q20 Timer/Counter 6 (TC6) */
- TC7_IRQn = 48, /**< 48 SAMS70Q20 Timer/Counter 7 (TC7) */
- TC8_IRQn = 49, /**< 49 SAMS70Q20 Timer/Counter 8 (TC8) */
- TC9_IRQn = 50, /**< 50 SAMS70Q20 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70Q20 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70Q20 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70Q20 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70Q20 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70Q20 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70Q20 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70Q20 Pulse Width Modulation 1 (PWM1) */
- SDRAMC_IRQn = 62, /**< 62 SAMS70Q20 SDRAM Controller (SDRAMC) */
- RSWDT_IRQn = 63, /**< 63 SAMS70Q20 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
- void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
- void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pfnTC6_Handler; /* 47 Timer/Counter 6 */
- void* pfnTC7_Handler; /* 48 Timer/Counter 7 */
- void* pfnTC8_Handler; /* 49 Timer/Counter 8 */
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void DACC_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOC_Handler ( void );
-void PIOD_Handler ( void );
-void PIOE_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SDRAMC_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC3_Handler ( void );
-void TC4_Handler ( void );
-void TC5_Handler ( void );
-void TC6_Handler ( void );
-void TC7_Handler ( void );
-void TC8_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void TWIHS2_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70Q20 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70Q20 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70Q20 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70Q20 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70Q20 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70Q20 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70Q20 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70Q20 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70Q20 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70Q20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q20_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/dacc.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/sdramc.h"
-#include "component/smc.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q20_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/tc1.h"
-#include "instance/tc2.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/dacc.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/twihs2.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/smc.h"
-#include "instance/sdramc.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/pioc.h"
-#include "instance/piod.h"
-#include "instance/pioe.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q20_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
-#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
-#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */
-#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */
-#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q20_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */
-#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */
-#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */
-#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */
-#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q20_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70q20.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x100000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (2048u)
-#define IFLASH_NB_OF_LOCK_BITS (64u)
-#define IRAM_SIZE (0x60000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA1120C00UL)
-#define CHIP_EXID (0x00000002UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70Q20_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70q21.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70q21.h
deleted file mode 100644
index 10bb674..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/include/sams70q21.h
+++ /dev/null
@@ -1,679 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70Q21_
-#define _SAMS70Q21_
-
-/** \addtogroup SAMS70Q21_definitions SAMS70Q21 definitions
- This file defines all structures and symbols for SAMS70Q21:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q21_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70Q21 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70Q21 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70Q21 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70Q21 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70Q21 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70Q21 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70Q21 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70Q21 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70Q21 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70Q21 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70Q21 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70Q21 Parallel I/O Controller B (PIOB) */
- PIOC_IRQn = 12, /**< 12 SAMS70Q21 Parallel I/O Controller C (PIOC) */
- USART0_IRQn = 13, /**< 13 SAMS70Q21 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70Q21 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70Q21 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70Q21 Parallel I/O Controller D (PIOD) */
- PIOE_IRQn = 17, /**< 17 SAMS70Q21 Parallel I/O Controller E (PIOE) */
- HSMCI_IRQn = 18, /**< 18 SAMS70Q21 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70Q21 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70Q21 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70Q21 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70Q21 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70Q21 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70Q21 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70Q21 Timer/Counter 2 (TC2) */
- TC3_IRQn = 26, /**< 26 SAMS70Q21 Timer/Counter 3 (TC3) */
- TC4_IRQn = 27, /**< 27 SAMS70Q21 Timer/Counter 4 (TC4) */
- TC5_IRQn = 28, /**< 28 SAMS70Q21 Timer/Counter 5 (TC5) */
- AFEC0_IRQn = 29, /**< 29 SAMS70Q21 Analog Front End 0 (AFEC0) */
- DACC_IRQn = 30, /**< 30 SAMS70Q21 Digital To Analog Converter (DACC) */
- PWM0_IRQn = 31, /**< 31 SAMS70Q21 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70Q21 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70Q21 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70Q21 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70Q21 Analog Front End 1 (AFEC1) */
- TWIHS2_IRQn = 41, /**< 41 SAMS70Q21 Two Wire Interface 2 HS (TWIHS2) */
- SPI1_IRQn = 42, /**< 42 SAMS70Q21 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70Q21 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70Q21 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70Q21 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70Q21 UART 4 (UART4) */
- TC6_IRQn = 47, /**< 47 SAMS70Q21 Timer/Counter 6 (TC6) */
- TC7_IRQn = 48, /**< 48 SAMS70Q21 Timer/Counter 7 (TC7) */
- TC8_IRQn = 49, /**< 49 SAMS70Q21 Timer/Counter 8 (TC8) */
- TC9_IRQn = 50, /**< 50 SAMS70Q21 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70Q21 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70Q21 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70Q21 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70Q21 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70Q21 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70Q21 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70Q21 Pulse Width Modulation 1 (PWM1) */
- SDRAMC_IRQn = 62, /**< 62 SAMS70Q21 SDRAM Controller (SDRAMC) */
- RSWDT_IRQn = 63, /**< 63 SAMS70Q21 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
- void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
- void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pfnTC6_Handler; /* 47 Timer/Counter 6 */
- void* pfnTC7_Handler; /* 48 Timer/Counter 7 */
- void* pfnTC8_Handler; /* 49 Timer/Counter 8 */
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void DACC_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOC_Handler ( void );
-void PIOD_Handler ( void );
-void PIOE_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SDRAMC_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC3_Handler ( void );
-void TC4_Handler ( void );
-void TC5_Handler ( void );
-void TC6_Handler ( void );
-void TC7_Handler ( void );
-void TC8_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void TWIHS2_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70Q21 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70Q21 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70Q21 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70Q21 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70Q21 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70Q21 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70Q21 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70Q21 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70Q21 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70Q21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q21_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/dacc.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/sdramc.h"
-#include "component/smc.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q21_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/tc1.h"
-#include "instance/tc2.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/dacc.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/twihs2.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/smc.h"
-#include "instance/sdramc.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/pioc.h"
-#include "instance/piod.h"
-#include "instance/pioe.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q21_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
-#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
-#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */
-#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */
-#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q21_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */
-#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */
-#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */
-#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */
-#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q21_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70q21.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x200000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (4096u)
-#define IFLASH_NB_OF_LOCK_BITS (128u)
-#define IRAM_SIZE (0x60000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA1120E00UL)
-#define CHIP_EXID (0x00000002UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70Q21_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/source/templates/gcc/startup_sams70.c b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/source/templates/gcc/startup_sams70.c
deleted file mode 100644
index b7e19af..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/source/templates/gcc/startup_sams70.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include "sams70.h"
-
-/* Initialize segments */
-extern uint32_t _sfixed;
-extern uint32_t _efixed;
-extern uint32_t _etext;
-extern uint32_t _srelocate;
-extern uint32_t _erelocate;
-extern uint32_t _szero;
-extern uint32_t _ezero;
-extern uint32_t _sstack;
-extern uint32_t _estack;
-
-/** \cond DOXYGEN_SHOULD_SKIP_THIS */
-int main(void);
-/** \endcond */
-
-void __libc_init_array(void);
-
-/* Default empty handler */
-void Dummy_Handler(void);
-
-/* Cortex-M7 core handlers */
-void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void MemManage_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void DebugMon_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-
-/* Peripherals handlers */
-void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef _SAMS70_PIOC_INSTANCE_
-void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_PIOC_INSTANCE_ */
-void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef _SAMS70_PIOE_INSTANCE_
-void PIOE_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_PIOE_INSTANCE_ */
-void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef _SAMS70_TC1_INSTANCE_
-void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_TC1_INSTANCE_ */
-#ifdef _SAMS70_TC1_INSTANCE_
-void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_TC1_INSTANCE_ */
-#ifdef _SAMS70_TC1_INSTANCE_
-void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_TC1_INSTANCE_ */
-void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef _SAMS70_DACC_INSTANCE_
-void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_DACC_INSTANCE_ */
-void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef _SAMS70_TWIHS2_INSTANCE_
-void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_TWIHS2_INSTANCE_ */
-void SPI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef _SAMS70_TC2_INSTANCE_
-void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_TC2_INSTANCE_ */
-#ifdef _SAMS70_TC2_INSTANCE_
-void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_TC2_INSTANCE_ */
-#ifdef _SAMS70_TC2_INSTANCE_
-void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_TC2_INSTANCE_ */
-void TC9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TC10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TC11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef _SAMS70_SDRAMC_INSTANCE_
-void SDRAMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_SDRAMC_INSTANCE_ */
-void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-
-/* Exception Table */
-__attribute__ ((section(".vectors")))
-const DeviceVectors exception_table = {
-
- /* Configure Initial Stack Pointer, using linker-generated symbols */
- .pvStack = (void*) (&_estack),
-
- .pfnReset_Handler = (void*) Reset_Handler,
- .pfnNMI_Handler = (void*) NMI_Handler,
- .pfnHardFault_Handler = (void*) HardFault_Handler,
- .pfnMemManage_Handler = (void*) MemManage_Handler,
- .pfnBusFault_Handler = (void*) BusFault_Handler,
- .pfnUsageFault_Handler = (void*) UsageFault_Handler,
- .pfnReserved1_Handler = (void*) (0UL), /* Reserved */
- .pfnReserved2_Handler = (void*) (0UL), /* Reserved */
- .pfnReserved3_Handler = (void*) (0UL), /* Reserved */
- .pfnReserved4_Handler = (void*) (0UL), /* Reserved */
- .pfnSVC_Handler = (void*) SVC_Handler,
- .pfnDebugMon_Handler = (void*) DebugMon_Handler,
- .pfnReserved5_Handler = (void*) (0UL), /* Reserved */
- .pfnPendSV_Handler = (void*) PendSV_Handler,
- .pfnSysTick_Handler = (void*) SysTick_Handler,
-
- /* Configurable interrupts */
- .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */
- .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */
- .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real Time Clock */
- .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real Time Timer */
- .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */
- .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */
- .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Enhanced Embedded Flash Controller */
- .pfnUART0_Handler = (void*) UART0_Handler, /* 7 UART 0 */
- .pfnUART1_Handler = (void*) UART1_Handler, /* 8 UART 1 */
- .pvReserved9 = (void*) (0UL), /* 9 Reserved */
- .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel I/O Controller A */
- .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel I/O Controller B */
-#ifdef _SAMS70_PIOC_INSTANCE_
- .pfnPIOC_Handler = (void*) PIOC_Handler, /* 12 Parallel I/O Controller C */
-#else
- .pvReserved12 = (void*) (0UL), /* 12 Reserved */
-#endif /* _SAMS70_PIOC_INSTANCE_ */
- .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 USART 0 */
- .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 USART 1 */
- .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 USART 2 */
- .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel I/O Controller D */
-#ifdef _SAMS70_PIOE_INSTANCE_
- .pfnPIOE_Handler = (void*) PIOE_Handler, /* 17 Parallel I/O Controller E */
-#else
- .pvReserved17 = (void*) (0UL), /* 17 Reserved */
-#endif /* _SAMS70_PIOE_INSTANCE_ */
- .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 Multimedia Card Interface */
- .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two Wire Interface 0 HS */
- .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two Wire Interface 1 HS */
- .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface 0 */
- .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */
- .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer/Counter 0 */
- .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer/Counter 1 */
- .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer/Counter 2 */
-#ifdef _SAMS70_TC1_INSTANCE_
- .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer/Counter 3 */
-#else
- .pvReserved26 = (void*) (0UL), /* 26 Reserved */
-#endif /* _SAMS70_TC1_INSTANCE_ */
-#ifdef _SAMS70_TC1_INSTANCE_
- .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer/Counter 4 */
-#else
- .pvReserved27 = (void*) (0UL), /* 27 Reserved */
-#endif /* _SAMS70_TC1_INSTANCE_ */
-#ifdef _SAMS70_TC1_INSTANCE_
- .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer/Counter 5 */
-#else
- .pvReserved28 = (void*) (0UL), /* 28 Reserved */
-#endif /* _SAMS70_TC1_INSTANCE_ */
- .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front End 0 */
-#ifdef _SAMS70_DACC_INSTANCE_
- .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital To Analog Converter */
-#else
- .pvReserved30 = (void*) (0UL), /* 30 Reserved */
-#endif /* _SAMS70_DACC_INSTANCE_ */
- .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation 0 */
- .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */
- .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator */
- .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB Host / Device Controller */
- .pvReserved35 = (void*) (0UL), /* 35 Reserved */
- .pvReserved36 = (void*) (0UL), /* 36 Reserved */
- .pvReserved37 = (void*) (0UL), /* 37 Reserved */
- .pvReserved38 = (void*) (0UL), /* 38 Reserved */
- .pvReserved39 = (void*) (0UL), /* 39 Reserved */
- .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front End 1 */
-#ifdef _SAMS70_TWIHS2_INSTANCE_
- .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two Wire Interface 2 HS */
-#else
- .pvReserved41 = (void*) (0UL), /* 41 Reserved */
-#endif /* _SAMS70_TWIHS2_INSTANCE_ */
- .pfnSPI1_Handler = (void*) SPI1_Handler, /* 42 Serial Peripheral Interface 1 */
- .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad I/O Serial Peripheral Interface */
- .pfnUART2_Handler = (void*) UART2_Handler, /* 44 UART 2 */
- .pfnUART3_Handler = (void*) UART3_Handler, /* 45 UART 3 */
- .pfnUART4_Handler = (void*) UART4_Handler, /* 46 UART 4 */
-#ifdef _SAMS70_TC2_INSTANCE_
- .pfnTC6_Handler = (void*) TC6_Handler, /* 47 Timer/Counter 6 */
-#else
- .pvReserved47 = (void*) (0UL), /* 47 Reserved */
-#endif /* _SAMS70_TC2_INSTANCE_ */
-#ifdef _SAMS70_TC2_INSTANCE_
- .pfnTC7_Handler = (void*) TC7_Handler, /* 48 Timer/Counter 7 */
-#else
- .pvReserved48 = (void*) (0UL), /* 48 Reserved */
-#endif /* _SAMS70_TC2_INSTANCE_ */
-#ifdef _SAMS70_TC2_INSTANCE_
- .pfnTC8_Handler = (void*) TC8_Handler, /* 49 Timer/Counter 8 */
-#else
- .pvReserved49 = (void*) (0UL), /* 49 Reserved */
-#endif /* _SAMS70_TC2_INSTANCE_ */
- .pfnTC9_Handler = (void*) TC9_Handler, /* 50 Timer/Counter 9 */
- .pfnTC10_Handler = (void*) TC10_Handler, /* 51 Timer/Counter 10 */
- .pfnTC11_Handler = (void*) TC11_Handler, /* 52 Timer/Counter 11 */
- .pvReserved53 = (void*) (0UL), /* 53 Reserved */
- .pvReserved54 = (void*) (0UL), /* 54 Reserved */
- .pvReserved55 = (void*) (0UL), /* 55 Reserved */
- .pfnAES_Handler = (void*) AES_Handler, /* 56 AES */
- .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Generator */
- .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 DMA */
- .pfnISI_Handler = (void*) ISI_Handler, /* 59 Camera Interface */
- .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation 1 */
- .pvReserved61 = (void*) (0UL), /* 61 Reserved */
-#ifdef _SAMS70_SDRAMC_INSTANCE_
- .pfnSDRAMC_Handler = (void*) SDRAMC_Handler, /* 62 SDRAM Controller */
-#else
- .pvReserved62 = (void*) (0UL), /* 62 Reserved */
-#endif /* _SAMS70_SDRAMC_INSTANCE_ */
- .pfnRSWDT_Handler = (void*) RSWDT_Handler /* 63 Reinforced Secure Watchdog Timer */
-};
-
-/**
- * \brief This is the code that gets called on processor reset.
- * To initialize the device, and call the main() routine.
- */
-void Reset_Handler(void)
-{
- uint32_t *pSrc, *pDest;
-
- /* Initialize the relocate segment */
- pSrc = &_etext;
- pDest = &_srelocate;
-
- if (pSrc != pDest) {
- for (; pDest < &_erelocate;) {
- *pDest++ = *pSrc++;
- }
- }
-
- /* Clear the zero segment */
- for (pDest = &_szero; pDest < &_ezero;) {
- *pDest++ = 0;
- }
-
- /* Set the vector table base address */
- pSrc = (uint32_t *) & _sfixed;
- SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
-
- /* Initialize the C library */
- __libc_init_array();
-
- /* Branch to main function */
- main();
-
- /* Infinite loop */
- while (1);
-}
-
-/**
- * \brief Default interrupt handler for unused IRQs.
- */
-void Dummy_Handler(void)
-{
- while (1) {
- }
-}
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/source/templates/system_sams70.c b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/source/templates/system_sams70.c
deleted file mode 100644
index 0f7215a..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/source/templates/system_sams70.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include "sams70.h"
-
-/* @cond 0 */
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/* @endcond */
-
-/* %ATMEL_SYSTEM% */
-/* Clock Settings (600MHz PLL VDDIO 3.3V and VDDCORE 1.2V) */
-/* Clock Settings (300MHz HCLK, 150MHz MCK)=> PRESC = 2, MDIV = 2 */
-#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U))
-#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x31U) | \
- CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U))
-#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK | (1<<8))
-
-uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
-
-/**
- * \brief Setup the microcontroller system.
- * Initialize the System and update the SystemFrequency variable.
- */
- void SystemInit( void )
-{
- /* Set FWS according to SYS_BOARD_MCKR configuration */
- EFC->EEFC_FMR = EEFC_FMR_FWS(5);
-
- /* Initialize main oscillator */
- if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
- {
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
-
- while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) )
- {
- }
- }
-
- /* Switch to 3-20MHz Xtal oscillator */
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
-
- while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) )
- {
- }
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
-
- while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
- {
- }
-
- /* Initialize PLLA */
- PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
- while ( !(PMC->PMC_SR & PMC_SR_LOCKA) )
- {
- }
-
- /* Switch to main clock */
- PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
- while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
- {
- }
-
- /* Switch to PLLA */
- PMC->PMC_MCKR = SYS_BOARD_MCKR;
- while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
- {
- }
-
- SystemCoreClock = CHIP_FREQ_CPU_MAX;
-}
-
-void SystemCoreClockUpdate( void )
-{
- /* Determine clock frequency according to clock register values */
- switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk)
- {
- case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
- if ( SUPC->SUPC_SR & SUPC_SR_OSCSEL )
- {
- SystemCoreClock = CHIP_FREQ_XTAL_32K;
- }
- else
- {
- SystemCoreClock = CHIP_FREQ_SLCK_RC;
- }
- break;
-
- case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
- if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL )
- {
- SystemCoreClock = CHIP_FREQ_XTAL_12M;
- }
- else
- {
- SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
-
- switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk )
- {
- case CKGR_MOR_MOSCRCF_4_MHz:
- break;
-
- case CKGR_MOR_MOSCRCF_8_MHz:
- SystemCoreClock *= 2U;
- break;
-
- case CKGR_MOR_MOSCRCF_12_MHz:
- SystemCoreClock *= 3U;
- break;
-
- default:
- break;
- }
- }
- break;
-
- case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
- if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL )
- {
- SystemCoreClock = CHIP_FREQ_XTAL_12M ;
- }
- else
- {
- SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
-
- switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk )
- {
- case CKGR_MOR_MOSCRCF_4_MHz:
- break;
-
- case CKGR_MOR_MOSCRCF_8_MHz:
- SystemCoreClock *= 2U;
- break;
-
- case CKGR_MOR_MOSCRCF_12_MHz:
- SystemCoreClock *= 3U;
- break;
-
- default:
- break;
- }
- }
-
- if ( (uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK )
- {
- SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos) + 1U);
- SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos));
- }
- break;
-
- default:
- break;
- }
-
- if ( (PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3 )
- {
- SystemCoreClock /= 3U;
- }
- else
- {
- SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
- }
-}
-/**
- * Initialize flash.
- */
-void system_init_flash( uint32_t ul_clk )
-{
- /* Set FWS for embedded Flash access according to operating frequency */
- if ( ul_clk < CHIP_FREQ_FWS_0 )
- {
- EFC->EEFC_FMR = EEFC_FMR_FWS(0)|EEFC_FMR_CLOE;
- }
- else
- {
- if (ul_clk < CHIP_FREQ_FWS_1)
- {
- EFC->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE;
- }
- else
- {
- if (ul_clk < CHIP_FREQ_FWS_2)
- {
- EFC->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE;
- }
- else
- {
- if ( ul_clk < CHIP_FREQ_FWS_3 )
- {
- EFC->EEFC_FMR = EEFC_FMR_FWS(3)|EEFC_FMR_CLOE;
- }
- else
- {
- if ( ul_clk < CHIP_FREQ_FWS_4 )
- {
- EFC->EEFC_FMR = EEFC_FMR_FWS(4)|EEFC_FMR_CLOE;
- }
- else
- {
- if ( ul_clk < CHIP_FREQ_FWS_5 )
- {
- EFC->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE;
- }
- else
- {
- EFC->EEFC_FMR = EEFC_FMR_FWS(6)|EEFC_FMR_CLOE;
- }
- }
- }
- }
- }
- }
-}
-/* @cond 0 */
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/* @endcond */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/source/templates/system_sams70.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/source/templates/system_sams70.h
deleted file mode 100644
index 3eaf055..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/cmsis/sams70/source/templates/system_sams70.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef SYSTEM_SAMS70_H_INCLUDED
-#define SYSTEM_SAMS70_H_INCLUDED
-
-/* @cond 0 */
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/* @endcond */
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
-
-/**
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-void SystemInit(void);
-
-/**
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-void SystemCoreClockUpdate(void);
-
-/**
- * Initialize flash.
- */
-void system_init_flash(uint32_t dw_clk);
-
-/* @cond 0 */
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/* @endcond */
-
-#endif /* SYSTEM_SAMS70_H_INCLUDED */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/compiler.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/compiler.h
deleted file mode 100644
index 201fa7e..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/compiler.h
+++ /dev/null
@@ -1,1199 +0,0 @@
-/**
- * \file
- *
- * \brief Commonly used includes, types and macros.
- *
- * Copyright (c) 2010-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef UTILS_COMPILER_H
-#define UTILS_COMPILER_H
-
-/**
- * \defgroup group_sam_utils Compiler abstraction layer and code utilities
- *
- * Compiler abstraction layer and code utilities for AT91SAM.
- * This module provides various abstraction layers and utilities to make code compatible between different compilers.
- *
- * \{
- */
-#include <stddef.h>
-
-#if (defined __ICCARM__)
-# include <intrinsics.h>
-#endif
-
-#include <parts.h>
-#include "preprocessor.h"
-
-#include <io.h>
-
-//_____ D E C L A R A T I O N S ____________________________________________
-
-#ifndef __ASSEMBLY__ // Not defined for assembling.
-
-#include <stdio.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-#ifdef __ICCARM__
-/*! \name Compiler Keywords
- *
- * Port of some keywords from GCC to IAR Embedded Workbench.
- */
-//! @{
-#define __asm__ asm
-#define __inline__ inline
-#define __volatile__
-//! @}
-
-#endif
-
-#define FUNC_PTR void *
-/**
- * \def UNUSED
- * \brief Marking \a v as a unused parameter or value.
- */
-#define UNUSED(v) (void)(v)
-
-/**
- * \def unused
- * \brief Marking \a v as a unused parameter or value.
- */
-#define unused(v) do { (void)(v); } while(0)
-
-/**
- * \def barrier
- * \brief Memory barrier
- */
-#define barrier() __DMB()
-
-/**
- * \brief Emit the compiler pragma \a arg.
- *
- * \param arg The pragma directive as it would appear after \e \#pragma
- * (i.e. not stringified).
- */
-#define COMPILER_PRAGMA(arg) _Pragma(#arg)
-
-/**
- * \def COMPILER_PACK_SET(alignment)
- * \brief Set maximum alignment for subsequent struct and union
- * definitions to \a alignment.
- */
-#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))
-
-/**
- * \def COMPILER_PACK_RESET()
- * \brief Set default alignment for subsequent struct and union
- * definitions.
- */
-#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())
-
-
-/**
- * \brief Set aligned boundary.
- */
-#if (defined __GNUC__) || (defined __CC_ARM)
-# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
-#elif (defined __ICCARM__)
-# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)
-#endif
-
-/**
- * \brief Set word-aligned boundary.
- */
-#if (defined __GNUC__) || defined(__CC_ARM)
-#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))
-#elif (defined __ICCARM__)
-#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4)
-#endif
-
-/**
- * \def __always_inline
- * \brief The function should always be inlined.
- *
- * This annotation instructs the compiler to ignore its inlining
- * heuristics and inline the function no matter how big it thinks it
- * becomes.
- */
-#if defined(__CC_ARM)
-# define __always_inline __forceinline
-#elif (defined __GNUC__)
-#ifdef __always_inline
-# undef __always_inline
-#endif
-# define __always_inline inline __attribute__((__always_inline__))
-#elif (defined __ICCARM__)
-# define __always_inline _Pragma("inline=forced")
-#endif
-
-/**
- * \def __no_inline
- * \brief The function should not be inlined.
- *
- * This annotation instructs the compiler to ignore its inlining
- * heuristics and not inline the function.
- */
-#if defined(__CC_ARM)
-# define __no_inline __attribute__((noinline))
-#elif (defined __GNUC__)
-# define __no_inline __attribute__((__noinline__))
-#elif (defined __ICCARM__)
-# define __no_inline _Pragma("inline=never")
-#endif
-
-/*! \brief This macro is used to test fatal errors.
- *
- * The macro tests if the expression is false. If it is, a fatal error is
- * detected and the application hangs up. If TEST_SUITE_DEFINE_ASSERT_MACRO
- * is defined, a unit test version of the macro is used, to allow execution
- * of further tests after a false expression.
- *
- * \param expr Expression to evaluate and supposed to be nonzero.
- */
-#if defined(_ASSERT_ENABLE_)
-# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)
- // Assert() is defined in unit_test/suite.h
-# include "unit_test/suite.h"
-# else
-#undef TEST_SUITE_DEFINE_ASSERT_MACRO
-# define Assert(expr) \
- {\
- if (!(expr)) while (true);\
- }
-# endif
-#else
-# define Assert(expr) ((void) 0)
-#endif
-
-/* Define WEAK attribute */
-#if defined ( __CC_ARM ) /* Keil µVision 4 */
-# define WEAK __attribute__ ((weak))
-#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
-# define WEAK __weak
-#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
-# define WEAK __attribute__ ((weak))
-#endif
-
-/* Define NO_INIT attribute */
-#if defined ( __CC_ARM )
-# define NO_INIT __attribute__((zero_init))
-#elif defined ( __ICCARM__ )
-# define NO_INIT __no_init
-#elif defined ( __GNUC__ )
-# define NO_INIT __attribute__((section(".no_init")))
-#endif
-
-/* Define RAMFUNC attribute */
-#if defined ( __CC_ARM ) /* Keil µVision 4 */
-# define RAMFUNC __attribute__ ((section(".ramfunc")))
-#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
-# define RAMFUNC __ramfunc
-#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
-# define RAMFUNC __attribute__ ((section(".ramfunc")))
-#endif
-
-/* Define OPTIMIZE_HIGH attribute */
-#if defined ( __CC_ARM ) /* Keil µVision 4 */
-# define OPTIMIZE_HIGH _Pragma("O3")
-#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
-# define OPTIMIZE_HIGH _Pragma("optimize=high")
-#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
-# define OPTIMIZE_HIGH __attribute__((optimize("s")))
-#endif
-
-#include "interrupt.h"
-
-/*! \name Usual Types
- */
-//! @{
-typedef unsigned char Bool; //!< Boolean.
-#ifndef __cplusplus
-#if !defined(__bool_true_false_are_defined)
-typedef unsigned char bool; //!< Boolean.
-#endif
-#endif
-typedef int8_t S8 ; //!< 8-bit signed integer.
-typedef uint8_t U8 ; //!< 8-bit unsigned integer.
-typedef int16_t S16; //!< 16-bit signed integer.
-typedef uint16_t U16; //!< 16-bit unsigned integer.
-typedef uint16_t le16_t;
-typedef uint16_t be16_t;
-typedef int32_t S32; //!< 32-bit signed integer.
-typedef uint32_t U32; //!< 32-bit unsigned integer.
-typedef uint32_t le32_t;
-typedef uint32_t be32_t;
-typedef int64_t S64; //!< 64-bit signed integer.
-typedef uint64_t U64; //!< 64-bit unsigned integer.
-typedef float F32; //!< 32-bit floating-point number.
-typedef double F64; //!< 64-bit floating-point number.
-typedef uint32_t iram_size_t;
-//! @}
-
-
-/*! \name Status Types
- */
-//! @{
-typedef bool Status_bool_t; //!< Boolean status.
-typedef U8 Status_t; //!< 8-bit-coded status.
-//! @}
-
-
-/*! \name Aliasing Aggregate Types
- */
-//! @{
-
-//! 16-bit union.
-typedef union
-{
- S16 s16 ;
- U16 u16 ;
- S8 s8 [2];
- U8 u8 [2];
-} Union16;
-
-//! 32-bit union.
-typedef union
-{
- S32 s32 ;
- U32 u32 ;
- S16 s16[2];
- U16 u16[2];
- S8 s8 [4];
- U8 u8 [4];
-} Union32;
-
-//! 64-bit union.
-typedef union
-{
- S64 s64 ;
- U64 u64 ;
- S32 s32[2];
- U32 u32[2];
- S16 s16[4];
- U16 u16[4];
- S8 s8 [8];
- U8 u8 [8];
-} Union64;
-
-//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
-typedef union
-{
- S64 *s64ptr;
- U64 *u64ptr;
- S32 *s32ptr;
- U32 *u32ptr;
- S16 *s16ptr;
- U16 *u16ptr;
- S8 *s8ptr ;
- U8 *u8ptr ;
-} UnionPtr;
-
-//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
-typedef union
-{
- volatile S64 *s64ptr;
- volatile U64 *u64ptr;
- volatile S32 *s32ptr;
- volatile U32 *u32ptr;
- volatile S16 *s16ptr;
- volatile U16 *u16ptr;
- volatile S8 *s8ptr ;
- volatile U8 *u8ptr ;
-} UnionVPtr;
-
-//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
-typedef union
-{
- const S64 *s64ptr;
- const U64 *u64ptr;
- const S32 *s32ptr;
- const U32 *u32ptr;
- const S16 *s16ptr;
- const U16 *u16ptr;
- const S8 *s8ptr ;
- const U8 *u8ptr ;
-} UnionCPtr;
-
-//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
-typedef union
-{
- const volatile S64 *s64ptr;
- const volatile U64 *u64ptr;
- const volatile S32 *s32ptr;
- const volatile U32 *u32ptr;
- const volatile S16 *s16ptr;
- const volatile U16 *u16ptr;
- const volatile S8 *s8ptr ;
- const volatile U8 *u8ptr ;
-} UnionCVPtr;
-
-//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
-typedef struct
-{
- S64 *s64ptr;
- U64 *u64ptr;
- S32 *s32ptr;
- U32 *u32ptr;
- S16 *s16ptr;
- U16 *u16ptr;
- S8 *s8ptr ;
- U8 *u8ptr ;
-} StructPtr;
-
-//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
-typedef struct
-{
- volatile S64 *s64ptr;
- volatile U64 *u64ptr;
- volatile S32 *s32ptr;
- volatile U32 *u32ptr;
- volatile S16 *s16ptr;
- volatile U16 *u16ptr;
- volatile S8 *s8ptr ;
- volatile U8 *u8ptr ;
-} StructVPtr;
-
-//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
-typedef struct
-{
- const S64 *s64ptr;
- const U64 *u64ptr;
- const S32 *s32ptr;
- const U32 *u32ptr;
- const S16 *s16ptr;
- const U16 *u16ptr;
- const S8 *s8ptr ;
- const U8 *u8ptr ;
-} StructCPtr;
-
-//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
-typedef struct
-{
- const volatile S64 *s64ptr;
- const volatile U64 *u64ptr;
- const volatile S32 *s32ptr;
- const volatile U32 *u32ptr;
- const volatile S16 *s16ptr;
- const volatile U16 *u16ptr;
- const volatile S8 *s8ptr ;
- const volatile U8 *u8ptr ;
-} StructCVPtr;
-
-//! @}
-
-#endif // #ifndef __ASSEMBLY__
-
-/*! \name Usual Constants
- */
-//! @{
-#define DISABLE 0
-#define ENABLE 1
-#ifndef __cplusplus
-#if !defined(__bool_true_false_are_defined)
-#define false 0
-#define true 1
-#endif
-#endif
-#define PASS 0
-#define FAIL 1
-#define LOW 0
-#define HIGH 1
-//! @}
-
-
-#ifndef __ASSEMBLY__ // not for assembling.
-
-//! \name Optimization Control
-//@{
-
-/**
- * \def likely(exp)
- * \brief The expression \a exp is likely to be true
- */
-#ifndef likely
-# define likely(exp) (exp)
-#endif
-
-/**
- * \def unlikely(exp)
- * \brief The expression \a exp is unlikely to be true
- */
-#ifndef unlikely
-# define unlikely(exp) (exp)
-#endif
-
-/**
- * \def is_constant(exp)
- * \brief Determine if an expression evaluates to a constant value.
- *
- * \param exp Any expression
- *
- * \return true if \a exp is constant, false otherwise.
- */
-#if (defined __GNUC__) || (defined __CC_ARM)
-# define is_constant(exp) __builtin_constant_p(exp)
-#else
-# define is_constant(exp) (0)
-#endif
-
-//! @}
-
-/*! \name Bit-Field Handling
- */
-//! @{
-
-/*! \brief Reads the bits of a value specified by a given bit-mask.
- *
- * \param value Value to read bits from.
- * \param mask Bit-mask indicating bits to read.
- *
- * \return Read bits.
- */
-#define Rd_bits( value, mask) ((value) & (mask))
-
-/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.
- *
- * \param lvalue C lvalue to write bits to.
- * \param mask Bit-mask indicating bits to write.
- * \param bits Bits to write.
- *
- * \return Resulting value with written bits.
- */
-#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\
- ((bits ) & (mask)))
-
-/*! \brief Tests the bits of a value specified by a given bit-mask.
- *
- * \param value Value of which to test bits.
- * \param mask Bit-mask indicating bits to test.
- *
- * \return \c 1 if at least one of the tested bits is set, else \c 0.
- */
-#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0)
-
-/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.
- *
- * \param lvalue C lvalue of which to clear bits.
- * \param mask Bit-mask indicating bits to clear.
- *
- * \return Resulting value with cleared bits.
- */
-#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask))
-
-/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.
- *
- * \param lvalue C lvalue of which to set bits.
- * \param mask Bit-mask indicating bits to set.
- *
- * \return Resulting value with set bits.
- */
-#define Set_bits(lvalue, mask) ((lvalue) |= (mask))
-
-/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.
- *
- * \param lvalue C lvalue of which to toggle bits.
- * \param mask Bit-mask indicating bits to toggle.
- *
- * \return Resulting value with toggled bits.
- */
-#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask))
-
-/*! \brief Reads the bit-field of a value specified by a given bit-mask.
- *
- * \param value Value to read a bit-field from.
- * \param mask Bit-mask indicating the bit-field to read.
- *
- * \return Read bit-field.
- */
-#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask))
-
-/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
- *
- * \param lvalue C lvalue to write a bit-field to.
- * \param mask Bit-mask indicating the bit-field to write.
- * \param bitfield Bit-field to write.
- *
- * \return Resulting value with written bit-field.
- */
-#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))
-
-//! @}
-
-
-/*! \name Zero-Bit Counting
- *
- * Under GCC, __builtin_clz and __builtin_ctz behave like macros when
- * applied to constant expressions (values known at compile time), so they are
- * more optimized than the use of the corresponding assembly instructions and
- * they can be used as constant expressions e.g. to initialize objects having
- * static storage duration, and like the corresponding assembly instructions
- * when applied to non-constant expressions (values unknown at compile time), so
- * they are more optimized than an assembly periphrasis. Hence, clz and ctz
- * ensure a possible and optimized behavior for both constant and non-constant
- * expressions.
- */
-//! @{
-
-/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
- *
- * \param u Value of which to count the leading zero bits.
- *
- * \return The count of leading zero bits in \a u.
- */
-#if (defined __GNUC__) || (defined __CC_ARM)
-# define clz(u) ((u) ? __builtin_clz(u) : 32)
-#elif (defined __ICCARM__)
-# define clz(u) ((u) ? __CLZ(u) : 32)
-#else
-# define clz(u) (((u) == 0) ? 32 : \
- ((u) & (1ul << 31)) ? 0 : \
- ((u) & (1ul << 30)) ? 1 : \
- ((u) & (1ul << 29)) ? 2 : \
- ((u) & (1ul << 28)) ? 3 : \
- ((u) & (1ul << 27)) ? 4 : \
- ((u) & (1ul << 26)) ? 5 : \
- ((u) & (1ul << 25)) ? 6 : \
- ((u) & (1ul << 24)) ? 7 : \
- ((u) & (1ul << 23)) ? 8 : \
- ((u) & (1ul << 22)) ? 9 : \
- ((u) & (1ul << 21)) ? 10 : \
- ((u) & (1ul << 20)) ? 11 : \
- ((u) & (1ul << 19)) ? 12 : \
- ((u) & (1ul << 18)) ? 13 : \
- ((u) & (1ul << 17)) ? 14 : \
- ((u) & (1ul << 16)) ? 15 : \
- ((u) & (1ul << 15)) ? 16 : \
- ((u) & (1ul << 14)) ? 17 : \
- ((u) & (1ul << 13)) ? 18 : \
- ((u) & (1ul << 12)) ? 19 : \
- ((u) & (1ul << 11)) ? 20 : \
- ((u) & (1ul << 10)) ? 21 : \
- ((u) & (1ul << 9)) ? 22 : \
- ((u) & (1ul << 8)) ? 23 : \
- ((u) & (1ul << 7)) ? 24 : \
- ((u) & (1ul << 6)) ? 25 : \
- ((u) & (1ul << 5)) ? 26 : \
- ((u) & (1ul << 4)) ? 27 : \
- ((u) & (1ul << 3)) ? 28 : \
- ((u) & (1ul << 2)) ? 29 : \
- ((u) & (1ul << 1)) ? 30 : \
- 31)
-#endif
-
-/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
- *
- * \param u Value of which to count the trailing zero bits.
- *
- * \return The count of trailing zero bits in \a u.
- */
-#if (defined __GNUC__) || (defined __CC_ARM)
-# define ctz(u) ((u) ? __builtin_ctz(u) : 32)
-#else
-# define ctz(u) ((u) & (1ul << 0) ? 0 : \
- (u) & (1ul << 1) ? 1 : \
- (u) & (1ul << 2) ? 2 : \
- (u) & (1ul << 3) ? 3 : \
- (u) & (1ul << 4) ? 4 : \
- (u) & (1ul << 5) ? 5 : \
- (u) & (1ul << 6) ? 6 : \
- (u) & (1ul << 7) ? 7 : \
- (u) & (1ul << 8) ? 8 : \
- (u) & (1ul << 9) ? 9 : \
- (u) & (1ul << 10) ? 10 : \
- (u) & (1ul << 11) ? 11 : \
- (u) & (1ul << 12) ? 12 : \
- (u) & (1ul << 13) ? 13 : \
- (u) & (1ul << 14) ? 14 : \
- (u) & (1ul << 15) ? 15 : \
- (u) & (1ul << 16) ? 16 : \
- (u) & (1ul << 17) ? 17 : \
- (u) & (1ul << 18) ? 18 : \
- (u) & (1ul << 19) ? 19 : \
- (u) & (1ul << 20) ? 20 : \
- (u) & (1ul << 21) ? 21 : \
- (u) & (1ul << 22) ? 22 : \
- (u) & (1ul << 23) ? 23 : \
- (u) & (1ul << 24) ? 24 : \
- (u) & (1ul << 25) ? 25 : \
- (u) & (1ul << 26) ? 26 : \
- (u) & (1ul << 27) ? 27 : \
- (u) & (1ul << 28) ? 28 : \
- (u) & (1ul << 29) ? 29 : \
- (u) & (1ul << 30) ? 30 : \
- (u) & (1ul << 31) ? 31 : \
- 32)
-#endif
-
-//! @}
-
-
-/*! \name Bit Reversing
- */
-//! @{
-
-/*! \brief Reverses the bits of \a u8.
- *
- * \param u8 U8 of which to reverse the bits.
- *
- * \return Value resulting from \a u8 with reversed bits.
- */
-#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24))
-
-/*! \brief Reverses the bits of \a u16.
- *
- * \param u16 U16 of which to reverse the bits.
- *
- * \return Value resulting from \a u16 with reversed bits.
- */
-#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16))
-
-/*! \brief Reverses the bits of \a u32.
- *
- * \param u32 U32 of which to reverse the bits.
- *
- * \return Value resulting from \a u32 with reversed bits.
- */
-#define bit_reverse32(u32) __RBIT(u32)
-
-/*! \brief Reverses the bits of \a u64.
- *
- * \param u64 U64 of which to reverse the bits.
- *
- * \return Value resulting from \a u64 with reversed bits.
- */
-#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\
- ((U64)bit_reverse32((U64)(u64)) << 32)))
-
-//! @}
-
-
-/*! \name Alignment
- */
-//! @{
-
-/*! \brief Tests alignment of the number \a val with the \a n boundary.
- *
- * \param val Input value.
- * \param n Boundary.
- *
- * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.
- */
-#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) )
-
-/*! \brief Gets alignment of the number \a val with respect to the \a n boundary.
- *
- * \param val Input value.
- * \param n Boundary.
- *
- * \return Alignment of the number \a val with respect to the \a n boundary.
- */
-#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) )
-
-/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.
- *
- * \param lval Input/output lvalue.
- * \param n Boundary.
- * \param alg Alignment.
- *
- * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.
- */
-#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) )
-
-/*! \brief Aligns the number \a val with the upper \a n boundary.
- *
- * \param val Input value.
- * \param n Boundary.
- *
- * \return Value resulting from the number \a val aligned with the upper \a n boundary.
- */
-#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1))
-
-/*! \brief Aligns the number \a val with the lower \a n boundary.
- *
- * \param val Input value.
- * \param n Boundary.
- *
- * \return Value resulting from the number \a val aligned with the lower \a n boundary.
- */
-#define Align_down(val, n ) ( (val) & ~((n) - 1))
-
-//! @}
-
-
-/*! \name Mathematics
- *
- * The same considerations as for clz and ctz apply here but GCC does not
- * provide built-in functions to access the assembly instructions abs, min and
- * max and it does not produce them by itself in most cases, so two sets of
- * macros are defined here:
- * - Abs, Min and Max to apply to constant expressions (values known at
- * compile time);
- * - abs, min and max to apply to non-constant expressions (values unknown at
- * compile time), abs is found in stdlib.h.
- */
-//! @{
-
-/*! \brief Takes the absolute value of \a a.
- *
- * \param a Input value.
- *
- * \return Absolute value of \a a.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Abs(a) (((a) < 0 ) ? -(a) : (a))
-
-/*! \brief Takes the minimal value of \a a and \a b.
- *
- * \param a Input value.
- * \param b Input value.
- *
- * \return Minimal value of \a a and \a b.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Min(a, b) (((a) < (b)) ? (a) : (b))
-
-/*! \brief Takes the maximal value of \a a and \a b.
- *
- * \param a Input value.
- * \param b Input value.
- *
- * \return Maximal value of \a a and \a b.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Max(a, b) (((a) > (b)) ? (a) : (b))
-
-// abs() is already defined by stdlib.h
-
-/*! \brief Takes the minimal value of \a a and \a b.
- *
- * \param a Input value.
- * \param b Input value.
- *
- * \return Minimal value of \a a and \a b.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#define min(a, b) Min(a, b)
-
-/*! \brief Takes the maximal value of \a a and \a b.
- *
- * \param a Input value.
- * \param b Input value.
- *
- * \return Maximal value of \a a and \a b.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#define max(a, b) Max(a, b)
-
-//! @}
-
-
-/*! \brief Calls the routine at address \a addr.
- *
- * It generates a long call opcode.
- *
- * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if
- * it is invoked from the CPU supervisor mode.
- *
- * \param addr Address of the routine to call.
- *
- * \note It may be used as a long jump opcode in some special cases.
- */
-#define Long_call(addr) ((*(void (*)(void))(addr))())
-
-
-/*! \name MCU Endianism Handling
- * ARM is MCU little endianism.
- */
-//! @{
-#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.
-#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.
-
-#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.
-#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.
-#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.
-#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.
-#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.
-#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.
-#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.
-#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.
-#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.
-#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.
-
-#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.
-#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.
-#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.
-#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.
-#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.
-#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.
-#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.
-#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.
-#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.
-#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.
-#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.
-#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.
-#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.
-#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.
-#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.
-#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.
-#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.
-#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.
-#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.
-#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.
-#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.
-#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.
-#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.
-#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.
-#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.
-#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.
-
-#define BE16(x) swap16(x)
-#define LE16(x) (x)
-
-#define le16_to_cpu(x) (x)
-#define cpu_to_le16(x) (x)
-#define LE16_TO_CPU(x) (x)
-#define CPU_TO_LE16(x) (x)
-
-#define be16_to_cpu(x) swap16(x)
-#define cpu_to_be16(x) swap16(x)
-#define BE16_TO_CPU(x) swap16(x)
-#define CPU_TO_BE16(x) swap16(x)
-
-#define le32_to_cpu(x) (x)
-#define cpu_to_le32(x) (x)
-#define LE32_TO_CPU(x) (x)
-#define CPU_TO_LE32(x) (x)
-
-#define be32_to_cpu(x) swap32(x)
-#define cpu_to_be32(x) swap32(x)
-#define BE32_TO_CPU(x) swap32(x)
-#define CPU_TO_BE32(x) swap32(x)
-//! @}
-
-
-/*! \name Endianism Conversion
- *
- * The same considerations as for clz and ctz apply here but GCC's
- * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when
- * applied to constant expressions, so two sets of macros are defined here:
- * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known
- * at compile time);
- * - swap16, swap32 and swap64 to apply to non-constant expressions (values
- * unknown at compile time).
- */
-//! @{
-
-/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
- *
- * \param u16 U16 of which to toggle the endianism.
- *
- * \return Value resulting from \a u16 with toggled endianism.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\
- ((U16)(u16) << 8)))
-
-/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
- *
- * \param u32 U32 of which to toggle the endianism.
- *
- * \return Value resulting from \a u32 with toggled endianism.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\
- ((U32)Swap16((U32)(u32)) << 16)))
-
-/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
- *
- * \param u64 U64 of which to toggle the endianism.
- *
- * \return Value resulting from \a u64 with toggled endianism.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\
- ((U64)Swap32((U64)(u64)) << 32)))
-
-/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
- *
- * \param u16 U16 of which to toggle the endianism.
- *
- * \return Value resulting from \a u16 with toggled endianism.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#define swap16(u16) Swap16(u16)
-
-/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
- *
- * \param u32 U32 of which to toggle the endianism.
- *
- * \return Value resulting from \a u32 with toggled endianism.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#if (defined __GNUC__)
-# define swap32(u32) ((U32)__builtin_bswap32((U32)(u32)))
-#else
-# define swap32(u32) Swap32(u32)
-#endif
-
-/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
- *
- * \param u64 U64 of which to toggle the endianism.
- *
- * \return Value resulting from \a u64 with toggled endianism.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#if (defined __GNUC__)
-# define swap64(u64) ((U64)__builtin_bswap64((U64)(u64)))
-#else
-# define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\
- ((U64)swap32((U64)(u64)) << 32)))
-#endif
-
-//! @}
-
-
-/*! \name Target Abstraction
- */
-//! @{
-
-#define _GLOBEXT_ extern //!< extern storage-class specifier.
-#define _CONST_TYPE_ const //!< const type qualifier.
-#define _MEM_TYPE_SLOW_ //!< Slow memory type.
-#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type.
-#define _MEM_TYPE_FAST_ //!< Fast memory type.
-
-typedef U8 Byte; //!< 8-bit unsigned integer.
-
-#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM.
-#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM.
-#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM.
-#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM.
-
-#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.
-#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.
-#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.
-#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.
-#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.
-#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.
-#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.
-#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.
-
-//! @}
-
-/**
- * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using
- * integer arithmetic.
- *
- * \param a An integer
- * \param b Another integer
- *
- * \return (\a a / \a b) rounded up to the nearest integer.
- */
-#define div_ceil(a, b) (((a) + (b) - 1) / (b))
-
-#endif // #ifndef __ASSEMBLY__
-
-
-#if defined(__ICCARM__)
-#define SHORTENUM __packed
-#elif defined(__GNUC__)
-#define SHORTENUM __attribute__((packed))
-#endif
-
-/* No operation */
-#if defined(__ICCARM__)
-#define nop() __no_operation()
-#elif defined(__GNUC__)
-#define nop() (__NOP())
-#endif
-
-#define FLASH_DECLARE(x) const x
-#define FLASH_EXTERN(x) extern const x
-#define PGM_READ_BYTE(x) *(x)
-#define PGM_READ_WORD(x) *(x)
-#define PGM_READ_DWORD(x) *(x)
-#define MEMCPY_ENDIAN memcpy
-#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len))
-
-/*Defines the Flash Storage for the request and response of MAC*/
-#define CMD_ID_OCTET (0)
-
-/* Converting of values from CPU endian to little endian. */
-#define CPU_ENDIAN_TO_LE16(x) (x)
-#define CPU_ENDIAN_TO_LE32(x) (x)
-#define CPU_ENDIAN_TO_LE64(x) (x)
-
-/* Converting of values from little endian to CPU endian. */
-#define LE16_TO_CPU_ENDIAN(x) (x)
-#define LE32_TO_CPU_ENDIAN(x) (x)
-#define LE64_TO_CPU_ENDIAN(x) (x)
-
-/* Converting of constants from little endian to CPU endian. */
-#define CLE16_TO_CPU_ENDIAN(x) (x)
-#define CLE32_TO_CPU_ENDIAN(x) (x)
-#define CLE64_TO_CPU_ENDIAN(x) (x)
-
-/* Converting of constants from CPU endian to little endian. */
-#define CCPU_ENDIAN_TO_LE16(x) (x)
-#define CCPU_ENDIAN_TO_LE32(x) (x)
-#define CCPU_ENDIAN_TO_LE64(x) (x)
-
-#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src))
-#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src))
-
-/**
- * @brief Converts a 64-Bit value into a 8 Byte array
- *
- * @param[in] value 64-Bit value
- * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value
- * @ingroup apiPalApi
- */
-static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data)
-{
- uint8_t val_index = 0;
-
- while (val_index < 8)
- {
- data[val_index++] = value & 0xFF;
- value = value >> 8;
- }
-}
-
-/**
- * @brief Converts a 16-Bit value into a 2 Byte array
- *
- * @param[in] value 16-Bit value
- * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value
- * @ingroup apiPalApi
- */
-static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data)
-{
- data[0] = value & 0xFF;
- data[1] = (value >> 8) & 0xFF;
-}
-
-/* Converts a 16-Bit value into a 2 Byte array */
-static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data)
-{
- data[0] = value & 0xFF;
- data[1] = (value >> 8) & 0xFF;
-}
-
-/* Converts a 16-Bit value into a 2 Byte array */
-static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data)
-{
- data[0] = value & 0xFF;
- data[1] = (value >> 8) & 0xFF;
-}
-
-/*
- * @brief Converts a 2 Byte array into a 16-Bit value
- *
- * @param data Specifies the pointer to the 2 Byte array
- *
- * @return 16-Bit value
- * @ingroup apiPalApi
- */
-static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data)
-{
- return (data[0] | ((uint16_t)data[1] << 8));
-}
-
-/* Converts a 8 Byte array into a 32-Bit value */
-static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data)
-{
- union
- {
- uint32_t u32;
- uint8_t u8[8];
- }long_addr;
- uint8_t index;
- for (index = 0; index < 4; index++)
- {
- long_addr.u8[index] = *data++;
- }
- return long_addr.u32;
-}
-
-/**
- * @brief Converts a 8 Byte array into a 64-Bit value
- *
- * @param data Specifies the pointer to the 8 Byte array
- *
- * @return 64-Bit value
- * @ingroup apiPalApi
- */
-static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data)
-{
- union
- {
- uint64_t u64;
- uint8_t u8[8];
- } long_addr;
-
- uint8_t val_index;
-
- for (val_index = 0; val_index < 8; val_index++)
- {
- long_addr.u8[val_index] = *data++;
- }
-
- return long_addr.u64;
-}
-/**
- * \}
- */
-
-#endif /* UTILS_COMPILER_H */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/fpu/fpu.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/fpu/fpu.h
deleted file mode 100644
index 763089d..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/fpu/fpu.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/**
- * \file
- *
- * \brief FPU support for SAM.
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _FPU_H_INCLUDED_
-#define _FPU_H_INCLUDED_
-
-#include <compiler.h>
-
-/** Address for ARM CPACR */
-#define ADDR_CPACR 0xE000ED88
-
-/** CPACR Register */
-#define REG_CPACR (*((volatile uint32_t *)ADDR_CPACR))
-
-/**
- * \brief Enable FPU
- */
-__always_inline static void fpu_enable(void)
-{
- irqflags_t flags;
- flags = cpu_irq_save();
- REG_CPACR |= (0xFu << 20);
- __DSB();
- __ISB();
- cpu_irq_restore(flags);
-}
-
-/**
- * \brief Disable FPU
- */
-__always_inline static void fpu_disable(void)
-{
- irqflags_t flags;
- flags = cpu_irq_save();
- REG_CPACR &= ~(0xFu << 20);
- __DSB();
- __ISB();
- cpu_irq_restore(flags);
-}
-
-/**
- * \brief Check if FPU is enabled
- *
- * \return Return ture if FPU is enabled, otherwise return false.
- */
-__always_inline static bool fpu_is_enabled(void)
-{
- return (REG_CPACR & (0xFu << 20));
-}
-
-#endif /* _FPU_H_INCLUDED_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/header_files/io.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/header_files/io.h
deleted file mode 100644
index a79c646..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/header_files/io.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/**
- * \file
- *
- * \brief Arch file for SAM.
- *
- * This file defines common SAM series.
- *
- * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAM_IO_
-#define _SAM_IO_
-
-/* SAM3 family */
-
-/* SAM3S series */
-#if (SAM3S)
-# if (SAM3S8 || SAM3SD8)
-# include "sam3s8.h"
-# else
-# include "sam3s.h"
-# endif
-#endif
-
-/* SAM3U series */
-#if (SAM3U)
-# include "sam3u.h"
-#endif
-
-/* SAM3N series */
-#if (SAM3N)
-# include "sam3n.h"
-#endif
-
-/* SAM3XA series */
-#if (SAM3XA)
-# include "sam3xa.h"
-#endif
-
-/* SAM4S series */
-#if (SAM4S)
-# include "sam4s.h"
-#endif
-
-/* SAM4L series */
-#if (SAM4L)
-# include "sam4l.h"
-#endif
-
-/* SAM4E series */
-#if (SAM4E)
-# include "sam4e.h"
-#endif
-
-/* SAM4N series */
-#if (SAM4N)
-# include "sam4n.h"
-#endif
-
-/* SAM4C series */
-#if (SAM4C)
-# include "sam4c.h"
-#endif
-
-/* SAM4CM series */
-#if (SAM4CM)
-# if (SAM4CMP32 || SAM4CMS32)
-# include "sam4cm32.h"
-# else
-# include "sam4cm.h"
-# endif
-#endif
-
-/* SAM4CP series */
-#if (SAM4CP)
-# include "sam4cp.h"
-#endif
-
-/* SAMG51 series */
-#if (SAMG51)
-# include "samg51.h"
-#endif
-
-/* SAMG53 series */
-#if (SAMG53)
-# include "samg53.h"
-#endif
-
-/* SAMG54 series */
-#if (SAMG54)
-# include "samg54.h"
-#endif
-
-/* SAMG55 series */
-#if (SAMG55)
-# include "samg55.h"
-#endif
-
-/* SAMV71 series */
-#if (SAMV71)
-# include "samv71.h"
-#endif
-
-/* SAMV70 series */
-#if (SAMV70)
-# include "samv70.h"
-#endif
-
-/* SAME70 series */
-#if (SAME70)
-# include "same70.h"
-#endif
-
-/* SAMS70 series */
-#if (SAMS70)
-# include "sams70.h"
-#endif
-
-#endif /* _SAM_IO_ */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/linker_scripts/sams70/sams70n20/gcc/flash.ld b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/linker_scripts/sams70/sams70n20/gcc/flash.ld
deleted file mode 100644
index cb4537d..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/linker_scripts/sams70/sams70n20/gcc/flash.ld
+++ /dev/null
@@ -1,174 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*------------------------------------------------------------------------------
- * Linker script for running in internal FLASH on the ATSAMS70N20
- *----------------------------------------------------------------------------*/
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
- rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000
- ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000;
-__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;
-
-/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
-HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200;
-
-/* Section Definitions */
-SECTIONS
-{
- .text :
- {
- . = ALIGN(4);
- _sfixed = .;
- KEEP(*(.vectors .vectors.*))
- *(.text .text.* .gnu.linkonce.t.*)
- *(.glue_7t) *(.glue_7)
- *(.rodata .rodata* .gnu.linkonce.r.*)
- *(.ARM.extab* .gnu.linkonce.armextab.*)
-
- /* Support C constructors, and C destructors in both user code
- and the C library. This also provides support for C++ code. */
- . = ALIGN(4);
- KEEP(*(.init))
- . = ALIGN(4);
- __preinit_array_start = .;
- KEEP (*(.preinit_array))
- __preinit_array_end = .;
-
- . = ALIGN(4);
- __init_array_start = .;
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array))
- __init_array_end = .;
-
- . = ALIGN(0x4);
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*crtend.o(.ctors))
-
- . = ALIGN(4);
- KEEP(*(.fini))
-
- . = ALIGN(4);
- __fini_array_start = .;
- KEEP (*(.fini_array))
- KEEP (*(SORT(.fini_array.*)))
- __fini_array_end = .;
-
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*crtend.o(.dtors))
-
- . = ALIGN(4);
- _efixed = .; /* End of text section */
- } > rom
-
- /* .ARM.exidx is sorted, so has to go in its own output section. */
- PROVIDE_HIDDEN (__exidx_start = .);
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > rom
- PROVIDE_HIDDEN (__exidx_end = .);
-
- . = ALIGN(4);
- _etext = .;
-
- .relocate : AT (_etext)
- {
- . = ALIGN(4);
- _srelocate = .;
- *(.ramfunc .ramfunc.*);
- *(.data .data.*);
- . = ALIGN(4);
- _erelocate = .;
- } > ram
-
- /* .bss section which is used for uninitialized data */
- .bss (NOLOAD) :
- {
- . = ALIGN(4);
- _sbss = . ;
- _szero = .;
- *(.bss .bss.*)
- *(COMMON)
- . = ALIGN(4);
- _ebss = . ;
- _ezero = .;
- } > ram
-
- /* stack section */
- .stack (NOLOAD):
- {
- . = ALIGN(8);
- _sstack = .;
- . = . + STACK_SIZE;
- . = ALIGN(8);
- _estack = .;
- } > ram
-
- /* heap section */
- .heap (NOLOAD):
- {
- . = ALIGN(8);
- _sheap = .;
- . = . + HEAP_SIZE;
- . = ALIGN(8);
- _eheap = .;
- } > ram
-
- . = ALIGN(4);
- _end = . ;
- _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ;
-}
-
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/make/Makefile.sam.in b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/make/Makefile.sam.in
deleted file mode 100644
index 23c6697..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/make/Makefile.sam.in
+++ /dev/null
@@ -1,496 +0,0 @@
-# List of available make goals:
-#
-# all Default target, builds the project
-# clean Clean up the project
-# rebuild Rebuild the project
-# debug_flash Builds the project and debug in flash
-# debug_sram Builds the project and debug in sram
-#
-# doc Build the documentation
-# cleandoc Clean up the documentation
-# rebuilddoc Rebuild the documentation
-#
-# \file
-#
-# Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved.
-#
-# \asf_license_start
-#
-# \page License
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# 3. The name of Atmel may not be used to endorse or promote products derived
-# from this software without specific prior written permission.
-#
-# 4. This software may only be redistributed and used in connection with an
-# Atmel microcontroller product.
-#
-# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
-# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
-# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-# \asf_license_stop
-#
-
-# Include the config.mk file from the current working path, e.g., where the
-# user called make.
-include config.mk
-
-# Tool to use to generate documentation from the source code
-DOCGEN ?= doxygen
-
-# Look for source files relative to the top-level source directory
-VPATH := $(PRJ_PATH)
-
-# Output target file
-project_type := $(PROJECT_TYPE)
-
-# Output target file
-ifeq ($(project_type),flash)
-target := $(TARGET_FLASH)
-linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH)
-debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)
-else
-target := $(TARGET_SRAM)
-linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM)
-debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)
-endif
-
-# Output project name (target name minus suffix)
-project := $(basename $(target))
-
-# Output target file (typically ELF or static library)
-ifeq ($(suffix $(target)),.a)
-target_type := lib
-else
-ifeq ($(suffix $(target)),.elf)
-target_type := elf
-else
-$(error "Target type $(target_type) is not supported")
-endif
-endif
-
-# Allow override of operating system detection. The user can add OS=Linux or
-# OS=Windows on the command line to explicit set the host OS.
-#
-# This allows to work around broken uname utility on certain systems.
-ifdef OS
- ifeq ($(strip $(OS)), Linux)
- os_type := Linux
- endif
- ifeq ($(strip $(OS)), Windows)
- os_type := windows32_64
- endif
-endif
-
-os_type ?= $(strip $(shell uname))
-
-ifeq ($(os_type),windows32)
-os := Windows
-else
-ifeq ($(os_type),windows64)
-os := Windows
-else
-ifeq ($(os_type),windows32_64)
-os ?= Windows
-else
-ifeq ($(os_type),)
-os := Windows
-else
-# Default to Linux style operating system. Both Cygwin and mingw are fully
-# compatible (for this Makefile) with Linux.
-os := Linux
-endif
-endif
-endif
-endif
-
-# Output documentation directory and configuration file.
-docdir := ../doxygen/html
-doccfg := ../doxygen/doxyfile.doxygen
-
-CROSS ?= arm-none-eabi-
-AR := $(CROSS)ar
-AS := $(CROSS)as
-CC := $(CROSS)gcc
-CPP := $(CROSS)gcc -E
-CXX := $(CROSS)g++
-LD := $(CROSS)g++
-NM := $(CROSS)nm
-OBJCOPY := $(CROSS)objcopy
-OBJDUMP := $(CROSS)objdump
-SIZE := $(CROSS)size
-GDB := $(CROSS)gdb
-
-RM := rm
-ifeq ($(os),Windows)
-RMDIR := rmdir /S /Q
-else
-RMDIR := rmdir -p --ignore-fail-on-non-empty
-endif
-
-# On Windows, we need to override the shell to force the use of cmd.exe
-ifeq ($(os),Windows)
-SHELL := cmd
-endif
-
-# Strings for beautifying output
-MSG_CLEAN_FILES = "RM *.o *.d"
-MSG_CLEAN_DIRS = "RMDIR $(strip $(clean-dirs))"
-MSG_CLEAN_DOC = "RMDIR $(docdir)"
-MSG_MKDIR = "MKDIR $(dir $@)"
-
-MSG_INFO = "INFO "
-MSG_PREBUILD = "PREBUILD $(PREBUILD_CMD)"
-MSG_POSTBUILD = "POSTBUILD $(POSTBUILD_CMD)"
-
-MSG_ARCHIVING = "AR $@"
-MSG_ASSEMBLING = "AS $@"
-MSG_BINARY_IMAGE = "OBJCOPY $@"
-MSG_COMPILING = "CC $@"
-MSG_COMPILING_CXX = "CXX $@"
-MSG_EXTENDED_LISTING = "OBJDUMP $@"
-MSG_IHEX_IMAGE = "OBJCOPY $@"
-MSG_LINKING = "LN $@"
-MSG_PREPROCESSING = "CPP $@"
-MSG_SIZE = "SIZE $@"
-MSG_SYMBOL_TABLE = "NM $@"
-
-MSG_GENERATING_DOC = "DOXYGEN $(docdir)"
-
-# Don't use make's built-in rules and variables
-MAKEFLAGS += -rR
-
-# Don't print 'Entering directory ...'
-MAKEFLAGS += --no-print-directory
-
-# Function for reversing the order of a list
-reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1))
-
-# Hide command output by default, but allow the user to override this
-# by adding V=1 on the command line.
-#
-# This is inspired by the Kbuild system used by the Linux kernel.
-ifdef V
- ifeq ("$(origin V)", "command line")
- VERBOSE = $(V)
- endif
-endif
-ifndef VERBOSE
- VERBOSE = 0
-endif
-
-ifeq ($(VERBOSE), 1)
- Q =
-else
- Q = @
-endif
-
-arflags-gnu-y := $(ARFLAGS)
-asflags-gnu-y := $(ASFLAGS)
-cflags-gnu-y := $(CFLAGS)
-cxxflags-gnu-y := $(CXXFLAGS)
-cppflags-gnu-y := $(CPPFLAGS)
-cpuflags-gnu-y :=
-dbgflags-gnu-y := $(DBGFLAGS)
-libflags-gnu-y := $(foreach LIB,$(LIBS),-l$(LIB))
-ldflags-gnu-y := $(LDFLAGS)
-flashflags-gnu-y :=
-clean-files :=
-clean-dirs :=
-
-clean-files += $(wildcard $(target) $(project).map)
-clean-files += $(wildcard $(project).hex $(project).bin)
-clean-files += $(wildcard $(project).lss $(project).sym)
-clean-files += $(wildcard $(build))
-
-# Use pipes instead of temporary files for communication between processes
-cflags-gnu-y += -pipe
-asflags-gnu-y += -pipe
-ldflags-gnu-y += -pipe
-
-# Archiver flags.
-arflags-gnu-y += rcs
-
-# Always enable warnings. And be very careful about implicit
-# declarations.
-cflags-gnu-y += -Wall -Wstrict-prototypes -Wmissing-prototypes
-cflags-gnu-y += -Werror-implicit-function-declaration
-cxxflags-gnu-y += -Wall
-# IAR doesn't allow arithmetic on void pointers, so warn about that.
-cflags-gnu-y += -Wpointer-arith
-cxxflags-gnu-y += -Wpointer-arith
-
-# Preprocessor flags.
-cppflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC))
-asflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)')
-
-# CPU specific flags.
-cpuflags-gnu-y += -mcpu=$(ARCH) -mthumb -D=__$(PART)__
-
-# Dependency file flags.
-depflags = -MD -MP -MQ $@
-
-# Debug specific flags.
-ifdef BUILD_DEBUG_LEVEL
-dbgflags-gnu-y += -g$(BUILD_DEBUG_LEVEL)
-else
-dbgflags-gnu-y += -g3
-endif
-
-# Optimization specific flags.
-ifdef BUILD_OPTIMIZATION
-optflags-gnu-y = -O$(BUILD_OPTIMIZATION)
-else
-optflags-gnu-y = $(OPTIMIZATION)
-endif
-
-# Always preprocess assembler files.
-asflags-gnu-y += -x assembler-with-cpp
-# Compile C files using the GNU99 standard.
-cflags-gnu-y += -std=gnu99
-# Compile C++ files using the GNU++98 standard.
-cxxflags-gnu-y += -std=gnu++98
-
-# Don't use strict aliasing (very common in embedded applications).
-cflags-gnu-y += -fno-strict-aliasing
-cxxflags-gnu-y += -fno-strict-aliasing
-
-# Separate each function and data into its own separate section to allow
-# garbage collection of unused sections.
-cflags-gnu-y += -ffunction-sections -fdata-sections
-cxxflags-gnu-y += -ffunction-sections -fdata-sections
-
-# Various cflags.
-cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
-cflags-gnu-y += -Wmain -Wparentheses
-cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
-cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
-cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings
-cflags-gnu-y += -Wsign-compare -Waggregate-return
-cflags-gnu-y += -Wmissing-declarations
-cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
-cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long
-cflags-gnu-y += -Wunreachable-code
-cflags-gnu-y += -Wcast-align
-cflags-gnu-y += --param max-inline-insns-single=500
-
-# Garbage collect unreferred sections when linking.
-ldflags-gnu-y += -Wl,--gc-sections
-
-# Use the linker script if provided by the project.
-ifneq ($(strip $(linker_script)),)
-ldflags-gnu-y += -Wl,-T $(linker_script)
-endif
-
-# Output a link map file and a cross reference table
-ldflags-gnu-y += -Wl,-Map=$(project).map,--cref
-
-# Add library search paths relative to the top level directory.
-ldflags-gnu-y += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH))
-
-a_flags = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__
-c_flags = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y)
-cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y)
-l_flags = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y)
-ar_flags = $(arflags-gnu-y)
-
-# Source files list and part informations must already be included before
-# running this makefile
-
-# If a custom build directory is specified, use it -- force trailing / in directory name.
-ifdef BUILD_DIR
- build-dir := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/)
-else
- build-dir =
-endif
-
-# Create object files list from source files list.
-obj-y := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS))))
-# Create dependency files list from source files list.
-dep-files := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d))
-
-clean-files += $(wildcard $(obj-y))
-clean-files += $(dep-files)
-
-clean-dirs += $(call reverse,$(sort $(wildcard $(dir $(obj-y)))))
-
-# Default target.
-.PHONY: all
-ifeq ($(project_type),all)
-all:
- $(MAKE) all PROJECT_TYPE=flash
- $(MAKE) all PROJECT_TYPE=sram
-else
-ifeq ($(target_type),lib)
-all: $(target) $(project).lss $(project).sym
-else
-ifeq ($(target_type),elf)
-all: prebuild $(target) $(project).lss $(project).sym $(project).hex $(project).bin postbuild
-endif
-endif
-endif
-
-prebuild:
-ifneq ($(strip $(PREBUILD_CMD)),)
- @echo $(MSG_PREBUILD)
- $(Q)$(PREBUILD_CMD)
-endif
-
-postbuild:
-ifneq ($(strip $(POSTBUILD_CMD)),)
- @echo $(MSG_POSTBUILD)
- $(Q)$(POSTBUILD_CMD)
-endif
-
-# Clean up the project.
-.PHONY: clean
-clean:
- @$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES))
- $(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),)
- @$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS))
-# Remove created directories, and make sure we only remove existing
-# directories, since recursive rmdir might help us a bit on the way.
-ifeq ($(os),Windows)
- $(Q)$(if $(strip $(clean-dirs)), \
- $(RMDIR) $(strip $(subst /,\,$(clean-dirs))))
-else
- $(Q)$(if $(strip $(clean-dirs)), \
- for directory in $(strip $(clean-dirs)); do \
- if [ -d "$$directory" ]; then \
- $(RMDIR) $$directory; \
- fi \
- done \
- )
-endif
-
-# Rebuild the project.
-.PHONY: rebuild
-rebuild: clean all
-
-# Debug the project in flash.
-.PHONY: debug_flash
-debug_flash: all
- $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH)
-
-# Debug the project in sram.
-.PHONY: debug_sram
-debug_sram: all
- $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM)
-
-.PHONY: objfiles
-objfiles: $(obj-y)
-
-# Create object files from C source files.
-$(build-dir)%.o: %.c $(MAKEFILE_PATH) config.mk
- $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
-ifeq ($(os),Windows)
- $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
-else
- $(Q)test -d $(dir $@) || mkdir -p $(dir $@)
-endif
- @echo $(MSG_COMPILING)
- $(Q)$(CC) $(c_flags) -c $< -o $@
-
-# Create object files from C++ source files.
-$(build-dir)%.o: %.cpp $(MAKEFILE_PATH) config.mk
- $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
-ifeq ($(os),Windows)
- $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
-else
- $(Q)test -d $(dir $@) || mkdir -p $(dir $@)
-endif
- @echo $(MSG_COMPILING_CXX)
- $(Q)$(CXX) $(cxx_flags) -c $< -o $@
-
-# Preprocess and assemble: create object files from assembler source files.
-$(build-dir)%.o: %.S $(MAKEFILE_PATH) config.mk
- $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
-ifeq ($(os),Windows)
- $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
-else
- $(Q)test -d $(dir $@) || mkdir -p $(dir $@)
-endif
- @echo $(MSG_ASSEMBLING)
- $(Q)$(CC) $(a_flags) -c $< -o $@
-
-# Include all dependency files to add depedency to all header files in use.
-include $(dep-files)
-
-ifeq ($(target_type),lib)
-# Archive object files into an archive
-$(target): $(MAKEFILE_PATH) config.mk $(obj-y)
- @echo $(MSG_ARCHIVING)
- $(Q)$(AR) $(ar_flags) $@ $(obj-y)
- @echo $(MSG_SIZE)
- $(Q)$(SIZE) -Bxt $@
-else
-ifeq ($(target_type),elf)
-# Link the object files into an ELF file. Also make sure the target is rebuilt
-# if the common Makefile.sam.in or project config.mk is changed.
-$(target): $(linker_script) $(MAKEFILE_PATH) config.mk $(obj-y)
- @echo $(MSG_LINKING)
- $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@
- @echo $(MSG_SIZE)
- $(Q)$(SIZE) -Ax $@
- $(Q)$(SIZE) -Bx $@
-endif
-endif
-
-# Create extended function listing from target output file.
-%.lss: $(target)
- @echo $(MSG_EXTENDED_LISTING)
- $(Q)$(OBJDUMP) -h -S $< > $@
-
-# Create symbol table from target output file.
-%.sym: $(target)
- @echo $(MSG_SYMBOL_TABLE)
- $(Q)$(NM) -n $< > $@
-
-# Create Intel HEX image from ELF output file.
-%.hex: $(target)
- @echo $(MSG_IHEX_IMAGE)
- $(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y) $< $@
-
-# Create binary image from ELF output file.
-%.bin: $(target)
- @echo $(MSG_BINARY_IMAGE)
- $(Q)$(OBJCOPY) -O binary $< $@
-
-# Provide information about the detected host operating system.
-.SECONDARY: info-os
-info-os:
- @echo $(MSG_INFO)$(os) build host detected
-
-# Build Doxygen generated documentation.
-.PHONY: doc
-doc:
- @echo $(MSG_GENERATING_DOC)
- $(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg))
-
-# Clean Doxygen generated documentation.
-.PHONY: cleandoc
-cleandoc:
- @$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC))
- $(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir))
-
-# Rebuild the Doxygen generated documentation.
-.PHONY: rebuilddoc
-rebuilddoc: cleandoc doc
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/preprocessor/mrepeat.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/preprocessor/mrepeat.h
deleted file mode 100644
index 5a2017b..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/preprocessor/mrepeat.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/**
- * \file
- *
- * \brief Preprocessor macro repeating utils.
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _MREPEAT_H_
-#define _MREPEAT_H_
-
-/**
- * \defgroup group_sam_utils_mrepeat Preprocessor - Macro Repeat
- *
- * \ingroup group_sam_utils
- *
- * \{
- */
-
-#include "preprocessor.h"
-
-
-//! Maximal number of repetitions supported by MREPEAT.
-#define MREPEAT_LIMIT 256
-
-/*! \brief Macro repeat.
- *
- * This macro represents a horizontal repetition construct.
- *
- * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT.
- * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with
- * the current repetition number and the auxiliary data argument.
- * \param data Auxiliary data passed to macro.
- *
- * \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>
- */
-#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data)
-
-#define MREPEAT0( macro, data)
-#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data)
-#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data)
-#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data)
-#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data)
-#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data)
-#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data)
-#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data)
-#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data)
-#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data)
-#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data)
-#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data)
-#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data)
-#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data)
-#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data)
-#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data)
-#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data)
-#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data)
-#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data)
-#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data)
-#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data)
-#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data)
-#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data)
-#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data)
-#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data)
-#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data)
-#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data)
-#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data)
-#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data)
-#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data)
-#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data)
-#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data)
-#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data)
-#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data)
-#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data)
-#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data)
-#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data)
-#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data)
-#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data)
-#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data)
-#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data)
-#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data)
-#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data)
-#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data)
-#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data)
-#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data)
-#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data)
-#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data)
-#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data)
-#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data)
-#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data)
-#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data)
-#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data)
-#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data)
-#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data)
-#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data)
-#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data)
-#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data)
-#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data)
-#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data)
-#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data)
-#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data)
-#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data)
-#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data)
-#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data)
-#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data)
-#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data)
-#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data)
-#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data)
-#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data)
-#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data)
-#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data)
-#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data)
-#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data)
-#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data)
-#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data)
-#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data)
-#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data)
-#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data)
-#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data)
-#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data)
-#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data)
-#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data)
-#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data)
-#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data)
-#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data)
-#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data)
-#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data)
-#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data)
-#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data)
-#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data)
-#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data)
-#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data)
-#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data)
-#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data)
-#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data)
-#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data)
-#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data)
-#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data)
-#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data)
-#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data)
-#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data)
-#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data)
-#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data)
-#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data)
-#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data)
-#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data)
-#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data)
-#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data)
-#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data)
-#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data)
-#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data)
-#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data)
-#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data)
-#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data)
-#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data)
-#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data)
-#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data)
-#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data)
-#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data)
-#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data)
-#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data)
-#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data)
-#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data)
-#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data)
-#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data)
-#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data)
-#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data)
-#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data)
-#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data)
-#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data)
-#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data)
-#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data)
-#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data)
-#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data)
-#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data)
-#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data)
-#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data)
-#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data)
-#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data)
-#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data)
-#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data)
-#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data)
-#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data)
-#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data)
-#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data)
-#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data)
-#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data)
-#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data)
-#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data)
-#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data)
-#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data)
-#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data)
-#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data)
-#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data)
-#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data)
-#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data)
-#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data)
-#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data)
-#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data)
-#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data)
-#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data)
-#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data)
-#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data)
-#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data)
-#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data)
-#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data)
-#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data)
-#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data)
-#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data)
-#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data)
-#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data)
-#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data)
-#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data)
-#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data)
-#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data)
-#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data)
-#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data)
-#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data)
-#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data)
-#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data)
-#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data)
-#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data)
-#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data)
-#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data)
-#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data)
-#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data)
-#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data)
-#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data)
-#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data)
-#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data)
-#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data)
-#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data)
-#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data)
-#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data)
-#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data)
-#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data)
-#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data)
-#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data)
-#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data)
-#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data)
-#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data)
-#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data)
-#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data)
-#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data)
-#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data)
-#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data)
-#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data)
-#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data)
-#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data)
-#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data)
-#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data)
-#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data)
-#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data)
-#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data)
-#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data)
-#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data)
-#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data)
-#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data)
-#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data)
-#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data)
-#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data)
-#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data)
-#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data)
-#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data)
-#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data)
-#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data)
-#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data)
-#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data)
-#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data)
-#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data)
-#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data)
-#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data)
-#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data)
-#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data)
-#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data)
-#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data)
-#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data)
-#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data)
-#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data)
-#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data)
-#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data)
-#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data)
-#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data)
-#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data)
-#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data)
-#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data)
-#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data)
-#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data)
-#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data)
-#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data)
-#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data)
-#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data)
-#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data)
-#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data)
-#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)
-#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)
-
-/**
- * \}
- */
-
-#endif // _MREPEAT_H_
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/preprocessor/preprocessor.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/preprocessor/preprocessor.h
deleted file mode 100644
index 184c03a..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/preprocessor/preprocessor.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- * \file
- *
- * \brief Preprocessor utils.
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _PREPROCESSOR_H_
-#define _PREPROCESSOR_H_
-
-#include "tpaste.h"
-#include "stringz.h"
-#include "mrepeat.h"
-
-
-#endif // _PREPROCESSOR_H_
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/preprocessor/stringz.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/preprocessor/stringz.h
deleted file mode 100644
index b914b73..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/preprocessor/stringz.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * \brief Preprocessor stringizing utils.
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _STRINGZ_H_
-#define _STRINGZ_H_
-
-/**
- * \defgroup group_sam_utils_stringz Preprocessor - Stringize
- *
- * \ingroup group_sam_utils
- *
- * \{
- */
-
-/*! \brief Stringize.
- *
- * Stringize a preprocessing token, this token being allowed to be \#defined.
- *
- * May be used only within macros with the token passed as an argument if the token is \#defined.
- *
- * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
- * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
- * writing "A0".
- */
-#define STRINGZ(x) #x
-
-/*! \brief Absolute stringize.
- *
- * Stringize a preprocessing token, this token being allowed to be \#defined.
- *
- * No restriction of use if the token is \#defined.
- *
- * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
- * equivalent to writing "A0".
- */
-#define ASTRINGZ(x) STRINGZ(x)
-
-/**
- * \}
- */
-
-#endif // _STRINGZ_H_
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/preprocessor/tpaste.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/preprocessor/tpaste.h
deleted file mode 100644
index f8ec44a..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/preprocessor/tpaste.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/**
- * \file
- *
- * \brief Preprocessor token pasting utils.
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _TPASTE_H_
-#define _TPASTE_H_
-
-/**
- * \defgroup group_sam_utils_tpaste Preprocessor - Token Paste
- *
- * \ingroup group_sam_utils
- *
- * \{
- */
-
-/*! \name Token Paste
- *
- * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
- *
- * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.
- *
- * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by
- * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is
- * equivalent to writing U32.
- */
-//! @{
-#define TPASTE2( a, b) a##b
-#define TPASTE3( a, b, c) a##b##c
-#define TPASTE4( a, b, c, d) a##b##c##d
-#define TPASTE5( a, b, c, d, e) a##b##c##d##e
-#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f
-#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g
-#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h
-#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i
-#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j
-//! @}
-
-/*! \name Absolute Token Paste
- *
- * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
- *
- * No restriction of use if the tokens are \#defined.
- *
- * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined
- * as 32 is equivalent to writing U32.
- */
-//! @{
-#define ATPASTE2( a, b) TPASTE2( a, b)
-#define ATPASTE3( a, b, c) TPASTE3( a, b, c)
-#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d)
-#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e)
-#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f)
-#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g)
-#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h)
-#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i)
-#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)
-//! @}
-
-/**
- * \}
- */
-
-#endif // _TPASTE_H_
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/status_codes.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/status_codes.h
deleted file mode 100644
index d5e6dd6..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/status_codes.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/**
- * \file
- *
- * \brief Status code definitions.
- *
- * This file defines various status codes returned by functions,
- * indicating success or failure as well as what kind of failure.
- *
- * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef STATUS_CODES_H_INCLUDED
-#define STATUS_CODES_H_INCLUDED
-
-/* Note: this is a local workaround to avoid a pre-processor clash due to the
- * lwIP macro ERR_TIMEOUT. */
-#if defined(__LWIP_ERR_H__) && defined(ERR_TIMEOUT)
-#if (ERR_TIMEOUT != -3)
-
-/* Internal check to make sure that the later restore of lwIP's ERR_TIMEOUT
- * macro is set to the correct value. Note that it is highly improbable that
- * this value ever changes in lwIP. */
-#error ASF developers: check lwip err.h new value for ERR_TIMEOUT
-#endif
-#undef ERR_TIMEOUT
-#endif
-
-/**
- * Status code that may be returned by shell commands and protocol
- * implementations.
- *
- * \note Any change to these status codes and the corresponding
- * message strings is strictly forbidden. New codes can be added,
- * however, but make sure that any message string tables are updated
- * at the same time.
- */
-enum status_code {
- STATUS_OK = 0, //!< Success
- STATUS_ERR_BUSY = 0x19,
- STATUS_ERR_DENIED = 0x1C,
- STATUS_ERR_TIMEOUT = 0x12,
- ERR_IO_ERROR = -1, //!< I/O error
- ERR_FLUSHED = -2, //!< Request flushed from queue
- ERR_TIMEOUT = -3, //!< Operation timed out
- ERR_BAD_DATA = -4, //!< Data integrity check failed
- ERR_PROTOCOL = -5, //!< Protocol error
- ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device
- ERR_NO_MEMORY = -7, //!< Insufficient memory
- ERR_INVALID_ARG = -8, //!< Invalid argument
- ERR_BAD_ADDRESS = -9, //!< Bad address
- ERR_BUSY = -10, //!< Resource is busy
- ERR_BAD_FORMAT = -11, //!< Data format not recognized
- ERR_NO_TIMER = -12, //!< No timer available
- ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running
- ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running
- ERR_ABORTED = -15, //!< Operation aborted by user
- /**
- * \brief Operation in progress
- *
- * This status code is for driver-internal use when an operation
- * is currently being performed.
- *
- * \note Drivers should never return this status code to any
- * callers. It is strictly for internal use.
- */
- OPERATION_IN_PROGRESS = -128,
-};
-
-typedef enum status_code status_code_t;
-
-#if defined(__LWIP_ERR_H__)
-#define ERR_TIMEOUT -3
-#endif
-
-#endif /* STATUS_CODES_H_INCLUDED */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/syscalls/gcc/syscalls.c b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/syscalls/gcc/syscalls.c
deleted file mode 100644
index 9ec9d7e..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/sam/utils/syscalls/gcc/syscalls.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/**
- * \file
- *
- * \brief Syscalls for SAM (GCC).
- *
- * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-#undef errno
-extern int errno;
-extern int _end;
-extern int __ram_end__;
-
-extern caddr_t _sbrk(int incr);
-extern int link(char *old, char *new);
-extern int _close(int file);
-extern int _fstat(int file, struct stat *st);
-extern int _isatty(int file);
-extern int _lseek(int file, int ptr, int dir);
-extern void _exit(int status);
-extern void _kill(int pid, int sig);
-extern int _getpid(void);
-
-extern caddr_t _sbrk(int incr)
-{
- static unsigned char *heap = NULL;
- unsigned char *prev_heap;
- int ramend = (int)&__ram_end__;
-
- if (heap == NULL) {
- heap = (unsigned char *)&_end;
- }
- prev_heap = heap;
-
- if (((int)prev_heap + incr) > ramend) {
- return (caddr_t) -1;
- }
-
- heap += incr;
-
- return (caddr_t) prev_heap;
-}
-
-extern int link(char *old, char *new)
-{
- return -1;
-}
-
-extern int _close(int file)
-{
- return -1;
-}
-
-extern int _fstat(int file, struct stat *st)
-{
- st->st_mode = S_IFCHR;
-
- return 0;
-}
-
-extern int _isatty(int file)
-{
- return 1;
-}
-
-extern int _lseek(int file, int ptr, int dir)
-{
- return 0;
-}
-
-extern void _exit(int status)
-{
- asm("BKPT #0");
- for (;;);
-}
-
-extern void _kill(int pid, int sig)
-{
- return;
-}
-
-extern int _getpid(void)
-{
- return -1;
-}
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt
deleted file mode 100644
index 422f7fe..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Only the CMSIS required parts for ASF are included here, go to the below
- * address for the full package:
- * http://www.arm.com/products/processors/cortex-m/cortex-microcontroller-software-interface-standard.php
- *
- * The library file thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math_softfp.a was generated by ATMEL, which
- * is support -mfloat-abi=softfp compiler flag, and this is also the default selection for device that
- * have FPU module and enabled.
- * If customer want to use -mfloat-abi=hard compiler flag, the project compile/link flag and link library
- * should be manual modified. The library thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a is used for
- * -mfloat-abi=hard configration.
- *
- * __CORTEX_SC is not defined for cortex-m0+, and may cause compiler warning, so the include file
- * thirdparty/CMSIS/Include/core_cmInstr.h was modified to void such warning.
- * Modified from:
- * #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
- * to:
- * #if (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300))
- *
- */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf
deleted file mode 100644
index b374366930b2d1b5689ff5044caba49eace6aa68..0000000000000000000000000000000000000000
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diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/arm_common_tables.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/arm_common_tables.h
deleted file mode 100644
index 76aadca..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/arm_common_tables.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date: 31. July 2014
-* $Revision: V1.4.4
-*
-* Project: CMSIS DSP Library
-* Title: arm_common_tables.h
-*
-* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-* - Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* - Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in
-* the documentation and/or other materials provided with the
-* distribution.
-* - Neither the name of ARM LIMITED nor the names of its contributors
-* may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
-//extern const q31_t realCoefAQ31[1024];
-//extern const q31_t realCoefBQ31[1024];
-extern const float32_t twiddleCoef_16[32];
-extern const float32_t twiddleCoef_32[64];
-extern const float32_t twiddleCoef_64[128];
-extern const float32_t twiddleCoef_128[256];
-extern const float32_t twiddleCoef_256[512];
-extern const float32_t twiddleCoef_512[1024];
-extern const float32_t twiddleCoef_1024[2048];
-extern const float32_t twiddleCoef_2048[4096];
-extern const float32_t twiddleCoef_4096[8192];
-#define twiddleCoef twiddleCoef_4096
-extern const q31_t twiddleCoef_16_q31[24];
-extern const q31_t twiddleCoef_32_q31[48];
-extern const q31_t twiddleCoef_64_q31[96];
-extern const q31_t twiddleCoef_128_q31[192];
-extern const q31_t twiddleCoef_256_q31[384];
-extern const q31_t twiddleCoef_512_q31[768];
-extern const q31_t twiddleCoef_1024_q31[1536];
-extern const q31_t twiddleCoef_2048_q31[3072];
-extern const q31_t twiddleCoef_4096_q31[6144];
-extern const q15_t twiddleCoef_16_q15[24];
-extern const q15_t twiddleCoef_32_q15[48];
-extern const q15_t twiddleCoef_64_q15[96];
-extern const q15_t twiddleCoef_128_q15[192];
-extern const q15_t twiddleCoef_256_q15[384];
-extern const q15_t twiddleCoef_512_q15[768];
-extern const q15_t twiddleCoef_1024_q15[1536];
-extern const q15_t twiddleCoef_2048_q15[3072];
-extern const q15_t twiddleCoef_4096_q15[6144];
-extern const float32_t twiddleCoef_rfft_32[32];
-extern const float32_t twiddleCoef_rfft_64[64];
-extern const float32_t twiddleCoef_rfft_128[128];
-extern const float32_t twiddleCoef_rfft_256[256];
-extern const float32_t twiddleCoef_rfft_512[512];
-extern const float32_t twiddleCoef_rfft_1024[1024];
-extern const float32_t twiddleCoef_rfft_2048[2048];
-extern const float32_t twiddleCoef_rfft_4096[4096];
-
-
-/* floating-point bit reversal tables */
-#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
-#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
-#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
-#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
-#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
-#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
-
-/* fixed-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
-#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
-#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
-#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
-#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
-#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
-#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
-#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
-
-/* Tables for Fast Math Sine and Cosine */
-extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
-
-#endif /* ARM_COMMON_TABLES_H */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/arm_const_structs.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/arm_const_structs.h
deleted file mode 100644
index 217f1d5..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/arm_const_structs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date: 31. July 2014
-* $Revision: V1.4.4
-*
-* Project: CMSIS DSP Library
-* Title: arm_const_structs.h
-*
-* Description: This file has constant structs that are initialized for
-* user convenience. For example, some can be given as
-* arguments to the arm_cfft_f32() function.
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-* - Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* - Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in
-* the documentation and/or other materials provided with the
-* distribution.
-* - Neither the name of ARM LIMITED nor the names of its contributors
-* may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
-
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
-
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
-
-#endif
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/arm_math.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/arm_math.h
deleted file mode 100644
index f06a071..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/arm_math.h
+++ /dev/null
@@ -1,7538 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date: 12. March 2014
-* $Revision: V1.4.4
-*
-* Project: CMSIS DSP Library
-* Title: arm_math.h
-*
-* Description: Public header file for CMSIS DSP Library
-*
-* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-* - Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* - Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in
-* the documentation and/or other materials provided with the
-* distribution.
-* - Neither the name of ARM LIMITED nor the names of its contributors
-* may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
- * -------------------------------------------------------------------- */
-
-/**
- \mainpage CMSIS DSP Software Library
- *
- * Introduction
- * ------------
- *
- * This user manual describes the CMSIS DSP software library,
- * a suite of common signal processing functions for use on Cortex-M processor based devices.
- *
- * The library is divided into a number of functions each covering a specific category:
- * - Basic math functions
- * - Fast math functions
- * - Complex math functions
- * - Filters
- * - Matrix functions
- * - Transforms
- * - Motor control functions
- * - Statistical functions
- * - Support functions
- * - Interpolation functions
- *
- * The library has separate functions for operating on 8-bit integers, 16-bit integers,
- * 32-bit integer and 32-bit floating-point values.
- *
- * Using the Library
- * ------------
- *
- * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
- * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
- * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
- * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
- * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
- * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
- * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
- * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
- * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
- *
- * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
- * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
- * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
- * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or
- * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
- *
- * Examples
- * --------
- *
- * The library ships with a number of examples which demonstrate how to use the library functions.
- *
- * Toolchain Support
- * ------------
- *
- * The library has been developed and tested with MDK-ARM version 4.60.
- * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
- *
- * Building the Library
- * ------------
- *
- * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
- * - arm_cortexM_math.uvproj
- *
- *
- * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
- *
- * Pre-processor Macros
- * ------------
- *
- * Each library project have differant pre-processor macros.
- *
- * - UNALIGNED_SUPPORT_DISABLE:
- *
- * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
- *
- * - ARM_MATH_BIG_ENDIAN:
- *
- * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
- *
- * - ARM_MATH_MATRIX_CHECK:
- *
- * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
- *
- * - ARM_MATH_ROUNDING:
- *
- * Define macro ARM_MATH_ROUNDING for rounding on support functions
- *
- * - ARM_MATH_CMx:
- *
- * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
- * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
- *
- * - __FPU_PRESENT:
- *
- * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
- *
- * <hr>
- * CMSIS-DSP in ARM::CMSIS Pack
- * -----------------------------
- *
- * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
- * |File/Folder |Content |
- * |------------------------------|------------------------------------------------------------------------|
- * |\b CMSIS\\Documentation\\DSP | This documentation |
- * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
- * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
- * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
- *
- * <hr>
- * Revision History of CMSIS-DSP
- * ------------
- * Please refer to \ref ChangeLog_pg.
- *
- * Copyright Notice
- * ------------
- *
- * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
- */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures. For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- * typedef struct
- * {
- * uint16_t numRows; // number of rows of the matrix.
- * uint16_t numCols; // number of columns of the matrix.
- * float32_t *pData; // points to the data of the matrix.
- * } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data. The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order. That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- * pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure. For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices. For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns. If the size check fails the functions return:
- * <pre>
- * ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- * ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * <pre>
- * ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings. By default this macro is defined
- * and size checking is enabled. By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster. With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
-
-#if defined(ARM_MATH_CM7)
- #include "core_cm7.h"
-#elif defined (ARM_MATH_CM4)
- #include "core_cm4.h"
-#elif defined (ARM_MATH_CM3)
- #include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
- #include "core_cm0.h"
-#define ARM_MATH_CM0_FAMILY
- #elif defined (ARM_MATH_CM0PLUS)
-#include "core_cm0plus.h"
- #define ARM_MATH_CM0_FAMILY
-#else
- #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
-#endif
-
-#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
- /**
- * @brief Macros required for reciprocal calculation in Normalized LMS
- */
-
-#define DELTA_Q31 (0x100)
-#define DELTA_Q15 0x5
-#define INDEX_MASK 0x0000003F
-#ifndef PI
-#define PI 3.14159265358979f
-#endif
-
- /**
- * @brief Macros required for SINE and COSINE Fast math approximations
- */
-
-#define FAST_MATH_TABLE_SIZE 512
-#define FAST_MATH_Q31_SHIFT (32 - 10)
-#define FAST_MATH_Q15_SHIFT (16 - 10)
-#define CONTROLLER_Q31_SHIFT (32 - 9)
-#define TABLE_SIZE 256
-#define TABLE_SPACING_Q31 0x400000
-#define TABLE_SPACING_Q15 0x80
-
- /**
- * @brief Macros required for SINE and COSINE Controller functions
- */
- /* 1.31(q31) Fixed value of 2/360 */
- /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING 0xB60B61
-
- /**
- * @brief Macro for Unaligned Support
- */
-#ifndef UNALIGNED_SUPPORT_DISABLE
- #define ALIGN4
-#else
- #if defined (__GNUC__)
- #define ALIGN4 __attribute__((aligned(4)))
- #else
- #define ALIGN4 __align(4)
- #endif
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /**
- * @brief Error status returned by some functions in the library.
- */
-
- typedef enum
- {
- ARM_MATH_SUCCESS = 0, /**< No error */
- ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
- ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
- ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
- ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
- ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
- ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
- } arm_status;
-
- /**
- * @brief 8-bit fractional data type in 1.7 format.
- */
- typedef int8_t q7_t;
-
- /**
- * @brief 16-bit fractional data type in 1.15 format.
- */
- typedef int16_t q15_t;
-
- /**
- * @brief 32-bit fractional data type in 1.31 format.
- */
- typedef int32_t q31_t;
-
- /**
- * @brief 64-bit fractional data type in 1.63 format.
- */
- typedef int64_t q63_t;
-
- /**
- * @brief 32-bit floating-point type definition.
- */
- typedef float float32_t;
-
- /**
- * @brief 64-bit floating-point type definition.
- */
- typedef double float64_t;
-
- /**
- * @brief definition to read/write two 16 bit values.
- */
-#if defined __CC_ARM
-#define __SIMD32_TYPE int32_t __packed
-#define CMSIS_UNUSED __attribute__((unused))
-#elif defined __ICCARM__
-#define CMSIS_UNUSED
-#define __SIMD32_TYPE int32_t __packed
-#elif defined __GNUC__
-#define __SIMD32_TYPE int32_t
-#define CMSIS_UNUSED __attribute__((unused))
-#elif defined __CSMC__ /* Cosmic */
-#define CMSIS_UNUSED
-#define __SIMD32_TYPE int32_t
-#else
-#error Unknown compiler
-#endif
-
-#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
-
-#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
-
-#define __SIMD64(addr) (*(int64_t **) & (addr))
-
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
- /**
- * @brief definition to pack two 16 bit values.
- */
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
- (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
- (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
-
-#endif
-
-
- /**
- * @brief definition to pack four 8 bit values.
- */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
- (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
- (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
- (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
- (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
- (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
- (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
-
-#endif
-
-
- /**
- * @brief Clips Q63 to Q31 values.
- */
- static __INLINE q31_t clip_q63_to_q31(
- q63_t x)
- {
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
- ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
- }
-
- /**
- * @brief Clips Q63 to Q15 values.
- */
- static __INLINE q15_t clip_q63_to_q15(
- q63_t x)
- {
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
- ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
- }
-
- /**
- * @brief Clips Q31 to Q7 values.
- */
- static __INLINE q7_t clip_q31_to_q7(
- q31_t x)
- {
- return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
- ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
- }
-
- /**
- * @brief Clips Q31 to Q15 values.
- */
- static __INLINE q15_t clip_q31_to_q15(
- q31_t x)
- {
- return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
- ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
- }
-
- /**
- * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
- */
-
- static __INLINE q63_t mult32x64(
- q63_t x,
- q31_t y)
- {
- return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
- (((q63_t) (x >> 32) * y)));
- }
-
-
-#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
-#define __CLZ __clz
-#endif
-
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
-
- static __INLINE uint32_t __CLZ(
- q31_t data);
-
-
- static __INLINE uint32_t __CLZ(
- q31_t data)
- {
- uint32_t count = 0;
- uint32_t mask = 0x80000000;
-
- while((data & mask) == 0)
- {
- count += 1u;
- mask = mask >> 1u;
- }
-
- return (count);
-
- }
-
-#endif
-
- /**
- * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
- */
-
- static __INLINE uint32_t arm_recip_q31(
- q31_t in,
- q31_t * dst,
- q31_t * pRecipTable)
- {
-
- uint32_t out, tempVal;
- uint32_t index, i;
- uint32_t signBits;
-
- if(in > 0)
- {
- signBits = __CLZ(in) - 1;
- }
- else
- {
- signBits = __CLZ(-in) - 1;
- }
-
- /* Convert input sample to 1.31 format */
- in = in << signBits;
-
- /* calculation of index for initial approximated Val */
- index = (uint32_t) (in >> 24u);
- index = (index & INDEX_MASK);
-
- /* 1.31 with exp 1 */
- out = pRecipTable[index];
-
- /* calculation of reciprocal value */
- /* running approximation for two iterations */
- for (i = 0u; i < 2u; i++)
- {
- tempVal = (q31_t) (((q63_t) in * out) >> 31u);
- tempVal = 0x7FFFFFFF - tempVal;
- /* 1.31 with exp 1 */
- //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
- out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
- }
-
- /* write output */
- *dst = out;
-
- /* return num of signbits of out = 1/in value */
- return (signBits + 1u);
-
- }
-
- /**
- * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
- */
- static __INLINE uint32_t arm_recip_q15(
- q15_t in,
- q15_t * dst,
- q15_t * pRecipTable)
- {
-
- uint32_t out = 0, tempVal = 0;
- uint32_t index = 0, i = 0;
- uint32_t signBits = 0;
-
- if(in > 0)
- {
- signBits = __CLZ(in) - 17;
- }
- else
- {
- signBits = __CLZ(-in) - 17;
- }
-
- /* Convert input sample to 1.15 format */
- in = in << signBits;
-
- /* calculation of index for initial approximated Val */
- index = in >> 8;
- index = (index & INDEX_MASK);
-
- /* 1.15 with exp 1 */
- out = pRecipTable[index];
-
- /* calculation of reciprocal value */
- /* running approximation for two iterations */
- for (i = 0; i < 2; i++)
- {
- tempVal = (q15_t) (((q31_t) in * out) >> 15);
- tempVal = 0x7FFF - tempVal;
- /* 1.15 with exp 1 */
- out = (q15_t) (((q31_t) out * tempVal) >> 14);
- }
-
- /* write output */
- *dst = out;
-
- /* return num of signbits of out = 1/in value */
- return (signBits + 1);
-
- }
-
-
- /*
- * @brief C custom defined intrinisic function for only M0 processors
- */
-#if defined(ARM_MATH_CM0_FAMILY)
-
- static __INLINE q31_t __SSAT(
- q31_t x,
- uint32_t y)
- {
- int32_t posMax, negMin;
- uint32_t i;
-
- posMax = 1;
- for (i = 0; i < (y - 1); i++)
- {
- posMax = posMax * 2;
- }
-
- if(x > 0)
- {
- posMax = (posMax - 1);
-
- if(x > posMax)
- {
- x = posMax;
- }
- }
- else
- {
- negMin = -posMax;
-
- if(x < negMin)
- {
- x = negMin;
- }
- }
- return (x);
-
-
- }
-
-#endif /* end of ARM_MATH_CM0_FAMILY */
-
-
-
- /*
- * @brief C custom defined intrinsic function for M3 and M0 processors
- */
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
-
- /*
- * @brief C custom defined QADD8 for M3 and M0 processors
- */
- static __INLINE q31_t __QADD8(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q7_t r, s, t, u;
-
- r = (q7_t) x;
- s = (q7_t) y;
-
- r = __SSAT((q31_t) (r + s), 8);
- s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
- t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
- u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
-
- sum =
- (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
- (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
-
- return sum;
-
- }
-
- /*
- * @brief C custom defined QSUB8 for M3 and M0 processors
- */
- static __INLINE q31_t __QSUB8(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s, t, u;
-
- r = (q7_t) x;
- s = (q7_t) y;
-
- r = __SSAT((r - s), 8);
- s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
- t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
- u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
-
- sum =
- (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
- 0x000000FF);
-
- return sum;
- }
-
- /*
- * @brief C custom defined QADD16 for M3 and M0 processors
- */
-
- /*
- * @brief C custom defined QADD16 for M3 and M0 processors
- */
- static __INLINE q31_t __QADD16(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (q15_t) x;
- s = (q15_t) y;
-
- r = __SSAT(r + s, 16);
- s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
-
- }
-
- /*
- * @brief C custom defined SHADD16 for M3 and M0 processors
- */
- static __INLINE q31_t __SHADD16(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (q15_t) x;
- s = (q15_t) y;
-
- r = ((r >> 1) + (s >> 1));
- s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
-
- }
-
- /*
- * @brief C custom defined QSUB16 for M3 and M0 processors
- */
- static __INLINE q31_t __QSUB16(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (q15_t) x;
- s = (q15_t) y;
-
- r = __SSAT(r - s, 16);
- s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
- }
-
- /*
- * @brief C custom defined SHSUB16 for M3 and M0 processors
- */
- static __INLINE q31_t __SHSUB16(
- q31_t x,
- q31_t y)
- {
-
- q31_t diff;
- q31_t r, s;
-
- r = (q15_t) x;
- s = (q15_t) y;
-
- r = ((r >> 1) - (s >> 1));
- s = (((x >> 17) - (y >> 17)) << 16);
-
- diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return diff;
- }
-
- /*
- * @brief C custom defined QASX for M3 and M0 processors
- */
- static __INLINE q31_t __QASX(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum = 0;
-
- sum =
- ((sum +
- clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
- clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
-
- return sum;
- }
-
- /*
- * @brief C custom defined SHASX for M3 and M0 processors
- */
- static __INLINE q31_t __SHASX(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (q15_t) x;
- s = (q15_t) y;
-
- r = ((r >> 1) - (y >> 17));
- s = (((x >> 17) + (s >> 1)) << 16);
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
- }
-
-
- /*
- * @brief C custom defined QSAX for M3 and M0 processors
- */
- static __INLINE q31_t __QSAX(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum = 0;
-
- sum =
- ((sum +
- clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
- clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
-
- return sum;
- }
-
- /*
- * @brief C custom defined SHSAX for M3 and M0 processors
- */
- static __INLINE q31_t __SHSAX(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (q15_t) x;
- s = (q15_t) y;
-
- r = ((r >> 1) + (y >> 17));
- s = (((x >> 17) - (s >> 1)) << 16);
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
- }
-
- /*
- * @brief C custom defined SMUSDX for M3 and M0 processors
- */
- static __INLINE q31_t __SMUSDX(
- q31_t x,
- q31_t y)
- {
-
- return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
- ((q15_t) (x >> 16) * (q15_t) y)));
- }
-
- /*
- * @brief C custom defined SMUADX for M3 and M0 processors
- */
- static __INLINE q31_t __SMUADX(
- q31_t x,
- q31_t y)
- {
-
- return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
- ((q15_t) (x >> 16) * (q15_t) y)));
- }
-
- /*
- * @brief C custom defined QADD for M3 and M0 processors
- */
- static __INLINE q31_t __QADD(
- q31_t x,
- q31_t y)
- {
- return clip_q63_to_q31((q63_t) x + y);
- }
-
- /*
- * @brief C custom defined QSUB for M3 and M0 processors
- */
- static __INLINE q31_t __QSUB(
- q31_t x,
- q31_t y)
- {
- return clip_q63_to_q31((q63_t) x - y);
- }
-
- /*
- * @brief C custom defined SMLAD for M3 and M0 processors
- */
- static __INLINE q31_t __SMLAD(
- q31_t x,
- q31_t y,
- q31_t sum)
- {
-
- return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
- ((q15_t) x * (q15_t) y));
- }
-
- /*
- * @brief C custom defined SMLADX for M3 and M0 processors
- */
- static __INLINE q31_t __SMLADX(
- q31_t x,
- q31_t y,
- q31_t sum)
- {
-
- return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
- ((q15_t) x * (q15_t) (y >> 16)));
- }
-
- /*
- * @brief C custom defined SMLSDX for M3 and M0 processors
- */
- static __INLINE q31_t __SMLSDX(
- q31_t x,
- q31_t y,
- q31_t sum)
- {
-
- return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
- ((q15_t) x * (q15_t) (y >> 16)));
- }
-
- /*
- * @brief C custom defined SMLALD for M3 and M0 processors
- */
- static __INLINE q63_t __SMLALD(
- q31_t x,
- q31_t y,
- q63_t sum)
- {
-
- return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
- ((q15_t) x * (q15_t) y));
- }
-
- /*
- * @brief C custom defined SMLALDX for M3 and M0 processors
- */
- static __INLINE q63_t __SMLALDX(
- q31_t x,
- q31_t y,
- q63_t sum)
- {
-
- return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
- ((q15_t) x * (q15_t) (y >> 16));
- }
-
- /*
- * @brief C custom defined SMUAD for M3 and M0 processors
- */
- static __INLINE q31_t __SMUAD(
- q31_t x,
- q31_t y)
- {
-
- return (((x >> 16) * (y >> 16)) +
- (((x << 16) >> 16) * ((y << 16) >> 16)));
- }
-
- /*
- * @brief C custom defined SMUSD for M3 and M0 processors
- */
- static __INLINE q31_t __SMUSD(
- q31_t x,
- q31_t y)
- {
-
- return (-((x >> 16) * (y >> 16)) +
- (((x << 16) >> 16) * ((y << 16) >> 16)));
- }
-
-
- /*
- * @brief C custom defined SXTB16 for M3 and M0 processors
- */
- static __INLINE q31_t __SXTB16(
- q31_t x)
- {
-
- return ((((x << 24) >> 24) & 0x0000FFFF) |
- (((x << 8) >> 8) & 0xFFFF0000));
- }
-
-
-#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-
-
- /**
- * @brief Instance structure for the Q7 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- } arm_fir_instance_q7;
-
- /**
- * @brief Instance structure for the Q15 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- } arm_fir_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- } arm_fir_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- } arm_fir_instance_f32;
-
-
- /**
- * @brief Processing function for the Q7 FIR filter.
- * @param[in] *S points to an instance of the Q7 FIR filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_q7(
- const arm_fir_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q7 FIR filter.
- * @param[in,out] *S points to an instance of the Q7 FIR structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed.
- * @return none
- */
- void arm_fir_init_q7(
- arm_fir_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 FIR filter.
- * @param[in] *S points to an instance of the Q15 FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q15 FIR filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_fast_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q15 FIR filter.
- * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
- * <code>numTaps</code> is not a supported value.
- */
-
- arm_status arm_fir_init_q15(
- arm_fir_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR filter.
- * @param[in] *S points to an instance of the Q31 FIR filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q31 FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_fast_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 FIR filter.
- * @param[in,out] *S points to an instance of the Q31 FIR structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- * @return none.
- */
- void arm_fir_init_q31(
- arm_fir_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the floating-point FIR filter.
- * @param[in] *S points to an instance of the floating-point FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_f32(
- const arm_fir_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point FIR filter.
- * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- * @return none.
- */
- void arm_fir_init_f32(
- arm_fir_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 Biquad cascade filter.
- */
- typedef struct
- {
- int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
-
- } arm_biquad_casd_df1_inst_q15;
-
-
- /**
- * @brief Instance structure for the Q31 Biquad cascade filter.
- */
- typedef struct
- {
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
-
- } arm_biquad_casd_df1_inst_q31;
-
- /**
- * @brief Instance structure for the floating-point Biquad cascade filter.
- */
- typedef struct
- {
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
-
-
- } arm_biquad_casd_df1_inst_f32;
-
-
-
- /**
- * @brief Processing function for the Q15 Biquad cascade filter.
- * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q15 Biquad cascade filter.
- * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
- * @return none
- */
-
- void arm_biquad_cascade_df1_init_q15(
- arm_biquad_casd_df1_inst_q15 * S,
- uint8_t numStages,
- q15_t * pCoeffs,
- q15_t * pState,
- int8_t postShift);
-
-
- /**
- * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_fast_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 Biquad cascade filter
- * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_fast_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 Biquad cascade filter.
- * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
- * @return none
- */
-
- void arm_biquad_cascade_df1_init_q31(
- arm_biquad_casd_df1_inst_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q31_t * pState,
- int8_t postShift);
-
- /**
- * @brief Processing function for the floating-point Biquad cascade filter.
- * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_f32(
- const arm_biquad_casd_df1_inst_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point Biquad cascade filter.
- * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @return none
- */
-
- void arm_biquad_cascade_df1_init_f32(
- arm_biquad_casd_df1_inst_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Instance structure for the floating-point matrix structure.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- float32_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_f32;
-
-
- /**
- * @brief Instance structure for the floating-point matrix structure.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- float64_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_f64;
-
- /**
- * @brief Instance structure for the Q15 matrix structure.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- q15_t *pData; /**< points to the data of the matrix. */
-
- } arm_matrix_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 matrix structure.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- q31_t *pData; /**< points to the data of the matrix. */
-
- } arm_matrix_instance_q31;
-
-
-
- /**
- * @brief Floating-point matrix addition.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_add_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix addition.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_add_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix addition.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_add_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
- /**
- * @brief Floating-point, complex, matrix multiplication.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_cmplx_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15, complex, matrix multiplication.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_cmplx_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pScratch);
-
- /**
- * @brief Q31, complex, matrix multiplication.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_cmplx_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix transpose.
- * @param[in] *pSrc points to the input matrix
- * @param[out] *pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_trans_f32(
- const arm_matrix_instance_f32 * pSrc,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix transpose.
- * @param[in] *pSrc points to the input matrix
- * @param[out] *pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_trans_q15(
- const arm_matrix_instance_q15 * pSrc,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix transpose.
- * @param[in] *pSrc points to the input matrix
- * @param[out] *pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_trans_q31(
- const arm_matrix_instance_q31 * pSrc,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix multiplication
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix multiplication
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @param[in] *pState points to the array for storing intermediate results
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
-
- /**
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @param[in] *pState points to the array for storing intermediate results
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_fast_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
-
- /**
- * @brief Q31 matrix multiplication
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
- /**
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_fast_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix subtraction
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_sub_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix subtraction
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_sub_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix subtraction
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_sub_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
- /**
- * @brief Floating-point matrix scaling.
- * @param[in] *pSrc points to the input matrix
- * @param[in] scale scale factor
- * @param[out] *pDst points to the output matrix
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_scale_f32(
- const arm_matrix_instance_f32 * pSrc,
- float32_t scale,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix scaling.
- * @param[in] *pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to output matrix
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_scale_q15(
- const arm_matrix_instance_q15 * pSrc,
- q15_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix scaling.
- * @param[in] *pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_scale_q31(
- const arm_matrix_instance_q31 * pSrc,
- q31_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Q31 matrix initialization.
- * @param[in,out] *S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] *pData points to the matrix data array.
- * @return none
- */
-
- void arm_mat_init_q31(
- arm_matrix_instance_q31 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q31_t * pData);
-
- /**
- * @brief Q15 matrix initialization.
- * @param[in,out] *S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] *pData points to the matrix data array.
- * @return none
- */
-
- void arm_mat_init_q15(
- arm_matrix_instance_q15 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q15_t * pData);
-
- /**
- * @brief Floating-point matrix initialization.
- * @param[in,out] *S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] *pData points to the matrix data array.
- * @return none
- */
-
- void arm_mat_init_f32(
- arm_matrix_instance_f32 * S,
- uint16_t nRows,
- uint16_t nColumns,
- float32_t * pData);
-
-
-
- /**
- * @brief Instance structure for the Q15 PID Control.
- */
- typedef struct
- {
- q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
-#ifdef ARM_MATH_CM0_FAMILY
- q15_t A1;
- q15_t A2;
-#else
- q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
- q15_t state[3]; /**< The state array of length 3. */
- q15_t Kp; /**< The proportional gain. */
- q15_t Ki; /**< The integral gain. */
- q15_t Kd; /**< The derivative gain. */
- } arm_pid_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 PID Control.
- */
- typedef struct
- {
- q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
- q31_t A2; /**< The derived gain, A2 = Kd . */
- q31_t state[3]; /**< The state array of length 3. */
- q31_t Kp; /**< The proportional gain. */
- q31_t Ki; /**< The integral gain. */
- q31_t Kd; /**< The derivative gain. */
-
- } arm_pid_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point PID Control.
- */
- typedef struct
- {
- float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
- float32_t A2; /**< The derived gain, A2 = Kd . */
- float32_t state[3]; /**< The state array of length 3. */
- float32_t Kp; /**< The proportional gain. */
- float32_t Ki; /**< The integral gain. */
- float32_t Kd; /**< The derivative gain. */
- } arm_pid_instance_f32;
-
-
-
- /**
- * @brief Initialization function for the floating-point PID Control.
- * @param[in,out] *S points to an instance of the PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- * @return none.
- */
- void arm_pid_init_f32(
- arm_pid_instance_f32 * S,
- int32_t resetStateFlag);
-
- /**
- * @brief Reset function for the floating-point PID Control.
- * @param[in,out] *S is an instance of the floating-point PID Control structure
- * @return none
- */
- void arm_pid_reset_f32(
- arm_pid_instance_f32 * S);
-
-
- /**
- * @brief Initialization function for the Q31 PID Control.
- * @param[in,out] *S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- * @return none.
- */
- void arm_pid_init_q31(
- arm_pid_instance_q31 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the Q31 PID Control.
- * @param[in,out] *S points to an instance of the Q31 PID Control structure
- * @return none
- */
-
- void arm_pid_reset_q31(
- arm_pid_instance_q31 * S);
-
- /**
- * @brief Initialization function for the Q15 PID Control.
- * @param[in,out] *S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- * @return none.
- */
- void arm_pid_init_q15(
- arm_pid_instance_q15 * S,
- int32_t resetStateFlag);
-
- /**
- * @brief Reset function for the Q15 PID Control.
- * @param[in,out] *S points to an instance of the q15 PID Control structure
- * @return none
- */
- void arm_pid_reset_q15(
- arm_pid_instance_q15 * S);
-
-
- /**
- * @brief Instance structure for the floating-point Linear Interpolate function.
- */
- typedef struct
- {
- uint32_t nValues; /**< nValues */
- float32_t x1; /**< x1 */
- float32_t xSpacing; /**< xSpacing */
- float32_t *pYData; /**< pointer to the table of Y values */
- } arm_linear_interp_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point bilinear interpolation function.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- float32_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_f32;
-
- /**
- * @brief Instance structure for the Q31 bilinear interpolation function.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q31_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q31;
-
- /**
- * @brief Instance structure for the Q15 bilinear interpolation function.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q15_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q15;
-
- /**
- * @brief Instance structure for the Q15 bilinear interpolation function.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q7_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q7;
-
-
- /**
- * @brief Q7 vector multiplication.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_mult_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q15 vector multiplication.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_mult_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q31 vector multiplication.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_mult_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Floating-point vector multiplication.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_mult_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
-
-
-
-
- /**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix2_instance_q15;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_q15(
- arm_cfft_radix2_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_q15(
- const arm_cfft_radix2_instance_q15 * S,
- q15_t * pSrc);
-
-
-
- /**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q15_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix4_instance_q15;
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_q15(
- arm_cfft_radix4_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix4_q15(
- const arm_cfft_radix4_instance_q15 * S,
- q15_t * pSrc);
-
- /**
- * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q31_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix2_instance_q31;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_q31(
- arm_cfft_radix2_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_q31(
- const arm_cfft_radix2_instance_q31 * S,
- q31_t * pSrc);
-
- /**
- * @brief Instance structure for the Q31 CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q31_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix4_instance_q31;
-
-/* Deprecated */
- void arm_cfft_radix4_q31(
- const arm_cfft_radix4_instance_q31 * S,
- q31_t * pSrc);
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_q31(
- arm_cfft_radix4_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- float32_t onebyfftLen; /**< value of 1/fftLen. */
- } arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_f32(
- arm_cfft_radix2_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_f32(
- const arm_cfft_radix2_instance_f32 * S,
- float32_t * pSrc);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- float32_t onebyfftLen; /**< value of 1/fftLen. */
- } arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_f32(
- arm_cfft_radix4_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix4_f32(
- const arm_cfft_radix4_instance_f32 * S,
- float32_t * pSrc);
-
- /**
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_q15;
-
-void arm_cfft_q15(
- const arm_cfft_instance_q15 * S,
- q15_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_q31;
-
-void arm_cfft_q31(
- const arm_cfft_instance_q31 * S,
- q31_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_f32;
-
- void arm_cfft_f32(
- const arm_cfft_instance_f32 * S,
- float32_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the Q15 RFFT/RIFFT function.
- */
-
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_q15;
-
- arm_status arm_rfft_init_q15(
- arm_rfft_instance_q15 * S,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_q15(
- const arm_rfft_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst);
-
- /**
- * @brief Instance structure for the Q31 RFFT/RIFFT function.
- */
-
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_q31;
-
- arm_status arm_rfft_init_q31(
- arm_rfft_instance_q31 * S,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_q31(
- const arm_rfft_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst);
-
- /**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
-
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint16_t fftLenBy2; /**< length of the complex FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_f32;
-
- arm_status arm_rfft_init_f32(
- arm_rfft_instance_f32 * S,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_f32(
- const arm_rfft_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst);
-
- /**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
-
-typedef struct
- {
- arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
- uint16_t fftLenRFFT; /**< length of the real sequence */
- float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
- } arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
- arm_rfft_fast_instance_f32 * S,
- uint16_t fftLen);
-
-void arm_rfft_fast_f32(
- arm_rfft_fast_instance_f32 * S,
- float32_t * p, float32_t * pOut,
- uint8_t ifftFlag);
-
- /**
- * @brief Instance structure for the floating-point DCT4/IDCT4 function.
- */
-
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- float32_t normalize; /**< normalizing factor. */
- float32_t *pTwiddle; /**< points to the twiddle factor table. */
- float32_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_f32;
-
- /**
- * @brief Initialization function for the floating-point DCT4/IDCT4.
- * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
- * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
- * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
- */
-
- arm_status arm_dct4_init_f32(
- arm_dct4_instance_f32 * S,
- arm_rfft_instance_f32 * S_RFFT,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- float32_t normalize);
-
- /**
- * @brief Processing function for the floating-point DCT4/IDCT4.
- * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
- * @param[in] *pState points to state buffer.
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
- * @return none.
- */
-
- void arm_dct4_f32(
- const arm_dct4_instance_f32 * S,
- float32_t * pState,
- float32_t * pInlineBuffer);
-
- /**
- * @brief Instance structure for the Q31 DCT4/IDCT4 function.
- */
-
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- q31_t normalize; /**< normalizing factor. */
- q31_t *pTwiddle; /**< points to the twiddle factor table. */
- q31_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_q31;
-
- /**
- * @brief Initialization function for the Q31 DCT4/IDCT4.
- * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
- * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
- * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
- */
-
- arm_status arm_dct4_init_q31(
- arm_dct4_instance_q31 * S,
- arm_rfft_instance_q31 * S_RFFT,
- arm_cfft_radix4_instance_q31 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q31_t normalize);
-
- /**
- * @brief Processing function for the Q31 DCT4/IDCT4.
- * @param[in] *S points to an instance of the Q31 DCT4 structure.
- * @param[in] *pState points to state buffer.
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
- * @return none.
- */
-
- void arm_dct4_q31(
- const arm_dct4_instance_q31 * S,
- q31_t * pState,
- q31_t * pInlineBuffer);
-
- /**
- * @brief Instance structure for the Q15 DCT4/IDCT4 function.
- */
-
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- q15_t normalize; /**< normalizing factor. */
- q15_t *pTwiddle; /**< points to the twiddle factor table. */
- q15_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_q15;
-
- /**
- * @brief Initialization function for the Q15 DCT4/IDCT4.
- * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
- * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
- * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
- */
-
- arm_status arm_dct4_init_q15(
- arm_dct4_instance_q15 * S,
- arm_rfft_instance_q15 * S_RFFT,
- arm_cfft_radix4_instance_q15 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q15_t normalize);
-
- /**
- * @brief Processing function for the Q15 DCT4/IDCT4.
- * @param[in] *S points to an instance of the Q15 DCT4 structure.
- * @param[in] *pState points to state buffer.
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
- * @return none.
- */
-
- void arm_dct4_q15(
- const arm_dct4_instance_q15 * S,
- q15_t * pState,
- q15_t * pInlineBuffer);
-
- /**
- * @brief Floating-point vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_add_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q7 vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_add_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q15 vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_add_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q31 vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_add_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Floating-point vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_sub_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q7 vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_sub_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q15 vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_sub_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q31 vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_sub_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Multiplies a floating-point vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scale scale factor to be applied
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_scale_f32(
- float32_t * pSrc,
- float32_t scale,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Multiplies a Q7 vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_scale_q7(
- q7_t * pSrc,
- q7_t scaleFract,
- int8_t shift,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Multiplies a Q15 vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_scale_q15(
- q15_t * pSrc,
- q15_t scaleFract,
- int8_t shift,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Multiplies a Q31 vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_scale_q31(
- q31_t * pSrc,
- q31_t scaleFract,
- int8_t shift,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q7 vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_abs_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Floating-point vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_abs_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q15 vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_abs_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q31 vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_abs_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Dot product of floating-point vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- */
-
- void arm_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t blockSize,
- float32_t * result);
-
- /**
- * @brief Dot product of Q7 vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- */
-
- void arm_dot_prod_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- uint32_t blockSize,
- q31_t * result);
-
- /**
- * @brief Dot product of Q15 vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- */
-
- void arm_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
-
- /**
- * @brief Dot product of Q31 vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- */
-
- void arm_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
-
- /**
- * @brief Shifts the elements of a Q7 vector a specified number of bits.
- * @param[in] *pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_shift_q7(
- q7_t * pSrc,
- int8_t shiftBits,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Shifts the elements of a Q15 vector a specified number of bits.
- * @param[in] *pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_shift_q15(
- q15_t * pSrc,
- int8_t shiftBits,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Shifts the elements of a Q31 vector a specified number of bits.
- * @param[in] *pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_shift_q31(
- q31_t * pSrc,
- int8_t shiftBits,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Adds a constant offset to a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_offset_f32(
- float32_t * pSrc,
- float32_t offset,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Adds a constant offset to a Q7 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_offset_q7(
- q7_t * pSrc,
- q7_t offset,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Adds a constant offset to a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_offset_q15(
- q15_t * pSrc,
- q15_t offset,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Adds a constant offset to a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_offset_q31(
- q31_t * pSrc,
- q31_t offset,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Negates the elements of a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_negate_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Negates the elements of a Q7 vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_negate_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Negates the elements of a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_negate_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Negates the elements of a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_negate_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
- /**
- * @brief Copies the elements of a floating-point vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_copy_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Copies the elements of a Q7 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_copy_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Copies the elements of a Q15 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_copy_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Copies the elements of a Q31 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_copy_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
- /**
- * @brief Fills a constant value into a floating-point vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_fill_f32(
- float32_t value,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Fills a constant value into a Q7 vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_fill_q7(
- q7_t value,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Fills a constant value into a Q15 vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_fill_q15(
- q15_t value,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Fills a constant value into a Q31 vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_fill_q31(
- q31_t value,
- q31_t * pDst,
- uint32_t blockSize);
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
-
-
- /**
- * @brief Convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return none.
- */
-
-
- void arm_conv_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
- /**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
- /**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return none.
- */
-
- void arm_conv_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-
- /**
- * @brief Convolution of Q31 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
- /**
- * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Convolution of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return none.
- */
-
- void arm_conv_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-
- /**
- * @brief Convolution of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
-
-
- /**
- * @brief Partial convolution of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
- /**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-/**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
- /**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Partial convolution of Q31 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q7 sequences
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-/**
- * @brief Partial convolution of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
-
- /**
- * @brief Instance structure for the Q15 FIR decimator.
- */
-
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR decimator.
- */
-
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
- } arm_fir_decimate_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR decimator.
- */
-
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
- } arm_fir_decimate_instance_f32;
-
-
-
- /**
- * @brief Processing function for the floating-point FIR decimator.
- * @param[in] *S points to an instance of the floating-point FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_f32(
- const arm_fir_decimate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point FIR decimator.
- * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-
- arm_status arm_fir_decimate_init_f32(
- arm_fir_decimate_instance_f32 * S,
- uint16_t numTaps,
- uint8_t M,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q15 FIR decimator.
- * @param[in] *S points to an instance of the Q15 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q15 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_fast_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-
- /**
- * @brief Initialization function for the Q15 FIR decimator.
- * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-
- arm_status arm_fir_decimate_init_q15(
- arm_fir_decimate_instance_q15 * S,
- uint16_t numTaps,
- uint8_t M,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR decimator.
- * @param[in] *S points to an instance of the Q31 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_q31(
- const arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q31 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_fast_q31(
- arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR decimator.
- * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-
- arm_status arm_fir_decimate_init_q31(
- arm_fir_decimate_instance_q31 * S,
- uint16_t numTaps,
- uint8_t M,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
-
- /**
- * @brief Instance structure for the Q15 FIR interpolator.
- */
-
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
- } arm_fir_interpolate_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR interpolator.
- */
-
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
- } arm_fir_interpolate_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR interpolator.
- */
-
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
- } arm_fir_interpolate_instance_f32;
-
-
- /**
- * @brief Processing function for the Q15 FIR interpolator.
- * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_interpolate_q15(
- const arm_fir_interpolate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 FIR interpolator.
- * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-
- arm_status arm_fir_interpolate_init_q15(
- arm_fir_interpolate_instance_q15 * S,
- uint8_t L,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR interpolator.
- * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_interpolate_q31(
- const arm_fir_interpolate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 FIR interpolator.
- * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-
- arm_status arm_fir_interpolate_init_q31(
- arm_fir_interpolate_instance_q31 * S,
- uint8_t L,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point FIR interpolator.
- * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_interpolate_f32(
- const arm_fir_interpolate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point FIR interpolator.
- * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-
- arm_status arm_fir_interpolate_init_f32(
- arm_fir_interpolate_instance_f32 * S,
- uint8_t L,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Instance structure for the high precision Q31 Biquad cascade filter.
- */
-
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
- q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
-
- } arm_biquad_cas_df1_32x64_ins_q31;
-
-
- /**
- * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cas_df1_32x64_q31(
- const arm_biquad_cas_df1_32x64_ins_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
- * @return none
- */
-
- void arm_biquad_cas_df1_32x64_init_q31(
- arm_biquad_cas_df1_32x64_ins_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q63_t * pState,
- uint8_t postShift);
-
-
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
-
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_df2T_instance_f32;
-
-
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
-
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_stereo_df2T_instance_f32;
-
-
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
-
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
- float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_df2T_instance_f64;
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in] *S points to an instance of the filter data structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df2T_f32(
- const arm_biquad_cascade_df2T_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
- * @param[in] *S points to an instance of the filter data structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_stereo_df2T_f32(
- const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in] *S points to an instance of the filter data structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df2T_f64(
- const arm_biquad_cascade_df2T_instance_f64 * S,
- float64_t * pSrc,
- float64_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] *S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @return none
- */
-
- void arm_biquad_cascade_df2T_init_f32(
- arm_biquad_cascade_df2T_instance_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] *S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @return none
- */
-
- void arm_biquad_cascade_stereo_df2T_init_f32(
- arm_biquad_cascade_stereo_df2T_instance_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] *S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @return none
- */
-
- void arm_biquad_cascade_df2T_init_f64(
- arm_biquad_cascade_df2T_instance_f64 * S,
- uint8_t numStages,
- float64_t * pCoeffs,
- float64_t * pState);
-
-
-
- /**
- * @brief Instance structure for the Q15 FIR lattice filter.
- */
-
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR lattice filter.
- */
-
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR lattice filter.
- */
-
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_f32;
-
- /**
- * @brief Initialization function for the Q15 FIR lattice filter.
- * @param[in] *S points to an instance of the Q15 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] *pState points to the state buffer. The array is of length numStages.
- * @return none.
- */
-
- void arm_fir_lattice_init_q15(
- arm_fir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pCoeffs,
- q15_t * pState);
-
-
- /**
- * @brief Processing function for the Q15 FIR lattice filter.
- * @param[in] *S points to an instance of the Q15 FIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_lattice_q15(
- const arm_fir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 FIR lattice filter.
- * @param[in] *S points to an instance of the Q31 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] *pState points to the state buffer. The array is of length numStages.
- * @return none.
- */
-
- void arm_fir_lattice_init_q31(
- arm_fir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pCoeffs,
- q31_t * pState);
-
-
- /**
- * @brief Processing function for the Q31 FIR lattice filter.
- * @param[in] *S points to an instance of the Q31 FIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_fir_lattice_q31(
- const arm_fir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] *pState points to the state buffer. The array is of length numStages.
- * @return none.
- */
-
- void arm_fir_lattice_init_f32(
- arm_fir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
- /**
- * @brief Processing function for the floating-point FIR lattice filter.
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_fir_lattice_f32(
- const arm_fir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Instance structure for the Q15 IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_f32;
-
- /**
- * @brief Processing function for the floating-point IIR lattice filter.
- * @param[in] *S points to an instance of the floating-point IIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_f32(
- const arm_iir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point IIR lattice filter.
- * @param[in] *S points to an instance of the floating-point IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_init_f32(
- arm_iir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pkCoeffs,
- float32_t * pvCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 IIR lattice filter.
- * @param[in] *S points to an instance of the Q31 IIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_q31(
- const arm_iir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 IIR lattice filter.
- * @param[in] *S points to an instance of the Q31 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_init_q31(
- arm_iir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pkCoeffs,
- q31_t * pvCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 IIR lattice filter.
- * @param[in] *S points to an instance of the Q15 IIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_q15(
- const arm_iir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
- * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- */
-
- void arm_iir_lattice_init_q15(
- arm_iir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pkCoeffs,
- q15_t * pvCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Instance structure for the floating-point LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- float32_t mu; /**< step size that controls filter coefficient updates. */
- } arm_lms_instance_f32;
-
- /**
- * @brief Processing function for floating-point LMS filter.
- * @param[in] *S points to an instance of the floating-point LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_f32(
- const arm_lms_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for floating-point LMS filter.
- * @param[in] *S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to the coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_init_f32(
- arm_lms_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
-
- /**
- * @brief Instance structure for the Q15 LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q15_t mu; /**< step size that controls filter coefficient updates. */
- uint32_t postShift; /**< bit shift applied to coefficients. */
- } arm_lms_instance_q15;
-
-
- /**
- * @brief Initialization function for the Q15 LMS filter.
- * @param[in] *S points to an instance of the Q15 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to the coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- */
-
- void arm_lms_init_q15(
- arm_lms_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint32_t postShift);
-
- /**
- * @brief Processing function for Q15 LMS filter.
- * @param[in] *S points to an instance of the Q15 LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_q15(
- const arm_lms_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q31 LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q31_t mu; /**< step size that controls filter coefficient updates. */
- uint32_t postShift; /**< bit shift applied to coefficients. */
-
- } arm_lms_instance_q31;
-
- /**
- * @brief Processing function for Q31 LMS filter.
- * @param[in] *S points to an instance of the Q15 LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_q31(
- const arm_lms_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for Q31 LMS filter.
- * @param[in] *S points to an instance of the Q31 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- */
-
- void arm_lms_init_q31(
- arm_lms_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint32_t postShift);
-
- /**
- * @brief Instance structure for the floating-point normalized LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- float32_t mu; /**< step size that control filter coefficient updates. */
- float32_t energy; /**< saves previous frame energy. */
- float32_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_f32;
-
- /**
- * @brief Processing function for floating-point normalized LMS filter.
- * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_norm_f32(
- arm_lms_norm_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for floating-point normalized LMS filter.
- * @param[in] *S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_norm_init_f32(
- arm_lms_norm_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q31 normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q31_t mu; /**< step size that controls filter coefficient updates. */
- uint8_t postShift; /**< bit shift applied to coefficients. */
- q31_t *recipTable; /**< points to the reciprocal initial value table. */
- q31_t energy; /**< saves previous frame energy. */
- q31_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_q31;
-
- /**
- * @brief Processing function for Q31 normalized LMS filter.
- * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_norm_q31(
- arm_lms_norm_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for Q31 normalized LMS filter.
- * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- */
-
- void arm_lms_norm_init_q31(
- arm_lms_norm_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint8_t postShift);
-
- /**
- * @brief Instance structure for the Q15 normalized LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< Number of coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q15_t mu; /**< step size that controls filter coefficient updates. */
- uint8_t postShift; /**< bit shift applied to coefficients. */
- q15_t *recipTable; /**< Points to the reciprocal initial value table. */
- q15_t energy; /**< saves previous frame energy. */
- q15_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_q15;
-
- /**
- * @brief Processing function for Q15 normalized LMS filter.
- * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_norm_q15(
- arm_lms_norm_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q15 normalized LMS filter.
- * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- */
-
- void arm_lms_norm_init_q15(
- arm_lms_norm_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint8_t postShift);
-
- /**
- * @brief Correlation of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
-
-
- /**
- * @brief Correlation of Q15 sequences
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @return none.
- */
- void arm_correlate_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch);
-
-
- /**
- * @brief Correlation of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
- /**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
-
- /**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @return none.
- */
-
- void arm_correlate_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch);
-
- /**
- * @brief Correlation of Q31 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
- /**
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
-
- /**
- * @brief Correlation of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return none.
- */
-
- void arm_correlate_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Correlation of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
-
-
- /**
- * @brief Instance structure for the floating-point sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_f32;
-
- /**
- * @brief Instance structure for the Q31 sparse FIR filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q31;
-
- /**
- * @brief Instance structure for the Q15 sparse FIR filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q15;
-
- /**
- * @brief Instance structure for the Q7 sparse FIR filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q7;
-
- /**
- * @brief Processing function for the floating-point sparse FIR filter.
- * @param[in] *S points to an instance of the floating-point sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_sparse_f32(
- arm_fir_sparse_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- float32_t * pScratchIn,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point sparse FIR filter.
- * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- */
-
- void arm_fir_sparse_init_f32(
- arm_fir_sparse_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 sparse FIR filter.
- * @param[in] *S points to an instance of the Q31 sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_sparse_q31(
- arm_fir_sparse_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- q31_t * pScratchIn,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 sparse FIR filter.
- * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- */
-
- void arm_fir_sparse_init_q31(
- arm_fir_sparse_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q15 sparse FIR filter.
- * @param[in] *S points to an instance of the Q15 sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_sparse_q15(
- arm_fir_sparse_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- q15_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 sparse FIR filter.
- * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- */
-
- void arm_fir_sparse_init_q15(
- arm_fir_sparse_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q7 sparse FIR filter.
- * @param[in] *S points to an instance of the Q7 sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_sparse_q7(
- arm_fir_sparse_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- q7_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q7 sparse FIR filter.
- * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- */
-
- void arm_fir_sparse_init_q7(
- arm_fir_sparse_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /*
- * @brief Floating-point sin_cos function.
- * @param[in] theta input value in degrees
- * @param[out] *pSinVal points to the processed sine output.
- * @param[out] *pCosVal points to the processed cos output.
- * @return none.
- */
-
- void arm_sin_cos_f32(
- float32_t theta,
- float32_t * pSinVal,
- float32_t * pCcosVal);
-
- /*
- * @brief Q31 sin_cos function.
- * @param[in] theta scaled input value in degrees
- * @param[out] *pSinVal points to the processed sine output.
- * @param[out] *pCosVal points to the processed cosine output.
- * @return none.
- */
-
- void arm_sin_cos_q31(
- q31_t theta,
- q31_t * pSinVal,
- q31_t * pCosVal);
-
-
- /**
- * @brief Floating-point complex conjugate.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_conj_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex conjugate.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_conj_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q15 complex conjugate.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_conj_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
-
- /**
- * @brief Floating-point complex magnitude squared
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_squared_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex magnitude squared
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_squared_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q15 complex magnitude squared
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_squared_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup PID PID Motor Control
- *
- * A Proportional Integral Derivative (PID) controller is a generic feedback control
- * loop mechanism widely used in industrial control systems.
- * A PID controller is the most commonly used type of feedback controller.
- *
- * This set of functions implements (PID) controllers
- * for Q15, Q31, and floating-point data types. The functions operate on a single sample
- * of data and each call to the function returns a single processed value.
- * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
- * is the input sample value. The functions return the output value.
- *
- * \par Algorithm:
- * <pre>
- * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
- * A0 = Kp + Ki + Kd
- * A1 = (-Kp ) - (2 * Kd )
- * A2 = Kd </pre>
- *
- * \par
- * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
- *
- * \par
- * \image html PID.gif "Proportional Integral Derivative Controller"
- *
- * \par
- * The PID controller calculates an "error" value as the difference between
- * the measured output and the reference input.
- * The controller attempts to minimize the error by adjusting the process control inputs.
- * The proportional value determines the reaction to the current error,
- * the integral value determines the reaction based on the sum of recent errors,
- * and the derivative value determines the reaction based on the rate at which the error has been changing.
- *
- * \par Instance Structure
- * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
- * A separate instance structure must be defined for each PID Controller.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Reset Functions
- * There is also an associated reset function for each data type which clears the state array.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
- * - Zeros out the values in the state buffer.
- *
- * \par
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
- *
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the PID Controller functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup PID
- * @{
- */
-
- /**
- * @brief Process function for the floating-point PID Control.
- * @param[in,out] *S is an instance of the floating-point PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- */
-
-
- static __INLINE float32_t arm_pid_f32(
- arm_pid_instance_f32 * S,
- float32_t in)
- {
- float32_t out;
-
- /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
- out = (S->A0 * in) +
- (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- * @brief Process function for the Q31 PID Control.
- * @param[in,out] *S points to an instance of the Q31 PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clip.
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
- */
-
- static __INLINE q31_t arm_pid_q31(
- arm_pid_instance_q31 * S,
- q31_t in)
- {
- q63_t acc;
- q31_t out;
-
- /* acc = A0 * x[n] */
- acc = (q63_t) S->A0 * in;
-
- /* acc += A1 * x[n-1] */
- acc += (q63_t) S->A1 * S->state[0];
-
- /* acc += A2 * x[n-2] */
- acc += (q63_t) S->A2 * S->state[1];
-
- /* convert output to 1.31 format to add y[n-1] */
- out = (q31_t) (acc >> 31u);
-
- /* out += y[n-1] */
- out += S->state[2];
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- * @brief Process function for the Q15 PID Control.
- * @param[in,out] *S points to an instance of the Q15 PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.
- */
-
- static __INLINE q15_t arm_pid_q15(
- arm_pid_instance_q15 * S,
- q15_t in)
- {
- q63_t acc;
- q15_t out;
-
-#ifndef ARM_MATH_CM0_FAMILY
- __SIMD32_TYPE *vstate;
-
- /* Implementation of PID controller */
-
- /* acc = A0 * x[n] */
- acc = (q31_t) __SMUAD(S->A0, in);
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- vstate = __SIMD32_CONST(S->state);
- acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
-
-#else
- /* acc = A0 * x[n] */
- acc = ((q31_t) S->A0) * in;
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- acc += (q31_t) S->A1 * S->state[0];
- acc += (q31_t) S->A2 * S->state[1];
-
-#endif
-
- /* acc += y[n-1] */
- acc += (q31_t) S->state[2] << 15;
-
- /* saturate the output */
- out = (q15_t) (__SSAT((acc >> 15), 16));
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- * @} end of PID group
- */
-
-
- /**
- * @brief Floating-point matrix inverse.
- * @param[in] *src points to the instance of the input floating-point matrix structure.
- * @param[out] *dst points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
-
- arm_status arm_mat_inverse_f32(
- const arm_matrix_instance_f32 * src,
- arm_matrix_instance_f32 * dst);
-
-
- /**
- * @brief Floating-point matrix inverse.
- * @param[in] *src points to the instance of the input floating-point matrix structure.
- * @param[out] *dst points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
-
- arm_status arm_mat_inverse_f64(
- const arm_matrix_instance_f64 * src,
- arm_matrix_instance_f64 * dst);
-
-
-
- /**
- * @ingroup groupController
- */
-
-
- /**
- * @defgroup clarke Vector Clarke Transform
- * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
- * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
- * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
- * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
- * \image html clarke.gif Stator current space vector and its components in (a,b).
- * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
- * can be calculated using only <code>Ia</code> and <code>Ib</code>.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeFormula.gif
- * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
- * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup clarke
- * @{
- */
-
- /**
- *
- * @brief Floating-point Clarke transform
- * @param[in] Ia input three-phase coordinate <code>a</code>
- * @param[in] Ib input three-phase coordinate <code>b</code>
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
- * @return none.
- */
-
- static __INLINE void arm_clarke_f32(
- float32_t Ia,
- float32_t Ib,
- float32_t * pIalpha,
- float32_t * pIbeta)
- {
- /* Calculate pIalpha using the equation, pIalpha = Ia */
- *pIalpha = Ia;
-
- /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
- *pIbeta =
- ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-
- }
-
- /**
- * @brief Clarke transform for Q31 version
- * @param[in] Ia input three-phase coordinate <code>a</code>
- * @param[in] Ib input three-phase coordinate <code>b</code>
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
- * @return none.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
-
- static __INLINE void arm_clarke_q31(
- q31_t Ia,
- q31_t Ib,
- q31_t * pIalpha,
- q31_t * pIbeta)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
-
- /* Calculating pIalpha from Ia by equation pIalpha = Ia */
- *pIalpha = Ia;
-
- /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
- product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
- /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
- product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
- /* pIbeta is calculated by adding the intermediate products */
- *pIbeta = __QADD(product1, product2);
- }
-
- /**
- * @} end of clarke group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to Q31 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_q7_to_q31(
- q7_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup inv_clarke Vector Inverse Clarke Transform
- * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeInvFormula.gif
- * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
- * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup inv_clarke
- * @{
- */
-
- /**
- * @brief Floating-point Inverse Clarke transform
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha
- * @param[in] Ibeta input two-phase orthogonal vector axis beta
- * @param[out] *pIa points to output three-phase coordinate <code>a</code>
- * @param[out] *pIb points to output three-phase coordinate <code>b</code>
- * @return none.
- */
-
-
- static __INLINE void arm_inv_clarke_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pIa,
- float32_t * pIb)
- {
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */
- *pIa = Ialpha;
-
- /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
- *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
-
- }
-
- /**
- * @brief Inverse Clarke transform for Q31 version
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha
- * @param[in] Ibeta input two-phase orthogonal vector axis beta
- * @param[out] *pIa points to output three-phase coordinate <code>a</code>
- * @param[out] *pIb points to output three-phase coordinate <code>b</code>
- * @return none.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the subtraction, hence there is no risk of overflow.
- */
-
- static __INLINE void arm_inv_clarke_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pIa,
- q31_t * pIb)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
-
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */
- *pIa = Ialpha;
-
- /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
- product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
- /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
- product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
- /* pIb is calculated by subtracting the products */
- *pIb = __QSUB(product2, product1);
-
- }
-
- /**
- * @} end of inv_clarke group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to Q15 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_q7_to_q15(
- q7_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup park Vector Park Transform
- *
- * Forward Park transform converts the input two-coordinate vector to flux and torque components.
- * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
- * from the stationary to the moving reference frame and control the spatial relationship between
- * the stator vector current and rotor flux vector.
- * If we consider the d axis aligned with the rotor flux, the diagram below shows the
- * current vector and the relationship from the two reference frames:
- * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkFormula.gif
- * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
- * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup park
- * @{
- */
-
- /**
- * @brief Floating-point Park transform
- * @param[in] Ialpha input two-phase vector coordinate alpha
- * @param[in] Ibeta input two-phase vector coordinate beta
- * @param[out] *pId points to output rotor reference frame d
- * @param[out] *pIq points to output rotor reference frame q
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- * @return none.
- *
- * The function implements the forward Park transform.
- *
- */
-
- static __INLINE void arm_park_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pId,
- float32_t * pIq,
- float32_t sinVal,
- float32_t cosVal)
- {
- /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
- *pId = Ialpha * cosVal + Ibeta * sinVal;
-
- /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
- *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-
- }
-
- /**
- * @brief Park transform for Q31 version
- * @param[in] Ialpha input two-phase vector coordinate alpha
- * @param[in] Ibeta input two-phase vector coordinate beta
- * @param[out] *pId points to output rotor reference frame d
- * @param[out] *pIq points to output rotor reference frame q
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- * @return none.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition and subtraction, hence there is no risk of overflow.
- */
-
-
- static __INLINE void arm_park_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pId,
- q31_t * pIq,
- q31_t sinVal,
- q31_t cosVal)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
- q31_t product3, product4; /* Temporary variables used to store intermediate results */
-
- /* Intermediate product is calculated by (Ialpha * cosVal) */
- product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
- /* Intermediate product is calculated by (Ibeta * sinVal) */
- product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
- /* Intermediate product is calculated by (Ialpha * sinVal) */
- product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
- /* Intermediate product is calculated by (Ibeta * cosVal) */
- product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
- /* Calculate pId by adding the two intermediate products 1 and 2 */
- *pId = __QADD(product1, product2);
-
- /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
- *pIq = __QSUB(product4, product3);
- }
-
- /**
- * @} end of park group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q7_to_float(
- q7_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup inv_park Vector Inverse Park transform
- * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkInvFormula.gif
- * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
- * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup inv_park
- * @{
- */
-
- /**
- * @brief Floating-point Inverse Park transform
- * @param[in] Id input coordinate of rotor reference frame d
- * @param[in] Iq input coordinate of rotor reference frame q
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- * @return none.
- */
-
- static __INLINE void arm_inv_park_f32(
- float32_t Id,
- float32_t Iq,
- float32_t * pIalpha,
- float32_t * pIbeta,
- float32_t sinVal,
- float32_t cosVal)
- {
- /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
- *pIalpha = Id * cosVal - Iq * sinVal;
-
- /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
- *pIbeta = Id * sinVal + Iq * cosVal;
-
- }
-
-
- /**
- * @brief Inverse Park transform for Q31 version
- * @param[in] Id input coordinate of rotor reference frame d
- * @param[in] Iq input coordinate of rotor reference frame q
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- * @return none.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
-
-
- static __INLINE void arm_inv_park_q31(
- q31_t Id,
- q31_t Iq,
- q31_t * pIalpha,
- q31_t * pIbeta,
- q31_t sinVal,
- q31_t cosVal)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
- q31_t product3, product4; /* Temporary variables used to store intermediate results */
-
- /* Intermediate product is calculated by (Id * cosVal) */
- product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
- /* Intermediate product is calculated by (Iq * sinVal) */
- product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
- /* Intermediate product is calculated by (Id * sinVal) */
- product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
- /* Intermediate product is calculated by (Iq * cosVal) */
- product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
- /* Calculate pIalpha by using the two intermediate products 1 and 2 */
- *pIalpha = __QSUB(product1, product2);
-
- /* Calculate pIbeta by using the two intermediate products 3 and 4 */
- *pIbeta = __QADD(product4, product3);
-
- }
-
- /**
- * @} end of Inverse park group
- */
-
-
- /**
- * @brief Converts the elements of the Q31 vector to floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q31_to_float(
- q31_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @ingroup groupInterpolation
- */
-
- /**
- * @defgroup LinearInterpolate Linear Interpolation
- *
- * Linear interpolation is a method of curve fitting using linear polynomials.
- * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
- *
- * \par
- * \image html LinearInterp.gif "Linear interpolation"
- *
- * \par
- * A Linear Interpolate function calculates an output value(y), for the input(x)
- * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
- *
- * \par Algorithm:
- * <pre>
- * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
- * where x0, x1 are nearest values of input x
- * y0, y1 are nearest values to output y
- * </pre>
- *
- * \par
- * This set of functions implements Linear interpolation process
- * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
- * sample of data and each call to the function returns a single processed value.
- * <code>S</code> points to an instance of the Linear Interpolate function data structure.
- * <code>x</code> is the input sample value. The functions returns the output value.
- *
- * \par
- * if x is outside of the table boundary, Linear interpolation returns first value of the table
- * if x is below input range and returns last value of table if x is above range.
- */
-
- /**
- * @addtogroup LinearInterpolate
- * @{
- */
-
- /**
- * @brief Process function for the floating-point Linear Interpolation Function.
- * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
- * @param[in] x input sample to process
- * @return y processed output sample.
- *
- */
-
- static __INLINE float32_t arm_linear_interp_f32(
- arm_linear_interp_instance_f32 * S,
- float32_t x)
- {
-
- float32_t y;
- float32_t x0, x1; /* Nearest input values */
- float32_t y0, y1; /* Nearest output values */
- float32_t xSpacing = S->xSpacing; /* spacing between input values */
- int32_t i; /* Index variable */
- float32_t *pYData = S->pYData; /* pointer to output table */
-
- /* Calculation of index */
- i = (int32_t) ((x - S->x1) / xSpacing);
-
- if(i < 0)
- {
- /* Iniatilize output for below specified range as least output value of table */
- y = pYData[0];
- }
- else if((uint32_t)i >= S->nValues)
- {
- /* Iniatilize output for above specified range as last output value of table */
- y = pYData[S->nValues - 1];
- }
- else
- {
- /* Calculation of nearest input values */
- x0 = S->x1 + i * xSpacing;
- x1 = S->x1 + (i + 1) * xSpacing;
-
- /* Read of nearest output values */
- y0 = pYData[i];
- y1 = pYData[i + 1];
-
- /* Calculation of output */
- y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
- }
-
- /* returns output value */
- return (y);
- }
-
- /**
- *
- * @brief Process function for the Q31 Linear Interpolation Function.
- * @param[in] *pYData pointer to Q31 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
-
-
- static __INLINE q31_t arm_linear_interp_q31(
- q31_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q31_t y; /* output */
- q31_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & 0xFFF00000) >> 20);
-
- if(index >= (int32_t)(nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else if(index < 0)
- {
- return (pYData[0]);
- }
- else
- {
-
- /* 20 bits for the fractional part */
- /* shift left by 11 to keep fract in 1.31 format */
- fract = (x & 0x000FFFFF) << 11;
-
- /* Read two nearest output values from the index in 1.31(q31) format */
- y0 = pYData[index];
- y1 = pYData[index + 1u];
-
- /* Calculation of y0 * (1-fract) and y is in 2.30 format */
- y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
- /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
- y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
- /* Convert y to 1.31 format */
- return (y << 1u);
-
- }
-
- }
-
- /**
- *
- * @brief Process function for the Q15 Linear Interpolation Function.
- * @param[in] *pYData pointer to Q15 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
-
-
- static __INLINE q15_t arm_linear_interp_q15(
- q15_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q63_t y; /* output */
- q15_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & 0xFFF00000) >> 20u);
-
- if(index >= (int32_t)(nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else if(index < 0)
- {
- return (pYData[0]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y0 = pYData[index];
- y1 = pYData[index + 1u];
-
- /* Calculation of y0 * (1-fract) and y is in 13.35 format */
- y = ((q63_t) y0 * (0xFFFFF - fract));
-
- /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
- y += ((q63_t) y1 * (fract));
-
- /* convert y to 1.15 format */
- return (y >> 20);
- }
-
-
- }
-
- /**
- *
- * @brief Process function for the Q7 Linear Interpolation Function.
- * @param[in] *pYData pointer to Q7 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- */
-
-
- static __INLINE q7_t arm_linear_interp_q7(
- q7_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q31_t y; /* output */
- q7_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- uint32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- if (x < 0)
- {
- return (pYData[0]);
- }
- index = (x >> 20) & 0xfff;
-
-
- if(index >= (nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else
- {
-
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index and are in 1.7(q7) format */
- y0 = pYData[index];
- y1 = pYData[index + 1u];
-
- /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
- y = ((y0 * (0xFFFFF - fract)));
-
- /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
- y += (y1 * fract);
-
- /* convert y to 1.7(q7) format */
- return (y >> 20u);
-
- }
-
- }
- /**
- * @} end of LinearInterpolate group
- */
-
- /**
- * @brief Fast approximation to the trigonometric sine function for floating-point data.
- * @param[in] x input value in radians.
- * @return sin(x).
- */
-
- float32_t arm_sin_f32(
- float32_t x);
-
- /**
- * @brief Fast approximation to the trigonometric sine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- */
-
- q31_t arm_sin_q31(
- q31_t x);
-
- /**
- * @brief Fast approximation to the trigonometric sine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- */
-
- q15_t arm_sin_q15(
- q15_t x);
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for floating-point data.
- * @param[in] x input value in radians.
- * @return cos(x).
- */
-
- float32_t arm_cos_f32(
- float32_t x);
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- */
-
- q31_t arm_cos_q31(
- q31_t x);
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- */
-
- q15_t arm_cos_q15(
- q15_t x);
-
-
- /**
- * @ingroup groupFastMath
- */
-
-
- /**
- * @defgroup SQRT Square Root
- *
- * Computes the square root of a number.
- * There are separate functions for Q15, Q31, and floating-point data types.
- * The square root function is computed using the Newton-Raphson algorithm.
- * This is an iterative algorithm of the form:
- * <pre>
- * x1 = x0 - f(x0)/f'(x0)
- * </pre>
- * where <code>x1</code> is the current estimate,
- * <code>x0</code> is the previous estimate, and
- * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
- * For the square root function, the algorithm reduces to:
- * <pre>
- * x0 = in/2 [initial guess]
- * x1 = 1/2 * ( x0 + in / x0) [each iteration]
- * </pre>
- */
-
-
- /**
- * @addtogroup SQRT
- * @{
- */
-
- /**
- * @brief Floating-point square root function.
- * @param[in] in input value.
- * @param[out] *pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
-
- static __INLINE arm_status arm_sqrt_f32(
- float32_t in,
- float32_t * pOut)
- {
- if(in > 0)
- {
-
-// #if __FPU_USED
-#if (__FPU_USED == 1) && defined ( __CC_ARM )
- *pOut = __sqrtf(in);
-#else
- *pOut = sqrtf(in);
-#endif
-
- return (ARM_MATH_SUCCESS);
- }
- else
- {
- *pOut = 0.0f;
- return (ARM_MATH_ARGUMENT_ERROR);
- }
-
- }
-
-
- /**
- * @brief Q31 square root function.
- * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
- * @param[out] *pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
- arm_status arm_sqrt_q31(
- q31_t in,
- q31_t * pOut);
-
- /**
- * @brief Q15 square root function.
- * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
- * @param[out] *pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
- arm_status arm_sqrt_q15(
- q15_t in,
- q15_t * pOut);
-
- /**
- * @} end of SQRT group
- */
-
-
-
-
-
-
- /**
- * @brief floating-point Circular write function.
- */
-
- static __INLINE void arm_circularWrite_f32(
- int32_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const int32_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = wOffset;
- }
-
-
-
- /**
- * @brief floating-point Circular Read function.
- */
- static __INLINE void arm_circularRead_f32(
- int32_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- int32_t * dst,
- int32_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if(dst == (int32_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if(rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
- /**
- * @brief Q15 Circular write function.
- */
-
- static __INLINE void arm_circularWrite_q15(
- q15_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q15_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = wOffset;
- }
-
-
-
- /**
- * @brief Q15 Circular Read function.
- */
- static __INLINE void arm_circularRead_q15(
- q15_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q15_t * dst,
- q15_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
-
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if(dst == (q15_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if(rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Q7 Circular write function.
- */
-
- static __INLINE void arm_circularWrite_q7(
- q7_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q7_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = wOffset;
- }
-
-
-
- /**
- * @brief Q7 Circular Read function.
- */
- static __INLINE void arm_circularRead_q7(
- q7_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q7_t * dst,
- q7_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
-
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if(dst == (q7_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if(rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Sum of the squares of the elements of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_power_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
- /**
- * @brief Sum of the squares of the elements of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_power_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Sum of the squares of the elements of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_power_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
- /**
- * @brief Sum of the squares of the elements of a Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_power_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Mean value of a Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_mean_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult);
-
- /**
- * @brief Mean value of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
- void arm_mean_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
- /**
- * @brief Mean value of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
- void arm_mean_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Mean value of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
- void arm_mean_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Variance of the elements of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_var_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Variance of the elements of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_var_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Variance of the elements of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_var_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
- /**
- * @brief Root Mean Square of the elements of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_rms_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Root Mean Square of the elements of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_rms_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Root Mean Square of the elements of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_rms_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
- /**
- * @brief Standard deviation of the elements of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_std_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Standard deviation of the elements of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_std_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Standard deviation of the elements of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_std_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
- /**
- * @brief Floating-point complex magnitude
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex magnitude
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q15 complex magnitude
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q15 complex dot product
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] *realResult real part of the result returned here
- * @param[out] *imagResult imaginary part of the result returned here
- * @return none.
- */
-
- void arm_cmplx_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t numSamples,
- q31_t * realResult,
- q31_t * imagResult);
-
- /**
- * @brief Q31 complex dot product
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] *realResult real part of the result returned here
- * @param[out] *imagResult imaginary part of the result returned here
- * @return none.
- */
-
- void arm_cmplx_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t numSamples,
- q63_t * realResult,
- q63_t * imagResult);
-
- /**
- * @brief Floating-point complex dot product
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] *realResult real part of the result returned here
- * @param[out] *imagResult imaginary part of the result returned here
- * @return none.
- */
-
- void arm_cmplx_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t numSamples,
- float32_t * realResult,
- float32_t * imagResult);
-
- /**
- * @brief Q15 complex-by-real multiplication
- * @param[in] *pSrcCmplx points to the complex input vector
- * @param[in] *pSrcReal points to the real input vector
- * @param[out] *pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_real_q15(
- q15_t * pSrcCmplx,
- q15_t * pSrcReal,
- q15_t * pCmplxDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex-by-real multiplication
- * @param[in] *pSrcCmplx points to the complex input vector
- * @param[in] *pSrcReal points to the real input vector
- * @param[out] *pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_real_q31(
- q31_t * pSrcCmplx,
- q31_t * pSrcReal,
- q31_t * pCmplxDst,
- uint32_t numSamples);
-
- /**
- * @brief Floating-point complex-by-real multiplication
- * @param[in] *pSrcCmplx points to the complex input vector
- * @param[in] *pSrcReal points to the real input vector
- * @param[out] *pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_real_f32(
- float32_t * pSrcCmplx,
- float32_t * pSrcReal,
- float32_t * pCmplxDst,
- uint32_t numSamples);
-
- /**
- * @brief Minimum value of a Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *result is output pointer
- * @param[in] index is the array index of the minimum value in the input buffer.
- * @return none.
- */
-
- void arm_min_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * result,
- uint32_t * index);
-
- /**
- * @brief Minimum value of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output pointer
- * @param[in] *pIndex is the array index of the minimum value in the input buffer.
- * @return none.
- */
-
- void arm_min_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
-
- /**
- * @brief Minimum value of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output pointer
- * @param[out] *pIndex is the array index of the minimum value in the input buffer.
- * @return none.
- */
- void arm_min_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
-
- /**
- * @brief Minimum value of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output pointer
- * @param[out] *pIndex is the array index of the minimum value in the input buffer.
- * @return none.
- */
-
- void arm_min_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in] *pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
- void arm_max_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult,
- uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in] *pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
- void arm_max_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in] *pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
- void arm_max_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in] *pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
- void arm_max_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
-
- /**
- * @brief Q15 complex-by-complex multiplication
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_cmplx_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex-by-complex multiplication
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_cmplx_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Floating-point complex-by-complex multiplication
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_cmplx_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Converts the elements of the floating-point vector to Q31 vector.
- * @param[in] *pSrc points to the floating-point input vector
- * @param[out] *pDst points to the Q31 output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- */
- void arm_float_to_q31(
- float32_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Converts the elements of the floating-point vector to Q15 vector.
- * @param[in] *pSrc points to the floating-point input vector
- * @param[out] *pDst points to the Q15 output vector
- * @param[in] blockSize length of the input vector
- * @return none
- */
- void arm_float_to_q15(
- float32_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Converts the elements of the floating-point vector to Q7 vector.
- * @param[in] *pSrc points to the floating-point input vector
- * @param[out] *pDst points to the Q7 output vector
- * @param[in] blockSize length of the input vector
- * @return none
- */
- void arm_float_to_q7(
- float32_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q31 vector to Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q31_to_q15(
- q31_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Converts the elements of the Q31 vector to Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q31_to_q7(
- q31_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Converts the elements of the Q15 vector to floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q15_to_float(
- q15_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q15_to_q31(
- q15_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q15_to_q7(
- q15_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @ingroup groupInterpolation
- */
-
- /**
- * @defgroup BilinearInterpolate Bilinear Interpolation
- *
- * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
- * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
- * determines values between the grid points.
- * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
- * Bilinear interpolation is often used in image processing to rescale images.
- * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
- *
- * <b>Algorithm</b>
- * \par
- * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
- * For floating-point, the instance structure is defined as:
- * <pre>
- * typedef struct
- * {
- * uint16_t numRows;
- * uint16_t numCols;
- * float32_t *pData;
- * } arm_bilinear_interp_instance_f32;
- * </pre>
- *
- * \par
- * where <code>numRows</code> specifies the number of rows in the table;
- * <code>numCols</code> specifies the number of columns in the table;
- * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
- * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
- * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
- *
- * \par
- * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
- * <pre>
- * XF = floor(x)
- * YF = floor(y)
- * </pre>
- * \par
- * The interpolated output point is computed as:
- * <pre>
- * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
- * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
- * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
- * + f(XF+1, YF+1) * (x-XF)*(y-YF)
- * </pre>
- * Note that the coordinates (x, y) contain integer and fractional components.
- * The integer components specify which portion of the table to use while the
- * fractional components control the interpolation processor.
- *
- * \par
- * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
- */
-
- /**
- * @addtogroup BilinearInterpolate
- * @{
- */
-
- /**
- *
- * @brief Floating-point bilinear interpolation.
- * @param[in,out] *S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate.
- * @param[in] Y interpolation coordinate.
- * @return out interpolated value.
- */
-
-
- static __INLINE float32_t arm_bilinear_interp_f32(
- const arm_bilinear_interp_instance_f32 * S,
- float32_t X,
- float32_t Y)
- {
- float32_t out;
- float32_t f00, f01, f10, f11;
- float32_t *pData = S->pData;
- int32_t xIndex, yIndex, index;
- float32_t xdiff, ydiff;
- float32_t b1, b2, b3, b4;
-
- xIndex = (int32_t) X;
- yIndex = (int32_t) Y;
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
- || yIndex > (S->numCols - 1))
- {
- return (0);
- }
-
- /* Calculation of index for two nearest points in X-direction */
- index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
- /* Read two nearest points in X-direction */
- f00 = pData[index];
- f01 = pData[index + 1];
-
- /* Calculation of index for two nearest points in Y-direction */
- index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
- /* Read two nearest points in Y-direction */
- f10 = pData[index];
- f11 = pData[index + 1];
-
- /* Calculation of intermediate values */
- b1 = f00;
- b2 = f01 - f00;
- b3 = f10 - f00;
- b4 = f00 - f01 - f10 + f11;
-
- /* Calculation of fractional part in X */
- xdiff = X - xIndex;
-
- /* Calculation of fractional part in Y */
- ydiff = Y - yIndex;
-
- /* Calculation of bi-linear interpolated output */
- out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- *
- * @brief Q31 bilinear interpolation.
- * @param[in,out] *S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
-
- static __INLINE q31_t arm_bilinear_interp_q31(
- arm_bilinear_interp_instance_q31 * S,
- q31_t X,
- q31_t Y)
- {
- q31_t out; /* Temporary output */
- q31_t acc = 0; /* output */
- q31_t xfract, yfract; /* X, Y fractional parts */
- q31_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
- q31_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & 0xFFF00000) >> 20u);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & 0xFFF00000) >> 20u);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* shift left xfract by 11 to keep 1.31 format */
- xfract = (X & 0x000FFFFF) << 11u;
-
- /* Read two nearest output values from the index */
- x1 = pYData[(rI) + nCols * (cI)];
- x2 = pYData[(rI) + nCols * (cI) + 1u];
-
- /* 20 bits for the fractional part */
- /* shift left yfract by 11 to keep 1.31 format */
- yfract = (Y & 0x000FFFFF) << 11u;
-
- /* Read two nearest output values from the index */
- y1 = pYData[(rI) + nCols * (cI + 1)];
- y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
- out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
- acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
- /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
- /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
- /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
- /* Convert acc to 1.31(q31) format */
- return (acc << 2u);
-
- }
-
- /**
- * @brief Q15 bilinear interpolation.
- * @param[in,out] *S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
-
- static __INLINE q15_t arm_bilinear_interp_q15(
- arm_bilinear_interp_instance_q15 * S,
- q31_t X,
- q31_t Y)
- {
- q63_t acc = 0; /* output */
- q31_t out; /* Temporary output */
- q15_t x1, x2, y1, y2; /* Nearest output values */
- q31_t xfract, yfract; /* X, Y fractional parts */
- int32_t rI, cI; /* Row and column indices */
- q15_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & 0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & 0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* xfract should be in 12.20 format */
- xfract = (X & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- x1 = pYData[(rI) + nCols * (cI)];
- x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
- /* 20 bits for the fractional part */
- /* yfract should be in 12.20 format */
- yfract = (Y & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y1 = pYData[(rI) + nCols * (cI + 1)];
- y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
- /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
- /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
- out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
- acc = ((q63_t) out * (0xFFFFF - yfract));
-
- /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
- acc += ((q63_t) out * (xfract));
-
- /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
- acc += ((q63_t) out * (yfract));
-
- /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
- acc += ((q63_t) out * (yfract));
-
- /* acc is in 13.51 format and down shift acc by 36 times */
- /* Convert out to 1.15 format */
- return (acc >> 36);
-
- }
-
- /**
- * @brief Q7 bilinear interpolation.
- * @param[in,out] *S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
-
- static __INLINE q7_t arm_bilinear_interp_q7(
- arm_bilinear_interp_instance_q7 * S,
- q31_t X,
- q31_t Y)
- {
- q63_t acc = 0; /* output */
- q31_t out; /* Temporary output */
- q31_t xfract, yfract; /* X, Y fractional parts */
- q7_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
- q7_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & 0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & 0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* xfract should be in 12.20 format */
- xfract = (X & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- x1 = pYData[(rI) + nCols * (cI)];
- x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
- /* 20 bits for the fractional part */
- /* yfract should be in 12.20 format */
- yfract = (Y & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y1 = pYData[(rI) + nCols * (cI + 1)];
- y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
- out = ((x1 * (0xFFFFF - xfract)));
- acc = (((q63_t) out * (0xFFFFF - yfract)));
-
- /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
- out = ((x2 * (0xFFFFF - yfract)));
- acc += (((q63_t) out * (xfract)));
-
- /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
- out = ((y1 * (0xFFFFF - xfract)));
- acc += (((q63_t) out * (yfract)));
-
- /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
- out = ((y2 * (yfract)));
- acc += (((q63_t) out * (xfract)));
-
- /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
- return (acc >> 40);
-
- }
-
- /**
- * @} end of BilinearInterpolate group
- */
-
-
-//SMMLAR
-#define multAcc_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-//SMMLSR
-#define multSub_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-//SMMULR
-#define mult_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-//SMMLA
-#define multAcc_32x32_keep32(a, x, y) \
- a += (q31_t) (((q63_t) x * y) >> 32)
-
-//SMMLS
-#define multSub_32x32_keep32(a, x, y) \
- a -= (q31_t) (((q63_t) x * y) >> 32)
-
-//SMMUL
-#define mult_32x32_keep32(a, x, y) \
- a = (q31_t) (((q63_t) x * y ) >> 32)
-
-
-#if defined ( __CC_ARM ) //Keil
-
-//Enter low optimization region - place directly above function definition
- #ifdef ARM_MATH_CM4
- #define LOW_OPTIMIZATION_ENTER \
- _Pragma ("push") \
- _Pragma ("O1")
- #else
- #define LOW_OPTIMIZATION_ENTER
- #endif
-
-//Exit low optimization region - place directly after end of function definition
- #ifdef ARM_MATH_CM4
- #define LOW_OPTIMIZATION_EXIT \
- _Pragma ("pop")
- #else
- #define LOW_OPTIMIZATION_EXIT
- #endif
-
-//Enter low optimization region - place directly above function definition
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-//Exit low optimization region - place directly after end of function definition
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__ICCARM__) //IAR
-
-//Enter low optimization region - place directly above function definition
- #ifdef ARM_MATH_CM4
- #define LOW_OPTIMIZATION_ENTER \
- _Pragma ("optimize=low")
- #else
- #define LOW_OPTIMIZATION_ENTER
- #endif
-
-//Exit low optimization region - place directly after end of function definition
- #define LOW_OPTIMIZATION_EXIT
-
-//Enter low optimization region - place directly above function definition
- #ifdef ARM_MATH_CM4
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
- _Pragma ("optimize=low")
- #else
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #endif
-
-//Exit low optimization region - place directly after end of function definition
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__GNUC__)
-
- #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
-
- #define LOW_OPTIMIZATION_EXIT
-
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__CSMC__) // Cosmic
-
-#define LOW_OPTIMIZATION_ENTER
-#define LOW_OPTIMIZATION_EXIT
-#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/core_cm7.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/core_cm7.h
deleted file mode 100644
index e21e9e2..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/core_cm7.h
+++ /dev/null
@@ -1,2221 +0,0 @@
-/**************************************************************************//**
- * @file core_cm7.h
- * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version V4.00
- * @date 01. September 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM7_H_GENERIC
-#define __CORE_CM7_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M7
- @{
- */
-
-/* CMSIS CM7 definitions */
-#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
-#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
-#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
- __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x07) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __CSMC__ )
- #define __packed
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
- #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __CSMC__ ) /* Cosmic */
- #if ( __CSMC__ & 0x400) // FPU present for parser
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-#endif
-
-#include <stdint.h> /* standard types definitions */
-#include <core_cmInstr.h> /* Core Instruction Access */
-#include <core_cmFunc.h> /* Core Function Access */
-#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM7_H_DEPENDANT
-#define __CORE_CM7_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM7_REV
- #define __CM7_REV 0x0000
- #warning "__CM7_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __ICACHE_PRESENT
- #define __ICACHE_PRESENT 0
- #warning "__ICACHE_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __DCACHE_PRESENT
- #define __DCACHE_PRESENT 0
- #warning "__DCACHE_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __DTCM_PRESENT
- #define __DTCM_PRESENT 0
- #warning "__DTCM_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex_M7 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core FPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x07)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x07)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[1];
- __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
- __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
- __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
- __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
- uint32_t RESERVED3[93];
- __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
- uint32_t RESERVED4[15];
- __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
- __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
- __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
- uint32_t RESERVED5[1];
- __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
- uint32_t RESERVED6[1];
- __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
- __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
- __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
- __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
- __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
- __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
- __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
- __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
- uint32_t RESERVED7[6];
- __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
- __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
- __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
- __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
- __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
- uint32_t RESERVED8[1];
- __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
-
-#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
-
-#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
-
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-
-/* Cache Level ID register */
-#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
-
-/* Cache Type register */
-#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */
-
-/* Cache Size ID Register */
-#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */
-
-/* Cache Size Selection Register */
-#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register */
-#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register*/
-#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk (0x1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk (0x1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk (0x1UL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Registers */
-#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register */
-#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register */
-#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */
-
-/* AHBS control register */
-#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register */
-#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/** \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
-
-#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
-#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
-
-#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
-#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1];
- __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1];
- __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1];
- __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED3[981];
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/** \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2];
- __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55];
- __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131];
- __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759];
- __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1];
- __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39];
- __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8];
- __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/** \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/** \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
- __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
-
-/* Media and FP Feature Register 2 */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/** \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-#if (__FPU_PRESENT == 1)
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/** \brief Set Priority Grouping
-
- The function sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/** \brief Get Priority Grouping
-
- The function reads the priority grouping field from the NVIC Interrupt Controller.
-
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-}
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
- NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Get Active Interrupt
-
- The function reads the active register in NVIC and returns the active bit.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief Encode Priority
-
- The function encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
- );
-}
-
-
-/** \brief Decode Priority
-
- The function decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## Cache functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_CacheFunctions Cache Functions
- \brief Functions that configure Instruction and Data cache.
- @{
- */
-
-/* Cache Size ID Register Macros */
-#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
-#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
-#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos )
-
-
-/** \brief Enable I-Cache
-
- The function turns on I-Cache
- */
-__STATIC_INLINE void SCB_EnableICache(void)
-{
- #if (__ICACHE_PRESENT == 1)
- __DSB();
- __ISB();
- SCB->ICIALLU = 0; // invalidate I-Cache
- SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache
- __DSB();
- __ISB();
- #endif
-}
-
-
-/** \brief Disable I-Cache
-
- The function turns off I-Cache
- */
-__STATIC_INLINE void SCB_DisableICache(void)
-{
- #if (__ICACHE_PRESENT == 1)
- __DSB();
- __ISB();
- SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache
- SCB->ICIALLU = 0; // invalidate I-Cache
- __DSB();
- __ISB();
- #endif
-}
-
-
-/** \brief Invalidate I-Cache
-
- The function invalidates I-Cache
- */
-__STATIC_INLINE void SCB_InvalidateICache(void)
-{
- #if (__ICACHE_PRESENT == 1)
- __DSB();
- __ISB();
- SCB->ICIALLU = 0;
- __DSB();
- __ISB();
- #endif
-}
-
-
-/** \brief Enable D-Cache
-
- The function turns on D-Cache
- */
-__STATIC_INLINE void SCB_EnableDCache(void)
-{
- #if (__DCACHE_PRESENT == 1)
- uint32_t ccsidr, sshift, wshift, sw;
- uint32_t sets, ways;
-
- ccsidr = SCB->CCSIDR;
- sets = CCSIDR_SETS(ccsidr);
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
- ways = CCSIDR_WAYS(ccsidr);
- wshift = __CLZ(ways) & 0x1f;
-
- __DSB();
-
- do { // invalidate D-Cache
- int32_t tmpways = ways;
- do {
- sw = ((tmpways << wshift) | (sets << sshift));
- SCB->DCISW = sw;
- } while(tmpways--);
- } while(sets--);
- __DSB();
-
- SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/** \brief Disable D-Cache
-
- The function turns off D-Cache
- */
-__STATIC_INLINE void SCB_DisableDCache(void)
-{
- #if (__DCACHE_PRESENT == 1)
- uint32_t ccsidr, sshift, wshift, sw;
- uint32_t sets, ways;
-
- ccsidr = SCB->CCSIDR;
- sets = CCSIDR_SETS(ccsidr);
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
- ways = CCSIDR_WAYS(ccsidr);
- wshift = __CLZ(ways) & 0x1f;
-
- __DSB();
-
- SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache
-
- do { // clean & invalidate D-Cache
- int32_t tmpways = ways;
- do {
- sw = ((tmpways << wshift) | (sets << sshift));
- SCB->DCCISW = sw;
- } while(tmpways--);
- } while(sets--);
-
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/** \brief Invalidate D-Cache
-
- The function invalidates D-Cache
- */
-__STATIC_INLINE void SCB_InvalidateDCache(void)
-{
- #if (__DCACHE_PRESENT == 1)
- uint32_t ccsidr, sshift, wshift, sw;
- uint32_t sets, ways;
-
- ccsidr = SCB->CCSIDR;
- sets = CCSIDR_SETS(ccsidr);
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
- ways = CCSIDR_WAYS(ccsidr);
- wshift = __CLZ(ways) & 0x1f;
-
- __DSB();
-
- do { // invalidate D-Cache
- int32_t tmpways = ways;
- do {
- sw = ((tmpways << wshift) | (sets << sshift));
- SCB->DCISW = sw;
- } while(tmpways--);
- } while(sets--);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/** \brief Clean D-Cache
-
- The function cleans D-Cache
- */
-__STATIC_INLINE void SCB_CleanDCache(void)
-{
- #if (__DCACHE_PRESENT == 1)
- uint32_t ccsidr, sshift, wshift, sw;
- uint32_t sets, ways;
-
- ccsidr = SCB->CCSIDR;
- sets = CCSIDR_SETS(ccsidr);
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
- ways = CCSIDR_WAYS(ccsidr);
- wshift = __CLZ(ways) & 0x1f;
-
- __DSB();
-
- do { // clean D-Cache
- int32_t tmpways = ways;
- do {
- sw = ((tmpways << wshift) | (sets << sshift));
- SCB->DCCSW = sw;
- } while(tmpways--);
- } while(sets--);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/** \brief Clean & Invalidate D-Cache
-
- The function cleans and Invalidates D-Cache
- */
-__STATIC_INLINE void SCB_CleanInvalidateDCache(void)
-{
- #if (__DCACHE_PRESENT == 1)
- uint32_t ccsidr, sshift, wshift, sw;
- uint32_t sets, ways;
-
- ccsidr = SCB->CCSIDR;
- sets = CCSIDR_SETS(ccsidr);
- sshift = CCSIDR_LSSHIFT(ccsidr) + 4;
- ways = CCSIDR_WAYS(ccsidr);
- wshift = __CLZ(ways) & 0x1f;
-
- __DSB();
-
- do { // clean & invalidate D-Cache
- int32_t tmpways = ways;
- do {
- sw = ((tmpways << wshift) | (sets << sshift));
- SCB->DCCISW = sw;
- } while(tmpways--);
- } while(sets--);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/*@} end of CMSIS_Core_CacheFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief ITM Send Character
-
- The function transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
- \param [in] ch Character to transmit.
-
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
-}
-
-
-/** \brief ITM Receive Character
-
- The function inputs a character via the external variable \ref ITM_RxBuffer.
-
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/** \brief ITM Check Character
-
- The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h
deleted file mode 100644
index 01089f1..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/core_cmFunc.h
+++ /dev/null
@@ -1,637 +0,0 @@
-/**************************************************************************//**
- * @file core_cmFunc.h
- * @brief CMSIS Cortex-M Core Function Access Header File
- * @version V4.00
- * @date 28. August 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-
-/** \brief Get IPSR Register
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
- register uint32_t __regIPSR __ASM("ipsr");
- return(__regIPSR);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
- register uint32_t __regXPSR __ASM("xpsr");
- return(__regXPSR);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- return(__regProcessStackPointer);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- return(__regMainStackPointer);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief Enable IRQ Interrupts
-
- This function enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief Disable IRQ Interrupts
-
- This function disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-/** \brief Get IPSR Register
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- uint32_t result;
-
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- __ASM volatile ("");
- return(result);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
- __ASM volatile ("");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-#endif /* __CORE_CMFUNC_H */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h
deleted file mode 100644
index 2e3bb0e..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/core_cmInstr.h
+++ /dev/null
@@ -1,880 +0,0 @@
-/**************************************************************************//**
- * @file core_cmInstr.h
- * @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V4.00
- * @date 28. August 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __nop
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-#define __WFI __wfi
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __wfe
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __sev
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-#define __ISB() __isb(0xF)
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() __dsb(0xF)
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() __dmb(0xF)
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV __rev
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
- rev16 r0, r0
- bx lr
-}
-#endif
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
- revsh r0, r0
- bx lr
-}
-#endif
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-#define __ROR __ror
-
-
-/** \brief Breakpoint
-
- This function causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __breakpoint(value)
-
-
-#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __RBIT __rbit
-
-
-/** \brief LDR Exclusive (8 bit)
-
- This function executes a exclusive LDR instruction for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function executes a exclusive LDR instruction for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function executes a exclusive LDR instruction for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function executes a exclusive STR instruction for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXB(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function executes a exclusive STR instruction for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXH(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function executes a exclusive STR instruction for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX __clrex
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT __ssat
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT __usat
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __clz
-
-
-/** \brief Rotate Right with Extend (32 bit)
-
- This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
-
- \param [in] value Value to rotate
- \return Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
- rrx r0, r0
- bx lr
-}
-#endif
-
-
-/** \brief LDRT Unprivileged (8 bit)
-
- This function executes a Unprivileged LDRT instruction for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
-
-
-/** \brief LDRT Unprivileged (16 bit)
-
- This function executes a Unprivileged LDRT instruction for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
-
-
-/** \brief LDRT Unprivileged (32 bit)
-
- This function executes a Unprivileged LDRT instruction for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
-
-
-/** \brief STRT Unprivileged (8 bit)
-
- This function executes a Unprivileged STRT instruction for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRBT(value, ptr) __strt(value, ptr)
-
-
-/** \brief STRT Unprivileged (16 bit)
-
- This function executes a Unprivileged STRT instruction for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRHT(value, ptr) __strt(value, ptr)
-
-
-/** \brief STRT Unprivileged (32 bit)
-
- This function executes a Unprivileged STRT instruction for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRT(value, ptr) __strt(value, ptr)
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
- * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
-{
- __ASM volatile ("nop");
-}
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
-{
- __ASM volatile ("wfi");
-}
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
-{
- __ASM volatile ("wfe");
-}
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
-{
- __ASM volatile ("sev");
-}
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
-{
- __ASM volatile ("isb");
-}
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
-{
- __ASM volatile ("dsb");
-}
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
-{
- __ASM volatile ("dmb");
-}
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
- return __builtin_bswap32(value);
-#else
- uint32_t result;
-
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- return (short)__builtin_bswap16(value);
-#else
- uint32_t result;
-
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- return (op1 >> op2) | (op1 << (32 - op2));
-}
-
-
-/** \brief Breakpoint
-
- This function causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-#if (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300))
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-
-/** \brief LDR Exclusive (8 bit)
-
- This function executes a exclusive LDR instruction for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function executes a exclusive LDR instruction for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function executes a exclusive LDR instruction for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function executes a exclusive STR instruction for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function executes a exclusive STR instruction for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function executes a exclusive STR instruction for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
-{
- __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/** \brief Rotate Right with Extend (32 bit)
-
- This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
-
- \param [in] value Value to rotate
- \return Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/** \brief LDRT Unprivileged (8 bit)
-
- This function executes a Unprivileged LDRT instruction for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/** \brief LDRT Unprivileged (16 bit)
-
- This function executes a Unprivileged LDRT instruction for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/** \brief LDRT Unprivileged (32 bit)
-
- This function executes a Unprivileged LDRT instruction for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/** \brief STRT Unprivileged (8 bit)
-
- This function executes a Unprivileged STRT instruction for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
-{
- __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief STRT Unprivileged (16 bit)
-
- This function executes a Unprivileged STRT instruction for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
-{
- __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief STRT Unprivileged (32 bit)
-
- This function executes a Unprivileged STRT instruction for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
-{
- __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/core_cmSimd.h b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/core_cmSimd.h
deleted file mode 100644
index ee58eee..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Include/core_cmSimd.h
+++ /dev/null
@@ -1,697 +0,0 @@
-/**************************************************************************//**
- * @file core_cmSimd.h
- * @brief CMSIS Cortex-M SIMD Header File
- * @version V4.00
- * @date 22. August 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CMSIMD_H
-#define __CORE_CMSIMD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-#define __SADD8 __sadd8
-#define __QADD8 __qadd8
-#define __SHADD8 __shadd8
-#define __UADD8 __uadd8
-#define __UQADD8 __uqadd8
-#define __UHADD8 __uhadd8
-#define __SSUB8 __ssub8
-#define __QSUB8 __qsub8
-#define __SHSUB8 __shsub8
-#define __USUB8 __usub8
-#define __UQSUB8 __uqsub8
-#define __UHSUB8 __uhsub8
-#define __SADD16 __sadd16
-#define __QADD16 __qadd16
-#define __SHADD16 __shadd16
-#define __UADD16 __uadd16
-#define __UQADD16 __uqadd16
-#define __UHADD16 __uhadd16
-#define __SSUB16 __ssub16
-#define __QSUB16 __qsub16
-#define __SHSUB16 __shsub16
-#define __USUB16 __usub16
-#define __UQSUB16 __uqsub16
-#define __UHSUB16 __uhsub16
-#define __SASX __sasx
-#define __QASX __qasx
-#define __SHASX __shasx
-#define __UASX __uasx
-#define __UQASX __uqasx
-#define __UHASX __uhasx
-#define __SSAX __ssax
-#define __QSAX __qsax
-#define __SHSAX __shsax
-#define __USAX __usax
-#define __UQSAX __uqsax
-#define __UHSAX __uhsax
-#define __USAD8 __usad8
-#define __USADA8 __usada8
-#define __SSAT16 __ssat16
-#define __USAT16 __usat16
-#define __UXTB16 __uxtb16
-#define __UXTAB16 __uxtab16
-#define __SXTB16 __sxtb16
-#define __SXTAB16 __sxtab16
-#define __SMUAD __smuad
-#define __SMUADX __smuadx
-#define __SMLAD __smlad
-#define __SMLADX __smladx
-#define __SMLALD __smlald
-#define __SMLALDX __smlaldx
-#define __SMUSD __smusd
-#define __SMUSDX __smusdx
-#define __SMLSD __smlsd
-#define __SMLSDX __smlsdx
-#define __SMLSLD __smlsld
-#define __SMLSLDX __smlsldx
-#define __SEL __sel
-#define __QADD __qadd
-#define __QSUB __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
- ((int64_t)(ARG3) << 32) ) >> 32))
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else // Big endian
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else // Big endian
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else // Big endian
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ // Little endian
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else // Big endian
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- if (ARG3 == 0) \
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/* not yet supported */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CMSIMD_H */
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Lib/GCC/libarm_cortexM7lfsp_math.a
deleted file mode 100644
index b01e81b5a55fb53cab77db33891053bf6a19f614..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001
literal 3199620
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diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Lib/license.txt b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Lib/license.txt
deleted file mode 100644
index 139c1ff..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/Lib/license.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-All pre-build libraries contained in the folders "ARM" and "GCC"
-are guided by the following license:
-
-Copyright (C) 2009-2014 ARM Limited.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
diff --git a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/README.txt b/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/README.txt
deleted file mode 100644
index e42a543..0000000
--- a/embedded/atsams70-hwtest/atsams70-hwtest/atsams70-hwtest/src/ASF/thirdparty/CMSIS/README.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-* -------------------------------------------------------------------
-* Copyright (C) 2011-2014 ARM Limited. All rights reserved.
-*
-* Date: 17 February 2014
-* Revision: V4.00
-*
-* Project: Cortex Microcontroller Software Interface Standard (CMSIS)
-* Title: Release Note for CMSIS
-*
-* -------------------------------------------------------------------
-
-
-NOTE - Open the index.html file to access CMSIS documentation
-
-
-The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all
-Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects
-and reduces time-to-market for new embedded applications.
-
-CMSIS is released under the terms of the end user license agreement ("CMSIS_END_USER_LICENCE_AGREEMENT.pdf").
-Any user of the software package is bound to the terms and conditions of the end user license agreement.
-
-
-You will find the following sub-directories:
-
-Documentation - Contains CMSIS documentation.
-
-DSP_Lib - MDK project files, Examples and source files etc.. to build the
- CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
-
-Include - CMSIS Core Support and CMSIS DSP Include Files.
-
-Lib - CMSIS DSP Libraries.
-
-RTOS - CMSIS RTOS API template header file.
-
-Driver - CMSIS Peripheral Driver Interface.
-
-Pack - CMSIS Software Packs.
- Mechanism to install software, device support, APIs, and example projects.
-
-SVD - CMSIS SVD Schema files and Conversion Utility.
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/boards/board.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/boards/board.h
deleted file mode 100644
index 0dc09cd..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/boards/board.h
+++ /dev/null
@@ -1,448 +0,0 @@
-/**
- * \file
- *
- * \brief Standard board header file.
- *
- * This file includes the appropriate board header file according to the
- * defined board (parameter BOARD).
- *
- * Copyright (c) 2009-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/**
- * \defgroup group_common_boards Generic board support
- *
- * The generic board support module includes board-specific definitions
- * and function prototypes, such as the board initialization function.
- *
- * \{
- */
-
-#include "compiler.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/*! \name Base Boards
- */
-//! @{
-#define EVK1100 1 //!< AT32UC3A EVK1100 board.
-#define EVK1101 2 //!< AT32UC3B EVK1101 board.
-#define UC3C_EK 3 //!< AT32UC3C UC3C-EK board.
-#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.
-#define EVK1105 5 //!< AT32UC3A EVK1105 board.
-#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board.
-#define UC3L_EK 7 //!< AT32UC3L-EK board.
-#define XPLAIN 8 //!< ATxmega128A1 Xplain board.
-#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board.
-#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board.
-#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board.
-#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board.
-#define STK600_RCUC3D 16 //!< STK600 RCUC3D board.
-#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board.
-#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board.
-#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board.
-#define XMEGA_A1U_XPLAINED_PRO 20 //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
-#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board.
-#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board.
-#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board.
-#define STK600_RC044X 24 //!< STK600 with RC044X routing card board.
-#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board.
-#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board.
-#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board.
-#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board.
-#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board.
-#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards.
-#define RZ600 31 //!< AT32UC3A RZ600 MCU board.
-#define SAM3S_EK 32 //!< SAM3S-EK board.
-#define SAM3U_EK 33 //!< SAM3U-EK board.
-#define SAM3X_EK 34 //!< SAM3X-EK board.
-#define SAM3N_EK 35 //!< SAM3N-EK board.
-#define SAM3S_EK2 36 //!< SAM3S-EK2 board.
-#define SAM4S_EK 37 //!< SAM4S-EK board.
-#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board.
-#define STK600_MEGA 39 //!< STK600 MEGA board.
-#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board.
-#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board.
-#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board.
-#define ARDUINO_DUE_X 43 //!< Arduino Due/X board.
-#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board.
-#define SAM4L_EK 45 //!< SAM4L-EK board.
-#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board.
-#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board.
-#define STK600_RC032X 48 //!< STK600 with RC032X routing card board.
-#define SAM4S_EK2 49 //!< SAM4S-EK2 board.
-#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board.
-#define SAM4E_EK 51 //!< SAM4E-EK board.
-#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board.
-#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board.
-#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board.
-#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit.
-#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 Zigbit.
-#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B Zigbit.
-#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board.
-#define SAMD20_XPLAINED_PRO 59 //!< SAM D20 Xplained Pro board.
-#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board.
-#define SAM4N_XPLAINED_PRO 61 //!< SAM4N Xplained Pro board.
-#define XMEGA_A3_REB_CBB 62 //!< XMEGA REB Controller Base board.
-#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB.
-#define SAM4C_EK 64 //!< SAM4C-EK board.
-#define RCB256RFR2_XPRO 65 //!< RFR2 RCB Xplained Pro board.
-#define SAMG53_XPLAINED_PRO 66 //!< SAMG53 Xplained Pro board.
-#define SAM4CP16BMB 67 //!< SAM4CP16BMB board.
-#define SAM4E_XPLAINED_PRO 68 //!< SAM4E Xplained Pro board.
-#define SAMD21_XPLAINED_PRO 69 //!< SAM D21 Xplained Pro board.
-#define SAMR21_XPLAINED_PRO 70 //!< SAM R21 Xplained Pro board.
-#define SAM4CMP_DB 71 //!< SAM4CMP demo board.
-#define SAM4CMS_DB 72 //!< SAM4CMS demo board.
-#define ATPL230AMB 73 //!< ATPL230AMB board.
-#define SAMD11_XPLAINED_PRO 74 //!< SAM D11 Xplained Pro board.
-#define SAMG55_XPLAINED_PRO 75 //!< SAMG55 Xplained Pro board.
-#define SAML21_XPLAINED_PRO 76 //!< SAM L21 Xplained Pro board.
-#define SAMD10_XPLAINED_MINI 77 //!< SAM D10 Xplained Mini board.
-#define SAMDA1_XPLAINED_PRO 78 //!< SAM DA1 Xplained Pro board.
-#define SAMW25_XPLAINED_PRO 79 //!< SAMW25 Xplained Pro board.
-#define SAMC21_XPLAINED_PRO 80 //!< SAM C21 Xplained Pro board.
-#define SAMV71_XPLAINED_ULTRA 81 //!< SAMV71 Xplained Ultra board.
-#define ATMEGA328P_XPLAINED_MINI 82 //!< ATMEGA328P Xplained MINI board.
-#define ATMEGA328PB_XPLAINED_MINI 83 //!< ATMEGA328PB Xplained MINI board.
-#define SAMB11_XPLAINED_PRO 84 //!< SAM B11 Xplained Pro board.
-#define SAME70_XPLAINED 85 //!< SAME70 Xplained board.
-#define SAML22_XPLAINED_PRO 86 //!< SAM L22 Xplained Pro board.
-#define SAML22_XPLAINED_PRO_B 87 //!< SAM L22 Xplained Pro board.
-#define SAMR21ZLL_EK 88 //!< SAMR21ZLL-EK board.
-#define ATMEGA168PB_XPLAINED_MINI 89 //!< ATMEGA168PB Xplained MINI board.
-#define ATMEGA324PB_XPLAINED_PRO 90 //!< ATMEGA324PB Xplained Pro board.
-#define SAMB11CSP_XPLAINED_PRO 91 //!< SAM B11 CSP Xplained Pro board.
-#define SAMB11ZR_XPLAINED_PRO 92 //!< SAM B11 ZR Xplained Pro board.
-#define SAMR30_XPLAINED_PRO 93 //!< SAM R30 Xplained Pro board.
-#define SAMHA1G16A_XPLAINED_PRO 94 //!< SAM HA1G16A Xplained Pro board.
-#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices.
-#define AVR_SIMULATOR_UC3 98 //!< Simulator for the AVR UC3 device family.
-#define USER_BOARD 99 //!< User-reserved board (if any).
-#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader).
-//! @}
-
-/*! \name Extension Boards
- */
-//! @{
-#define EXT1102 1 //!< AT32UC3B EXT1102 board
-#define MC300 2 //!< AT32UC3 MC300 board
-#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1
-#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2
-#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board
-#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board
-#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A"
-#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600
-#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600
-#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600
-#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard
-#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board
-#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).
-//! @}
-
-#if BOARD == EVK1100
-# include "evk1100/evk1100.h"
-#elif BOARD == EVK1101
-# include "evk1101/evk1101.h"
-#elif BOARD == UC3C_EK
-# include "uc3c_ek/uc3c_ek.h"
-#elif BOARD == EVK1104
-# include "evk1104/evk1104.h"
-#elif BOARD == EVK1105
-# include "evk1105/evk1105.h"
-#elif BOARD == STK600_RCUC3L0
-# include "stk600/rcuc3l0/stk600_rcuc3l0.h"
-#elif BOARD == UC3L_EK
-# include "uc3l_ek/uc3l_ek.h"
-#elif BOARD == STK600_RCUC3L4
-# include "stk600/rcuc3l4/stk600_rcuc3l4.h"
-#elif BOARD == XPLAIN
-# include "xplain/xplain.h"
-#elif BOARD == STK600_MEGA
- /*No header-file to include*/
-#elif BOARD == STK600_MEGA_RF
-# include "stk600.h"
-#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO
-# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"
-#elif BOARD == ATMEGA256RFR2_ZIGBIT
-# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"
-#elif BOARD == STK600_RC032X
-# include "stk600/rc032x/stk600_rc032x.h"
-#elif BOARD == STK600_RC044X
-# include "stk600/rc044x/stk600_rc044x.h"
-#elif BOARD == STK600_RC064X
-# include "stk600/rc064x/stk600_rc064x.h"
-#elif BOARD == STK600_RC100X
-# include "stk600/rc100x/stk600_rc100x.h"
-#elif BOARD == UC3_A3_XPLAINED
-# include "uc3_a3_xplained/uc3_a3_xplained.h"
-#elif BOARD == UC3_L0_XPLAINED
-# include "uc3_l0_xplained/uc3_l0_xplained.h"
-#elif BOARD == STK600_RCUC3B0
-# include "stk600/rcuc3b0/stk600_rcuc3b0.h"
-#elif BOARD == STK600_RCUC3D
-# include "stk600/rcuc3d/stk600_rcuc3d.h"
-#elif BOARD == STK600_RCUC3C0
-# include "stk600/rcuc3c0/stk600_rcuc3c0.h"
-#elif BOARD == SAMG53_XPLAINED_PRO
-# include "samg53_xplained_pro/samg53_xplained_pro.h"
-#elif BOARD == SAMG55_XPLAINED_PRO
-# include "samg55_xplained_pro/samg55_xplained_pro.h"
-#elif BOARD == XMEGA_B1_XPLAINED
-# include "xmega_b1_xplained/xmega_b1_xplained.h"
-#elif BOARD == STK600_RC064X_LCDX
-# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"
-#elif BOARD == STK600_RC100X_LCDX
-# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"
-#elif BOARD == XMEGA_A1_XPLAINED
-# include "xmega_a1_xplained/xmega_a1_xplained.h"
-#elif BOARD == XMEGA_A1U_XPLAINED_PRO
-# include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h"
-#elif BOARD == UC3_L0_XPLAINED_BC
-# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"
-#elif BOARD == SAM3S_EK
-# include "sam3s_ek/sam3s_ek.h"
-# include "system_sam3s.h"
-#elif BOARD == SAM3S_EK2
-# include "sam3s_ek2/sam3s_ek2.h"
-# include "system_sam3sd8.h"
-#elif BOARD == SAM3U_EK
-# include "sam3u_ek/sam3u_ek.h"
-# include "system_sam3u.h"
-#elif BOARD == SAM3X_EK
-# include "sam3x_ek/sam3x_ek.h"
-# include "system_sam3x.h"
-#elif BOARD == SAM3N_EK
-# include "sam3n_ek/sam3n_ek.h"
-# include "system_sam3n.h"
-#elif BOARD == SAM4S_EK
-# include "sam4s_ek/sam4s_ek.h"
-# include "system_sam4s.h"
-#elif BOARD == SAM4S_WPIR_RD
-# include "sam4s_wpir_rd/sam4s_wpir_rd.h"
-# include "system_sam4s.h"
-#elif BOARD == SAM4S_XPLAINED
-# include "sam4s_xplained/sam4s_xplained.h"
-# include "system_sam4s.h"
-#elif BOARD == SAM4S_EK2
-# include "sam4s_ek2/sam4s_ek2.h"
-# include "system_sam4s.h"
-#elif BOARD == MEGA_1284P_XPLAINED
- /*No header-file to include*/
-#elif BOARD == ARDUINO_DUE_X
-# include "arduino_due_x/arduino_due_x.h"
-# include "system_sam3x.h"
-#elif BOARD == SAM4L_EK
-# include "sam4l_ek/sam4l_ek.h"
-#elif BOARD == SAM4E_EK
-# include "sam4e_ek/sam4e_ek.h"
-#elif BOARD == SAMD20_XPLAINED_PRO
-# include "samd20_xplained_pro/samd20_xplained_pro.h"
-#elif BOARD == SAMD21_XPLAINED_PRO
-# include "samd21_xplained_pro/samd21_xplained_pro.h"
-#elif BOARD == SAMR21_XPLAINED_PRO
-# include "samr21_xplained_pro/samr21_xplained_pro.h"
-#elif BOARD == SAMR30_XPLAINED_PRO
-# include "samr30_xplained_pro/samr30_xplained_pro.h"
-#elif BOARD == SAMR21ZLL_EK
-# include "samr21zll_ek/samr21zll_ek.h"
-#elif BOARD == SAMD11_XPLAINED_PRO
-# include "samd11_xplained_pro/samd11_xplained_pro.h"
-#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__)
-# include "saml21_xplained_pro/saml21_xplained_pro.h"
-#elif BOARD == SAML22_XPLAINED_PRO
-# include "saml22_xplained_pro/saml22_xplained_pro.h"
-#elif BOARD == SAML22_XPLAINED_PRO_B
-# include "saml22_xplained_pro_b/saml22_xplained_pro_b.h"
-#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__)
-# include "saml21_xplained_pro_b/saml21_xplained_pro.h"
-#elif BOARD == SAMD10_XPLAINED_MINI
-# include "samd10_xplained_mini/samd10_xplained_mini.h"
-#elif BOARD == SAMDA1_XPLAINED_PRO
-# include "samda1_xplained_pro/samda1_xplained_pro.h"
-#elif BOARD == SAMHA1G16A_XPLAINED_PRO
-# include "samha1g16a_xplained_pro/samha1g16a_xplained_pro.h"
-#elif BOARD == SAMC21_XPLAINED_PRO
-# include "samc21_xplained_pro/samc21_xplained_pro.h"
-#elif BOARD == SAM4N_XPLAINED_PRO
-# include "sam4n_xplained_pro/sam4n_xplained_pro.h"
-#elif BOARD == SAMW25_XPLAINED_PRO
-# include "samw25_xplained_pro/samw25_xplained_pro.h"
-#elif BOARD == SAMV71_XPLAINED_ULTRA
-# include "samv71_xplained_ultra/samv71_xplained_ultra.h"
-#elif BOARD == MEGA1284P_XPLAINED_BC
-# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"
-#elif BOARD == UC3_L0_QT600
-# include "uc3_l0_qt600/uc3_l0_qt600.h"
-#elif BOARD == XMEGA_A3BU_XPLAINED
-# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"
-#elif BOARD == XMEGA_E5_XPLAINED
-# include "xmega_e5_xplained/xmega_e5_xplained.h"
-#elif BOARD == UC3B_BOARD_CONTROLLER
-# include "uc3b_board_controller/uc3b_board_controller.h"
-#elif BOARD == RZ600
-# include "rz600/rz600.h"
-#elif BOARD == STK600_RCUC3A0
-# include "stk600/rcuc3a0/stk600_rcuc3a0.h"
-#elif BOARD == ATXMEGA128A1_QT600
-# include "atxmega128a1_qt600/atxmega128a1_qt600.h"
-#elif BOARD == STK600_RCUC3L3
-# include "stk600/rcuc3l3/stk600_rcuc3l3.h"
-#elif BOARD == SAM4S_XPLAINED_PRO
-# include "sam4s_xplained_pro/sam4s_xplained_pro.h"
-#elif BOARD == SAM4L_XPLAINED_PRO
-# include "sam4l_xplained_pro/sam4l_xplained_pro.h"
-#elif BOARD == SAM4L8_XPLAINED_PRO
-# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"
-#elif BOARD == SAM4C_EK
-# include "sam4c_ek/sam4c_ek.h"
-#elif BOARD == SAM4CMP_DB
-# include "sam4cmp_db/sam4cmp_db.h"
-#elif BOARD == SAM4CMS_DB
-# include "sam4cms_db/sam4cms_db.h"
-#elif BOARD == SAM4CP16BMB
-# include "sam4cp16bmb/sam4cp16bmb.h"
-#elif BOARD == ATPL230AMB
-# include "atpl230amb/atpl230amb.h"
-#elif BOARD == XMEGA_C3_XPLAINED
-# include "xmega_c3_xplained/xmega_c3_xplained.h"
-#elif BOARD == XMEGA_RF233_ZIGBIT
-# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"
-#elif BOARD == XMEGA_A3_REB_CBB
-# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"
-#elif BOARD == ATMEGARFX_RCB
-# include "atmegarfx_rcb/atmegarfx_rcb.h"
-#elif BOARD == RCB256RFR2_XPRO
-# include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h"
-#elif BOARD == XMEGA_RF212B_ZIGBIT
-# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"
-#elif BOARD == SAM4E_XPLAINED_PRO
-# include "sam4e_xplained_pro/sam4e_xplained_pro.h"
-#elif BOARD == ATMEGA328P_XPLAINED_MINI
-# include "atmega328p_xplained_mini/atmega328p_xplained_mini.h"
-#elif BOARD == ATMEGA328PB_XPLAINED_MINI
-# include "atmega328pb_xplained_mini/atmega328pb_xplained_mini.h"
-#elif BOARD == SAMB11_XPLAINED_PRO
-# include "samb11_xplained_pro/samb11_xplained_pro.h"
-#elif BOARD == SAME70_XPLAINED
-# include "same70_xplained/same70_xplained.h"
-#elif BOARD == ATMEGA168PB_XPLAINED_MINI
-# include "atmega168pb_xplained_mini/atmega168pb_xplained_mini.h"
-#elif BOARD == ATMEGA324PB_XPLAINED_PRO
-# include "atmega324pb_xplained_pro/atmega324pb_xplained_pro.h"
-#elif BOARD == SAMB11CSP_XPLAINED_PRO
-# include "samb11csp_xplained_pro/samb11csp_xplained_pro.h"
-#elif BOARD == SAMB11ZR_XPLAINED_PRO
-# include "samb11zr_xplained_pro/samb11zr_xplained_pro.h"
-#elif BOARD == SIMULATOR_XMEGA_A1
-# include "simulator/xmega_a1/simulator_xmega_a1.h"
-#elif BOARD == AVR_SIMULATOR_UC3
-# include "avr_simulator_uc3/avr_simulator_uc3.h"
-#elif BOARD == USER_BOARD
- // User-reserved area: #include the header file of your board here (if any).
-# include "user_board.h"
-#elif BOARD == DUMMY_BOARD
-# include "dummy/dummy_board.h"
-#else
-# error No known Atmel board defined
-#endif
-
-#if (defined EXT_BOARD)
-# if EXT_BOARD == MC300
-# include "mc300/mc300.h"
-# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \
- (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \
- (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \
- (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \
- (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \
- (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
-# include "sensors_xplained/sensors_xplained.h"
-# elif EXT_BOARD == RZ600_AT86RF231
-# include "at86rf231/at86rf231.h"
-# elif EXT_BOARD == RZ600_AT86RF230B
-# include "at86rf230b/at86rf230b.h"
-# elif EXT_BOARD == RZ600_AT86RF212
-# include "at86rf212/at86rf212.h"
-# elif EXT_BOARD == SECURITY_XPLAINED
-# include "security_xplained.h"
-# elif EXT_BOARD == USER_EXT_BOARD
- // User-reserved area: #include the header file of your extension board here
- // (if any).
-# endif
-#endif
-
-
-#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
-#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
-
-/*! \brief This function initializes the board target resources
- *
- * This function should be called to ensure proper initialization of the target
- * board hardware connected to the part.
- */
-extern void board_init(void);
-
-#endif // #ifdef __AVR32_ABI_COMPILER__
-#else
-/*! \brief This function initializes the board target resources
- *
- * This function should be called to ensure proper initialization of the target
- * board hardware connected to the part.
- */
-extern void board_init(void);
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * \}
- */
-
-#endif // _BOARD_H_
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/boards/user_board/init.c b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/boards/user_board/init.c
deleted file mode 100644
index 32fba36..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/boards/user_board/init.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/**
- * \file
- *
- * \brief User board initialization template
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include <asf.h>
-#include <board.h>
-#include <conf_board.h>
-
-void board_init(void)
-{
- /* This function is meant to contain board-specific initialization code
- * for, e.g., the I/O pins. The initialization can rely on application-
- * specific board configuration, found in conf_board.h.
- */
-}
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/boards/user_board/user_board.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/boards/user_board/user_board.h
deleted file mode 100644
index 39980a7..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/boards/user_board/user_board.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/**
- * \file
- *
- * \brief User board definition template
- *
- */
-
- /* This file is intended to contain definitions and configuration details for
- * features and devices that are available on the board, e.g., frequency and
- * startup time for an external crystal, external memory devices, LED and USART
- * pins.
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef USER_BOARD_H
-#define USER_BOARD_H
-
-#include <conf_board.h>
-
-// External oscillator settings.
-// Uncomment and set correct values if external oscillator is used.
-
-// External oscillator frequency
-//#define BOARD_XOSC_HZ 8000000
-
-// External oscillator type.
-//!< External clock signal
-//#define BOARD_XOSC_TYPE XOSC_TYPE_EXTERNAL
-//!< 32.768 kHz resonator on TOSC
-//#define BOARD_XOSC_TYPE XOSC_TYPE_32KHZ
-//!< 0.4 to 16 MHz resonator on XTALS
-//#define BOARD_XOSC_TYPE XOSC_TYPE_XTAL
-
-// External oscillator startup time
-//#define BOARD_XOSC_STARTUP_US 500000
-
-
-#endif // USER_BOARD_H
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/genclk.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/genclk.h
deleted file mode 100644
index 503a50a..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/genclk.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/**
- * \file
- *
- * \brief Generic clock management
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef CLK_GENCLK_H_INCLUDED
-#define CLK_GENCLK_H_INCLUDED
-
-#include "parts.h"
-
-#if SAM3S
-# include "sam3s/genclk.h"
-#elif SAM3U
-# include "sam3u/genclk.h"
-#elif SAM3N
-# include "sam3n/genclk.h"
-#elif SAM3XA
-# include "sam3x/genclk.h"
-#elif SAM4S
-# include "sam4s/genclk.h"
-#elif SAM4L
-# include "sam4l/genclk.h"
-#elif SAM4E
-# include "sam4e/genclk.h"
-#elif SAM4N
-# include "sam4n/genclk.h"
-#elif SAM4C
-# include "sam4c/genclk.h"
-#elif SAM4CM
-# include "sam4cm/genclk.h"
-#elif SAM4CP
-# include "sam4cp/genclk.h"
-#elif SAMG
-# include "samg/genclk.h"
-#elif SAMV71
-# include "samv71/genclk.h"
-#elif SAMV70
-# include "samv70/genclk.h"
-#elif SAME70
-# include "same70/genclk.h"
-#elif SAMS70
-# include "sams70/genclk.h"
-#elif (UC3A0 || UC3A1)
-# include "uc3a0_a1/genclk.h"
-#elif UC3A3
-# include "uc3a3_a4/genclk.h"
-#elif UC3B
-# include "uc3b0_b1/genclk.h"
-#elif UC3C
-# include "uc3c/genclk.h"
-#elif UC3D
-# include "uc3d/genclk.h"
-#elif UC3L
-# include "uc3l/genclk.h"
-#else
-# error Unsupported chip type
-#endif
-
-/**
- * \ingroup clk_group
- * \defgroup genclk_group Generic Clock Management
- *
- * Generic clocks are configurable clocks which run outside the system
- * clock domain. They are often connected to peripherals which have an
- * asynchronous component running independently of the bus clock, e.g.
- * USB controllers, low-power timers and RTCs, etc.
- *
- * Note that not all platforms have support for generic clocks; on such
- * platforms, this API will not be available.
- *
- * @{
- */
-
-/**
- * \def GENCLK_DIV_MAX
- * \brief Maximum divider supported by the generic clock implementation
- */
-/**
- * \enum genclk_source
- * \brief Generic clock source ID
- *
- * Each generic clock may be generated from a different clock source.
- * These are the available alternatives provided by the chip.
- */
-
-//! \name Generic clock configuration
-//@{
-/**
- * \struct genclk_config
- * \brief Hardware representation of a set of generic clock parameters
- */
-/**
- * \fn void genclk_config_defaults(struct genclk_config *cfg,
- * unsigned int id)
- * \brief Initialize \a cfg to the default configuration for the clock
- * identified by \a id.
- */
-/**
- * \fn void genclk_config_read(struct genclk_config *cfg, unsigned int id)
- * \brief Read the currently active configuration of the clock
- * identified by \a id into \a cfg.
- */
-/**
- * \fn void genclk_config_write(const struct genclk_config *cfg,
- * unsigned int id)
- * \brief Activate the configuration \a cfg on the clock identified by
- * \a id.
- */
-/**
- * \fn void genclk_config_set_source(struct genclk_config *cfg,
- * enum genclk_source src)
- * \brief Select a new source clock \a src in configuration \a cfg.
- */
-/**
- * \fn void genclk_config_set_divider(struct genclk_config *cfg,
- * unsigned int divider)
- * \brief Set a new \a divider in configuration \a cfg.
- */
-/**
- * \fn void genclk_enable_source(enum genclk_source src)
- * \brief Enable the source clock \a src used by a generic clock.
- */
- //@}
-
-//! \name Enabling and disabling Generic Clocks
-//@{
-/**
- * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id)
- * \brief Activate the configuration \a cfg on the clock identified by
- * \a id and enable it.
- */
-/**
- * \fn void genclk_disable(unsigned int id)
- * \brief Disable the generic clock identified by \a id.
- */
-//@}
-
-/**
- * \brief Enable the configuration defined by \a src and \a divider
- * for the generic clock identified by \a id.
- *
- * \param id The ID of the generic clock.
- * \param src The source clock of the generic clock.
- * \param divider The divider used to generate the generic clock.
- */
-static inline void genclk_enable_config(unsigned int id, enum genclk_source src, unsigned int divider)
-{
- struct genclk_config gcfg;
-
- genclk_config_defaults(&gcfg, id);
- genclk_enable_source(src);
- genclk_config_set_source(&gcfg, src);
- genclk_config_set_divider(&gcfg, divider);
- genclk_enable(&gcfg, id);
-}
-
-//! @}
-
-#endif /* CLK_GENCLK_H_INCLUDED */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/osc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/osc.h
deleted file mode 100644
index e67f01f..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/osc.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/**
- * \file
- *
- * \brief Oscillator management
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef OSC_H_INCLUDED
-#define OSC_H_INCLUDED
-
-#include "parts.h"
-#include "conf_clock.h"
-
-#if SAM3S
-# include "sam3s/osc.h"
-#elif SAM3XA
-# include "sam3x/osc.h"
-#elif SAM3U
-# include "sam3u/osc.h"
-#elif SAM3N
-# include "sam3n/osc.h"
-#elif SAM4S
-# include "sam4s/osc.h"
-#elif SAM4E
-# include "sam4e/osc.h"
-#elif SAM4C
-# include "sam4c/osc.h"
-#elif SAM4CM
-# include "sam4cm/osc.h"
-#elif SAM4CP
-# include "sam4cp/osc.h"
-#elif SAM4L
-# include "sam4l/osc.h"
-#elif SAM4N
-# include "sam4n/osc.h"
-#elif SAMG
-# include "samg/osc.h"
-#elif SAMV71
-# include "samv71/osc.h"
-#elif SAMV70
-# include "samv70/osc.h"
-#elif SAME70
-# include "same70/osc.h"
-#elif SAMS70
-# include "sams70/osc.h"
-#elif (UC3A0 || UC3A1)
-# include "uc3a0_a1/osc.h"
-#elif UC3A3
-# include "uc3a3_a4/osc.h"
-#elif UC3B
-# include "uc3b0_b1/osc.h"
-#elif UC3C
-# include "uc3c/osc.h"
-#elif UC3D
-# include "uc3d/osc.h"
-#elif UC3L
-# include "uc3l/osc.h"
-#elif XMEGA
-# include "xmega/osc.h"
-#else
-# error Unsupported chip type
-#endif
-
-/**
- * \ingroup clk_group
- * \defgroup osc_group Oscillator Management
- *
- * This group contains functions and definitions related to configuring
- * and enabling/disabling on-chip oscillators. Internal RC-oscillators,
- * external crystal oscillators and external clock generators are
- * supported by this module. What all of these have in common is that
- * they swing at a fixed, nominal frequency which is normally not
- * adjustable.
- *
- * \par Example: Enabling an oscillator
- *
- * The following example demonstrates how to enable the external
- * oscillator on XMEGA A and wait for it to be ready to use. The
- * oscillator identifiers are platform-specific, so while the same
- * procedure is used on all platforms, the parameter to osc_enable()
- * will be different from device to device.
- * \code
- osc_enable(OSC_ID_XOSC);
- osc_wait_ready(OSC_ID_XOSC); \endcode
- *
- * \section osc_group_board Board-specific Definitions
- * If external oscillators are used, the board code must provide the
- * following definitions for each of those:
- * - \b BOARD_<osc name>_HZ: The nominal frequency of the oscillator.
- * - \b BOARD_<osc name>_STARTUP_US: The startup time of the
- * oscillator in microseconds.
- * - \b BOARD_<osc name>_TYPE: The type of oscillator connected, i.e.
- * whether it's a crystal or external clock, and sometimes what kind
- * of crystal it is. The meaning of this value is platform-specific.
- *
- * @{
- */
-
-//! \name Oscillator Management
-//@{
-/**
- * \fn void osc_enable(uint8_t id)
- * \brief Enable oscillator \a id
- *
- * The startup time and mode value is automatically determined based on
- * definitions in the board code.
- */
-/**
- * \fn void osc_disable(uint8_t id)
- * \brief Disable oscillator \a id
- */
-/**
- * \fn osc_is_ready(uint8_t id)
- * \brief Determine whether oscillator \a id is ready.
- * \retval true Oscillator \a id is running and ready to use as a clock
- * source.
- * \retval false Oscillator \a id is not running.
- */
-/**
- * \fn uint32_t osc_get_rate(uint8_t id)
- * \brief Return the frequency of oscillator \a id in Hz
- */
-
-#ifndef __ASSEMBLY__
-
-/**
- * \brief Wait until the oscillator identified by \a id is ready
- *
- * This function will busy-wait for the oscillator identified by \a id
- * to become stable and ready to use as a clock source.
- *
- * \param id A number identifying the oscillator to wait for.
- */
-static inline void osc_wait_ready(uint8_t id)
-{
- while (!osc_is_ready(id)) {
- /* Do nothing */
- }
-}
-
-#endif /* __ASSEMBLY__ */
-
-//@}
-
-//! @}
-
-#endif /* OSC_H_INCLUDED */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/pll.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/pll.h
deleted file mode 100644
index 23e930c..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/pll.h
+++ /dev/null
@@ -1,341 +0,0 @@
-/**
- * \file
- *
- * \brief PLL management
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef CLK_PLL_H_INCLUDED
-#define CLK_PLL_H_INCLUDED
-
-#include "parts.h"
-#include "conf_clock.h"
-
-#if SAM3S
-# include "sam3s/pll.h"
-#elif SAM3XA
-# include "sam3x/pll.h"
-#elif SAM3U
-# include "sam3u/pll.h"
-#elif SAM3N
-# include "sam3n/pll.h"
-#elif SAM4S
-# include "sam4s/pll.h"
-#elif SAM4E
-# include "sam4e/pll.h"
-#elif SAM4C
-# include "sam4c/pll.h"
-#elif SAM4CM
-# include "sam4cm/pll.h"
-#elif SAM4CP
-# include "sam4cp/pll.h"
-#elif SAM4L
-# include "sam4l/pll.h"
-#elif SAM4N
-# include "sam4n/pll.h"
-#elif SAMG
-# include "samg/pll.h"
-#elif SAMV71
-# include "samv71/pll.h"
-#elif SAMV70
-# include "samv70/pll.h"
-#elif SAME70
-# include "same70/pll.h"
-#elif SAMS70
-# include "sams70/pll.h"
-#elif (UC3A0 || UC3A1)
-# include "uc3a0_a1/pll.h"
-#elif UC3A3
-# include "uc3a3_a4/pll.h"
-#elif UC3B
-# include "uc3b0_b1/pll.h"
-#elif UC3C
-# include "uc3c/pll.h"
-#elif UC3D
-# include "uc3d/pll.h"
-#elif (UC3L0128 || UC3L0256 || UC3L3_L4)
-# include "uc3l/pll.h"
-#elif XMEGA
-# include "xmega/pll.h"
-#else
-# error Unsupported chip type
-#endif
-
-/**
- * \ingroup clk_group
- * \defgroup pll_group PLL Management
- *
- * This group contains functions and definitions related to configuring
- * and enabling/disabling on-chip PLLs. A PLL will take an input signal
- * (the \em source), optionally divide the frequency by a configurable
- * \em divider, and then multiply the frequency by a configurable \em
- * multiplier.
- *
- * Some devices don't support input dividers; specifying any other
- * divisor than 1 on these devices will result in an assertion failure.
- * Other devices may have various restrictions to the frequency range of
- * the input and output signals.
- *
- * \par Example: Setting up PLL0 with default parameters
- *
- * The following example shows how to configure and enable PLL0 using
- * the default parameters specified using the configuration symbols
- * listed above.
- * \code
- pll_enable_config_defaults(0); \endcode
- *
- * To configure, enable PLL0 using the default parameters and to disable
- * a specific feature like Wide Bandwidth Mode (a UC3A3-specific
- * PLL option.), you can use this initialization process.
- * \code
- struct pll_config pllcfg;
- if (pll_is_locked(pll_id)) {
- return; // Pll already running
- }
- pll_enable_source(CONFIG_PLL0_SOURCE);
- pll_config_defaults(&pllcfg, 0);
- pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);
- pll_enable(&pllcfg, 0);
- pll_wait_for_lock(0); \endcode
- *
- * When the last function call returns, PLL0 is ready to be used as the
- * main system clock source.
- *
- * \section pll_group_config Configuration Symbols
- *
- * Each PLL has a set of default parameters determined by the following
- * configuration symbols in the application's configuration file:
- * - \b CONFIG_PLLn_SOURCE: The default clock source connected to the
- * input of PLL \a n. Must be one of the values defined by the
- * #pll_source enum.
- * - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL
- * \a n.
- * - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n.
- *
- * These configuration symbols determine the result of calling
- * pll_config_defaults() and pll_get_default_rate().
- *
- * @{
- */
-
-//! \name Chip-specific PLL characteristics
-//@{
-/**
- * \def PLL_MAX_STARTUP_CYCLES
- * \brief Maximum PLL startup time in number of slow clock cycles
- */
-/**
- * \def NR_PLLS
- * \brief Number of on-chip PLLs
- */
-
-/**
- * \def PLL_MIN_HZ
- * \brief Minimum frequency that the PLL can generate
- */
-/**
- * \def PLL_MAX_HZ
- * \brief Maximum frequency that the PLL can generate
- */
-/**
- * \def PLL_NR_OPTIONS
- * \brief Number of PLL option bits
- */
-//@}
-
-/**
- * \enum pll_source
- * \brief PLL clock source
- */
-
-//! \name PLL configuration
-//@{
-
-/**
- * \struct pll_config
- * \brief Hardware-specific representation of PLL configuration.
- *
- * This structure contains one or more device-specific values
- * representing the current PLL configuration. The contents of this
- * structure is typically different from platform to platform, and the
- * user should not access any fields except through the PLL
- * configuration API.
- */
-
-/**
- * \fn void pll_config_init(struct pll_config *cfg,
- * enum pll_source src, unsigned int div, unsigned int mul)
- * \brief Initialize PLL configuration from standard parameters.
- *
- * \note This function may be defined inline because it is assumed to be
- * called very few times, and usually with constant parameters. Inlining
- * it will in such cases reduce the code size significantly.
- *
- * \param cfg The PLL configuration to be initialized.
- * \param src The oscillator to be used as input to the PLL.
- * \param div PLL input divider.
- * \param mul PLL loop divider (i.e. multiplier).
- *
- * \return A configuration which will make the PLL run at
- * (\a mul / \a div) times the frequency of \a src
- */
-/**
- * \def pll_config_defaults(cfg, pll_id)
- * \brief Initialize PLL configuration using default parameters.
- *
- * After this function returns, \a cfg will contain a configuration
- * which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV)
- * times the frequency of CONFIG_PLLx_SOURCE.
- *
- * \param cfg The PLL configuration to be initialized.
- * \param pll_id Use defaults for this PLL.
- */
-/**
- * \def pll_get_default_rate(pll_id)
- * \brief Get the default rate in Hz of \a pll_id
- */
-/**
- * \fn void pll_config_set_option(struct pll_config *cfg,
- * unsigned int option)
- * \brief Set the PLL option bit \a option in the configuration \a cfg.
- *
- * \param cfg The PLL configuration to be changed.
- * \param option The PLL option bit to be set.
- */
-/**
- * \fn void pll_config_clear_option(struct pll_config *cfg,
- * unsigned int option)
- * \brief Clear the PLL option bit \a option in the configuration \a cfg.
- *
- * \param cfg The PLL configuration to be changed.
- * \param option The PLL option bit to be cleared.
- */
-/**
- * \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id)
- * \brief Read the currently active configuration of \a pll_id.
- *
- * \param cfg The configuration object into which to store the currently
- * active configuration.
- * \param pll_id The ID of the PLL to be accessed.
- */
-/**
- * \fn void pll_config_write(const struct pll_config *cfg,
- * unsigned int pll_id)
- * \brief Activate the configuration \a cfg on \a pll_id
- *
- * \param cfg The configuration object representing the PLL
- * configuration to be activated.
- * \param pll_id The ID of the PLL to be updated.
- */
-
-//@}
-
-//! \name Interaction with the PLL hardware
-//@{
-/**
- * \fn void pll_enable(const struct pll_config *cfg,
- * unsigned int pll_id)
- * \brief Activate the configuration \a cfg and enable PLL \a pll_id.
- *
- * \param cfg The PLL configuration to be activated.
- * \param pll_id The ID of the PLL to be enabled.
- */
-/**
- * \fn void pll_disable(unsigned int pll_id)
- * \brief Disable the PLL identified by \a pll_id.
- *
- * After this function is called, the PLL identified by \a pll_id will
- * be disabled. The PLL configuration stored in hardware may be affected
- * by this, so if the caller needs to restore the same configuration
- * later, it should either do a pll_config_read() before disabling the
- * PLL, or remember the last configuration written to the PLL.
- *
- * \param pll_id The ID of the PLL to be disabled.
- */
-/**
- * \fn bool pll_is_locked(unsigned int pll_id)
- * \brief Determine whether the PLL is locked or not.
- *
- * \param pll_id The ID of the PLL to check.
- *
- * \retval true The PLL is locked and ready to use as a clock source
- * \retval false The PLL is not yet locked, or has not been enabled.
- */
-/**
- * \fn void pll_enable_source(enum pll_source src)
- * \brief Enable the source of the pll.
- * The source is enabled, if the source is not already running.
- *
- * \param src The ID of the PLL source to enable.
- */
-/**
- * \fn void pll_enable_config_defaults(unsigned int pll_id)
- * \brief Enable the pll with the default configuration.
- * PLL is enabled, if the PLL is not already locked.
- *
- * \param pll_id The ID of the PLL to enable.
- */
-
-/**
- * \brief Wait for PLL \a pll_id to become locked
- *
- * \todo Use a timeout to avoid waiting forever and hanging the system
- *
- * \param pll_id The ID of the PLL to wait for.
- *
- * \retval STATUS_OK The PLL is now locked.
- * \retval ERR_TIMEOUT Timed out waiting for PLL to become locked.
- */
-static inline int pll_wait_for_lock(unsigned int pll_id)
-{
- Assert(pll_id < NR_PLLS);
-
- while (!pll_is_locked(pll_id)) {
- /* Do nothing */
- }
-
- return 0;
-}
-
-//@}
-//! @}
-
-#endif /* CLK_PLL_H_INCLUDED */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/genclk.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/genclk.h
deleted file mode 100644
index fbb069a..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/genclk.h
+++ /dev/null
@@ -1,269 +0,0 @@
-/**
- * \file
- *
- * \brief Chip-specific generic clock management.
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef CHIP_GENCLK_H_INCLUDED
-#define CHIP_GENCLK_H_INCLUDED
-
-#include <osc.h>
-#include <pll.h>
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-/**
- * \weakgroup genclk_group
- * @{
- */
-
-//! \name Programmable Clock Identifiers (PCK)
-//@{
-#define GENCLK_PCK_0 0 //!< PCK0 ID
-#define GENCLK_PCK_1 1 //!< PCK1 ID
-#define GENCLK_PCK_2 2 //!< PCK2 ID
-//@}
-
-//! \name Programmable Clock Sources (PCK)
-//@{
-
-enum genclk_source {
- GENCLK_PCK_SRC_SLCK_RC = 0,//!< Internal 32kHz RC oscillator as PCK source clock
- GENCLK_PCK_SRC_SLCK_XTAL = 1,//!< External 32kHz crystal oscillator as PCK source clock
- GENCLK_PCK_SRC_SLCK_BYPASS = 2,//!< External 32kHz bypass oscillator as PCK source clock
- GENCLK_PCK_SRC_MAINCK_4M_RC = 3,//!< Internal 4MHz RC oscillator as PCK source clock
- GENCLK_PCK_SRC_MAINCK_8M_RC = 4,//!< Internal 8MHz RC oscillator as PCK source clock
- GENCLK_PCK_SRC_MAINCK_12M_RC = 5,//!< Internal 12MHz RC oscillator as PCK source clock
- GENCLK_PCK_SRC_MAINCK_XTAL = 6,//!< External crystal oscillator as PCK source clock
- GENCLK_PCK_SRC_MAINCK_BYPASS = 7,//!< External bypass oscillator as PCK source clock
- GENCLK_PCK_SRC_PLLACK = 8,//!< Use PLLACK as PCK source clock
- GENCLK_PCK_SRC_MCK = 9,//!< Use Master Clk as PCK source clock
-};
-
-//@}
-
-//! \name Programmable Clock Prescalers (PCK)
-//@{
-
-enum genclk_divider {
- GENCLK_PCK_PRES_1 = PMC_PCK_PRES(0), //!< Set PCK clock prescaler to 1
- GENCLK_PCK_PRES_2 = PMC_PCK_PRES(1), //!< Set PCK clock prescaler to 2
- GENCLK_PCK_PRES_4 = PMC_PCK_PRES(2), //!< Set PCK clock prescaler to 4
- GENCLK_PCK_PRES_8 = PMC_PCK_PRES(3), //!< Set PCK clock prescaler to 8
- GENCLK_PCK_PRES_16 = PMC_PCK_PRES(4), //!< Set PCK clock prescaler to 16
- GENCLK_PCK_PRES_32 = PMC_PCK_PRES(5), //!< Set PCK clock prescaler to 32
- GENCLK_PCK_PRES_64 = PMC_PCK_PRES(6), //!< Set PCK clock prescaler to 64
-};
-
-//@}
-
-struct genclk_config {
- uint32_t ctrl;
-};
-
-static inline void genclk_config_defaults(struct genclk_config *p_cfg,
- uint32_t ul_id)
-{
- ul_id = ul_id;
- p_cfg->ctrl = 0;
-}
-
-static inline void genclk_config_read(struct genclk_config *p_cfg,
- uint32_t ul_id)
-{
- p_cfg->ctrl = PMC->PMC_PCK[ul_id];
-}
-
-static inline void genclk_config_write(const struct genclk_config *p_cfg,
- uint32_t ul_id)
-{
- PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
-}
-
-//! \name Programmable Clock Source and Prescaler configuration
-//@{
-
-static inline void genclk_config_set_source(struct genclk_config *p_cfg,
- enum genclk_source e_src)
-{
- p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);
-
- switch (e_src) {
- case GENCLK_PCK_SRC_SLCK_RC:
- case GENCLK_PCK_SRC_SLCK_XTAL:
- case GENCLK_PCK_SRC_SLCK_BYPASS:
- p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK);
- break;
-
- case GENCLK_PCK_SRC_MAINCK_4M_RC:
- case GENCLK_PCK_SRC_MAINCK_8M_RC:
- case GENCLK_PCK_SRC_MAINCK_12M_RC:
- case GENCLK_PCK_SRC_MAINCK_XTAL:
- case GENCLK_PCK_SRC_MAINCK_BYPASS:
- p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK);
- break;
-
- case GENCLK_PCK_SRC_PLLACK:
- p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK);
- break;
-
- case GENCLK_PCK_SRC_MCK:
- p_cfg->ctrl |= (PMC_PCK_CSS_MCK);
- break;
-
- default:
- break;
- }
-}
-
-static inline void genclk_config_set_divider(struct genclk_config *p_cfg,
- uint32_t e_divider)
-{
- p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;
- p_cfg->ctrl |= e_divider;
-}
-
-//@}
-
-static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id)
-{
- PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
- pmc_enable_pck(ul_id);
-}
-
-static inline void genclk_disable(uint32_t ul_id)
-{
- pmc_disable_pck(ul_id);
-}
-
-static inline void genclk_enable_source(enum genclk_source e_src)
-{
- switch (e_src) {
- case GENCLK_PCK_SRC_SLCK_RC:
- if (!osc_is_ready(OSC_SLCK_32K_RC)) {
- osc_enable(OSC_SLCK_32K_RC);
- osc_wait_ready(OSC_SLCK_32K_RC);
- }
- break;
-
- case GENCLK_PCK_SRC_SLCK_XTAL:
- if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {
- osc_enable(OSC_SLCK_32K_XTAL);
- osc_wait_ready(OSC_SLCK_32K_XTAL);
- }
- break;
-
- case GENCLK_PCK_SRC_SLCK_BYPASS:
- if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {
- osc_enable(OSC_SLCK_32K_BYPASS);
- osc_wait_ready(OSC_SLCK_32K_BYPASS);
- }
- break;
-
- case GENCLK_PCK_SRC_MAINCK_4M_RC:
- if (!osc_is_ready(OSC_MAINCK_4M_RC)) {
- osc_enable(OSC_MAINCK_4M_RC);
- osc_wait_ready(OSC_MAINCK_4M_RC);
- }
- break;
-
- case GENCLK_PCK_SRC_MAINCK_8M_RC:
- if (!osc_is_ready(OSC_MAINCK_8M_RC)) {
- osc_enable(OSC_MAINCK_8M_RC);
- osc_wait_ready(OSC_MAINCK_8M_RC);
- }
- break;
-
- case GENCLK_PCK_SRC_MAINCK_12M_RC:
- if (!osc_is_ready(OSC_MAINCK_12M_RC)) {
- osc_enable(OSC_MAINCK_12M_RC);
- osc_wait_ready(OSC_MAINCK_12M_RC);
- }
- break;
-
- case GENCLK_PCK_SRC_MAINCK_XTAL:
- if (!osc_is_ready(OSC_MAINCK_XTAL)) {
- osc_enable(OSC_MAINCK_XTAL);
- osc_wait_ready(OSC_MAINCK_XTAL);
- }
- break;
-
- case GENCLK_PCK_SRC_MAINCK_BYPASS:
- if (!osc_is_ready(OSC_MAINCK_BYPASS)) {
- osc_enable(OSC_MAINCK_BYPASS);
- osc_wait_ready(OSC_MAINCK_BYPASS);
- }
- break;
-
-#ifdef CONFIG_PLL0_SOURCE
- case GENCLK_PCK_SRC_PLLACK:
- pll_enable_config_defaults(0);
- break;
-#endif
-
- case GENCLK_PCK_SRC_MCK:
- break;
-
- default:
- Assert(false);
- break;
- }
-}
-
-//! @}
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-#endif /* CHIP_GENCLK_H_INCLUDED */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/osc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/osc.h
deleted file mode 100644
index 191c4ed..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/osc.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/**
- * \file
- *
- * \brief Chip-specific oscillator management functions.
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef CHIP_OSC_H_INCLUDED
-#define CHIP_OSC_H_INCLUDED
-
-#include "board.h"
-#include "pmc.h"
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-/*
- * Below BOARD_XXX macros are related to the specific board, and
- * should be defined by the board code, otherwise default value are used.
- */
-#if !defined(BOARD_FREQ_SLCK_XTAL)
-# warning The board slow clock xtal frequency has not been defined.
-# define BOARD_FREQ_SLCK_XTAL (32768UL)
-#endif
-
-#if !defined(BOARD_FREQ_SLCK_BYPASS)
-# warning The board slow clock bypass frequency has not been defined.
-# define BOARD_FREQ_SLCK_BYPASS (32768UL)
-#endif
-
-#if !defined(BOARD_FREQ_MAINCK_XTAL)
-# warning The board main clock xtal frequency has not been defined.
-# define BOARD_FREQ_MAINCK_XTAL (12000000UL)
-#endif
-
-#if !defined(BOARD_FREQ_MAINCK_BYPASS)
-# warning The board main clock bypass frequency has not been defined.
-# define BOARD_FREQ_MAINCK_BYPASS (12000000UL)
-#endif
-
-#if !defined(BOARD_OSC_STARTUP_US)
-# warning The board main clock xtal startup time has not been defined.
-# define BOARD_OSC_STARTUP_US (15625UL)
-#endif
-
-/**
- * \weakgroup osc_group
- * @{
- */
-
-//! \name Oscillator identifiers
-//@{
-#define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator.
-#define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator.
-#define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator.
-#define OSC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator.
-#define OSC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator.
-#define OSC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator.
-#define OSC_MAINCK_XTAL 6 //!< External crystal oscillator.
-#define OSC_MAINCK_BYPASS 7 //!< External bypass oscillator.
-//@}
-
-//! \name Oscillator clock speed in hertz
-//@{
-#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator.
-#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator.
-#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator.
-#define OSC_MAINCK_4M_RC_HZ CHIP_FREQ_MAINCK_RC_4MHZ //!< Internal 4MHz RC oscillator.
-#define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator.
-#define OSC_MAINCK_12M_RC_HZ CHIP_FREQ_MAINCK_RC_12MHZ //!< Internal 12MHz RC oscillator.
-#define OSC_MAINCK_XTAL_HZ BOARD_FREQ_MAINCK_XTAL //!< External crystal oscillator.
-#define OSC_MAINCK_BYPASS_HZ BOARD_FREQ_MAINCK_BYPASS //!< External bypass oscillator.
-//@}
-
-static inline void osc_enable(uint32_t ul_id)
-{
- switch (ul_id) {
- case OSC_SLCK_32K_RC:
- break;
-
- case OSC_SLCK_32K_XTAL:
- pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);
- break;
-
- case OSC_SLCK_32K_BYPASS:
- pmc_switch_sclk_to_32kxtal(PMC_OSC_BYPASS);
- break;
-
-
- case OSC_MAINCK_4M_RC:
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);
- break;
-
- case OSC_MAINCK_8M_RC:
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);
- break;
-
- case OSC_MAINCK_12M_RC:
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);
- break;
-
-
- case OSC_MAINCK_XTAL:
- pmc_switch_mainck_to_xtal(PMC_OSC_XTAL,
- pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US,
- OSC_SLCK_32K_RC_HZ));
- break;
-
- case OSC_MAINCK_BYPASS:
- pmc_switch_mainck_to_xtal(PMC_OSC_BYPASS,
- pmc_us_to_moscxtst(BOARD_OSC_STARTUP_US,
- OSC_SLCK_32K_RC_HZ));
- break;
- }
-}
-
-static inline void osc_disable(uint32_t ul_id)
-{
- switch (ul_id) {
- case OSC_SLCK_32K_RC:
- case OSC_SLCK_32K_XTAL:
- case OSC_SLCK_32K_BYPASS:
- break;
-
- case OSC_MAINCK_4M_RC:
- case OSC_MAINCK_8M_RC:
- case OSC_MAINCK_12M_RC:
- pmc_osc_disable_fastrc();
- break;
-
- case OSC_MAINCK_XTAL:
- pmc_osc_disable_xtal(PMC_OSC_XTAL);
- break;
-
- case OSC_MAINCK_BYPASS:
- pmc_osc_disable_xtal(PMC_OSC_BYPASS);
- break;
- }
-}
-
-static inline bool osc_is_ready(uint32_t ul_id)
-{
- switch (ul_id) {
- case OSC_SLCK_32K_RC:
- return 1;
-
- case OSC_SLCK_32K_XTAL:
- case OSC_SLCK_32K_BYPASS:
- return pmc_osc_is_ready_32kxtal();
-
- case OSC_MAINCK_4M_RC:
- case OSC_MAINCK_8M_RC:
- case OSC_MAINCK_12M_RC:
- case OSC_MAINCK_XTAL:
- case OSC_MAINCK_BYPASS:
- return pmc_osc_is_ready_mainck();
- }
-
- return 0;
-}
-
-static inline uint32_t osc_get_rate(uint32_t ul_id)
-{
- switch (ul_id) {
- case OSC_SLCK_32K_RC:
- return OSC_SLCK_32K_RC_HZ;
-
- case OSC_SLCK_32K_XTAL:
- return BOARD_FREQ_SLCK_XTAL;
-
- case OSC_SLCK_32K_BYPASS:
- return BOARD_FREQ_SLCK_BYPASS;
-
- case OSC_MAINCK_4M_RC:
- return OSC_MAINCK_4M_RC_HZ;
-
- case OSC_MAINCK_8M_RC:
- return OSC_MAINCK_8M_RC_HZ;
-
- case OSC_MAINCK_12M_RC:
- return OSC_MAINCK_12M_RC_HZ;
-
- case OSC_MAINCK_XTAL:
- return BOARD_FREQ_MAINCK_XTAL;
-
- case OSC_MAINCK_BYPASS:
- return BOARD_FREQ_MAINCK_BYPASS;
- }
-
- return 0;
-}
-
-//! @}
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-#endif /* CHIP_OSC_H_INCLUDED */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/pll.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/pll.h
deleted file mode 100644
index 5006ebb..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/pll.h
+++ /dev/null
@@ -1,269 +0,0 @@
-/**
- * \file
- *
- * \brief Chip-specific PLL definitions.
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef CHIP_PLL_H_INCLUDED
-#define CHIP_PLL_H_INCLUDED
-
-#include <osc.h>
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-/**
- * \weakgroup pll_group
- * @{
- */
-
-#define PLL_OUTPUT_MIN_HZ 160000000
-#define PLL_OUTPUT_MAX_HZ 500000000
-
-#define PLL_INPUT_MIN_HZ 3000000
-#define PLL_INPUT_MAX_HZ 32000000
-
-#define NR_PLLS 2
-#define PLLA_ID 0
-#define UPLL_ID 1 //!< USB UTMI PLL.
-
-#define PLL_UPLL_HZ 480000000
-
-#define PLL_COUNT 0x3fU
-
-enum pll_source {
- PLL_SRC_MAINCK_4M_RC = OSC_MAINCK_4M_RC, //!< Internal 4MHz RC oscillator.
- PLL_SRC_MAINCK_8M_RC = OSC_MAINCK_8M_RC, //!< Internal 8MHz RC oscillator.
- PLL_SRC_MAINCK_12M_RC = OSC_MAINCK_12M_RC, //!< Internal 12MHz RC oscillator.
- PLL_SRC_MAINCK_XTAL = OSC_MAINCK_XTAL, //!< External crystal oscillator.
- PLL_SRC_MAINCK_BYPASS = OSC_MAINCK_BYPASS, //!< External bypass oscillator.
- PLL_NR_SOURCES, //!< Number of PLL sources.
-};
-
-struct pll_config {
- uint32_t ctrl;
-};
-
-#define pll_get_default_rate(pll_id) \
- ((osc_get_rate(CONFIG_PLL##pll_id##_SOURCE) \
- * CONFIG_PLL##pll_id##_MUL) \
- / CONFIG_PLL##pll_id##_DIV)
-
-/* Force UTMI PLL parameters (Hardware defined) */
-#ifdef CONFIG_PLL1_SOURCE
-# undef CONFIG_PLL1_SOURCE
-#endif
-#ifdef CONFIG_PLL1_MUL
-# undef CONFIG_PLL1_MUL
-#endif
-#ifdef CONFIG_PLL1_DIV
-# undef CONFIG_PLL1_DIV
-#endif
-#define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL
-#define CONFIG_PLL1_MUL 0
-#define CONFIG_PLL1_DIV 0
-
-/**
- * \note The SAMV71 PLL hardware interprets mul as mul+1. For readability the
- * hardware mul+1 is hidden in this implementation. Use mul as mul effective
- * value.
- */
-static inline void pll_config_init(struct pll_config *p_cfg,
- enum pll_source e_src, uint32_t ul_div, uint32_t ul_mul)
-{
- uint32_t vco_hz;
-
- Assert(e_src < PLL_NR_SOURCES);
-
- if (ul_div == 0 && ul_mul == 0) { /* Must only be true for UTMI PLL */
- p_cfg->ctrl = CKGR_UCKR_UPLLCOUNT(PLL_COUNT);
- } else { /* PLLA */
- /* Calculate internal VCO frequency */
- vco_hz = osc_get_rate(e_src) / ul_div;
- Assert(vco_hz >= PLL_INPUT_MIN_HZ);
- Assert(vco_hz <= PLL_INPUT_MAX_HZ);
-
- vco_hz *= ul_mul;
- Assert(vco_hz >= PLL_OUTPUT_MIN_HZ);
- Assert(vco_hz <= PLL_OUTPUT_MAX_HZ);
-
- /* PMC hardware will automatically make it mul+1 */
- p_cfg->ctrl = CKGR_PLLAR_MULA(ul_mul - 1) | CKGR_PLLAR_DIVA(ul_div) \
- | CKGR_PLLAR_PLLACOUNT(PLL_COUNT);
- }
-}
-
-#define pll_config_defaults(cfg, pll_id) \
- pll_config_init(cfg, \
- CONFIG_PLL##pll_id##_SOURCE, \
- CONFIG_PLL##pll_id##_DIV, \
- CONFIG_PLL##pll_id##_MUL)
-
-static inline void pll_config_read(struct pll_config *p_cfg, uint32_t ul_pll_id)
-{
- Assert(ul_pll_id < NR_PLLS);
-
- if (ul_pll_id == PLLA_ID) {
- p_cfg->ctrl = PMC->CKGR_PLLAR;
- } else {
- p_cfg->ctrl = PMC->CKGR_UCKR;
- }
-}
-
-static inline void pll_config_write(const struct pll_config *p_cfg, uint32_t ul_pll_id)
-{
- Assert(ul_pll_id < NR_PLLS);
-
- if (ul_pll_id == PLLA_ID) {
- pmc_disable_pllack(); // Always stop PLL first!
- PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;
- } else {
- PMC->CKGR_UCKR = p_cfg->ctrl;
- }
-}
-
-static inline void pll_enable(const struct pll_config *p_cfg, uint32_t ul_pll_id)
-{
- Assert(ul_pll_id < NR_PLLS);
-
- if (ul_pll_id == PLLA_ID) {
- pmc_disable_pllack(); // Always stop PLL first!
- PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | p_cfg->ctrl;
- } else {
- PMC->CKGR_UCKR = p_cfg->ctrl | CKGR_UCKR_UPLLEN;
- }
-}
-
-/**
- * \note This will only disable the selected PLL, not the underlying oscillator (mainck).
- */
-static inline void pll_disable(uint32_t ul_pll_id)
-{
- Assert(ul_pll_id < NR_PLLS);
-
- if (ul_pll_id == PLLA_ID) {
- pmc_disable_pllack();
- } else {
- PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
- }
-}
-
-static inline uint32_t pll_is_locked(uint32_t ul_pll_id)
-{
- Assert(ul_pll_id < NR_PLLS);
-
- if (ul_pll_id == PLLA_ID) {
- return pmc_is_locked_pllack();
- } else {
- return pmc_is_locked_upll();
- }
-}
-
-static inline void pll_enable_source(enum pll_source e_src)
-{
- switch (e_src) {
- case PLL_SRC_MAINCK_4M_RC:
- case PLL_SRC_MAINCK_8M_RC:
- case PLL_SRC_MAINCK_12M_RC:
- case PLL_SRC_MAINCK_XTAL:
- case PLL_SRC_MAINCK_BYPASS:
- osc_enable(e_src);
- osc_wait_ready(e_src);
- break;
-
- default:
- Assert(false);
- break;
- }
-}
-
-static inline void pll_enable_config_defaults(unsigned int ul_pll_id)
-{
- struct pll_config pllcfg;
-
- if (pll_is_locked(ul_pll_id)) {
- return; // Pll already running
- }
- switch (ul_pll_id) {
-#ifdef CONFIG_PLL0_SOURCE
- case 0:
- pll_enable_source(CONFIG_PLL0_SOURCE);
- pll_config_init(&pllcfg,
- CONFIG_PLL0_SOURCE,
- CONFIG_PLL0_DIV,
- CONFIG_PLL0_MUL);
- break;
-#endif
-#ifdef CONFIG_PLL1_SOURCE
- case 1:
- pll_enable_source(CONFIG_PLL1_SOURCE);
- pll_config_init(&pllcfg,
- CONFIG_PLL1_SOURCE,
- CONFIG_PLL1_DIV,
- CONFIG_PLL1_MUL);
- break;
-#endif
- default:
- Assert(false);
- break;
- }
- pll_enable(&pllcfg, ul_pll_id);
- while (!pll_is_locked(ul_pll_id));
-}
-
-//! @}
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-#endif /* CHIP_PLL_H_INCLUDED */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/sysclk.c b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/sysclk.c
deleted file mode 100644
index 8e21e83..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/sysclk.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/**
- * \file
- *
- * \brief Chip-specific system clock management functions.
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include <sysclk.h>
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-/**
- * \weakgroup sysclk_group
- * @{
- */
-
-#if defined(CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
-/**
- * \brief boolean signalling that the sysclk_init is done.
- */
-uint32_t sysclk_initialized = 0;
-#endif
-
-/**
- * \brief Set system clock prescaler configuration
- *
- * This function will change the system clock prescaler configuration to
- * match the parameters.
- *
- * \note The parameters to this function are device-specific.
- *
- * \param ul_pres The CPU clock will be divided by \f$2^{mck\_pres}\f$
- */
-void sysclk_set_prescalers(uint32_t ul_pres)
-{
- pmc_mck_set_prescaler(ul_pres);
- SystemCoreClockUpdate();
-}
-
-/**
- * \brief Change the source of the main system clock.
- *
- * \param ul_src The new system clock source. Must be one of the constants
- * from the <em>System Clock Sources</em> section.
- */
-void sysclk_set_source(uint32_t ul_src)
-{
- switch (ul_src) {
- case SYSCLK_SRC_SLCK_RC:
- case SYSCLK_SRC_SLCK_XTAL:
- case SYSCLK_SRC_SLCK_BYPASS:
- pmc_mck_set_source(PMC_MCKR_CSS_SLOW_CLK);
- break;
-
- case SYSCLK_SRC_MAINCK_4M_RC:
- case SYSCLK_SRC_MAINCK_8M_RC:
- case SYSCLK_SRC_MAINCK_12M_RC:
- case SYSCLK_SRC_MAINCK_XTAL:
- case SYSCLK_SRC_MAINCK_BYPASS:
- pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK);
- break;
-
- case SYSCLK_SRC_PLLACK:
- pmc_mck_set_source(PMC_MCKR_CSS_PLLA_CLK);
- break;
-
- case SYSCLK_SRC_UPLLCK:
- pmc_mck_set_source(PMC_MCKR_CSS_UPLL_CLK);
- break;
- }
-
- SystemCoreClockUpdate();
-}
-
-#if defined(CONFIG_USBCLK_SOURCE) || defined(__DOXYGEN__)
-/**
- * \brief Enable USB clock.
- *
- * \note The SAMV71 UDP hardware interprets div as div+1. For readability the hardware div+1
- * is hidden in this implementation. Use div as div effective value.
- *
- * \param pll_id Source of the USB clock.
- * \param div Actual clock divisor. Must be superior to 0.
- */
-void sysclk_enable_usb(void)
-{
- Assert(CONFIG_USBCLK_DIV > 0);
-
-#ifdef CONFIG_PLL0_SOURCE
- if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_PLL0) {
- struct pll_config pllcfg;
-
- pll_enable_source(CONFIG_PLL0_SOURCE);
- pll_config_defaults(&pllcfg, 0);
- pll_enable(&pllcfg, 0);
- pll_wait_for_lock(0);
- pmc_switch_udpck_to_pllack(CONFIG_USBCLK_DIV - 1);
- pmc_enable_udpck();
- return;
- }
-#endif
-
- if (CONFIG_USBCLK_SOURCE == USBCLK_SRC_UPLL) {
-
- pmc_enable_upll_clock();
- pmc_switch_udpck_to_upllck(CONFIG_USBCLK_DIV - 1);
- pmc_enable_udpck();
- return;
- }
-}
-
-/**
- * \brief Disable the USB clock.
- *
- * \note This implementation does not switch off the PLL, it just turns off the USB clock.
- */
-void sysclk_disable_usb(void)
-{
- pmc_disable_udpck();
-}
-#endif // CONFIG_USBCLK_SOURCE
-
-void sysclk_init(void)
-{
- struct pll_config pllcfg;
-
- /* Set flash wait state to max in case the below clock switching. */
- system_init_flash(CHIP_FREQ_CPU_MAX);
-
- /* Config system clock setting */
- if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) {
- osc_enable(OSC_SLCK_32K_RC);
- osc_wait_ready(OSC_SLCK_32K_RC);
- pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
- }
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) {
- osc_enable(OSC_SLCK_32K_XTAL);
- osc_wait_ready(OSC_SLCK_32K_XTAL);
- pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
- }
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) {
- osc_enable(OSC_SLCK_32K_BYPASS);
- osc_wait_ready(OSC_SLCK_32K_BYPASS);
- pmc_switch_mck_to_sclk(CONFIG_SYSCLK_PRES);
- }
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) {
- /* Already running from SYSCLK_SRC_MAINCK_4M_RC */
- }
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) {
- osc_enable(OSC_MAINCK_8M_RC);
- osc_wait_ready(OSC_MAINCK_8M_RC);
- pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
- }
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) {
- osc_enable(OSC_MAINCK_12M_RC);
- osc_wait_ready(OSC_MAINCK_12M_RC);
- pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
- }
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) {
- osc_enable(OSC_MAINCK_XTAL);
- osc_wait_ready(OSC_MAINCK_XTAL);
- pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
- }
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) {
- osc_enable(OSC_MAINCK_BYPASS);
- osc_wait_ready(OSC_MAINCK_BYPASS);
- pmc_switch_mck_to_mainck(CONFIG_SYSCLK_PRES);
- }
-
-#ifdef CONFIG_PLL0_SOURCE
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) {
- pll_enable_source(CONFIG_PLL0_SOURCE);
- pll_config_defaults(&pllcfg, 0);
- pll_enable(&pllcfg, 0);
- pll_wait_for_lock(0);
- pmc_mck_set_division(CONFIG_SYSCLK_DIV);
- pmc_switch_mck_to_pllack(CONFIG_SYSCLK_PRES);
- }
-#endif
-
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_UPLLCK) {
- pll_enable_source(CONFIG_PLL1_SOURCE);
- pll_config_defaults(&pllcfg, 1);
- pll_enable(&pllcfg, 1);
- pll_wait_for_lock(1);
- pmc_mck_set_division(CONFIG_SYSCLK_DIV);
- pmc_switch_mck_to_upllck(CONFIG_SYSCLK_PRES);
- }
- /* Update the SystemFrequency variable */
- SystemCoreClockUpdate();
-
- /* Set a flash wait state depending on the new cpu frequency */
- system_init_flash(sysclk_get_cpu_hz());
-
-#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
- /* Signal that the internal frequencies are setup */
- sysclk_initialized = 1;
-#endif
-}
-
-//! @}
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/sysclk.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/sysclk.h
deleted file mode 100644
index 4a2826a..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sams70/sysclk.h
+++ /dev/null
@@ -1,473 +0,0 @@
-/**
- * \file
- *
- * \brief Chip-specific system clock management functions.
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef CHIP_SYSCLK_H_INCLUDED
-#define CHIP_SYSCLK_H_INCLUDED
-
-#include <osc.h>
-#include <pll.h>
-
-/**
- * \page sysclk_quickstart Quick Start Guide for the System Clock Management
- * service (SAMV71)
- *
- * This is the quick start guide for the \ref sysclk_group "System Clock
- * Management" service, with step-by-step instructions on how to configure and
- * use the service for specific use cases.
- *
- * \section sysclk_quickstart_usecases System Clock Management use cases
- * - \ref sysclk_quickstart_basic
- * - \ref sysclk_quickstart_use_case_2
- *
- * \section sysclk_quickstart_basic Basic usage of the System Clock Management
- * service
- * This section will present a basic use case for the System Clock Management
- * service. This use case will configure the main system clock to 120MHz,
- * using an internal PLL module to multiply the frequency of a crystal attached
- * to the microcontroller.
- *
- * \subsection sysclk_quickstart_use_case_1_prereq Prerequisites
- * - None
- *
- * \subsection sysclk_quickstart_use_case_1_setup_steps Initialization code
- * Add to the application initialization code:
- * \code
- sysclk_init();
-\endcode
- *
- * \subsection sysclk_quickstart_use_case_1_setup_steps_workflow Workflow
- * -# Configure the system clocks according to the settings in conf_clock.h:
- * \code sysclk_init(); \endcode
- *
- * \subsection sysclk_quickstart_use_case_1_example_code Example code
- * Add or uncomment the following in your conf_clock.h header file,
- * commenting out all other definitions of the same symbol(s):
- * \code
- #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
-
- // Fpll0 = (Fclk * PLL_mul) / PLL_div
- #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
- #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL)
- #define CONFIG_PLL0_DIV 1
-
- // Fbus = Fsys / BUS_div
- #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
-\endcode
- *
- * \subsection sysclk_quickstart_use_case_1_example_workflow Workflow
- * -# Configure the main system clock to use the output of the PLL module as
- * its source:
- * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode
- * -# Configure the PLL module to use the fast external fast crystal
- * oscillator as its source:
- * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode
- * -# Configure the PLL module to multiply the external fast crystal
- * oscillator frequency up to 120MHz:
- * \code
- #define CONFIG_PLL0_MUL (120000000UL / BOARD_FREQ_MAINCK_XTAL)
- #define CONFIG_PLL0_DIV 1
-\endcode
- * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the
- * board \c conf_board.h configuration
- * file as the frequency of the fast crystal attached to the microcontroller.
- * -# Configure the main clock to run at the full 120MHz, disable scaling of
- * the main system clock speed:
- * \code
- #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
-\endcode
- * \note Some dividers are powers of two, while others are integer division
- * factors. Refer to the formulas in the conf_clock.h template commented
- * above each division define.
- */
-
-/**
- * \page sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus Clock
- * Management (SAMV71)
- *
- * \section sysclk_quickstart_use_case_2 Advanced use case - Peripheral Bus
- * Clock Management
- * This section will present a more advanced use case for the System Clock
- * Management service. This use case will configure the main system clock to
- * 96MHz, using an internal PLL module to multiply the frequency of a crystal
- * attached to the microcontroller. The USB clock will be configured via the
- * same PLL module.
- *
- * \subsection sysclk_quickstart_use_case_2_prereq Prerequisites
- * - None
- *
- * \subsection sysclk_quickstart_use_case_2_setup_steps Initialization code
- * Add to the application initialization code:
- * \code
- sysclk_init();
-\endcode
- *
- * \subsection sysclk_quickstart_use_case_2_setup_steps_workflow Workflow
- * -# Configure the system clocks according to the settings in conf_clock.h:
- * \code sysclk_init(); \endcode
- *
- * \subsection sysclk_quickstart_use_case_2_example_code Example code
- * Add or uncomment the following in your conf_clock.h header file,
- * commenting out all other definitions of the same symbol(s):
- * \code
- #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
-
- // Fpll0 = (Fclk * PLL_mul) / PLL_div
- #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
- #define CONFIG_PLL0_MUL (96000000UL / BOARD_FREQ_MAINCK_XTAL)
- #define CONFIG_PLL0_DIV 1
-
- // Fbus = Fsys / BUS_div
- #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
-
- // Fusb = Fsys / USB_div
- #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0
- #define CONFIG_USBCLK_DIV 2
-\endcode
- *
- * \subsection sysclk_quickstart_use_case_2_example_workflow Workflow
- * -# Configure the main system clock to use the output of the PLL0 module as
- * its source:
- * \code #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK \endcode
- * -# Configure the PLL0 module to use the fast external fast crystal
- * oscillator as its source:
- * \code #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL \endcode
- * -# Configure the PLL0 module to multiply the external fast crystal
- * oscillator frequency up to 96MHz:
- * \code
- #define CONFIG_PLL0_MUL (96000000UL / BOARD_FREQ_MAINCK_XTAL)
- #define CONFIG_PLL0_DIV 1
-\endcode
- * \note For user boards, \c BOARD_FREQ_MAINCK_XTAL should be defined in the
- * board \c conf_board.h configuration file as the frequency of the fast
- * crystal attached to the microcontroller.
- * -# Configure the main clock to run at the full 96MHz, disable scaling of
- * the main system clock speed:
- * \code
- #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
-\endcode
- * \note Some dividers are powers of two, while others are integer division
- * factors. Refer to the formulas in the conf_clock.h template commented
- * above each division define.
- * -# Configure the USB module clock to use the output of the PLL0 module as
- * its source with division 2:
- * \code
- #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0
- #define CONFIG_USBCLK_DIV 2
-\endcode
- */
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-/**
- * \weakgroup sysclk_group
- * @{
- */
-
-//! \name Configuration Symbols
-//@{
-/**
- * \def CONFIG_SYSCLK_SOURCE
- * \brief Initial/static main system clock source
- *
- * The main system clock will be configured to use this clock during
- * initialization.
- */
-#ifndef CONFIG_SYSCLK_SOURCE
-# define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
-#endif
-/**
- * \def CONFIG_SYSCLK_PRES
- * \brief Initial CPU clock divider (mck)
- *
- * The MCK will run at
- * \f[
- * f_{MCK} = \frac{f_{sys}}{\mathrm{CONFIG\_SYSCLK\_PRES}}\,\mbox{Hz}
- * \f]
- * after initialization.
- */
-#ifndef CONFIG_SYSCLK_PRES
-# define CONFIG_SYSCLK_PRES 0
-#endif
-
-//@}
-
-//! \name Master Clock Sources (MCK)
-//@{
-#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock
-#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock
-#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock
-#define SYSCLK_SRC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator as master source clock
-#define SYSCLK_SRC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator as master source clock
-#define SYSCLK_SRC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator as master source clock
-#define SYSCLK_SRC_MAINCK_XTAL 6 //!< External crystal oscillator as master source clock
-#define SYSCLK_SRC_MAINCK_BYPASS 7 //!< External bypass oscillator as master source clock
-#define SYSCLK_SRC_PLLACK 8 //!< Use PLLACK as master source clock
-#define SYSCLK_SRC_UPLLCK 9 //!< Use UPLLCK as master source clock
-//@}
-
-//! \name Master Clock Prescalers (MCK)
-//@{
-#define SYSCLK_PRES_1 PMC_MCKR_PRES_CLK_1 //!< Set master clock prescaler to 1
-#define SYSCLK_PRES_2 PMC_MCKR_PRES_CLK_2 //!< Set master clock prescaler to 2
-#define SYSCLK_PRES_4 PMC_MCKR_PRES_CLK_4 //!< Set master clock prescaler to 4
-#define SYSCLK_PRES_8 PMC_MCKR_PRES_CLK_8 //!< Set master clock prescaler to 8
-#define SYSCLK_PRES_16 PMC_MCKR_PRES_CLK_16 //!< Set master clock prescaler to 16
-#define SYSCLK_PRES_32 PMC_MCKR_PRES_CLK_32 //!< Set master clock prescaler to 32
-#define SYSCLK_PRES_64 PMC_MCKR_PRES_CLK_64 //!< Set master clock prescaler to 64
-#define SYSCLK_PRES_3 PMC_MCKR_PRES_CLK_3 //!< Set master clock prescaler to 3
-//@}
-
-//! \name Master Clock Division (MCK)
-//@{
-#define SYSCLK_DIV_1 PMC_MCKR_MDIV_EQ_PCK //!< Set master clock division to 1
-#define SYSCLK_DIV_2 PMC_MCKR_MDIV_PCK_DIV2 //!< Set master clock division to 2
-#define SYSCLK_DIV_4 PMC_MCKR_MDIV_PCK_DIV4 //!< Set master clock division to 4
-#define SYSCLK_DIV_3 PMC_MCKR_MDIV_PCK_DIV3 //!< Set master clock division to 3
-//@}
-
-//! \name USB Clock Sources
-//@{
-#define USBCLK_SRC_PLL0 0 //!< Use PLLA
-#define USBCLK_SRC_UPLL 1 //!< Use UPLL
-//@}
-
-/**
- * \def CONFIG_USBCLK_SOURCE
- * \brief Configuration symbol for the USB generic clock source
- *
- * Sets the clock source to use for the USB. The source must also be properly
- * configured.
- *
- * Define this to one of the \c USBCLK_SRC_xxx settings. Leave it undefined if
- * USB is not required.
- */
-#ifdef __DOXYGEN__
-# define CONFIG_USBCLK_SOURCE
-#endif
-
-/**
- * \def CONFIG_USBCLK_DIV
- * \brief Configuration symbol for the USB generic clock divider setting
- *
- * Sets the clock division for the USB generic clock. If a USB clock source is
- * selected with CONFIG_USBCLK_SOURCE, this configuration symbol must also be
- * defined.
- */
-#ifdef __DOXYGEN__
-# define CONFIG_USBCLK_DIV
-#endif
-
-/**
- * \name Querying the system clock
- *
- * The following functions may be used to query the current frequency of
- * the system clock and the CPU and bus clocks derived from it.
- * sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be
- * available on all platforms, although some platforms may define
- * additional accessors for various chip-internal bus clocks. These are
- * usually not intended to be queried directly by generic code.
- */
-//@{
-
-/**
- * \brief Return the current rate in Hz of the main system clock
- *
- * \todo This function assumes that the main clock source never changes
- * once it's been set up, and that PLL0 always runs at the compile-time
- * configured default rate. While this is probably the most common
- * configuration, which we want to support as a special case for
- * performance reasons, we will at some point need to support more
- * dynamic setups as well.
- */
-#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
-extern uint32_t sysclk_initialized;
-#endif
-static inline uint32_t sysclk_get_main_hz(void)
-{
-#if (defined CONFIG_SYSCLK_DEFAULT_RETURNS_SLOW_OSC)
- if (!sysclk_initialized ) {
- return OSC_MAINCK_4M_RC_HZ;
- }
-#endif
-
- /* Config system clock setting */
- if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_RC) {
- return OSC_SLCK_32K_RC_HZ;
- } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_XTAL) {
- return OSC_SLCK_32K_XTAL_HZ;
- } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_SLCK_BYPASS) {
- return OSC_SLCK_32K_BYPASS_HZ;
- } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_4M_RC) {
- return OSC_MAINCK_4M_RC_HZ;
- } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_8M_RC) {
- return OSC_MAINCK_8M_RC_HZ;
- } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_12M_RC) {
- return OSC_MAINCK_12M_RC_HZ;
- } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_XTAL) {
- return OSC_MAINCK_XTAL_HZ;
- } else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_MAINCK_BYPASS) {
- return OSC_MAINCK_BYPASS_HZ;
- }
-#ifdef CONFIG_PLL0_SOURCE
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_PLLACK) {
- return pll_get_default_rate(0);
- }
-#endif
-
-#ifdef CONFIG_PLL1_SOURCE
- else if (CONFIG_SYSCLK_SOURCE == SYSCLK_SRC_UPLLCK) {
- return PLL_UPLL_HZ;
- }
-#endif
- else {
- /* unhandled_case(CONFIG_SYSCLK_SOURCE); */
- return 0;
- }
-}
-
-/**
- * \brief Return the current rate in Hz of the CPU clock
- *
- * \todo This function assumes that the CPU always runs at the system
- * clock frequency. We want to support at least two more scenarios:
- * Fixed CPU/bus clock dividers (config symbols) and dynamic CPU/bus
- * clock dividers (which may change at run time). Ditto for all the bus
- * clocks.
- *
- * \return Frequency of the CPU clock, in Hz.
- */
-static inline uint32_t sysclk_get_cpu_hz(void)
-{
- /* CONFIG_SYSCLK_PRES is the register value for setting the expected */
- /* prescaler, not an immediate value. */
- return sysclk_get_main_hz() /
- ((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 :
- (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos)));
-}
-
-/**
- * \brief Retrieves the current rate in Hz of the peripheral clocks.
- *
- * \return Frequency of the peripheral clocks, in Hz.
- */
-static inline uint32_t sysclk_get_peripheral_hz(void)
-{
- /* CONFIG_SYSCLK_PRES is the register value for setting the expected */
- /* prescaler, not an immediate value. */
- return sysclk_get_main_hz() /
- (((CONFIG_SYSCLK_PRES == SYSCLK_PRES_3) ? 3 : (1 << (CONFIG_SYSCLK_PRES >> PMC_MCKR_PRES_Pos))) * CONFIG_SYSCLK_DIV);
-}
-
-/**
- * \brief Retrieves the current rate in Hz of the Peripheral Bus clock attached
- * to the specified peripheral.
- *
- * \param module Pointer to the module's base address.
- *
- * \return Frequency of the bus attached to the specified peripheral, in Hz.
- */
-static inline uint32_t sysclk_get_peripheral_bus_hz(const volatile void *module)
-{
- UNUSED(module);
- return sysclk_get_peripheral_hz();
-}
-//@}
-
-//! \name Enabling and disabling synchronous clocks
-//@{
-
-/**
- * \brief Enable a peripheral's clock.
- *
- * \param ul_id Id (number) of the peripheral clock.
- */
-static inline void sysclk_enable_peripheral_clock(uint32_t ul_id)
-{
- pmc_enable_periph_clk(ul_id);
-}
-
-/**
- * \brief Disable a peripheral's clock.
- *
- * \param ul_id Id (number) of the peripheral clock.
- */
-static inline void sysclk_disable_peripheral_clock(uint32_t ul_id)
-{
- pmc_disable_periph_clk(ul_id);
-}
-
-//@}
-
-//! \name System Clock Source and Prescaler configuration
-//@{
-
-extern void sysclk_set_prescalers(uint32_t ul_pres);
-extern void sysclk_set_source(uint32_t ul_src);
-
-//@}
-
-extern void sysclk_enable_usb(void);
-extern void sysclk_disable_usb(void);
-
-extern void sysclk_init(void);
-
-//! @}
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-#endif /* CHIP_SYSCLK_H_INCLUDED */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sysclk.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sysclk.h
deleted file mode 100644
index 86e4bf7..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/clock/sysclk.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/**
- * \file
- *
- * \brief System clock management
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef SYSCLK_H_INCLUDED
-#define SYSCLK_H_INCLUDED
-
-#include "parts.h"
-#include "conf_clock.h"
-
-#if SAM3S
-# include "sam3s/sysclk.h"
-#elif SAM3U
-# include "sam3u/sysclk.h"
-#elif SAM3N
-# include "sam3n/sysclk.h"
-#elif SAM3XA
-# include "sam3x/sysclk.h"
-#elif SAM4S
-# include "sam4s/sysclk.h"
-#elif SAM4E
-# include "sam4e/sysclk.h"
-#elif SAM4C
-# include "sam4c/sysclk.h"
-#elif SAM4CM
-# include "sam4cm/sysclk.h"
-#elif SAM4CP
-# include "sam4cp/sysclk.h"
-#elif SAM4L
-# include "sam4l/sysclk.h"
-#elif SAM4N
-# include "sam4n/sysclk.h"
-#elif SAMG
-# include "samg/sysclk.h"
-#elif SAMV71
-# include "samv71/sysclk.h"
-#elif SAMV70
-# include "samv70/sysclk.h"
-#elif SAME70
-# include "same70/sysclk.h"
-#elif SAMS70
-# include "sams70/sysclk.h"
-#elif (UC3A0 || UC3A1)
-# include "uc3a0_a1/sysclk.h"
-#elif UC3A3
-# include "uc3a3_a4/sysclk.h"
-#elif UC3B
-# include "uc3b0_b1/sysclk.h"
-#elif UC3C
-# include "uc3c/sysclk.h"
-#elif UC3D
-# include "uc3d/sysclk.h"
-#elif UC3L
-# include "uc3l/sysclk.h"
-#elif XMEGA
-# include "xmega/sysclk.h"
-#elif MEGA
-# include "mega/sysclk.h"
-#else
-# error Unsupported chip type
-#endif
-
-/**
- * \defgroup clk_group Clock Management
- */
-
-/**
- * \ingroup clk_group
- * \defgroup sysclk_group System Clock Management
- *
- * See \ref sysclk_quickstart.
- *
- * The <em>sysclk</em> API covers the <em>system clock</em> and all
- * clocks derived from it. The system clock is a chip-internal clock on
- * which all <em>synchronous clocks</em>, i.e. CPU and bus/peripheral
- * clocks, are based. The system clock is typically generated from one
- * of a variety of sources, which may include crystal and RC oscillators
- * as well as PLLs. The clocks derived from the system clock are
- * sometimes also known as <em>synchronous clocks</em>, since they
- * always run synchronously with respect to each other, as opposed to
- * <em>generic clocks</em> which may run from different oscillators or
- * PLLs.
- *
- * Most applications should simply call sysclk_init() to initialize
- * everything related to the system clock and its source (oscillator,
- * PLL or DFLL), and leave it at that. More advanced applications, and
- * platform-specific drivers, may require additional services from the
- * clock system, some of which may be platform-specific.
- *
- * \section sysclk_group_platform Platform Dependencies
- *
- * The sysclk API is partially chip- or platform-specific. While all
- * platforms provide mostly the same functionality, there are some
- * variations around how different bus types and clock tree structures
- * are handled.
- *
- * The following functions are available on all platforms with the same
- * parameters and functionality. These functions may be called freely by
- * portable applications, drivers and services:
- * - sysclk_init()
- * - sysclk_set_source()
- * - sysclk_get_main_hz()
- * - sysclk_get_cpu_hz()
- * - sysclk_get_peripheral_bus_hz()
- *
- * The following functions are available on all platforms, but there may
- * be variations in the function signature (i.e. parameters) and
- * behavior. These functions are typically called by platform-specific
- * parts of drivers, and applications that aren't intended to be
- * portable:
- * - sysclk_enable_peripheral_clock()
- * - sysclk_disable_peripheral_clock()
- * - sysclk_enable_module()
- * - sysclk_disable_module()
- * - sysclk_module_is_enabled()
- * - sysclk_set_prescalers()
- *
- * All other functions should be considered platform-specific.
- * Enabling/disabling clocks to specific peripherals as well as
- * determining the speed of these clocks should be done by calling
- * functions provided by the driver for that peripheral.
- *
- * @{
- */
-
-//! \name System Clock Initialization
-//@{
-/**
- * \fn void sysclk_init(void)
- * \brief Initialize the synchronous clock system.
- *
- * This function will initialize the system clock and its source. This
- * includes:
- * - Mask all synchronous clocks except for any clocks which are
- * essential for normal operation (for example internal memory
- * clocks).
- * - Set up the system clock prescalers as specified by the
- * application's configuration file.
- * - Enable the clock source specified by the application's
- * configuration file (oscillator or PLL) and wait for it to become
- * stable.
- * - Set the main system clock source to the clock specified by the
- * application's configuration file.
- *
- * Since all non-essential peripheral clocks are initially disabled, it
- * is the responsibility of the peripheral driver to re-enable any
- * clocks that are needed for normal operation.
- */
-//@}
-
-//! @}
-
-#endif /* SYSCLK_H_INCLUDED */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/delay/delay.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/delay/delay.h
deleted file mode 100644
index cab97f5..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/delay/delay.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/**
- * \file
- *
- * \brief Common Delay Service
- *
- * Copyright (c) 2014-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef _DELAY_H_
-#define _DELAY_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <sysclk.h>
-
-#if UC3
-# include <cycle_counter.h>
-#elif XMEGA
-# include "xmega/cycle_counter.h"
-#elif MEGA
-# include "mega/cycle_counter.h"
-#elif SAM
-# include "sam/cycle_counter.h"
-#endif
-
-/**
- * @defgroup group_common_services_delay Busy-Wait Delay Routines
- *
- * This module provides simple loop-based delay routines for those
- * applications requiring a brief wait during execution. Common API
- * for UC3, XMEGA, and AVR MEGA.
- *
- * @{
- */
-
-/**
- * @def F_CPU
- * @brief MCU Clock Frequency (Hertz)
- *
- * @deprecated
- * The \ref F_CPU configuration constant is used for compatibility with the
- * \ref group_common_services_delay routines. The common loop-based delay
- * routines are designed to use the \ref clk_group modules while anticipating
- * support for legacy applications assuming a statically defined clock
- * frequency. Applications using a statically configured MCU clock frequency
- * can define \ref F_CPU (Hertz), in which case the common delay routines will
- * use this value rather than calling sysclk_get_cpu_hz() to get the current
- * MCU clock frequency.
- */
-#ifndef F_CPU
-# define F_CPU sysclk_get_cpu_hz()
-#endif
-
-/**
- * @def delay_init
- *
- * @brief Initialize the delay driver.
- * @param fcpu_hz CPU frequency in Hz
- *
- * @deprecated
- * This function is provided for compatibility with ASF applications that
- * may not have been updated to configure the system clock via the common
- * clock service; e.g. sysclk_init() and a configuration header file are
- * used to configure clocks.
- *
- * The functions in this module call \ref sysclk_get_cpu_hz() function to
- * obtain the system clock frequency.
- */
-#define delay_init(fcpu_hz)
-
-/**
- * @def delay_s
- * @brief Delay in seconds.
- * @param delay Delay in seconds
- */
-#define delay_s(delay) ((delay) ? cpu_delay_ms(1000 * delay, F_CPU) : cpu_delay_us(1, F_CPU))
-
-/**
- * @def delay_ms
- * @brief Delay in milliseconds.
- * @param delay Delay in milliseconds
- */
-#define delay_ms(delay) ((delay) ? cpu_delay_ms(delay, F_CPU) : cpu_delay_us(1, F_CPU))
-
-/**
- * @def delay_us
- * @brief Delay in microseconds.
- * @param delay Delay in microseconds
- */
-#define delay_us(delay) ((delay) ? cpu_delay_us(delay, F_CPU) : cpu_delay_us(1, F_CPU))
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @}
- */
-
-#endif /* _DELAY_H_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/delay/sam/cycle_counter.c b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/delay/sam/cycle_counter.c
deleted file mode 100644
index 96669ef..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/delay/sam/cycle_counter.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/**
- * \file
- *
- * \brief ARM functions for busy-wait delay loops
- *
- * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include "cycle_counter.h"
-
-// Delay loop is put to SRAM so that FWS will not affect delay time
-OPTIMIZE_HIGH
-RAMFUNC
-void portable_delay_cycles(unsigned long n)
-{
- UNUSED(n);
-
- __asm (
- "loop: DMB \n"
- "SUBS R0, R0, #1 \n"
- "BNE.N loop "
- );
-}
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/delay/sam/cycle_counter.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/delay/sam/cycle_counter.h
deleted file mode 100644
index 4ac1c6b..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/services/delay/sam/cycle_counter.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/**
- * \file
- *
- * \brief ARM functions for busy-wait delay loops
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef _cycle_counter_h_
-#define _cycle_counter_h_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-#include <compiler.h>
-
-/**
- * @name Convenience functions for busy-wait delay loops
- *
- * @def delay_cycles
- * @brief Delay program execution for a specified number of CPU cycles.
- * @param n number of CPU cycles to wait
- *
- * @def cpu_delay_ms
- * @brief Delay program execution for a specified number of milliseconds.
- * @param delay number of milliseconds to wait
- * @param f_cpu CPU frequency in Hertz
- *
- * @def cpu_delay_us
- * @brief Delay program execution for a specified number of microseconds.
- * @param delay number of microseconds to wait
- * @param f_cpu CPU frequency in Hertz
- *
- * @def cpu_ms_2_cy
- * @brief Convert milli-seconds into CPU cycles.
- * @param ms number of milliseconds
- * @param f_cpu CPU frequency in Hertz
- * @return the converted number of CPU cycles
- *
- * @def cpu_us_2_cy
- * @brief Convert micro-seconds into CPU cycles.
- * @param ms number of microseconds
- * @param f_cpu CPU frequency in Hertz
- * @return the converted number of CPU cycles
- *
- * @{
- */
-
-/**
- * \brief Delay loop to delay n number of cycles
- *
- * \note The function runs in internal RAM so that flash wait states
- * will not affect the delay time.
- *
- * \param n Number of cycles
- */
-void portable_delay_cycles(unsigned long n);
-
-/* Cortex-M7 is faster than Cortex-M3/M4/M0+ */
-#ifdef __CM7_REV
-
-# define cpu_ms_2_cy(ms, f_cpu) \
- (((uint64_t)(ms) * (f_cpu) + (uint64_t)(5.932e3 - 1ul)) / (uint64_t)5.932e3)
-# define cpu_us_2_cy(us, f_cpu) \
- (((uint64_t)(us) * (f_cpu) + (uint64_t)(5.932e6 - 1ul)) / (uint64_t)5.932e6)
-
-#else
-
-# define cpu_ms_2_cy(ms, f_cpu) \
- (((uint64_t)(ms) * (f_cpu) + (uint64_t)(14e3 - 1ul)) / (uint64_t)14e3)
-# define cpu_us_2_cy(us, f_cpu) \
- (((uint64_t)(us) * (f_cpu) + (uint64_t)(14e6 - 1ul)) / (uint64_t)14e6)
-
-#endif
-
-#define delay_cycles portable_delay_cycles
-
-#define cpu_delay_ms(delay, f_cpu) delay_cycles(cpu_ms_2_cy(delay, f_cpu))
-#define cpu_delay_us(delay, f_cpu) delay_cycles(cpu_us_2_cy(delay, f_cpu))
-//! @}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _cycle_counter_h_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/utils/interrupt.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/utils/interrupt.h
deleted file mode 100644
index a88c6f0..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/utils/interrupt.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/**
- * \file
- *
- * \brief Global interrupt management for 8- and 32-bit AVR
- *
- * Copyright (c) 2010-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef UTILS_INTERRUPT_H
-#define UTILS_INTERRUPT_H
-
-#include <parts.h>
-
-#if XMEGA || MEGA
-# include "interrupt/interrupt_avr8.h"
-#elif UC3
-# include "interrupt/interrupt_avr32.h"
-#elif SAM || SAMB
-# include "interrupt/interrupt_sam_nvic.h"
-#else
-# error Unsupported device.
-#endif
-
-/**
- * \defgroup interrupt_group Global interrupt management
- *
- * This is a driver for global enabling and disabling of interrupts.
- *
- * @{
- */
-
-#if defined(__DOXYGEN__)
-/**
- * \def CONFIG_INTERRUPT_FORCE_INTC
- * \brief Force usage of the ASF INTC driver
- *
- * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.
- * This is useful to ensure compatibility across compilers and shall be used only when required
- * by the application needs.
- */
-# define CONFIG_INTERRUPT_FORCE_INTC
-#endif
-
-//! \name Global interrupt flags
-//@{
-/**
- * \typedef irqflags_t
- * \brief Type used for holding state of interrupt flag
- */
-
-/**
- * \def cpu_irq_enable
- * \brief Enable interrupts globally
- */
-
-/**
- * \def cpu_irq_disable
- * \brief Disable interrupts globally
- */
-
-/**
- * \fn irqflags_t cpu_irq_save(void)
- * \brief Get and clear the global interrupt flags
- *
- * Use in conjunction with \ref cpu_irq_restore.
- *
- * \return Current state of interrupt flags.
- *
- * \note This function leaves interrupts disabled.
- */
-
-/**
- * \fn void cpu_irq_restore(irqflags_t flags)
- * \brief Restore global interrupt flags
- *
- * Use in conjunction with \ref cpu_irq_save.
- *
- * \param flags State to set interrupt flag to.
- */
-
-/**
- * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)
- * \brief Check if interrupts are globally enabled in supplied flags
- *
- * \param flags Currents state of interrupt flags.
- *
- * \return True if interrupts are enabled.
- */
-
-/**
- * \def cpu_irq_is_enabled
- * \brief Check if interrupts are globally enabled
- *
- * \return True if interrupts are enabled.
- */
-//@}
-
-//! @}
-
-/**
- * \ingroup interrupt_group
- * \defgroup interrupt_deprecated_group Deprecated interrupt definitions
- */
-
-#endif /* UTILS_INTERRUPT_H */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
deleted file mode 100644
index 26dcc91..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/**
- * \file
- *
- * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
- *
- * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include "interrupt_sam_nvic.h"
-
-#if !defined(__DOXYGEN__)
-/* Deprecated - global flag to determine the global interrupt state. Required by
- * QTouch library, however new applications should use cpu_irq_is_enabled()
- * which probes the true global interrupt state from the CPU special registers.
- */
-volatile bool g_interrupt_enabled = true;
-#endif
-
-void cpu_irq_enter_critical(void)
-{
- if (cpu_irq_critical_section_counter == 0) {
- if (cpu_irq_is_enabled()) {
- cpu_irq_disable();
- cpu_irq_prev_interrupt_state = true;
- } else {
- /* Make sure the to save the prev state as false */
- cpu_irq_prev_interrupt_state = false;
- }
-
- }
-
- cpu_irq_critical_section_counter++;
-}
-
-void cpu_irq_leave_critical(void)
-{
- /* Check if the user is trying to leave a critical section when not in a critical section */
- Assert(cpu_irq_critical_section_counter > 0);
-
- cpu_irq_critical_section_counter--;
-
- /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
- was enabled when entering critical state */
- if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
- cpu_irq_enable();
- }
-}
-
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
deleted file mode 100644
index 419ad20..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/**
- * \file
- *
- * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
- *
- * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef UTILS_INTERRUPT_INTERRUPT_H
-#define UTILS_INTERRUPT_INTERRUPT_H
-
-#include <compiler.h>
-#include <parts.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \weakgroup interrupt_group
- *
- * @{
- */
-
-/**
- * \name Interrupt Service Routine definition
- *
- * @{
- */
-
-/**
- * \brief Define service routine
- *
- * \note For NVIC devices the interrupt service routines are predefined to
- * add to vector table in binary generation, so there is no service
- * register at run time. The routine collections are in exceptions.h.
- *
- * Usage:
- * \code
- ISR(foo_irq_handler)
- {
- // Function definition
- ...
- }
-\endcode
- *
- * \param func Name for the function.
- */
-# define ISR(func) \
- void func (void)
-
-/**
- * \brief Initialize interrupt vectors
- *
- * For NVIC the interrupt vectors are put in vector table. So nothing
- * to do to initialize them, except defined the vector function with
- * right name.
- *
- * This must be called prior to \ref irq_register_handler.
- */
-# define irq_initialize_vectors() \
- do { \
- } while(0)
-
-/**
- * \brief Register handler for interrupt
- *
- * For NVIC the interrupt vectors are put in vector table. So nothing
- * to do to register them, except defined the vector function with
- * right name.
- *
- * Usage:
- * \code
- irq_initialize_vectors();
- irq_register_handler(foo_irq_handler);
-\endcode
- *
- * \note The function \a func must be defined with the \ref ISR macro.
- * \note The functions prototypes can be found in the device exception header
- * files (exceptions.h).
- */
-# define irq_register_handler(int_num, int_prio) \
- NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \
- NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \
- NVIC_EnableIRQ( (IRQn_Type)int_num); \
-
-//@}
-
-# define cpu_irq_enable() \
- do { \
- g_interrupt_enabled = true; \
- __DMB(); \
- __enable_irq(); \
- } while (0)
-# define cpu_irq_disable() \
- do { \
- __disable_irq(); \
- __DMB(); \
- g_interrupt_enabled = false; \
- } while (0)
-
-typedef uint32_t irqflags_t;
-
-#if !defined(__DOXYGEN__)
-extern volatile bool g_interrupt_enabled;
-#endif
-
-#define cpu_irq_is_enabled() (__get_PRIMASK() == 0)
-
-static volatile uint32_t cpu_irq_critical_section_counter;
-static volatile bool cpu_irq_prev_interrupt_state;
-
-static inline irqflags_t cpu_irq_save(void)
-{
- volatile irqflags_t flags = cpu_irq_is_enabled();
- cpu_irq_disable();
- return flags;
-}
-
-static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
-{
- return (flags);
-}
-
-static inline void cpu_irq_restore(irqflags_t flags)
-{
- if (cpu_irq_is_enabled_flags(flags))
- cpu_irq_enable();
-}
-
-void cpu_irq_enter_critical(void);
-void cpu_irq_leave_critical(void);
-
-/**
- * \weakgroup interrupt_deprecated_group
- * @{
- */
-
-#define Enable_global_interrupt() cpu_irq_enable()
-#define Disable_global_interrupt() cpu_irq_disable()
-#define Is_global_interrupt_enabled() cpu_irq_is_enabled()
-
-//@}
-
-//@}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* UTILS_INTERRUPT_INTERRUPT_H */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/utils/parts.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/utils/parts.h
deleted file mode 100644
index 27cbe5f..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/common/utils/parts.h
+++ /dev/null
@@ -1,1594 +0,0 @@
-/**
- * \file
- *
- * \brief Atmel part identification macros
- *
- * Copyright (C) 2012-2017 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef ATMEL_PARTS_H
-#define ATMEL_PARTS_H
-
-/**
- * \defgroup part_macros_group Atmel part identification macros
- *
- * This collection of macros identify which series and families that the various
- * Atmel parts belong to. These can be used to select part-dependent sections of
- * code at compile time.
- *
- * @{
- */
-
-/**
- * \name Convenience macros for part checking
- * @{
- */
-/* ! Check GCC and IAR part definition for 8-bit AVR */
-#define AVR8_PART_IS_DEFINED(part) \
- (defined(__ ## part ## __) || defined(__AVR_ ## part ## __))
-
-/* ! Check GCC and IAR part definition for 32-bit AVR */
-#define AVR32_PART_IS_DEFINED(part) \
- (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __))
-
-/* ! Check GCC and IAR part definition for SAM */
-#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __))
-/** @} */
-
-/**
- * \defgroup uc3_part_macros_group AVR UC3 parts
- * @{
- */
-
-/**
- * \name AVR UC3 A series
- * @{
- */
-#define UC3A0 ( \
- AVR32_PART_IS_DEFINED(UC3A0128) || \
- AVR32_PART_IS_DEFINED(UC3A0256) || \
- AVR32_PART_IS_DEFINED(UC3A0512) \
- )
-
-#define UC3A1 ( \
- AVR32_PART_IS_DEFINED(UC3A1128) || \
- AVR32_PART_IS_DEFINED(UC3A1256) || \
- AVR32_PART_IS_DEFINED(UC3A1512) \
- )
-
-#define UC3A3 ( \
- AVR32_PART_IS_DEFINED(UC3A364) || \
- AVR32_PART_IS_DEFINED(UC3A364S) || \
- AVR32_PART_IS_DEFINED(UC3A3128) || \
- AVR32_PART_IS_DEFINED(UC3A3128S) || \
- AVR32_PART_IS_DEFINED(UC3A3256) || \
- AVR32_PART_IS_DEFINED(UC3A3256S) \
- )
-
-#define UC3A4 ( \
- AVR32_PART_IS_DEFINED(UC3A464) || \
- AVR32_PART_IS_DEFINED(UC3A464S) || \
- AVR32_PART_IS_DEFINED(UC3A4128) || \
- AVR32_PART_IS_DEFINED(UC3A4128S) || \
- AVR32_PART_IS_DEFINED(UC3A4256) || \
- AVR32_PART_IS_DEFINED(UC3A4256S) \
- )
-/** @} */
-
-/**
- * \name AVR UC3 B series
- * @{
- */
-#define UC3B0 ( \
- AVR32_PART_IS_DEFINED(UC3B064) || \
- AVR32_PART_IS_DEFINED(UC3B0128) || \
- AVR32_PART_IS_DEFINED(UC3B0256) || \
- AVR32_PART_IS_DEFINED(UC3B0512) \
- )
-
-#define UC3B1 ( \
- AVR32_PART_IS_DEFINED(UC3B164) || \
- AVR32_PART_IS_DEFINED(UC3B1128) || \
- AVR32_PART_IS_DEFINED(UC3B1256) || \
- AVR32_PART_IS_DEFINED(UC3B1512) \
- )
-/** @} */
-
-/**
- * \name AVR UC3 C series
- * @{
- */
-#define UC3C0 ( \
- AVR32_PART_IS_DEFINED(UC3C064C) || \
- AVR32_PART_IS_DEFINED(UC3C0128C) || \
- AVR32_PART_IS_DEFINED(UC3C0256C) || \
- AVR32_PART_IS_DEFINED(UC3C0512C) \
- )
-
-#define UC3C1 ( \
- AVR32_PART_IS_DEFINED(UC3C164C) || \
- AVR32_PART_IS_DEFINED(UC3C1128C) || \
- AVR32_PART_IS_DEFINED(UC3C1256C) || \
- AVR32_PART_IS_DEFINED(UC3C1512C) \
- )
-
-#define UC3C2 ( \
- AVR32_PART_IS_DEFINED(UC3C264C) || \
- AVR32_PART_IS_DEFINED(UC3C2128C) || \
- AVR32_PART_IS_DEFINED(UC3C2256C) || \
- AVR32_PART_IS_DEFINED(UC3C2512C) \
- )
-/** @} */
-
-/**
- * \name AVR UC3 D series
- * @{
- */
-#define UC3D3 ( \
- AVR32_PART_IS_DEFINED(UC64D3) || \
- AVR32_PART_IS_DEFINED(UC128D3) \
- )
-
-#define UC3D4 ( \
- AVR32_PART_IS_DEFINED(UC64D4) || \
- AVR32_PART_IS_DEFINED(UC128D4) \
- )
-/** @} */
-
-/**
- * \name AVR UC3 L series
- * @{
- */
-#define UC3L0 ( \
- AVR32_PART_IS_DEFINED(UC3L016) || \
- AVR32_PART_IS_DEFINED(UC3L032) || \
- AVR32_PART_IS_DEFINED(UC3L064) \
- )
-
-#define UC3L0128 ( \
- AVR32_PART_IS_DEFINED(UC3L0128) \
- )
-
-#define UC3L0256 ( \
- AVR32_PART_IS_DEFINED(UC3L0256) \
- )
-
-#define UC3L3 ( \
- AVR32_PART_IS_DEFINED(UC64L3U) || \
- AVR32_PART_IS_DEFINED(UC128L3U) || \
- AVR32_PART_IS_DEFINED(UC256L3U) \
- )
-
-#define UC3L4 ( \
- AVR32_PART_IS_DEFINED(UC64L4U) || \
- AVR32_PART_IS_DEFINED(UC128L4U) || \
- AVR32_PART_IS_DEFINED(UC256L4U) \
- )
-
-#define UC3L3_L4 (UC3L3 || UC3L4)
-/** @} */
-
-/**
- * \name AVR UC3 families
- * @{
- */
-/** AVR UC3 A family */
-#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4)
-
-/** AVR UC3 B family */
-#define UC3B (UC3B0 || UC3B1)
-
-/** AVR UC3 C family */
-#define UC3C (UC3C0 || UC3C1 || UC3C2)
-
-/** AVR UC3 D family */
-#define UC3D (UC3D3 || UC3D4)
-
-/** AVR UC3 L family */
-#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4)
-/** @} */
-
-/** AVR UC3 product line */
-#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L)
-
-/** @} */
-
-/**
- * \defgroup xmega_part_macros_group AVR XMEGA parts
- * @{
- */
-
-/**
- * \name AVR XMEGA A series
- * @{
- */
-#define XMEGA_A1 ( \
- AVR8_PART_IS_DEFINED(ATxmega64A1) || \
- AVR8_PART_IS_DEFINED(ATxmega128A1) \
- )
-
-#define XMEGA_A3 ( \
- AVR8_PART_IS_DEFINED(ATxmega64A3) || \
- AVR8_PART_IS_DEFINED(ATxmega128A3) || \
- AVR8_PART_IS_DEFINED(ATxmega192A3) || \
- AVR8_PART_IS_DEFINED(ATxmega256A3) \
- )
-
-#define XMEGA_A3B ( \
- AVR8_PART_IS_DEFINED(ATxmega256A3B) \
- )
-
-#define XMEGA_A4 ( \
- AVR8_PART_IS_DEFINED(ATxmega16A4) || \
- AVR8_PART_IS_DEFINED(ATxmega32A4) \
- )
-/** @} */
-
-/**
- * \name AVR XMEGA AU series
- * @{
- */
-#define XMEGA_A1U ( \
- AVR8_PART_IS_DEFINED(ATxmega64A1U) || \
- AVR8_PART_IS_DEFINED(ATxmega128A1U) \
- )
-
-#define XMEGA_A3U ( \
- AVR8_PART_IS_DEFINED(ATxmega64A3U) || \
- AVR8_PART_IS_DEFINED(ATxmega128A3U) || \
- AVR8_PART_IS_DEFINED(ATxmega192A3U) || \
- AVR8_PART_IS_DEFINED(ATxmega256A3U) \
- )
-
-#define XMEGA_A3BU ( \
- AVR8_PART_IS_DEFINED(ATxmega256A3BU) \
- )
-
-#define XMEGA_A4U ( \
- AVR8_PART_IS_DEFINED(ATxmega16A4U) || \
- AVR8_PART_IS_DEFINED(ATxmega32A4U) || \
- AVR8_PART_IS_DEFINED(ATxmega64A4U) || \
- AVR8_PART_IS_DEFINED(ATxmega128A4U) \
- )
-/** @} */
-
-/**
- * \name AVR XMEGA B series
- * @{
- */
-#define XMEGA_B1 ( \
- AVR8_PART_IS_DEFINED(ATxmega64B1) || \
- AVR8_PART_IS_DEFINED(ATxmega128B1) \
- )
-
-#define XMEGA_B3 ( \
- AVR8_PART_IS_DEFINED(ATxmega64B3) || \
- AVR8_PART_IS_DEFINED(ATxmega128B3) \
- )
-/** @} */
-
-/**
- * \name AVR XMEGA C series
- * @{
- */
-#define XMEGA_C3 ( \
- AVR8_PART_IS_DEFINED(ATxmega384C3) || \
- AVR8_PART_IS_DEFINED(ATxmega256C3) || \
- AVR8_PART_IS_DEFINED(ATxmega192C3) || \
- AVR8_PART_IS_DEFINED(ATxmega128C3) || \
- AVR8_PART_IS_DEFINED(ATxmega64C3) || \
- AVR8_PART_IS_DEFINED(ATxmega32C3) \
- )
-
-#define XMEGA_C4 ( \
- AVR8_PART_IS_DEFINED(ATxmega32C4) || \
- AVR8_PART_IS_DEFINED(ATxmega16C4) \
- )
-/** @} */
-
-/**
- * \name AVR XMEGA D series
- * @{
- */
-#define XMEGA_D3 ( \
- AVR8_PART_IS_DEFINED(ATxmega32D3) || \
- AVR8_PART_IS_DEFINED(ATxmega64D3) || \
- AVR8_PART_IS_DEFINED(ATxmega128D3) || \
- AVR8_PART_IS_DEFINED(ATxmega192D3) || \
- AVR8_PART_IS_DEFINED(ATxmega256D3) || \
- AVR8_PART_IS_DEFINED(ATxmega384D3) \
- )
-
-#define XMEGA_D4 ( \
- AVR8_PART_IS_DEFINED(ATxmega16D4) || \
- AVR8_PART_IS_DEFINED(ATxmega32D4) || \
- AVR8_PART_IS_DEFINED(ATxmega64D4) || \
- AVR8_PART_IS_DEFINED(ATxmega128D4) \
- )
-/** @} */
-
-/**
- * \name AVR XMEGA E series
- * @{
- */
-#define XMEGA_E5 ( \
- AVR8_PART_IS_DEFINED(ATxmega8E5) || \
- AVR8_PART_IS_DEFINED(ATxmega16E5) || \
- AVR8_PART_IS_DEFINED(ATxmega32E5) \
- )
-/** @} */
-
-
-/**
- * \name AVR XMEGA families
- * @{
- */
-/** AVR XMEGA A family */
-#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4)
-
-/** AVR XMEGA AU family */
-#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U)
-
-/** AVR XMEGA B family */
-#define XMEGA_B (XMEGA_B1 || XMEGA_B3)
-
-/** AVR XMEGA C family */
-#define XMEGA_C (XMEGA_C3 || XMEGA_C4)
-
-/** AVR XMEGA D family */
-#define XMEGA_D (XMEGA_D3 || XMEGA_D4)
-
-/** AVR XMEGA E family */
-#define XMEGA_E (XMEGA_E5)
-/** @} */
-
-
-/** AVR XMEGA product line */
-#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E)
-
-/** @} */
-
-/**
- * \defgroup mega_part_macros_group megaAVR parts
- *
- * \note These megaAVR groupings are based on the groups in AVR Libc for the
- * part header files. They are not names of official megaAVR device series or
- * families.
- *
- * @{
- */
-
-/**
- * \name ATmegaxx0/xx1 subgroups
- * @{
- */
-#define MEGA_XX0 ( \
- AVR8_PART_IS_DEFINED(ATmega640) || \
- AVR8_PART_IS_DEFINED(ATmega1280) || \
- AVR8_PART_IS_DEFINED(ATmega2560) \
- )
-
-#define MEGA_XX1 ( \
- AVR8_PART_IS_DEFINED(ATmega1281) || \
- AVR8_PART_IS_DEFINED(ATmega2561) \
- )
-/** @} */
-
-/**
- * \name megaAVR groups
- * @{
- */
-/** ATmegaxx0/xx1 group */
-#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1)
-
-/** ATmegaxx4 group */
-#define MEGA_XX4 ( \
- AVR8_PART_IS_DEFINED(ATmega164A) || \
- AVR8_PART_IS_DEFINED(ATmega164PA) || \
- AVR8_PART_IS_DEFINED(ATmega324A) || \
- AVR8_PART_IS_DEFINED(ATmega324PA) || \
- AVR8_PART_IS_DEFINED(ATmega324PB) || \
- AVR8_PART_IS_DEFINED(ATmega644) || \
- AVR8_PART_IS_DEFINED(ATmega644A) || \
- AVR8_PART_IS_DEFINED(ATmega644PA) || \
- AVR8_PART_IS_DEFINED(ATmega1284P) || \
- AVR8_PART_IS_DEFINED(ATmega128RFA1) \
- )
-
-/** ATmegaxx4 group */
-#define MEGA_XX4_A ( \
- AVR8_PART_IS_DEFINED(ATmega164A) || \
- AVR8_PART_IS_DEFINED(ATmega164PA) || \
- AVR8_PART_IS_DEFINED(ATmega324A) || \
- AVR8_PART_IS_DEFINED(ATmega324PA) || \
- AVR8_PART_IS_DEFINED(ATmega644A) || \
- AVR8_PART_IS_DEFINED(ATmega644PA) || \
- AVR8_PART_IS_DEFINED(ATmega1284P) \
- )
-
-/** ATmegaxx8 group */
-#define MEGA_XX8 ( \
- AVR8_PART_IS_DEFINED(ATmega48) || \
- AVR8_PART_IS_DEFINED(ATmega48A) || \
- AVR8_PART_IS_DEFINED(ATmega48PA) || \
- AVR8_PART_IS_DEFINED(ATmega48PB) || \
- AVR8_PART_IS_DEFINED(ATmega88) || \
- AVR8_PART_IS_DEFINED(ATmega88A) || \
- AVR8_PART_IS_DEFINED(ATmega88PA) || \
- AVR8_PART_IS_DEFINED(ATmega88PB) || \
- AVR8_PART_IS_DEFINED(ATmega168) || \
- AVR8_PART_IS_DEFINED(ATmega168A) || \
- AVR8_PART_IS_DEFINED(ATmega168PA) || \
- AVR8_PART_IS_DEFINED(ATmega168PB) || \
- AVR8_PART_IS_DEFINED(ATmega328) || \
- AVR8_PART_IS_DEFINED(ATmega328P) || \
- AVR8_PART_IS_DEFINED(ATmega328PB) \
- )
-
-/** ATmegaxx8A/P/PA group */
-#define MEGA_XX8_A ( \
- AVR8_PART_IS_DEFINED(ATmega48A) || \
- AVR8_PART_IS_DEFINED(ATmega48PA) || \
- AVR8_PART_IS_DEFINED(ATmega88A) || \
- AVR8_PART_IS_DEFINED(ATmega88PA) || \
- AVR8_PART_IS_DEFINED(ATmega168A) || \
- AVR8_PART_IS_DEFINED(ATmega168PA) || \
- AVR8_PART_IS_DEFINED(ATmega328P) \
- )
-
-/** ATmegaxx group */
-#define MEGA_XX ( \
- AVR8_PART_IS_DEFINED(ATmega16) || \
- AVR8_PART_IS_DEFINED(ATmega16A) || \
- AVR8_PART_IS_DEFINED(ATmega32) || \
- AVR8_PART_IS_DEFINED(ATmega32A) || \
- AVR8_PART_IS_DEFINED(ATmega64) || \
- AVR8_PART_IS_DEFINED(ATmega64A) || \
- AVR8_PART_IS_DEFINED(ATmega128) || \
- AVR8_PART_IS_DEFINED(ATmega128A) \
- )
-
-/** ATmegaxxA/P/PA group */
-#define MEGA_XX_A ( \
- AVR8_PART_IS_DEFINED(ATmega16A) || \
- AVR8_PART_IS_DEFINED(ATmega32A) || \
- AVR8_PART_IS_DEFINED(ATmega64A) || \
- AVR8_PART_IS_DEFINED(ATmega128A) \
- )
-/** ATmegaxxRFA1 group */
-#define MEGA_RFA1 ( \
- AVR8_PART_IS_DEFINED(ATmega128RFA1) \
- )
-
-/** ATmegaxxRFR2 group */
-#define MEGA_RFR2 ( \
- AVR8_PART_IS_DEFINED(ATmega64RFR2) || \
- AVR8_PART_IS_DEFINED(ATmega128RFR2) || \
- AVR8_PART_IS_DEFINED(ATmega256RFR2) || \
- AVR8_PART_IS_DEFINED(ATmega644RFR2) || \
- AVR8_PART_IS_DEFINED(ATmega1284RFR2) || \
- AVR8_PART_IS_DEFINED(ATmega2564RFR2) \
- )
-
-
-/** ATmegaxxRFxx group */
-#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2)
-
-/**
- * \name ATmegaxx_un0/un1/un2 subgroups
- * @{
- */
-#define MEGA_XX_UN0 ( \
- AVR8_PART_IS_DEFINED(ATmega16) || \
- AVR8_PART_IS_DEFINED(ATmega16A) || \
- AVR8_PART_IS_DEFINED(ATmega32) || \
- AVR8_PART_IS_DEFINED(ATmega32A) \
- )
-
-/** ATmegaxx group without power reduction and
- * And interrupt sense register.
- */
-#define MEGA_XX_UN1 ( \
- AVR8_PART_IS_DEFINED(ATmega64) || \
- AVR8_PART_IS_DEFINED(ATmega64A) || \
- AVR8_PART_IS_DEFINED(ATmega128) || \
- AVR8_PART_IS_DEFINED(ATmega128A) \
- )
-
-/** ATmegaxx group without power reduction and
- * And interrupt sense register.
- */
-#define MEGA_XX_UN2 ( \
- AVR8_PART_IS_DEFINED(ATmega169P) || \
- AVR8_PART_IS_DEFINED(ATmega169PA) || \
- AVR8_PART_IS_DEFINED(ATmega329P) || \
- AVR8_PART_IS_DEFINED(ATmega329PA) \
- )
-
-/** Devices added to complete megaAVR offering.
- * Please do not use this group symbol as it is not intended
- * to be permanent: the devices should be regrouped.
- */
-#define MEGA_UNCATEGORIZED ( \
- AVR8_PART_IS_DEFINED(AT90CAN128) || \
- AVR8_PART_IS_DEFINED(AT90CAN32) || \
- AVR8_PART_IS_DEFINED(AT90CAN64) || \
- AVR8_PART_IS_DEFINED(AT90PWM1) || \
- AVR8_PART_IS_DEFINED(AT90PWM216) || \
- AVR8_PART_IS_DEFINED(AT90PWM2B) || \
- AVR8_PART_IS_DEFINED(AT90PWM316) || \
- AVR8_PART_IS_DEFINED(AT90PWM3B) || \
- AVR8_PART_IS_DEFINED(AT90PWM81) || \
- AVR8_PART_IS_DEFINED(AT90USB1286) || \
- AVR8_PART_IS_DEFINED(AT90USB1287) || \
- AVR8_PART_IS_DEFINED(AT90USB162) || \
- AVR8_PART_IS_DEFINED(AT90USB646) || \
- AVR8_PART_IS_DEFINED(AT90USB647) || \
- AVR8_PART_IS_DEFINED(AT90USB82) || \
- AVR8_PART_IS_DEFINED(ATmega1284) || \
- AVR8_PART_IS_DEFINED(ATmega162) || \
- AVR8_PART_IS_DEFINED(ATmega164P) || \
- AVR8_PART_IS_DEFINED(ATmega165A) || \
- AVR8_PART_IS_DEFINED(ATmega165P) || \
- AVR8_PART_IS_DEFINED(ATmega165PA) || \
- AVR8_PART_IS_DEFINED(ATmega168P) || \
- AVR8_PART_IS_DEFINED(ATmega169A) || \
- AVR8_PART_IS_DEFINED(ATmega16M1) || \
- AVR8_PART_IS_DEFINED(ATmega16U2) || \
- AVR8_PART_IS_DEFINED(ATmega16U4) || \
- AVR8_PART_IS_DEFINED(ATmega256RFA2) || \
- AVR8_PART_IS_DEFINED(ATmega324P) || \
- AVR8_PART_IS_DEFINED(ATmega325) || \
- AVR8_PART_IS_DEFINED(ATmega3250) || \
- AVR8_PART_IS_DEFINED(ATmega3250A) || \
- AVR8_PART_IS_DEFINED(ATmega3250P) || \
- AVR8_PART_IS_DEFINED(ATmega3250PA) || \
- AVR8_PART_IS_DEFINED(ATmega325A) || \
- AVR8_PART_IS_DEFINED(ATmega325P) || \
- AVR8_PART_IS_DEFINED(ATmega325PA) || \
- AVR8_PART_IS_DEFINED(ATmega329) || \
- AVR8_PART_IS_DEFINED(ATmega3290) || \
- AVR8_PART_IS_DEFINED(ATmega3290A) || \
- AVR8_PART_IS_DEFINED(ATmega3290P) || \
- AVR8_PART_IS_DEFINED(ATmega3290PA) || \
- AVR8_PART_IS_DEFINED(ATmega329A) || \
- AVR8_PART_IS_DEFINED(ATmega32M1) || \
- AVR8_PART_IS_DEFINED(ATmega32U2) || \
- AVR8_PART_IS_DEFINED(ATmega32U4) || \
- AVR8_PART_IS_DEFINED(ATmega48P) || \
- AVR8_PART_IS_DEFINED(ATmega644P) || \
- AVR8_PART_IS_DEFINED(ATmega645) || \
- AVR8_PART_IS_DEFINED(ATmega6450) || \
- AVR8_PART_IS_DEFINED(ATmega6450A) || \
- AVR8_PART_IS_DEFINED(ATmega6450P) || \
- AVR8_PART_IS_DEFINED(ATmega645A) || \
- AVR8_PART_IS_DEFINED(ATmega645P) || \
- AVR8_PART_IS_DEFINED(ATmega649) || \
- AVR8_PART_IS_DEFINED(ATmega6490) || \
- AVR8_PART_IS_DEFINED(ATmega6490A) || \
- AVR8_PART_IS_DEFINED(ATmega6490P) || \
- AVR8_PART_IS_DEFINED(ATmega649A) || \
- AVR8_PART_IS_DEFINED(ATmega649P) || \
- AVR8_PART_IS_DEFINED(ATmega64M1) || \
- AVR8_PART_IS_DEFINED(ATmega64RFA2) || \
- AVR8_PART_IS_DEFINED(ATmega8) || \
- AVR8_PART_IS_DEFINED(ATmega8515) || \
- AVR8_PART_IS_DEFINED(ATmega8535) || \
- AVR8_PART_IS_DEFINED(ATmega88P) || \
- AVR8_PART_IS_DEFINED(ATmega8A) || \
- AVR8_PART_IS_DEFINED(ATmega8U2) \
- )
-
-/** Unspecified group */
-#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \
- MEGA_UNCATEGORIZED)
-
-/** @} */
-
-/** megaAVR product line */
-#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \
- MEGA_UNSPECIFIED)
-
-/** @} */
-
-/**
- * \defgroup sam_part_macros_group SAM parts
- * @{
- */
-
-/**
- * \name SAM3S series
- * @{
- */
-#define SAM3S1 ( \
- SAM_PART_IS_DEFINED(SAM3S1A) || \
- SAM_PART_IS_DEFINED(SAM3S1B) || \
- SAM_PART_IS_DEFINED(SAM3S1C) \
- )
-
-#define SAM3S2 ( \
- SAM_PART_IS_DEFINED(SAM3S2A) || \
- SAM_PART_IS_DEFINED(SAM3S2B) || \
- SAM_PART_IS_DEFINED(SAM3S2C) \
- )
-
-#define SAM3S4 ( \
- SAM_PART_IS_DEFINED(SAM3S4A) || \
- SAM_PART_IS_DEFINED(SAM3S4B) || \
- SAM_PART_IS_DEFINED(SAM3S4C) \
- )
-
-#define SAM3S8 ( \
- SAM_PART_IS_DEFINED(SAM3S8B) || \
- SAM_PART_IS_DEFINED(SAM3S8C) \
- )
-
-#define SAM3SD8 ( \
- SAM_PART_IS_DEFINED(SAM3SD8B) || \
- SAM_PART_IS_DEFINED(SAM3SD8C) \
- )
-/** @} */
-
-/**
- * \name SAM3U series
- * @{
- */
-#define SAM3U1 ( \
- SAM_PART_IS_DEFINED(SAM3U1C) || \
- SAM_PART_IS_DEFINED(SAM3U1E) \
- )
-
-#define SAM3U2 ( \
- SAM_PART_IS_DEFINED(SAM3U2C) || \
- SAM_PART_IS_DEFINED(SAM3U2E) \
- )
-
-#define SAM3U4 ( \
- SAM_PART_IS_DEFINED(SAM3U4C) || \
- SAM_PART_IS_DEFINED(SAM3U4E) \
- )
-/** @} */
-
-/**
- * \name SAM3N series
- * @{
- */
-#define SAM3N00 ( \
- SAM_PART_IS_DEFINED(SAM3N00A) || \
- SAM_PART_IS_DEFINED(SAM3N00B) \
- )
-
-#define SAM3N0 ( \
- SAM_PART_IS_DEFINED(SAM3N0A) || \
- SAM_PART_IS_DEFINED(SAM3N0B) || \
- SAM_PART_IS_DEFINED(SAM3N0C) \
- )
-
-#define SAM3N1 ( \
- SAM_PART_IS_DEFINED(SAM3N1A) || \
- SAM_PART_IS_DEFINED(SAM3N1B) || \
- SAM_PART_IS_DEFINED(SAM3N1C) \
- )
-
-#define SAM3N2 ( \
- SAM_PART_IS_DEFINED(SAM3N2A) || \
- SAM_PART_IS_DEFINED(SAM3N2B) || \
- SAM_PART_IS_DEFINED(SAM3N2C) \
- )
-
-#define SAM3N4 ( \
- SAM_PART_IS_DEFINED(SAM3N4A) || \
- SAM_PART_IS_DEFINED(SAM3N4B) || \
- SAM_PART_IS_DEFINED(SAM3N4C) \
- )
-/** @} */
-
-/**
- * \name SAM3X series
- * @{
- */
-#define SAM3X4 ( \
- SAM_PART_IS_DEFINED(SAM3X4C) || \
- SAM_PART_IS_DEFINED(SAM3X4E) \
- )
-
-#define SAM3X8 ( \
- SAM_PART_IS_DEFINED(SAM3X8C) || \
- SAM_PART_IS_DEFINED(SAM3X8E) || \
- SAM_PART_IS_DEFINED(SAM3X8H) \
- )
-/** @} */
-
-/**
- * \name SAM3A series
- * @{
- */
-#define SAM3A4 ( \
- SAM_PART_IS_DEFINED(SAM3A4C) \
- )
-
-#define SAM3A8 ( \
- SAM_PART_IS_DEFINED(SAM3A8C) \
- )
-/** @} */
-
-/**
- * \name SAM4S series
- * @{
- */
-#define SAM4S2 ( \
- SAM_PART_IS_DEFINED(SAM4S2A) || \
- SAM_PART_IS_DEFINED(SAM4S2B) || \
- SAM_PART_IS_DEFINED(SAM4S2C) \
- )
-
-#define SAM4S4 ( \
- SAM_PART_IS_DEFINED(SAM4S4A) || \
- SAM_PART_IS_DEFINED(SAM4S4B) || \
- SAM_PART_IS_DEFINED(SAM4S4C) \
- )
-
-#define SAM4S8 ( \
- SAM_PART_IS_DEFINED(SAM4S8B) || \
- SAM_PART_IS_DEFINED(SAM4S8C) \
- )
-
-#define SAM4S16 ( \
- SAM_PART_IS_DEFINED(SAM4S16B) || \
- SAM_PART_IS_DEFINED(SAM4S16C) \
- )
-
-#define SAM4SA16 ( \
- SAM_PART_IS_DEFINED(SAM4SA16B) || \
- SAM_PART_IS_DEFINED(SAM4SA16C) \
- )
-
-#define SAM4SD16 ( \
- SAM_PART_IS_DEFINED(SAM4SD16B) || \
- SAM_PART_IS_DEFINED(SAM4SD16C) \
- )
-
-#define SAM4SD32 ( \
- SAM_PART_IS_DEFINED(SAM4SD32B) || \
- SAM_PART_IS_DEFINED(SAM4SD32C) \
- )
-/** @} */
-
-/**
- * \name SAM4L series
- * @{
- */
-#define SAM4LS ( \
- SAM_PART_IS_DEFINED(SAM4LS2A) || \
- SAM_PART_IS_DEFINED(SAM4LS2B) || \
- SAM_PART_IS_DEFINED(SAM4LS2C) || \
- SAM_PART_IS_DEFINED(SAM4LS4A) || \
- SAM_PART_IS_DEFINED(SAM4LS4B) || \
- SAM_PART_IS_DEFINED(SAM4LS4C) || \
- SAM_PART_IS_DEFINED(SAM4LS8A) || \
- SAM_PART_IS_DEFINED(SAM4LS8B) || \
- SAM_PART_IS_DEFINED(SAM4LS8C) \
- )
-
-#define SAM4LC ( \
- SAM_PART_IS_DEFINED(SAM4LC2A) || \
- SAM_PART_IS_DEFINED(SAM4LC2B) || \
- SAM_PART_IS_DEFINED(SAM4LC2C) || \
- SAM_PART_IS_DEFINED(SAM4LC4A) || \
- SAM_PART_IS_DEFINED(SAM4LC4B) || \
- SAM_PART_IS_DEFINED(SAM4LC4C) || \
- SAM_PART_IS_DEFINED(SAM4LC8A) || \
- SAM_PART_IS_DEFINED(SAM4LC8B) || \
- SAM_PART_IS_DEFINED(SAM4LC8C) \
- )
-/** @} */
-
-/**
- * \name SAMD20 series
- * @{
- */
-#define SAMD20J ( \
- SAM_PART_IS_DEFINED(SAMD20J14) || \
- SAM_PART_IS_DEFINED(SAMD20J15) || \
- SAM_PART_IS_DEFINED(SAMD20J16) || \
- SAM_PART_IS_DEFINED(SAMD20J17) || \
- SAM_PART_IS_DEFINED(SAMD20J18) \
- )
-
-#define SAMD20G ( \
- SAM_PART_IS_DEFINED(SAMD20G14) || \
- SAM_PART_IS_DEFINED(SAMD20G15) || \
- SAM_PART_IS_DEFINED(SAMD20G16) || \
- SAM_PART_IS_DEFINED(SAMD20G17) || \
- SAM_PART_IS_DEFINED(SAMD20G17U) || \
- SAM_PART_IS_DEFINED(SAMD20G18) || \
- SAM_PART_IS_DEFINED(SAMD20G18U) \
- )
-
-#define SAMD20E ( \
- SAM_PART_IS_DEFINED(SAMD20E14) || \
- SAM_PART_IS_DEFINED(SAMD20E15) || \
- SAM_PART_IS_DEFINED(SAMD20E16) || \
- SAM_PART_IS_DEFINED(SAMD20E17) || \
- SAM_PART_IS_DEFINED(SAMD20E18) \
- )
-/** @} */
-
-/**
- * \name SAMD21 series
- * @{
- */
-#define SAMD21J ( \
- SAM_PART_IS_DEFINED(SAMD21J15A) || \
- SAM_PART_IS_DEFINED(SAMD21J16A) || \
- SAM_PART_IS_DEFINED(SAMD21J17A) || \
- SAM_PART_IS_DEFINED(SAMD21J18A) || \
- SAM_PART_IS_DEFINED(SAMD21J15B) || \
- SAM_PART_IS_DEFINED(SAMD21J16B) \
- )
-
-#define SAMD21G ( \
- SAM_PART_IS_DEFINED(SAMD21G15A) || \
- SAM_PART_IS_DEFINED(SAMD21G16A) || \
- SAM_PART_IS_DEFINED(SAMD21G17A) || \
- SAM_PART_IS_DEFINED(SAMD21G17AU) || \
- SAM_PART_IS_DEFINED(SAMD21G18A) || \
- SAM_PART_IS_DEFINED(SAMD21G18AU) || \
- SAM_PART_IS_DEFINED(SAMD21G15B) || \
- SAM_PART_IS_DEFINED(SAMD21G16B) || \
- SAM_PART_IS_DEFINED(SAMD21G15L) || \
- SAM_PART_IS_DEFINED(SAMD21G16L) \
- )
-
-#define SAMD21GXXL ( \
- SAM_PART_IS_DEFINED(SAMD21G15L) || \
- SAM_PART_IS_DEFINED(SAMD21G16L) \
- )
-
-#define SAMD21E ( \
- SAM_PART_IS_DEFINED(SAMD21E15A) || \
- SAM_PART_IS_DEFINED(SAMD21E16A) || \
- SAM_PART_IS_DEFINED(SAMD21E17A) || \
- SAM_PART_IS_DEFINED(SAMD21E18A) || \
- SAM_PART_IS_DEFINED(SAMD21E15B) || \
- SAM_PART_IS_DEFINED(SAMD21E15BU) || \
- SAM_PART_IS_DEFINED(SAMD21E16B) || \
- SAM_PART_IS_DEFINED(SAMD21E16BU) || \
- SAM_PART_IS_DEFINED(SAMD21E15L) || \
- SAM_PART_IS_DEFINED(SAMD21E16L) \
- )
-
-#define SAMD21EXXL ( \
- SAM_PART_IS_DEFINED(SAMD21E15L) || \
- SAM_PART_IS_DEFINED(SAMD21E16L) \
- )
-
-/** @} */
-
-/**
- * \name SAMR21 series
- * @{
- */
-#define SAMR21G ( \
- SAM_PART_IS_DEFINED(SAMR21G16A) || \
- SAM_PART_IS_DEFINED(SAMR21G17A) || \
- SAM_PART_IS_DEFINED(SAMR21G18A) \
- )
-
-#define SAMR21E ( \
- SAM_PART_IS_DEFINED(SAMR21E16A) || \
- SAM_PART_IS_DEFINED(SAMR21E17A) || \
- SAM_PART_IS_DEFINED(SAMR21E18A) || \
- SAM_PART_IS_DEFINED(SAMR21E19A) \
- )
-/** @} */
-
-/**
- * \name SAMR30 series
- * @{
- */
-#define SAMR30G ( \
- SAM_PART_IS_DEFINED(SAMR30G18A) \
- )
-
-#define SAMR30E ( \
- SAM_PART_IS_DEFINED(SAMR30E18A) \
- )
-/** @} */
-
-/**
- * \name SAMB11 series
- * @{
- */
-#define SAMB11G ( \
- SAM_PART_IS_DEFINED(SAMB11G18A) || \
- SAM_PART_IS_DEFINED(SAMB11ZR) \
- )
-#define BTLC1000 ( \
- SAM_PART_IS_DEFINED(BTLC1000WLCSP) \
- )
-
-/** @} */
-
-/**
- * \name SAMD09 series
- * @{
- */
-#define SAMD09C ( \
- SAM_PART_IS_DEFINED(SAMD09C13A) \
- )
-
-#define SAMD09D ( \
- SAM_PART_IS_DEFINED(SAMD09D14A) \
- )
-/** @} */
-
-/**
- * \name SAMD10 series
- * @{
- */
-#define SAMD10C ( \
- SAM_PART_IS_DEFINED(SAMD10C12A) || \
- SAM_PART_IS_DEFINED(SAMD10C13A) || \
- SAM_PART_IS_DEFINED(SAMD10C14A) \
- )
-
-#define SAMD10DS ( \
- SAM_PART_IS_DEFINED(SAMD10D12AS) || \
- SAM_PART_IS_DEFINED(SAMD10D13AS) || \
- SAM_PART_IS_DEFINED(SAMD10D14AS) \
- )
-
-#define SAMD10DM ( \
- SAM_PART_IS_DEFINED(SAMD10D12AM) || \
- SAM_PART_IS_DEFINED(SAMD10D13AM) || \
- SAM_PART_IS_DEFINED(SAMD10D14AM) \
- )
-
-#define SAMD10DU ( \
- SAM_PART_IS_DEFINED(SAMD10D14AU) \
- )
-/** @} */
-
-/**
- * \name SAMD11 series
- * @{
- */
-#define SAMD11C ( \
- SAM_PART_IS_DEFINED(SAMD11C14A) \
- )
-
-#define SAMD11DS ( \
- SAM_PART_IS_DEFINED(SAMD11D14AS) \
- )
-
-#define SAMD11DM ( \
- SAM_PART_IS_DEFINED(SAMD11D14AM) \
- )
-
-#define SAMD11DU ( \
- SAM_PART_IS_DEFINED(SAMD11D14AU) \
- )
-/** @} */
-
-/**
- * \name SAML21 series
- * @{
- */
-#define SAML21E ( \
- SAM_PART_IS_DEFINED(SAML21E18A) || \
- SAM_PART_IS_DEFINED(SAML21E15B) || \
- SAM_PART_IS_DEFINED(SAML21E16B) || \
- SAM_PART_IS_DEFINED(SAML21E17B) || \
- SAM_PART_IS_DEFINED(SAML21E18B) \
- )
-
-#define SAML21G ( \
- SAM_PART_IS_DEFINED(SAML21G18A) || \
- SAM_PART_IS_DEFINED(SAML21G16B) || \
- SAM_PART_IS_DEFINED(SAML21G17B) || \
- SAM_PART_IS_DEFINED(SAML21G18B) \
- )
-
-#define SAML21J ( \
- SAM_PART_IS_DEFINED(SAML21J18A) || \
- SAM_PART_IS_DEFINED(SAML21J16B) || \
- SAM_PART_IS_DEFINED(SAML21J17B) || \
- SAM_PART_IS_DEFINED(SAML21J18B) \
- )
-
-/* Group for SAML21 A variant: SAML21[E/G/J][18]A */
-#define SAML21XXXA ( \
- SAM_PART_IS_DEFINED(SAML21E18A) || \
- SAM_PART_IS_DEFINED(SAML21G18A) || \
- SAM_PART_IS_DEFINED(SAML21J18A) \
- )
-
-/* Group for SAML21 B variant: SAML21[E/G/J][15/16/1718]B */
-#define SAML21XXXB ( \
- SAM_PART_IS_DEFINED(SAML21E15B) || \
- SAM_PART_IS_DEFINED(SAML21E16B) || \
- SAM_PART_IS_DEFINED(SAML21E17B) || \
- SAM_PART_IS_DEFINED(SAML21E18B) || \
- SAM_PART_IS_DEFINED(SAML21G16B) || \
- SAM_PART_IS_DEFINED(SAML21G17B) || \
- SAM_PART_IS_DEFINED(SAML21G18B) || \
- SAM_PART_IS_DEFINED(SAML21J16B) || \
- SAM_PART_IS_DEFINED(SAML21J17B) || \
- SAM_PART_IS_DEFINED(SAML21J18B) \
- )
-
-/** @} */
-
-/**
- * \name SAML22 series
- * @{
- */
-#define SAML22N ( \
- SAM_PART_IS_DEFINED(SAML22N16A) || \
- SAM_PART_IS_DEFINED(SAML22N17A) || \
- SAM_PART_IS_DEFINED(SAML22N18A) \
- )
-
-#define SAML22G ( \
- SAM_PART_IS_DEFINED(SAML22G16A) || \
- SAM_PART_IS_DEFINED(SAML22G17A) || \
- SAM_PART_IS_DEFINED(SAML22G18A) \
- )
-
-#define SAML22J ( \
- SAM_PART_IS_DEFINED(SAML22J16A) || \
- SAM_PART_IS_DEFINED(SAML22J17A) || \
- SAM_PART_IS_DEFINED(SAML22J18A) \
- )
-/** @} */
-
-/**
- * \name SAMDA1 series
- * @{
- */
-#define SAMDA1J ( \
- SAM_PART_IS_DEFINED(SAMDA1J14A) || \
- SAM_PART_IS_DEFINED(SAMDA1J15B) || \
- SAM_PART_IS_DEFINED(SAMDA1J15A) || \
- SAM_PART_IS_DEFINED(SAMDA1J15B) || \
- SAM_PART_IS_DEFINED(SAMDA1J16A) || \
- SAM_PART_IS_DEFINED(SAMDA1J16B) \
- )
-
-#define SAMDA1G ( \
- SAM_PART_IS_DEFINED(SAMDA1G14A) || \
- SAM_PART_IS_DEFINED(SAMDA1G14B) || \
- SAM_PART_IS_DEFINED(SAMDA1G15A) || \
- SAM_PART_IS_DEFINED(SAMDA1G15B) || \
- SAM_PART_IS_DEFINED(SAMDA1G16A) || \
- SAM_PART_IS_DEFINED(SAMDA1G16B) \
- )
-
-#define SAMDA1E ( \
- SAM_PART_IS_DEFINED(SAMDA1E14A) || \
- SAM_PART_IS_DEFINED(SAMDA1E14B) || \
- SAM_PART_IS_DEFINED(SAMDA1E15A) || \
- SAM_PART_IS_DEFINED(SAMDA1E15B) || \
- SAM_PART_IS_DEFINED(SAMDA1E16A) || \
- SAM_PART_IS_DEFINED(SAMDA1E16B) \
- )
-/** @} */
-
-/**
- * \name SAMHA1 series
- * @{
- */
-#define SAMHA1G ( \
- SAM_PART_IS_DEFINED(SAMHA1G14A) || \
- SAM_PART_IS_DEFINED(SAMHA1G15A) || \
- SAM_PART_IS_DEFINED(SAMHA1G16A) \
- )
-
-/** @} */
-
-/**
- * \name SAMC20 series
- * @{
- */
-#define SAMC20E ( \
- SAM_PART_IS_DEFINED(SAMC20E15A) || \
- SAM_PART_IS_DEFINED(SAMC20E16A) || \
- SAM_PART_IS_DEFINED(SAMC20E17A) || \
- SAM_PART_IS_DEFINED(SAMC20E18A) \
- )
-
-#define SAMC20G ( \
- SAM_PART_IS_DEFINED(SAMC20G15A) || \
- SAM_PART_IS_DEFINED(SAMC20G16A) || \
- SAM_PART_IS_DEFINED(SAMC20G17A) || \
- SAM_PART_IS_DEFINED(SAMC20G18A) \
- )
-
-#define SAMC20J ( \
- SAM_PART_IS_DEFINED(SAMC20J15A) || \
- SAM_PART_IS_DEFINED(SAMC20J16A) || \
- SAM_PART_IS_DEFINED(SAMC20J17A) || \
- SAM_PART_IS_DEFINED(SAMC20J18A) \
- )
-/** @} */
-
-/**
- * \name SAMC21 series
- * @{
- */
-#define SAMC21E ( \
- SAM_PART_IS_DEFINED(SAMC21E15A) || \
- SAM_PART_IS_DEFINED(SAMC21E16A) || \
- SAM_PART_IS_DEFINED(SAMC21E17A) || \
- SAM_PART_IS_DEFINED(SAMC21E18A) \
- )
-
-#define SAMC21G ( \
- SAM_PART_IS_DEFINED(SAMC21G15A) || \
- SAM_PART_IS_DEFINED(SAMC21G16A) || \
- SAM_PART_IS_DEFINED(SAMC21G17A) || \
- SAM_PART_IS_DEFINED(SAMC21G18A) \
- )
-
-#define SAMC21J ( \
- SAM_PART_IS_DEFINED(SAMC21J15A) || \
- SAM_PART_IS_DEFINED(SAMC21J16A) || \
- SAM_PART_IS_DEFINED(SAMC21J17A) || \
- SAM_PART_IS_DEFINED(SAMC21J18A) \
- )
-/** @} */
-
-/**
- * \name SAM4E series
- * @{
- */
-#define SAM4E8 ( \
- SAM_PART_IS_DEFINED(SAM4E8C) || \
- SAM_PART_IS_DEFINED(SAM4E8CB) || \
- SAM_PART_IS_DEFINED(SAM4E8E) \
- )
-
-#define SAM4E16 ( \
- SAM_PART_IS_DEFINED(SAM4E16C) || \
- SAM_PART_IS_DEFINED(SAM4E16CB) || \
- SAM_PART_IS_DEFINED(SAM4E16E) \
- )
-/** @} */
-
-/**
- * \name SAM4N series
- * @{
- */
-#define SAM4N8 ( \
- SAM_PART_IS_DEFINED(SAM4N8A) || \
- SAM_PART_IS_DEFINED(SAM4N8B) || \
- SAM_PART_IS_DEFINED(SAM4N8C) \
- )
-
-#define SAM4N16 ( \
- SAM_PART_IS_DEFINED(SAM4N16B) || \
- SAM_PART_IS_DEFINED(SAM4N16C) \
- )
-/** @} */
-
-/**
- * \name SAM4C series
- * @{
- */
-#define SAM4C4_0 ( \
- SAM_PART_IS_DEFINED(SAM4C4C_0) \
- )
-
-#define SAM4C4_1 ( \
- SAM_PART_IS_DEFINED(SAM4C4C_1) \
- )
-
-#define SAM4C4 (SAM4C4_0 || SAM4C4_1)
-
-#define SAM4C8_0 ( \
- SAM_PART_IS_DEFINED(SAM4C8C_0) \
- )
-
-#define SAM4C8_1 ( \
- SAM_PART_IS_DEFINED(SAM4C8C_1) \
- )
-
-#define SAM4C8 (SAM4C8_0 || SAM4C8_1)
-
-#define SAM4C16_0 ( \
- SAM_PART_IS_DEFINED(SAM4C16C_0) \
- )
-
-#define SAM4C16_1 ( \
- SAM_PART_IS_DEFINED(SAM4C16C_1) \
- )
-
-#define SAM4C16 (SAM4C16_0 || SAM4C16_1)
-
-#define SAM4C32_0 ( \
- SAM_PART_IS_DEFINED(SAM4C32C_0) ||\
- SAM_PART_IS_DEFINED(SAM4C32E_0) \
- )
-
-#define SAM4C32_1 ( \
- SAM_PART_IS_DEFINED(SAM4C32C_1) ||\
- SAM_PART_IS_DEFINED(SAM4C32E_1) \
- )
-
-
-#define SAM4C32 (SAM4C32_0 || SAM4C32_1)
-
-/** @} */
-
-/**
- * \name SAM4CM series
- * @{
- */
-#define SAM4CMP8_0 ( \
- SAM_PART_IS_DEFINED(SAM4CMP8C_0) \
- )
-
-#define SAM4CMP8_1 ( \
- SAM_PART_IS_DEFINED(SAM4CMP8C_1) \
- )
-
-#define SAM4CMP8 (SAM4CMP8_0 || SAM4CMP8_1)
-
-#define SAM4CMP16_0 ( \
- SAM_PART_IS_DEFINED(SAM4CMP16C_0) \
- )
-
-#define SAM4CMP16_1 ( \
- SAM_PART_IS_DEFINED(SAM4CMP16C_1) \
- )
-
-#define SAM4CMP16 (SAM4CMP16_0 || SAM4CMP16_1)
-
-#define SAM4CMP32_0 ( \
- SAM_PART_IS_DEFINED(SAM4CMP32C_0) \
- )
-
-#define SAM4CMP32_1 ( \
- SAM_PART_IS_DEFINED(SAM4CMP32C_1) \
- )
-
-#define SAM4CMP32 (SAM4CMP32_0 || SAM4CMP32_1)
-
-#define SAM4CMS4_0 ( \
- SAM_PART_IS_DEFINED(SAM4CMS4C_0) \
- )
-
-#define SAM4CMS4_1 ( \
- SAM_PART_IS_DEFINED(SAM4CMS4C_1) \
- )
-
-#define SAM4CMS4 (SAM4CMS4_0 || SAM4CMS4_1)
-
-#define SAM4CMS8_0 ( \
- SAM_PART_IS_DEFINED(SAM4CMS8C_0) \
- )
-
-#define SAM4CMS8_1 ( \
- SAM_PART_IS_DEFINED(SAM4CMS8C_1) \
- )
-
-#define SAM4CMS8 (SAM4CMS8_0 || SAM4CMS8_1)
-
-#define SAM4CMS16_0 ( \
- SAM_PART_IS_DEFINED(SAM4CMS16C_0) \
- )
-
-#define SAM4CMS16_1 ( \
- SAM_PART_IS_DEFINED(SAM4CMS16C_1) \
- )
-
-#define SAM4CMS16 (SAM4CMS16_0 || SAM4CMS16_1)
-
-#define SAM4CMS32_0 ( \
- SAM_PART_IS_DEFINED(SAM4CMS32C_0) \
- )
-
-#define SAM4CMS32_1 ( \
- SAM_PART_IS_DEFINED(SAM4CMS32C_1) \
- )
-
-#define SAM4CMS32 (SAM4CMS32_0 || SAM4CMS32_1)
-
-/** @} */
-
-/**
- * \name SAM4CP series
- * @{
- */
-#define SAM4CP16_0 ( \
- SAM_PART_IS_DEFINED(SAM4CP16B_0) \
- )
-
-#define SAM4CP16_1 ( \
- SAM_PART_IS_DEFINED(SAM4CP16B_1) \
- )
-
-#define SAM4CP16 (SAM4CP16_0 || SAM4CP16_1)
-/** @} */
-
-/**
- * \name SAMG series
- * @{
- */
-#define SAMG51 ( \
- SAM_PART_IS_DEFINED(SAMG51G18) \
- )
-
-#define SAMG53 ( \
- SAM_PART_IS_DEFINED(SAMG53G19) ||\
- SAM_PART_IS_DEFINED(SAMG53N19) \
- )
-
-#define SAMG54 ( \
- SAM_PART_IS_DEFINED(SAMG54G19) ||\
- SAM_PART_IS_DEFINED(SAMG54J19) ||\
- SAM_PART_IS_DEFINED(SAMG54N19) \
- )
-
-#define SAMG55 ( \
- SAM_PART_IS_DEFINED(SAMG55G18) ||\
- SAM_PART_IS_DEFINED(SAMG55G19) ||\
- SAM_PART_IS_DEFINED(SAMG55J18) ||\
- SAM_PART_IS_DEFINED(SAMG55J19) ||\
- SAM_PART_IS_DEFINED(SAMG55N19) \
- )
-/** @} */
-
-/**
- * \name SAMV71 series
- * @{
- */
-#define SAMV71J ( \
- SAM_PART_IS_DEFINED(SAMV71J19) || \
- SAM_PART_IS_DEFINED(SAMV71J20) || \
- SAM_PART_IS_DEFINED(SAMV71J21) \
- )
-
-#define SAMV71N ( \
- SAM_PART_IS_DEFINED(SAMV71N19) || \
- SAM_PART_IS_DEFINED(SAMV71N20) || \
- SAM_PART_IS_DEFINED(SAMV71N21) \
- )
-
-#define SAMV71Q ( \
- SAM_PART_IS_DEFINED(SAMV71Q19) || \
- SAM_PART_IS_DEFINED(SAMV71Q20) || \
- SAM_PART_IS_DEFINED(SAMV71Q21) \
- )
-/** @} */
-
-/**
- * \name SAMV70 series
- * @{
- */
-#define SAMV70J ( \
- SAM_PART_IS_DEFINED(SAMV70J19) || \
- SAM_PART_IS_DEFINED(SAMV70J20) \
- )
-
-#define SAMV70N ( \
- SAM_PART_IS_DEFINED(SAMV70N19) || \
- SAM_PART_IS_DEFINED(SAMV70N20) \
- )
-
-#define SAMV70Q ( \
- SAM_PART_IS_DEFINED(SAMV70Q19) || \
- SAM_PART_IS_DEFINED(SAMV70Q20) \
- )
-/** @} */
-
-/**
- * \name SAMS70 series
- * @{
- */
-#define SAMS70J ( \
- SAM_PART_IS_DEFINED(SAMS70J19) || \
- SAM_PART_IS_DEFINED(SAMS70J20) || \
- SAM_PART_IS_DEFINED(SAMS70J21) \
- )
-
-#define SAMS70N ( \
- SAM_PART_IS_DEFINED(SAMS70N19) || \
- SAM_PART_IS_DEFINED(SAMS70N20) || \
- SAM_PART_IS_DEFINED(SAMS70N21) \
- )
-
-#define SAMS70Q ( \
- SAM_PART_IS_DEFINED(SAMS70Q19) || \
- SAM_PART_IS_DEFINED(SAMS70Q20) || \
- SAM_PART_IS_DEFINED(SAMS70Q21) \
- )
-/** @} */
-
-/**
- * \name SAME70 series
- * @{
- */
-#define SAME70J ( \
- SAM_PART_IS_DEFINED(SAME70J19) || \
- SAM_PART_IS_DEFINED(SAME70J20) || \
- SAM_PART_IS_DEFINED(SAME70J21) \
- )
-
-#define SAME70N ( \
- SAM_PART_IS_DEFINED(SAME70N19) || \
- SAM_PART_IS_DEFINED(SAME70N20) || \
- SAM_PART_IS_DEFINED(SAME70N21) \
- )
-
-#define SAME70Q ( \
- SAM_PART_IS_DEFINED(SAME70Q19) || \
- SAM_PART_IS_DEFINED(SAME70Q20) || \
- SAM_PART_IS_DEFINED(SAME70Q21) \
- )
-/** @} */
-
-/**
- * \name SAM families
- * @{
- */
-/** SAM3S Family */
-#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8)
-
-/** SAM3U Family */
-#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4)
-
-/** SAM3N Family */
-#define SAM3N (SAM3N00 || SAM3N0 || SAM3N1 || SAM3N2 || SAM3N4)
-
-/** SAM3XA Family */
-#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8)
-
-/** SAM4S Family */
-#define SAM4S (SAM4S2 || SAM4S4 || SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32)
-
-/** SAM4L Family */
-#define SAM4L (SAM4LS || SAM4LC)
-
-/** SAMD20 Family */
-#define SAMD20 (SAMD20J || SAMD20G || SAMD20E)
-
-/** SAMD21 Family */
-#define SAMD21 (SAMD21J || SAMD21G || SAMD21E)
-
-/** SAMD09 Family */
-#define SAMD09 (SAMD09C || SAMD09D)
-
-/** SAMD10 Family */
-#define SAMD10 (SAMD10C || SAMD10DS || SAMD10DM || SAMD10DU)
-
-/** SAMD11 Family */
-#define SAMD11 (SAMD11C || SAMD11DS || SAMD11DM || SAMD11DU)
-
-/** SAMDA1 Family */
-#define SAMDA1 (SAMDA1J || SAMDA1G || SAMDA1E)
-
-/** SAMHA1 Family */
-#define SAMHA1 (SAMHA1G)
-
-/** SAMD Family */
-#define SAMD (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAMDA1)
-
-/** SAMR21 Family */
-#define SAMR21 (SAMR21G || SAMR21E)
-
-/** SAMR30 Family */
-#define SAMR30 (SAMR30G || SAMR30E)
-
-/** SAMB11 Family */
-#define SAMB11 (SAMB11G || BTLC1000)
-
-/** SAML21 Family */
-#define SAML21 (SAML21J || SAML21G || SAML21E)
-
-/** SAML22 Family */
-#define SAML22 (SAML22J || SAML22G || SAML22N)
-/** SAMC20 Family */
-#define SAMC20 (SAMC20J || SAMC20G || SAMC20E)
-
-/** SAMC21 Family */
-#define SAMC21 (SAMC21J || SAMC21G || SAMC21E)
-
-/** SAM4E Family */
-#define SAM4E (SAM4E8 || SAM4E16)
-
-/** SAM4N Family */
-#define SAM4N (SAM4N8 || SAM4N16)
-
-/** SAM4C Family */
-#define SAM4C_0 (SAM4C4_0 || SAM4C8_0 || SAM4C16_0 || SAM4C32_0)
-#define SAM4C_1 (SAM4C4_1 || SAM4C8_1 || SAM4C16_1 || SAM4C32_1)
-#define SAM4C (SAM4C4 || SAM4C8 || SAM4C16 || SAM4C32)
-
-/** SAM4CM Family */
-#define SAM4CM_0 (SAM4CMP8_0 || SAM4CMP16_0 || SAM4CMP32_0 || \
- SAM4CMS4_0 || SAM4CMS8_0 || SAM4CMS16_0 || SAM4CMS32_0)
-#define SAM4CM_1 (SAM4CMP8_1 || SAM4CMP16_1 || SAM4CMP32_1 || \
- SAM4CMS4_1 || SAM4CMS8_1 || SAM4CMS16_1 || SAM4CMS32_1)
-#define SAM4CM (SAM4CMP8 || SAM4CMP16 || SAM4CMP32 || \
- SAM4CMS4 || SAM4CMS8 || SAM4CMS16 || SAM4CMS32)
-
-/** SAM4CP Family */
-#define SAM4CP_0 (SAM4CP16_0)
-#define SAM4CP_1 (SAM4CP16_1)
-#define SAM4CP (SAM4CP16)
-
-/** SAMG Family */
-#define SAMG (SAMG51 || SAMG53 || SAMG54 || SAMG55)
-
-/** SAMB Family */
-#define SAMB (SAMB11)
-
-/** SAMV71 Family */
-#define SAMV71 (SAMV71J || SAMV71N || SAMV71Q)
-
-/** SAMV70 Family */
-#define SAMV70 (SAMV70J || SAMV70N || SAMV70Q)
-
-/** SAME70 Family */
-#define SAME70 (SAME70J || SAME70N || SAME70Q)
-
-/** SAMS70 Family */
-#define SAMS70 (SAMS70J || SAMS70N || SAMS70Q)
-
-/** SAM0 product line (cortex-m0+) */
-#define SAM0 (SAMD20 || SAMD21 || SAMR21 || SAMD10 || SAMD11 || SAML21 ||\
- SAMDA1 || SAMC20 || SAMC21 || SAML22 || SAMD09 || SAMR30 || SAMHA1)
-
-/** @} */
-
-/** SAM product line */
-#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || \
- SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAME70 || SAMS70)
-
-/** @} */
-
-/** @} */
-
-/** @} */
-
-#endif /* ATMEL_PARTS_H */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/drivers/pmc/pmc.c b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/drivers/pmc/pmc.c
deleted file mode 100644
index bb330e4..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/drivers/pmc/pmc.c
+++ /dev/null
@@ -1,1657 +0,0 @@
-/**
- * \file
- *
- * \brief Power Management Controller (PMC) driver for SAM.
- *
- * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include "pmc.h"
-
-#if (SAM3N)
-# define MAX_PERIPH_ID 31
-#elif (SAM3XA)
-# define MAX_PERIPH_ID 44
-#elif (SAM3U)
-# define MAX_PERIPH_ID 29
-#elif (SAM3S || SAM4S)
-# define MAX_PERIPH_ID 34
-#elif (SAM4E)
-# define MAX_PERIPH_ID 47
-#elif (SAMV71)
-# define MAX_PERIPH_ID 63
-#elif (SAMV70)
-# define MAX_PERIPH_ID 63
-#elif (SAME70)
-# define MAX_PERIPH_ID 63
-#elif (SAMS70)
-# define MAX_PERIPH_ID 63
-#elif (SAM4N)
-# define MAX_PERIPH_ID 31
-#elif (SAM4C || SAM4CM || SAM4CP)
-# define MAX_PERIPH_ID 43
-#elif (SAMG51)
-# define MAX_PERIPH_ID 47
-#elif (SAMG53)
-# define MAX_PERIPH_ID 47
-#elif (SAMG54)
-# define MAX_PERIPH_ID 47
-#elif (SAMG55)
-# define MAX_PERIPH_ID 50
-#endif
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-/**
- * \defgroup sam_drivers_pmc_group Power Management Controller (PMC)
- *
- * \par Purpose
- *
- * The Power Management Controller (PMC) optimizes power consumption by
- * controlling all system and user peripheral clocks. The PMC enables/disables
- * the clock inputs to many of the peripherals and the Cortex-M Processor.
- *
- * @{
- */
-
-/**
- * \brief Set the prescaler of the MCK.
- *
- * \param ul_pres Prescaler value.
- */
-void pmc_mck_set_prescaler(uint32_t ul_pres)
-{
- PMC->PMC_MCKR =
- (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-}
-
-#if SAMV71 || SAMV70 || SAME70 || SAMS70
-/**
- * \brief Set the division of the MCK.
- *
- * \param ul_div Division value.
- */
-void pmc_mck_set_division(uint32_t ul_div)
-{
- switch (ul_div) {
- case 1:
- ul_div = PMC_MCKR_MDIV_EQ_PCK;
- break;
- case 2:
- ul_div = PMC_MCKR_MDIV_PCK_DIV2;
- break;
- case 3:
- ul_div = PMC_MCKR_MDIV_PCK_DIV3;
- break;
- case 4:
- ul_div = PMC_MCKR_MDIV_PCK_DIV4;
- break;
- default:
- ul_div = PMC_MCKR_MDIV_EQ_PCK;
- break;
- }
- PMC->PMC_MCKR =
- (PMC->PMC_MCKR & (~PMC_MCKR_MDIV_Msk)) | ul_div;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-}
-#endif
-
-/**
- * \brief Set the source of the MCK.
- *
- * \param ul_source Source selection value.
- */
-void pmc_mck_set_source(uint32_t ul_source)
-{
- PMC->PMC_MCKR =
- (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) | ul_source;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-}
-
-/**
- * \brief Switch master clock source selection to slow clock.
- *
- * \param ul_pres Processor clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
- PMC_MCKR_CSS_SLOW_CLK;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-
-/**
- * \brief Switch master clock source selection to main clock.
- *
- * \param ul_pres Processor clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
- PMC_MCKR_CSS_MAIN_CLK;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-
-/**
- * \brief Switch master clock source selection to PLLA clock.
- *
- * \param ul_pres Processor clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
- PMC_MCKR_CSS_PLLA_CLK;
-
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
-/**
- * \brief Switch master clock source selection to PLLB clock.
- *
- * \param ul_pres Processor clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
- PMC_MCKR_CSS_PLLB_CLK;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-#endif
-
-#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Switch master clock source selection to UPLL clock.
- *
- * \param ul_pres Processor clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_PRES_Msk)) | ul_pres;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & (~PMC_MCKR_CSS_Msk)) |
- PMC_MCKR_CSS_UPLL_CLK;
- for (ul_timeout = PMC_TIMEOUT; !(PMC->PMC_SR & PMC_SR_MCKRDY);
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-#endif
-
-/**
- * \brief Switch slow clock source selection to external 32k (Xtal or Bypass).
- *
- * \note Switching SCLK back to 32krc is only possible by shutting down the
- * VDDIO power supply.
- *
- * \param ul_bypass 0 for Xtal, 1 for bypass.
- */
-void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass)
-{
- /* Set Bypass mode if required */
- if (ul_bypass == 1) {
- SUPC->SUPC_MR |= SUPC_MR_KEY_PASSWD |
- SUPC_MR_OSCBYPASS;
- }
-
- SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL;
-}
-
-/**
- * \brief Check if the external 32k Xtal is ready.
- *
- * \retval 1 External 32k Xtal is ready.
- * \retval 0 External 32k Xtal is not ready.
- */
-uint32_t pmc_osc_is_ready_32kxtal(void)
-{
- return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL)
- && (PMC->PMC_SR & PMC_SR_OSCSELS));
-}
-
-/**
- * \brief Switch main clock source selection to internal fast RC.
- *
- * \param ul_moscrcf Fast RC oscillator(4/8/12Mhz).
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- * \retval 2 Invalid frequency.
- */
-void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf)
-{
- /* Enable Fast RC oscillator but DO NOT switch to RC now */
- PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
-
- /* Wait the Fast RC to stabilize */
- while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
-
- /* Change Fast RC oscillator frequency */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
- CKGR_MOR_KEY_PASSWD | ul_moscrcf;
-
- /* Wait the Fast RC to stabilize */
- while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
-
- /* Switch to Fast RC */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) |
- CKGR_MOR_KEY_PASSWD;
-}
-
-/**
- * \brief Enable fast RC oscillator.
- *
- * \param ul_rc Fast RC oscillator(4/8/12Mhz).
- */
-void pmc_osc_enable_fastrc(uint32_t ul_rc)
-{
- /* Enable Fast RC oscillator but DO NOT switch to RC */
- PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
- /* Wait the Fast RC to stabilize */
- while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
-
- /* Change Fast RC oscillator frequency */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) |
- CKGR_MOR_KEY_PASSWD | ul_rc;
- /* Wait the Fast RC to stabilize */
- while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
-}
-
-/**
- * \brief Disable the internal fast RC.
- */
-void pmc_osc_disable_fastrc(void)
-{
- /* Disable Fast RC oscillator */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN &
- ~CKGR_MOR_MOSCRCF_Msk)
- | CKGR_MOR_KEY_PASSWD;
-}
-
-/**
- * \brief Check if the main fastrc is ready.
- *
- * \retval 0 Xtal is not ready, otherwise ready.
- */
-uint32_t pmc_osc_is_ready_fastrc(void)
-{
- return (PMC->PMC_SR & PMC_SR_MOSCRCS);
-}
-
-/**
- * \brief Enable main XTAL oscillator.
- *
- * \param ul_xtal_startup_time Xtal start-up time, in number of slow clocks.
- */
-void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time)
-{
- uint32_t mor = PMC->CKGR_MOR;
- mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
- mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN |
- CKGR_MOR_MOSCXTST(ul_xtal_startup_time);
- PMC->CKGR_MOR = mor;
- /* Wait the main Xtal to stabilize */
- while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
-}
-
-/**
- * \brief Bypass main XTAL.
- */
-void pmc_osc_bypass_main_xtal(void)
-{
- uint32_t mor = PMC->CKGR_MOR;
- mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
- mor |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY;
- /* Enable Crystal oscillator but DO NOT switch now. Keep MOSCSEL to 0 */
- PMC->CKGR_MOR = mor;
- /* The MOSCXTS in PMC_SR is automatically set */
-}
-
-/**
- * \brief Disable the main Xtal.
- */
-void pmc_osc_disable_main_xtal(void)
-{
- uint32_t mor = PMC->CKGR_MOR;
- mor &= ~(CKGR_MOR_MOSCXTBY|CKGR_MOR_MOSCXTEN);
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
-}
-
-/**
- * \brief Check if the main crystal is bypassed.
- *
- * \retval 0 Xtal is bypassed, otherwise not.
- */
-uint32_t pmc_osc_is_bypassed_main_xtal(void)
-{
- return (PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY);
-}
-
-/**
- * \brief Check if the main crystal is ready.
- *
- * \note If main crystal is bypassed, it's always ready.
- *
- * \retval 0 main crystal is not ready, otherwise ready.
- */
-uint32_t pmc_osc_is_ready_main_xtal(void)
-{
- return (PMC->PMC_SR & PMC_SR_MOSCXTS);
-}
-
-/**
- * \brief Switch main clock source selection to external Xtal/Bypass.
- *
- * \note The function may switch MCK to SCLK if MCK source is MAINCK to avoid
- * any system crash.
- *
- * \note If used in Xtal mode, the Xtal is automatically enabled.
- *
- * \param ul_bypass 0 for Xtal, 1 for bypass.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-void pmc_switch_mainck_to_xtal(uint32_t ul_bypass,
- uint32_t ul_xtal_startup_time)
-{
- /* Enable Main Xtal oscillator */
- if (ul_bypass) {
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
- CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY |
- CKGR_MOR_MOSCSEL;
- } else {
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
- CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN |
- CKGR_MOR_MOSCXTST(ul_xtal_startup_time);
- /* Wait the Xtal to stabilize */
- while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
-
- PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;
- }
-}
-
-/**
- * \brief Disable the external Xtal.
- *
- * \param ul_bypass 0 for Xtal, 1 for bypass.
- */
-void pmc_osc_disable_xtal(uint32_t ul_bypass)
-{
- /* Disable xtal oscillator */
- if (ul_bypass) {
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
- CKGR_MOR_KEY_PASSWD;
- } else {
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
- CKGR_MOR_KEY_PASSWD;
- }
-}
-
-/**
- * \brief Check if the MAINCK is ready. Depending on MOSCEL, MAINCK can be one
- * of Xtal, bypass or internal RC.
- *
- * \retval 1 Xtal is ready.
- * \retval 0 Xtal is not ready.
- */
-uint32_t pmc_osc_is_ready_mainck(void)
-{
- return PMC->PMC_SR & PMC_SR_MOSCSELS;
-}
-
-/**
- * \brief Select Main Crystal or internal RC as main clock source.
- *
- * \note This function will not enable/disable RC or Main Crystal.
- *
- * \param ul_xtal_rc 0 internal RC is selected, otherwise Main Crystal.
- */
-void pmc_mainck_osc_select(uint32_t ul_xtal_rc)
-{
- uint32_t mor = PMC->CKGR_MOR;
- if (ul_xtal_rc) {
- mor |= CKGR_MOR_MOSCSEL;
- } else {
- mor &= ~CKGR_MOR_MOSCSEL;
- }
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor;
-}
-
-/**
- * \brief Enable PLLA clock.
- *
- * \param mula PLLA multiplier.
- * \param pllacount PLLA counter.
- * \param diva Divider.
- */
-void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva)
-{
- /* first disable the PLL to unlock the lock */
- pmc_disable_pllack();
-
-#if (SAM4C || SAM4CM || SAM4CP || SAMG)
- PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(diva) |
- CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
-#else
- PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_DIVA(diva) |
- CKGR_PLLAR_PLLACOUNT(pllacount) | CKGR_PLLAR_MULA(mula);
-#endif
- while ((PMC->PMC_SR & PMC_SR_LOCKA) == 0);
-}
-
-/**
- * \brief Disable PLLA clock.
- */
-void pmc_disable_pllack(void)
-{
-#if (SAM4C || SAM4CM || SAM4CP || SAMG)
- PMC->CKGR_PLLAR = CKGR_PLLAR_MULA(0);
-#else
- PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0);
-#endif
-}
-
-/**
- * \brief Is PLLA locked?
- *
- * \retval 0 Not locked.
- * \retval 1 Locked.
- */
-uint32_t pmc_is_locked_pllack(void)
-{
- return (PMC->PMC_SR & PMC_SR_LOCKA);
-}
-
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
-/**
- * \brief Enable PLLB clock.
- *
- * \param mulb PLLB multiplier.
- * \param pllbcount PLLB counter.
- * \param divb Divider.
- */
-void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb)
-{
- /* first disable the PLL to unlock the lock */
- pmc_disable_pllbck();
-
-#if SAMG55
- PMC->CKGR_PLLAR = CKGR_PLLAR_PLLAEN(divb) |
- CKGR_PLLAR_PLLACOUNT(pllbcount) | CKGR_PLLAR_MULA(mulb);
-#else
- PMC->CKGR_PLLBR =
- CKGR_PLLBR_DIVB(divb) | CKGR_PLLBR_PLLBCOUNT(pllbcount)
- | CKGR_PLLBR_MULB(mulb);
-#endif
- while ((PMC->PMC_SR & PMC_SR_LOCKB) == 0);
-}
-
-/**
- * \brief Disable PLLB clock.
- */
-void pmc_disable_pllbck(void)
-{
- PMC->CKGR_PLLBR = CKGR_PLLBR_MULB(0);
-}
-
-/**
- * \brief Is PLLB locked?
- *
- * \retval 0 Not locked.
- * \retval 1 Locked.
- */
-uint32_t pmc_is_locked_pllbck(void)
-{
- return (PMC->PMC_SR & PMC_SR_LOCKB);
-}
-#endif
-
-#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Enable UPLL clock.
- */
-void pmc_enable_upll_clock(void)
-{
- PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN;
-
- /* Wait UTMI PLL Lock Status */
- while (!(PMC->PMC_SR & PMC_SR_LOCKU));
-}
-
-/**
- * \brief Disable UPLL clock.
- */
-void pmc_disable_upll_clock(void)
-{
- PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
-}
-
-/**
- * \brief Is UPLL locked?
- *
- * \retval 0 Not locked.
- * \retval 1 Locked.
- */
-uint32_t pmc_is_locked_upll(void)
-{
- return (PMC->PMC_SR & PMC_SR_LOCKU);
-}
-#endif
-
-/**
- * \brief Enable the specified peripheral clock.
- *
- * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
- *
- * \param ul_id Peripheral ID (ID_xxx).
- *
- * \retval 0 Success.
- * \retval 1 Invalid parameter.
- */
-uint32_t pmc_enable_periph_clk(uint32_t ul_id)
-{
- if (ul_id > MAX_PERIPH_ID) {
- return 1;
- }
-
- if (ul_id < 32) {
- if ((PMC->PMC_PCSR0 & (1u << ul_id)) != (1u << ul_id)) {
- PMC->PMC_PCER0 = 1 << ul_id;
- }
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
- } else {
- ul_id -= 32;
- if ((PMC->PMC_PCSR1 & (1u << ul_id)) != (1u << ul_id)) {
- PMC->PMC_PCER1 = 1 << ul_id;
- }
-#endif
- }
-
- return 0;
-}
-
-/**
- * \brief Disable the specified peripheral clock.
- *
- * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
- *
- * \param ul_id Peripheral ID (ID_xxx).
- *
- * \retval 0 Success.
- * \retval 1 Invalid parameter.
- */
-uint32_t pmc_disable_periph_clk(uint32_t ul_id)
-{
- if (ul_id > MAX_PERIPH_ID) {
- return 1;
- }
-
- if (ul_id < 32) {
- if ((PMC->PMC_PCSR0 & (1u << ul_id)) == (1u << ul_id)) {
- PMC->PMC_PCDR0 = 1 << ul_id;
- }
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 \
- || SAMV70 || SAME70 || SAMS70)
- } else {
- ul_id -= 32;
- if ((PMC->PMC_PCSR1 & (1u << ul_id)) == (1u << ul_id)) {
- PMC->PMC_PCDR1 = 1 << ul_id;
- }
-#endif
- }
- return 0;
-}
-
-/**
- * \brief Enable all peripheral clocks.
- */
-void pmc_enable_all_periph_clk(void)
-{
- PMC->PMC_PCER0 = PMC_MASK_STATUS0;
- while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != PMC_MASK_STATUS0);
-
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
- || SAMV70 || SAME70 || SAMS70)
- PMC->PMC_PCER1 = PMC_MASK_STATUS1;
- while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != PMC_MASK_STATUS1);
-#endif
-}
-
-/**
- * \brief Disable all peripheral clocks.
- */
-void pmc_disable_all_periph_clk(void)
-{
- PMC->PMC_PCDR0 = PMC_MASK_STATUS0;
- while ((PMC->PMC_PCSR0 & PMC_MASK_STATUS0) != 0);
-
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
- || SAMV70 || SAME70 || SAMS70)
- PMC->PMC_PCDR1 = PMC_MASK_STATUS1;
- while ((PMC->PMC_PCSR1 & PMC_MASK_STATUS1) != 0);
-#endif
-}
-
-/**
- * \brief Check if the specified peripheral clock is enabled.
- *
- * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
- *
- * \param ul_id Peripheral ID (ID_xxx).
- *
- * \retval 0 Peripheral clock is disabled or unknown.
- * \retval 1 Peripheral clock is enabled.
- */
-uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id)
-{
- if (ul_id > MAX_PERIPH_ID) {
- return 0;
- }
-
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
- || SAMV70 || SAME70 || SAMS70)
- if (ul_id < 32) {
-#endif
- if ((PMC->PMC_PCSR0 & (1u << ul_id))) {
- return 1;
- } else {
- return 0;
- }
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAM4C || SAM4CM || SAM4CP || SAMV71 \
- || SAMV70 || SAME70 || SAMS70)
- } else {
- ul_id -= 32;
- if ((PMC->PMC_PCSR1 & (1u << ul_id))) {
- return 1;
- } else {
- return 0;
- }
- }
-#endif
-}
-
-/**
- * \brief Set the prescaler for the specified programmable clock.
- *
- * \param ul_id Peripheral ID.
- * \param ul_pres Prescaler value.
- */
-void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres)
-{
- PMC->PMC_PCK[ul_id] =
- (PMC->PMC_PCK[ul_id] & ~PMC_PCK_PRES_Msk) | ul_pres;
- while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
- && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
-}
-
-/**
- * \brief Set the source oscillator for the specified programmable clock.
- *
- * \param ul_id Peripheral ID.
- * \param ul_source Source selection value.
- */
-void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source)
-{
- PMC->PMC_PCK[ul_id] =
- (PMC->PMC_PCK[ul_id] & ~PMC_PCK_CSS_Msk) | ul_source;
- while ((PMC->PMC_SCER & (PMC_SCER_PCK0 << ul_id))
- && !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)));
-}
-
-/**
- * \brief Switch programmable clock source selection to slow clock.
- *
- * \param ul_id Id of the programmable clock.
- * \param ul_pres Programmable clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_SLOW_CLK | ul_pres;
- for (ul_timeout = PMC_TIMEOUT;
- !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-
-/**
- * \brief Switch programmable clock source selection to main clock.
- *
- * \param ul_id Id of the programmable clock.
- * \param ul_pres Programmable clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MAIN_CLK | ul_pres;
- for (ul_timeout = PMC_TIMEOUT;
- !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-
-/**
- * \brief Switch programmable clock source selection to PLLA clock.
- *
- * \param ul_id Id of the programmable clock.
- * \param ul_pres Programmable clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLA_CLK | ul_pres;
- for (ul_timeout = PMC_TIMEOUT;
- !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
-/**
- * \brief Switch programmable clock source selection to PLLB clock.
- *
- * \param ul_id Id of the programmable clock.
- * \param ul_pres Programmable clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_PLLB_CLK | ul_pres;
- for (ul_timeout = PMC_TIMEOUT;
- !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-#endif
-
-#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Switch programmable clock source selection to UPLL clock.
- *
- * \param ul_id Id of the programmable clock.
- * \param ul_pres Programmable clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_UPLL_CLK | ul_pres;
- for (ul_timeout = PMC_TIMEOUT;
- !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id));
- --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-#endif
-
-/**
- * \brief Switch programmable clock source selection to mck.
- *
- * \param ul_id Id of the programmable clock.
- * \param ul_pres Programmable clock prescaler.
- *
- * \retval 0 Success.
- * \retval 1 Timeout error.
- */
-uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres)
-{
- uint32_t ul_timeout;
-
- PMC->PMC_PCK[ul_id] = PMC_PCK_CSS_MCK | ul_pres;
- for (ul_timeout = PMC_TIMEOUT;
- !(PMC->PMC_SR & (PMC_SR_PCKRDY0 << ul_id)); --ul_timeout) {
- if (ul_timeout == 0) {
- return 1;
- }
- }
-
- return 0;
-}
-
-/**
- * \brief Enable the specified programmable clock.
- *
- * \param ul_id Id of the programmable clock.
- */
-void pmc_enable_pck(uint32_t ul_id)
-{
- PMC->PMC_SCER = PMC_SCER_PCK0 << ul_id;
-}
-
-/**
- * \brief Disable the specified programmable clock.
- *
- * \param ul_id Id of the programmable clock.
- */
-void pmc_disable_pck(uint32_t ul_id)
-{
- PMC->PMC_SCDR = PMC_SCER_PCK0 << ul_id;
-}
-
-/**
- * \brief Enable all programmable clocks.
- */
-void pmc_enable_all_pck(void)
-{
- PMC->PMC_SCER = PMC_SCER_PCK0 | PMC_SCER_PCK1 | PMC_SCER_PCK2;
-}
-
-/**
- * \brief Disable all programmable clocks.
- */
-void pmc_disable_all_pck(void)
-{
- PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2;
-}
-
-/**
- * \brief Check if the specified programmable clock is enabled.
- *
- * \param ul_id Id of the programmable clock.
- *
- * \retval 0 Programmable clock is disabled or unknown.
- * \retval 1 Programmable clock is enabled.
- */
-uint32_t pmc_is_pck_enabled(uint32_t ul_id)
-{
- if (ul_id > 2) {
- return 0;
- }
-
- return (PMC->PMC_SCSR & (PMC_SCSR_PCK0 << ul_id));
-}
-
-#if (SAM4C || SAM4CM || SAM4CP)
-/**
- * \brief Enable Coprocessor Clocks.
- */
-void pmc_enable_cpck(void)
-{
- PMC->PMC_SCER = PMC_SCER_CPCK | PMC_SCER_CPKEY_PASSWD;
-}
-
-/**
- * \brief Disable Coprocessor Clocks.
- */
-void pmc_disable_cpck(void)
-{
- PMC->PMC_SCDR = PMC_SCDR_CPCK | PMC_SCDR_CPKEY_PASSWD;
-}
-
-/**
- * \brief Check if the Coprocessor Clocks is enabled.
- *
- * \retval 0 Coprocessor Clocks is disabled.
- * \retval 1 Coprocessor Clocks is enabled.
- */
-bool pmc_is_cpck_enabled(void)
-{
- if(PMC->PMC_SCSR & PMC_SCSR_CPCK) {
- return 1;
- } else {
- return 0;
- }
-}
-
-/**
- * \brief Enable Coprocessor Bus Master Clocks.
- */
-void pmc_enable_cpbmck(void)
-{
- PMC->PMC_SCER = PMC_SCER_CPBMCK | PMC_SCER_CPKEY_PASSWD;
-}
-
-/**
- * \brief Disable Coprocessor Bus Master Clocks.
- */
-void pmc_disable_cpbmck(void)
-{
- PMC->PMC_SCDR = PMC_SCDR_CPBMCK | PMC_SCDR_CPKEY_PASSWD;
-}
-
-/**
- * \brief Check if the Coprocessor Bus Master Clocks is enabled.
- *
- * \retval 0 Coprocessor Bus Master Clocks is disabled.
- * \retval 1 Coprocessor Bus Master Clocks is enabled.
- */
-bool pmc_is_cpbmck_enabled(void)
-{
- if(PMC->PMC_SCSR & PMC_SCSR_CPBMCK) {
- return 1;
- } else {
- return 0;
- }
-}
-
-/**
- * \brief Set the prescaler for the Coprocessor Master Clock.
- *
- * \param ul_pres Prescaler value.
- */
-void pmc_cpck_set_prescaler(uint32_t ul_pres)
-{
- PMC->PMC_MCKR =
- (PMC->PMC_MCKR & (~PMC_MCKR_CPPRES_Msk)) | PMC_MCKR_CPPRES(ul_pres);
-}
-
-/**
- * \brief Set the source for the Coprocessor Master Clock.
- *
- * \param ul_source Source selection value.
- */
-void pmc_cpck_set_source(uint32_t ul_source)
-{
- PMC->PMC_MCKR =
- (PMC->PMC_MCKR & (~PMC_MCKR_CPCSS_Msk)) | ul_source;
-}
-#endif
-
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Switch UDP (USB) clock source selection to PLLA clock.
- *
- * \param ul_usbdiv Clock divisor.
- */
-void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv)
-{
- PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
-}
-#endif
-
-#if (SAM3S || SAM4S || SAMG55)
-/**
- * \brief Switch UDP (USB) clock source selection to PLLB clock.
- *
- * \param ul_usbdiv Clock divisor.
- */
-void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv)
-{
- PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
-}
-#endif
-
-#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Switch UDP (USB) clock source selection to UPLL clock.
- *
- * \param ul_usbdiv Clock divisor.
- */
-void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv)
-{
- PMC->PMC_USB = PMC_USB_USBS | PMC_USB_USBDIV(ul_usbdiv);
-}
-#endif
-
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Enable UDP (USB) clock.
- */
-void pmc_enable_udpck(void)
-{
-#if (SAM3S || SAM4S || SAM4E || SAMG55)
- PMC->PMC_SCER = PMC_SCER_UDP;
-#elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
- PMC->PMC_SCER = PMC_SCER_USBCLK;
-#else
- PMC->PMC_SCER = PMC_SCER_UOTGCLK;
-# endif
-}
-
-/**
- * \brief Disable UDP (USB) clock.
- */
-void pmc_disable_udpck(void)
-{
-#if (SAM3S || SAM4S || SAM4E || SAMG55)
- PMC->PMC_SCDR = PMC_SCDR_UDP;
-#elif (SAMV71 || SAMV70 || SAME70 || SAMS70)
- PMC->PMC_SCDR = PMC_SCDR_USBCLK;
-#else
- PMC->PMC_SCDR = PMC_SCDR_UOTGCLK;
-# endif
-}
-#endif
-
-#if SAMG55
-/**
- * \brief Switch UHP (USB) clock source selection to PLLA clock.
- *
- * \param ul_usbdiv Clock divisor.
- */
-void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv)
-{
- PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv);
-}
-
-/**
- * \brief Switch UHP (USB) clock source selection to PLLB clock.
- *
- * \param ul_usbdiv Clock divisor.
- */
-void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv)
-{
- PMC->PMC_USB = PMC_USB_USBDIV(ul_usbdiv) | PMC_USB_USBS;
-}
-
-/**
- * \brief Enable UHP (USB) clock.
- */
-void pmc_enable_uhpck(void)
-{
- PMC->PMC_SCER = PMC_SCER_UHP;
-}
-#endif
-
-/**
- * \brief Enable PMC interrupts.
- *
- * \param ul_sources Interrupt sources bit map.
- */
-void pmc_enable_interrupt(uint32_t ul_sources)
-{
- PMC->PMC_IER = ul_sources;
-}
-
-/**
- * \brief Disable PMC interrupts.
- *
- * \param ul_sources Interrupt sources bit map.
- */
-void pmc_disable_interrupt(uint32_t ul_sources)
-{
- PMC->PMC_IDR = ul_sources;
-}
-
-/**
- * \brief Get PMC interrupt mask.
- *
- * \return The interrupt mask value.
- */
-uint32_t pmc_get_interrupt_mask(void)
-{
- return PMC->PMC_IMR;
-}
-
-/**
- * \brief Get current status.
- *
- * \return The current PMC status.
- */
-uint32_t pmc_get_status(void)
-{
- return PMC->PMC_SR;
-}
-
-/**
- * \brief Set the wake-up inputs for fast startup mode registers
- * (event generation).
- *
- * \param ul_inputs Wake up inputs to enable.
- */
-void pmc_set_fast_startup_input(uint32_t ul_inputs)
-{
- ul_inputs &= PMC_FAST_STARTUP_Msk;
- PMC->PMC_FSMR |= ul_inputs;
-}
-
-/**
- * \brief Clear the wake-up inputs for fast startup mode registers
- * (remove event generation).
- *
- * \param ul_inputs Wake up inputs to disable.
- */
-void pmc_clr_fast_startup_input(uint32_t ul_inputs)
-{
- ul_inputs &= PMC_FAST_STARTUP_Msk;
- PMC->PMC_FSMR &= ~ul_inputs;
-}
-
-#if (SAM4C || SAM4CM || SAM4CP)
-/**
- * \brief Set the wake-up inputs of coprocessor for fast startup mode registers
- * (event generation).
- *
- * \param ul_inputs Wake up inputs to enable.
- */
-void pmc_cp_set_fast_startup_input(uint32_t ul_inputs)
-{
- ul_inputs &= PMC_FAST_STARTUP_Msk;
- PMC->PMC_CPFSMR |= ul_inputs;
-}
-
-/**
- * \brief Clear the wake-up inputs of coprocessor for fast startup mode registers
- * (remove event generation).
- *
- * \param ul_inputs Wake up inputs to disable.
- */
-void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs)
-{
- ul_inputs &= PMC_FAST_STARTUP_Msk;
- PMC->PMC_CPFSMR &= ~ul_inputs;
-}
-#endif
-
-/**
- * \brief Enable Sleep Mode.
- * Enter condition: (WFE or WFI) + (SLEEPDEEP bit = 0) + (LPM bit = 0)
- *
- * \param uc_type 0 for wait for interrupt, 1 for wait for event.
- * \note For SAM4S, SAM4C, SAM4CM, SAM4CP, SAMV71 and SAM4E series,
- * since only WFI is effective, uc_type = 1 will be treated as uc_type = 0.
- */
-void pmc_enable_sleepmode(uint8_t uc_type)
-{
-#if !(SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
- PMC->PMC_FSMR &= (uint32_t) ~ PMC_FSMR_LPM; // Enter Sleep mode
-#endif
- SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; // Deep sleep
-
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
- UNUSED(uc_type);
- __DSB();
- __WFI();
-#else
- if (uc_type == 0) {
- __DSB();
- __WFI();
- } else {
- __DSB();
- __WFE();
- }
-#endif
-}
-
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
-static uint32_t ul_flash_in_wait_mode = PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN;
-/**
- * \brief Set the embedded flash state in wait mode
- *
- * \param ul_flash_state PMC_WAIT_MODE_FLASH_STANDBY flash in standby mode,
- * PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN flash in deep power down mode.
- */
-void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state)
-{
- ul_flash_in_wait_mode = ul_flash_state;
-}
-
-/**
- * \brief Enable Wait Mode. Enter condition: (WAITMODE bit = 1) + FLPM
- *
- * \note In this function, FLPM will retain, WAITMODE bit will be set,
- * Generally, this function will be called by pmc_sleep() in order to
- * complete all sequence entering wait mode.
- * See \ref pmc_sleep() for entering different sleep modes.
- */
-void pmc_enable_waitmode(void)
-{
- uint32_t i;
-
- /* Flash in wait mode */
- i = PMC->PMC_FSMR;
- i &= ~PMC_FSMR_FLPM_Msk;
-#if !(SAMV71 || SAMV70 || SAME70 || SAMS70)
- i |= ul_flash_in_wait_mode;
-#else
- i |= PMC_WAIT_MODE_FLASH_IDLE;
-#endif
- PMC->PMC_FSMR = i;
-
- /* Set the WAITMODE bit = 1 */
- PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_WAITMODE;
-
- /* Waiting for Master Clock Ready MCKRDY = 1 */
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-
- /* Waiting for MOSCRCEN bit cleared is strongly recommended
- * to ensure that the core will not execute undesired instructions
- */
- for (i = 0; i < 500; i++) {
- __NOP();
- }
- while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));
-
-#if (!SAMG)
- /* Restore Flash in idle mode */
- i = PMC->PMC_FSMR;
- i &= ~PMC_FSMR_FLPM_Msk;
- i |= PMC_WAIT_MODE_FLASH_IDLE;
- PMC->PMC_FSMR = i;
-#endif
-}
-#else
-/**
- * \brief Enable Wait Mode. Enter condition: WFE + (SLEEPDEEP bit = 0) +
- * (LPM bit = 1)
- */
-void pmc_enable_waitmode(void)
-{
- uint32_t i;
-
- PMC->PMC_FSMR |= PMC_FSMR_LPM; /* Enter Wait mode */
- SCB->SCR &= (uint32_t) ~ SCB_SCR_SLEEPDEEP_Msk; /* Deep sleep */
-
- __DSB();
- __WFE();
-
- /* Waiting for MOSCRCEN bit cleared is strongly recommended
- * to ensure that the core will not execute undesired instructions
- */
- for (i = 0; i < 500; i++) {
- __NOP();
- }
- while (!(PMC->CKGR_MOR & CKGR_MOR_MOSCRCEN));
-
-}
-#endif
-
-#if (!(SAMG51 || SAMG53 || SAMG54))
-/**
- * \brief Enable Backup Mode. Enter condition: WFE/(VROFF bit = 1) +
- * (SLEEPDEEP bit = 1)
- */
-void pmc_enable_backupmode(void)
-{
-#if (SAM4C || SAM4CM || SAM4CP)
- uint32_t tmp = SUPC->SUPC_MR & ~(SUPC_MR_BUPPOREN | SUPC_MR_KEY_Msk);
- SUPC->SUPC_MR = tmp | SUPC_MR_KEY_PASSWD;
- while (SUPC->SUPC_SR & SUPC_SR_BUPPORS);
-#endif
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
- SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG;
- uint32_t ul_dummy = SUPC->SUPC_MR;
- UNUSED(ul_dummy);
- __DSB();
- __WFE();
- __WFI();
-#else
- __DSB();
- __WFE();
-#endif
-}
-#endif
-
-/**
- * \brief Enable Clock Failure Detector.
- */
-void pmc_enable_clock_failure_detector(void)
-{
- uint32_t ul_reg = PMC->CKGR_MOR;
-
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_CFDEN | ul_reg;
-}
-
-/**
- * \brief Disable Clock Failure Detector.
- */
-void pmc_disable_clock_failure_detector(void)
-{
- uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_CFDEN);
-
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg;
-}
-
-#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Enable Slow Crystal Oscillator Frequency Monitoring.
- */
-void pmc_enable_sclk_osc_freq_monitor(void)
-{
- uint32_t ul_reg = PMC->CKGR_MOR;
-
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | CKGR_MOR_XT32KFME | ul_reg;
-}
-
-/**
- * \brief Disable Slow Crystal Oscillator Frequency Monitoring.
- */
-void pmc_disable_sclk_osc_freq_monitor(void)
-{
- uint32_t ul_reg = PMC->CKGR_MOR & (~CKGR_MOR_XT32KFME);
-
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | ul_reg;
-}
-#endif
-
-/**
- * \brief Enable or disable write protect of PMC registers.
- *
- * \param ul_enable 1 to enable, 0 to disable.
- */
-void pmc_set_writeprotect(uint32_t ul_enable)
-{
- if (ul_enable) {
- PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD | PMC_WPMR_WPEN;
- } else {
- PMC->PMC_WPMR = PMC_WPMR_WPKEY_PASSWD;
- }
-}
-
-/**
- * \brief Return write protect status.
- *
- * \return Return write protect status.
- */
-uint32_t pmc_get_writeprotect_status(void)
-{
- return PMC->PMC_WPSR;
-}
-
-#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Enable the specified peripheral clock.
- *
- * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
- *
- * \param ul_id Peripheral ID (ID_xxx).
- *
- * \retval 0 Success.
- * \retval 1 Fail.
- */
-uint32_t pmc_enable_sleepwalking(uint32_t ul_id)
-{
- uint32_t temp;
-#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
- if ((7 <= ul_id) && (ul_id<= 29)) {
-#else
- if ((8 <= ul_id) && (ul_id<= 29)) {
-#endif
- temp = pmc_get_active_status0();
- if (temp & (1 << ul_id)) {
- return 1;
- }
- PMC->PMC_SLPWK_ER0 = 1 << ul_id;
- temp = pmc_get_active_status0();
- if (temp & (1 << ul_id)) {
- pmc_disable_sleepwalking(ul_id);
- return 1;
- }
- return 0;
- }
-#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
- else if ((32 <= ul_id) && (ul_id<= 60)) {
- ul_id -= 32;
- temp = pmc_get_active_status1();
- if (temp & (1 << ul_id)) {
- return 1;
- }
- PMC->PMC_SLPWK_ER1 = 1 << ul_id;
- temp = pmc_get_active_status1();
- if (temp & (1 << ul_id)) {
- pmc_disable_sleepwalking(ul_id);
- return 1;
- }
- return 0;
- }
-#endif
- else {
- return 1;
- }
-}
-
-/**
- * \brief Disable the sleepwalking of specified peripheral.
- *
- * \note The ID must NOT be shifted (i.e., 1 << ID_xxx).
- *
- * \param ul_id Peripheral ID (ID_xxx).
- *
- * \retval 0 Success.
- * \retval 1 Invalid parameter.
- */
-uint32_t pmc_disable_sleepwalking(uint32_t ul_id)
-{
-#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
- if ((7 <= ul_id) && (ul_id<= 29)) {
-#else
- if ((8 <= ul_id) && (ul_id<= 29)) {
-#endif
- PMC->PMC_SLPWK_DR0 = 1 << ul_id;
- return 0;
- }
-#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
- else if ((32 <= ul_id) && (ul_id<= 60)) {
- ul_id -= 32;
- PMC->PMC_SLPWK_DR1 = 1 << ul_id;
- return 0;
- }
-#endif
- else {
- return 1;
- }
-}
-
-/**
- * \brief Return peripheral sleepwalking enable status.
- *
- * \return the status register value.
- */
-uint32_t pmc_get_sleepwalking_status0(void)
-{
- return PMC->PMC_SLPWK_SR0;
-}
-
-/**
- * \brief Return peripheral active status.
- *
- * \return the status register value.
- */
-uint32_t pmc_get_active_status0(void)
-{
- return PMC->PMC_SLPWK_ASR0;
-}
-
-#endif
-
-#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \brief Return peripheral sleepwalking enable status.
- *
- * \return the status register value.
- */
-uint32_t pmc_get_sleepwalking_status1(void)
-{
- return PMC->PMC_SLPWK_SR1;
-}
-
-/**
- * \brief Return peripheral active status.
- *
- * \return the status register value.
- */
-uint32_t pmc_get_active_status1(void)
-{
- return PMC->PMC_SLPWK_ASR1;
-}
-#endif
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/drivers/pmc/pmc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/drivers/pmc/pmc.h
deleted file mode 100644
index 497825f..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/drivers/pmc/pmc.h
+++ /dev/null
@@ -1,550 +0,0 @@
-/**
- * \file
- *
- * \brief Power Management Controller (PMC) driver for SAM.
- *
- * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef PMC_H_INCLUDED
-#define PMC_H_INCLUDED
-
-#include "compiler.h"
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-/** Bit mask for peripheral clocks (PCER0) */
-#define PMC_MASK_STATUS0 (0xFFFFFFFC)
-
-/** Bit mask for peripheral clocks (PCER1) */
-#define PMC_MASK_STATUS1 (0xFFFFFFFF)
-
-/** Loop counter timeout value */
-#if !(SAME70)
-#define PMC_TIMEOUT (2048)
-#else
-#define PMC_TIMEOUT (4096)
-#endif
-
-/** Key to unlock CKGR_MOR register */
-#ifndef CKGR_MOR_KEY_PASSWD
-#define CKGR_MOR_KEY_PASSWD CKGR_MOR_KEY(0x37U)
-#endif
-
-/** Key used to write SUPC registers */
-#ifndef SUPC_CR_KEY_PASSWD
-#define SUPC_CR_KEY_PASSWD SUPC_CR_KEY(0xA5U)
-#endif
-
-#ifndef SUPC_MR_KEY_PASSWD
-#define SUPC_MR_KEY_PASSWD SUPC_MR_KEY(0xA5U)
-#endif
-
-/** Mask to access fast startup input */
-#define PMC_FAST_STARTUP_Msk (0x7FFFFu)
-
-/** PMC_WPMR Write Protect KEY, unlock it */
-#ifndef PMC_WPMR_WPKEY_PASSWD
-#define PMC_WPMR_WPKEY_PASSWD PMC_WPMR_WPKEY((uint32_t) 0x504D43)
-#endif
-
-/** Using external oscillator */
-#define PMC_OSC_XTAL 0
-
-/** Oscillator in bypass mode */
-#define PMC_OSC_BYPASS 1
-
-#define PMC_PCK_0 0 /* PCK0 ID */
-#define PMC_PCK_1 1 /* PCK1 ID */
-#define PMC_PCK_2 2 /* PCK2 ID */
-#if (SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
-#define PMC_PCK_3 3 /* PCK3 ID */
-#define PMC_PCK_4 4 /* PCK4 ID */
-#define PMC_PCK_5 5 /* PCK5 ID */
-#define PMC_PCK_6 6 /* PCK6 ID */
-#if SAMG55
-#define PMC_PCK_7 7 /* PCK7 ID */
-#endif
-#endif
-
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/** Flash state in Wait Mode */
-#define PMC_WAIT_MODE_FLASH_STANDBY PMC_FSMR_FLPM_FLASH_STANDBY
-#define PMC_WAIT_MODE_FLASH_DEEP_POWERDOWN PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN
-#define PMC_WAIT_MODE_FLASH_IDLE PMC_FSMR_FLPM_FLASH_IDLE
-#endif
-
-/** Convert startup time from us to MOSCXTST */
-#define pmc_us_to_moscxtst(startup_us, slowck_freq) \
- ((startup_us * slowck_freq / 8 / 1000000) < 0x100 ? \
- (startup_us * slowck_freq / 8 / 1000000) : 0xFF)
-
-/**
- * \name Master clock (MCK) Source and Prescaler configuration
- *
- * \note The following functions may be used to select the clock source and
- * prescaler for the master clock.
- */
-//@{
-
-void pmc_mck_set_prescaler(uint32_t ul_pres);
-#if SAMV71 || SAMV70 || SAME70 || SAMS70
-void pmc_mck_set_division(uint32_t ul_div);
-#endif
-void pmc_mck_set_source(uint32_t ul_source);
-uint32_t pmc_switch_mck_to_sclk(uint32_t ul_pres);
-uint32_t pmc_switch_mck_to_mainck(uint32_t ul_pres);
-uint32_t pmc_switch_mck_to_pllack(uint32_t ul_pres);
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
-uint32_t pmc_switch_mck_to_pllbck(uint32_t ul_pres);
-#endif
-#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
-uint32_t pmc_switch_mck_to_upllck(uint32_t ul_pres);
-#endif
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
-void pmc_set_flash_in_wait_mode(uint32_t ul_flash_state);
-#endif
-
-
-//@}
-
-/**
- * \name Slow clock (SLCK) oscillator and configuration
- *
- */
-//@{
-
-void pmc_switch_sclk_to_32kxtal(uint32_t ul_bypass);
-uint32_t pmc_osc_is_ready_32kxtal(void);
-
-//@}
-
-/**
- * \name Main Clock (MAINCK) oscillator and configuration
- *
- */
-//@{
-
-void pmc_switch_mainck_to_fastrc(uint32_t ul_moscrcf);
-void pmc_osc_enable_fastrc(uint32_t ul_rc);
-void pmc_osc_disable_fastrc(void);
-uint32_t pmc_osc_is_ready_fastrc(void);
-void pmc_osc_enable_main_xtal(uint32_t ul_xtal_startup_time);
-void pmc_osc_bypass_main_xtal(void);
-void pmc_osc_disable_main_xtal(void);
-uint32_t pmc_osc_is_bypassed_main_xtal(void);
-uint32_t pmc_osc_is_ready_main_xtal(void);
-void pmc_switch_mainck_to_xtal(uint32_t ul_bypass,
- uint32_t ul_xtal_startup_time);
-void pmc_osc_disable_xtal(uint32_t ul_bypass);
-uint32_t pmc_osc_is_ready_mainck(void);
-void pmc_mainck_osc_select(uint32_t ul_xtal_rc);
-
-//@}
-
-/**
- * \name PLL oscillator and configuration
- *
- */
-//@{
-
-void pmc_enable_pllack(uint32_t mula, uint32_t pllacount, uint32_t diva);
-void pmc_disable_pllack(void);
-uint32_t pmc_is_locked_pllack(void);
-
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
-void pmc_enable_pllbck(uint32_t mulb, uint32_t pllbcount, uint32_t divb);
-void pmc_disable_pllbck(void);
-uint32_t pmc_is_locked_pllbck(void);
-#endif
-
-#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
-void pmc_enable_upll_clock(void);
-void pmc_disable_upll_clock(void);
-uint32_t pmc_is_locked_upll(void);
-#endif
-
-//@}
-
-/**
- * \name Peripherals clock configuration
- *
- */
-//@{
-
-uint32_t pmc_enable_periph_clk(uint32_t ul_id);
-uint32_t pmc_disable_periph_clk(uint32_t ul_id);
-void pmc_enable_all_periph_clk(void);
-void pmc_disable_all_periph_clk(void);
-uint32_t pmc_is_periph_clk_enabled(uint32_t ul_id);
-
-//@}
-
-/**
- * \name Programmable clock Source and Prescaler configuration
- *
- * The following functions may be used to select the clock source and
- * prescaler for the specified programmable clock.
- */
-//@{
-
-void pmc_pck_set_prescaler(uint32_t ul_id, uint32_t ul_pres);
-void pmc_pck_set_source(uint32_t ul_id, uint32_t ul_source);
-uint32_t pmc_switch_pck_to_sclk(uint32_t ul_id, uint32_t ul_pres);
-uint32_t pmc_switch_pck_to_mainck(uint32_t ul_id, uint32_t ul_pres);
-uint32_t pmc_switch_pck_to_pllack(uint32_t ul_id, uint32_t ul_pres);
-#if (SAM4C || SAM4CM || SAM4CP)
-void pmc_enable_cpck(void);
-void pmc_disable_cpck(void);
-bool pmc_is_cpck_enabled(void);
-void pmc_enable_cpbmck(void);
-void pmc_disable_cpbmck(void);
-bool pmc_is_cpbmck_enabled(void);
-void pmc_cpck_set_prescaler(uint32_t ul_pres);
-void pmc_cpck_set_source(uint32_t ul_source);
-#endif
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP || SAMG55)
-uint32_t pmc_switch_pck_to_pllbck(uint32_t ul_id, uint32_t ul_pres);
-#endif
-#if (SAM3XA || SAM3U || SAMV71 || SAMV70 || SAME70 || SAMS70)
-uint32_t pmc_switch_pck_to_upllck(uint32_t ul_id, uint32_t ul_pres);
-#endif
-uint32_t pmc_switch_pck_to_mck(uint32_t ul_id, uint32_t ul_pres);
-void pmc_enable_pck(uint32_t ul_id);
-void pmc_disable_pck(uint32_t ul_id);
-void pmc_enable_all_pck(void);
-void pmc_disable_all_pck(void);
-uint32_t pmc_is_pck_enabled(uint32_t ul_id);
-
-//@}
-
-/**
- * \name USB clock configuration
- *
- */
-//@{
-
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
-void pmc_switch_udpck_to_pllack(uint32_t ul_usbdiv);
-#endif
-#if (SAM3S || SAM4S || SAMG55)
-void pmc_switch_udpck_to_pllbck(uint32_t ul_usbdiv);
-#endif
-#if (SAM3XA || SAMV71 || SAMV70 || SAME70 || SAMS70)
-void pmc_switch_udpck_to_upllck(uint32_t ul_usbdiv);
-#endif
-#if (SAM3S || SAM3XA || SAM4S || SAM4E || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
-void pmc_enable_udpck(void);
-void pmc_disable_udpck(void);
-#endif
-#if SAMG55
-void pmc_switch_uhpck_to_pllack(uint32_t ul_usbdiv);
-void pmc_switch_uhpck_to_pllbck(uint32_t ul_usbdiv);
-void pmc_enable_uhpck(void);
-#endif
-
-//@}
-
-/**
- * \name Interrupt and status management
- *
- */
-//@{
-
-void pmc_enable_interrupt(uint32_t ul_sources);
-void pmc_disable_interrupt(uint32_t ul_sources);
-uint32_t pmc_get_interrupt_mask(void);
-uint32_t pmc_get_status(void);
-
-//@}
-
-/**
- * \name Power management
- *
- * The following functions are used to configure sleep mode and additional
- * wake up inputs.
- */
-//@{
-
-void pmc_set_fast_startup_input(uint32_t ul_inputs);
-void pmc_clr_fast_startup_input(uint32_t ul_inputs);
-#if (SAM4C || SAM4CM || SAM4CP)
-void pmc_cp_set_fast_startup_input(uint32_t ul_inputs);
-void pmc_cp_clr_fast_startup_input(uint32_t ul_inputs);
-#endif
-void pmc_enable_sleepmode(uint8_t uc_type);
-void pmc_enable_waitmode(void);
-#if (!(SAMG51 || SAMG53 || SAMG54))
-void pmc_enable_backupmode(void);
-#endif
-//@}
-
-/**
- * \name Failure detector
- *
- */
-//@{
-
-void pmc_enable_clock_failure_detector(void);
-void pmc_disable_clock_failure_detector(void);
-
-//@}
-
-#if (SAM4N || SAM4C || SAM4CM || SAM4CP || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \name Slow Crystal Oscillator Frequency Monitoring
- *
- */
-//@{
-
-void pmc_enable_sclk_osc_freq_monitor(void);
-void pmc_disable_sclk_osc_freq_monitor(void);
-
-//@}
-#endif
-
-/**
- * \name Write protection
- *
- */
-//@{
-
-void pmc_set_writeprotect(uint32_t ul_enable);
-uint32_t pmc_get_writeprotect_status(void);
-
-//@}
-
-#if (SAMG53 || SAMG54 || SAMG55 || SAMV71 || SAMV70 || SAME70 || SAMS70)
-/**
- * \name Sleepwalking configuration
- *
- */
-//@{
-
-uint32_t pmc_enable_sleepwalking(uint32_t ul_id);
-uint32_t pmc_disable_sleepwalking(uint32_t ul_id);
-uint32_t pmc_get_sleepwalking_status0(void);
-uint32_t pmc_get_active_status0(void);
-#if (SAMV71 || SAMV70 || SAME70 || SAMS70)
-uint32_t pmc_get_sleepwalking_status1(void);
-uint32_t pmc_get_active_status1(void);
-#endif
-//@}
-#endif
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-//! @}
-
-/**
- * \page sam_pmc_quickstart Quick start guide for the SAM PMC module
- *
- * This is the quick start guide for the \ref sam_drivers_pmc_group "PMC module",
- * with step-by-step instructions on how to configure and use the driver in a
- * selection of use cases.
- *
- * The use cases contain several code fragments. The code fragments in the
- * steps for setup can be copied into a custom initialization function, while
- * the steps for usage can be copied into, e.g., the main application function.
- *
- * \section pmc_use_cases PMC use cases
- * - \ref pmc_basic_use_case Basic use case - Switch Main Clock sources
- * - \ref pmc_use_case_2 Advanced use case - Configure Programmable Clocks
- *
- * \section pmc_basic_use_case Basic use case - Switch Main Clock sources
- * In this use case, the PMC module is configured for a variety of system clock
- * sources and speeds. A LED is used to visually indicate the current clock
- * speed as the source is switched.
- *
- * \section pmc_basic_use_case_setup Setup
- *
- * \subsection pmc_basic_use_case_setup_prereq Prerequisites
- * -# \ref gpio_group "General Purpose I/O Management (gpio)"
- *
- * \subsection pmc_basic_use_case_setup_code Code
- * The following function needs to be added to the user application, to flash a
- * board LED a variable number of times at a rate given in CPU ticks.
- *
- * \code
- #define FLASH_TICK_COUNT 0x00012345
-
- void flash_led(uint32_t tick_count, uint8_t flash_count)
- {
- SysTick->CTRL = SysTick_CTRL_ENABLE_Msk;
- SysTick->LOAD = tick_count;
-
- while (flash_count--)
- {
- gpio_toggle_pin(LED0_GPIO);
- while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));
- gpio_toggle_pin(LED0_GPIO);
- while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk));
- }
- }
-\endcode
- *
- * \section pmc_basic_use_case_usage Use case
- *
- * \subsection pmc_basic_use_case_usage_code Example code
- * Add to application C-file:
- * \code
- for (;;)
- {
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);
- flash_led(FLASH_TICK_COUNT, 5);
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);
- flash_led(FLASH_TICK_COUNT, 5);
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);
- flash_led(FLASH_TICK_COUNT, 5);
- pmc_switch_mainck_to_xtal(0);
- flash_led(FLASH_TICK_COUNT, 5);
- }
-\endcode
- *
- * \subsection pmc_basic_use_case_usage_flow Workflow
- * -# Wrap the code in an infinite loop:
- * \code
- for (;;)
-\endcode
- * -# Switch the Master CPU frequency to the internal 12MHz RC oscillator, flash
- * a LED on the board several times:
- * \code
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_12_MHz);
- flash_led(FLASH_TICK_COUNT, 5);
-\endcode
- * -# Switch the Master CPU frequency to the internal 8MHz RC oscillator, flash
- * a LED on the board several times:
- * \code
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_8_MHz);
- flash_led(FLASH_TICK_COUNT, 5);
-\endcode
- * -# Switch the Master CPU frequency to the internal 4MHz RC oscillator, flash
- * a LED on the board several times:
- * \code
- pmc_switch_mainck_to_fastrc(CKGR_MOR_MOSCRCF_4_MHz);
- flash_led(FLASH_TICK_COUNT, 5);
-\endcode
- * -# Switch the Master CPU frequency to the external crystal oscillator, flash
- * a LED on the board several times:
- * \code
- pmc_switch_mainck_to_xtal(0, BOARD_OSC_STARTUP_US);
- flash_led(FLASH_TICK_COUNT, 5);
-\endcode
- *
- * \section pmc_use_case_2 Use case #2 - Configure Programmable Clocks
- * In this use case, the PMC module is configured to start the Slow Clock from
- * an attached 32KHz crystal, and start one of the Programmable Clock modules
- * sourced from the Slow Clock divided down with a prescale factor of 64.
- *
- * \section pmc_use_case_2_setup Setup
- *
- * \subsection pmc_use_case_2_setup_prereq Prerequisites
- * -# \ref pio_group "Parallel Input/Output Controller (pio)"
- *
- * \subsection pmc_use_case_2_setup_code Code
- * The following code must be added to the user application:
- * \code
- pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);
-\endcode
- *
- * \subsection pmc_use_case_2_setup_code_workflow Workflow
- * -# Configure the PCK1 pin to output on a specific port pin (in this case,
- * PIOA pin 17) of the microcontroller.
- * \code
- pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);
-\endcode
- * \note The peripheral selection and pin will vary according to your selected
- * SAM device model. Refer to the "Peripheral Signal Multiplexing on I/O
- * Lines" of your device's datasheet.
- *
- * \section pmc_use_case_2_usage Use case
- * The generated PCK1 clock output can be viewed on an oscilloscope attached to
- * the correct pin of the microcontroller.
- *
- * \subsection pmc_use_case_2_usage_code Example code
- * Add to application C-file:
- * \code
- pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);
- pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);
- pmc_enable_pck(PMC_PCK_1);
-
- for (;;)
- {
- // Do Nothing
- }
-\endcode
- *
- * \subsection pmc_use_case_2_usage_flow Workflow
- * -# Switch the Slow Clock source input to an external 32KHz crystal:
- * \code
- pmc_switch_sclk_to_32kxtal(PMC_OSC_XTAL);
-\endcode
- * -# Switch the Programmable Clock module PCK1 source clock to the Slow Clock,
- * with a prescaler of 64:
- * \code
- pmc_switch_pck_to_sclk(PMC_PCK_1, PMC_PCK_PRES_CLK_64);
-\endcode
- * -# Enable Programmable Clock module PCK1:
- * \code
- pmc_enable_pck(PMC_PCK_1);
-\endcode
- * -# Enter an infinite loop:
- * \code
- for (;;)
- {
- // Do Nothing
- }
-\endcode
- */
-
-#endif /* PMC_H_INCLUDED */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/drivers/pmc/sleep.c b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/drivers/pmc/sleep.c
deleted file mode 100644
index 5d461e4..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/drivers/pmc/sleep.c
+++ /dev/null
@@ -1,391 +0,0 @@
-/**
- * \file
- *
- * \brief Sleep mode access
- *
- * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include <compiler.h>
-#include "sleep.h"
-
-/* SAM3,SAM4,SAMG,SAMV,SAMS and SAME series */
-#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \
- SAM4CM || SAMG || SAM4CP || SAMV71 || SAMV70 || SAMS70 || SAME70)
-# include "pmc.h"
-# include "board.h"
-
-/* Checking board configuration of main clock xtal statup time */
-#if !defined(BOARD_OSC_STARTUP_US)
-# warning The board main clock xtal statup time has not been defined. Using default settings.
-# define BOARD_OSC_STARTUP_US (15625UL)
-#endif
-
-#if !defined(EFC0)
-# define EFC0 EFC
-#endif
-
-/**
- * Save clock settings and shutdown PLLs
- */
-__always_inline static void pmc_save_clock_settings(
- uint32_t *p_osc_setting,
- uint32_t *p_pll0_setting,
- uint32_t *p_pll1_setting,
- uint32_t *p_mck_setting,
- uint32_t *p_fmr_setting,
-#if defined(EFC1)
- uint32_t *p_fmr_setting1,
-#endif
- const bool disable_xtal)
-{
- uint32_t mor = PMC->CKGR_MOR;
- uint32_t mckr = PMC->PMC_MCKR;
- uint32_t fmr = EFC0->EEFC_FMR;
-# if defined(EFC1)
- uint32_t fmr1 = EFC1->EEFC_FMR;
-# endif
-
- if (p_osc_setting) {
- *p_osc_setting = mor;
- }
- if (p_pll0_setting) {
- *p_pll0_setting = PMC->CKGR_PLLAR;
- }
- if (p_pll1_setting) {
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP)
- *p_pll1_setting = PMC->CKGR_PLLBR;
-#elif (SAM3U || SAM3XA)
- *p_pll1_setting = PMC->CKGR_UCKR;
-#else
- *p_pll1_setting = 0;
-#endif
- }
- if (p_mck_setting) {
- *p_mck_setting = mckr;
- }
- if (p_fmr_setting) {
- *p_fmr_setting = fmr;
- }
-#if defined(EFC1)
- if (p_fmr_setting1) {
- *p_fmr_setting1 = fmr1;
- }
-#endif
-
- /* Enable FAST RC */
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | mor | CKGR_MOR_MOSCRCEN;
- /* if MCK source is PLL, switch to mainck */
- if ((mckr & PMC_MCKR_CSS_Msk) > PMC_MCKR_CSS_MAIN_CLK) {
- /* MCK -> MAINCK */
- mckr = (mckr & (~PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS_MAIN_CLK;
- PMC->PMC_MCKR = mckr;
- while(!(PMC->PMC_SR & PMC_SR_MCKRDY));
- }
- /* MCK prescale -> 1 */
- if (mckr & PMC_MCKR_PRES_Msk) {
- mckr = (mckr & (~PMC_MCKR_PRES_Msk));
- PMC->PMC_MCKR = mckr;
- while(!(PMC->PMC_SR & PMC_SR_MCKRDY));
- }
- /* Disable PLLs */
- pmc_disable_pllack();
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP)
- pmc_disable_pllbck();
-#elif (SAM3U || SAM3XA)
- pmc_disable_upll_clock();
-#endif
-
- /* Prepare for entering WAIT mode */
- /* Wait fast RC ready */
- while (!(PMC->PMC_SR & PMC_SR_MOSCRCS));
-
- /* Switch mainck to FAST RC */
-#if SAMG
- /**
- * For the sleepwalking feature, we need an accurate RC clock. Only 24M and
- * 16M are trimmed in production. Here we select the 24M.
- * And so wait state need to be 1.
- */
- EFC0->EEFC_FMR = (fmr & (~EEFC_FMR_FWS_Msk)) | EEFC_FMR_FWS(1);
-
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | CKGR_MOR_MOSCRCF_24_MHz |
- CKGR_MOR_KEY_PASSWD;
-#else
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) |
- CKGR_MOR_KEY_PASSWD;
-#endif
- while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));
-
-#if (!SAMG)
- /* FWS update */
- EFC0->EEFC_FMR = fmr & (~EEFC_FMR_FWS_Msk);
-#if defined(EFC1)
- EFC1->EEFC_FMR = fmr1 & (~EEFC_FMR_FWS_Msk);
-#endif
-#endif
-
- /* Disable XTALs */
- if (disable_xtal) {
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
- CKGR_MOR_KEY_PASSWD;
- }
-}
-
-/**
- * Restore clock settings
- */
-__always_inline static void pmc_restore_clock_setting(
- const uint32_t osc_setting,
- const uint32_t pll0_setting,
- const uint32_t pll1_setting,
- const uint32_t mck_setting,
- const uint32_t fmr_setting
-#if defined(EFC1)
- , const uint32_t fmr_setting1
-#endif
- )
-{
- uint32_t mckr;
- uint32_t pll_sr = 0;
-
- /* Switch mainck to external xtal */
- if (CKGR_MOR_MOSCXTBY == (osc_setting & CKGR_MOR_MOSCXTBY)) {
- /* Bypass mode */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTEN) |
- CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY |
- CKGR_MOR_MOSCSEL;
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN &
- ~CKGR_MOR_MOSCRCF_Msk)
- | CKGR_MOR_KEY_PASSWD;
- } else if (CKGR_MOR_MOSCXTEN == (osc_setting & CKGR_MOR_MOSCXTEN)) {
- /* Enable External XTAL */
- if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCXTEN)) {
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCXTBY) |
- CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTEN;
- /* Wait the Xtal to stabilize */
- while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
- }
- /* Select External XTAL */
- if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
- PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL;
- while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));
- }
- /* Disable Fast RC */
- PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCEN &
- ~CKGR_MOR_MOSCRCF_Msk)
- | CKGR_MOR_KEY_PASSWD;
- }
-
- if (pll0_setting & CKGR_PLLAR_MULA_Msk) {
-#if (SAM4C || SAM4CM || SAMG || SAM4CP)
- PMC->CKGR_PLLAR = pll0_setting;
-#else
- PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | pll0_setting;
-#endif
- pll_sr |= PMC_SR_LOCKA;
- }
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP)
- if (pll1_setting & CKGR_PLLBR_MULB_Msk) {
- PMC->CKGR_PLLBR = pll1_setting;
- pll_sr |= PMC_SR_LOCKB;
- }
-#elif (SAM3U || SAM3XA)
- if (pll1_setting & CKGR_UCKR_UPLLEN) {
- PMC->CKGR_UCKR = pll1_setting;
- pll_sr |= PMC_SR_LOCKU;
- }
-#else
- UNUSED(pll1_setting);
-#endif
- /* Wait MCK source ready */
- switch(mck_setting & PMC_MCKR_CSS_Msk) {
- case PMC_MCKR_CSS_PLLA_CLK:
- while (!(PMC->PMC_SR & PMC_SR_LOCKA));
- break;
-#if (SAM3S || SAM4S || SAM4C || SAM4CM || SAM4CP)
- case PMC_MCKR_CSS_PLLB_CLK:
- while (!(PMC->PMC_SR & PMC_SR_LOCKB));
- break;
-#elif (SAM3U || SAM3XA)
- case PMC_MCKR_CSS_UPLL_CLK:
- while (!(PMC->PMC_SR & PMC_SR_LOCKU));
- break;
-#endif
- }
-
- /* Switch to faster clock */
- mckr = PMC->PMC_MCKR;
-
- /* Set PRES */
- PMC->PMC_MCKR = (mckr & ~PMC_MCKR_PRES_Msk)
- | (mck_setting & PMC_MCKR_PRES_Msk);
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-
- /* Restore flash wait states */
- EFC0->EEFC_FMR = fmr_setting;
-#if defined(EFC1)
- EFC1->EEFC_FMR = fmr_setting1;
-#endif
-
- /* Set CSS and others */
- PMC->PMC_MCKR = mck_setting;
- while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
-
- /* Waiting all restored PLLs ready */
- while (!(PMC->PMC_SR & pll_sr));
-}
-
-/** If clocks are switched for some sleep mode */
-static volatile bool b_is_sleep_clock_used = false;
-/** Callback invoked once when clocks are restored */
-static pmc_callback_wakeup_clocks_restored_t callback_clocks_restored = NULL;
-
-void pmc_sleep(int sleep_mode)
-{
- switch (sleep_mode) {
- case SAM_PM_SMODE_SLEEP_WFI:
- case SAM_PM_SMODE_SLEEP_WFE:
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAMS70 || SAME70)
- SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;
- cpu_irq_enable();
- __DSB();
- __WFI();
- break;
-#else
- PMC->PMC_FSMR &= (uint32_t)~PMC_FSMR_LPM;
- SCB->SCR &= (uint32_t)~SCR_SLEEPDEEP;
- cpu_irq_enable();
- if (sleep_mode == SAM_PM_SMODE_SLEEP_WFI) {
- __DSB();
- __WFI();
- } else {
- __DSB();
- __WFE();
- }
- break;
-#endif
-
- case SAM_PM_SMODE_WAIT_FAST:
- case SAM_PM_SMODE_WAIT: {
- uint32_t mor, pllr0, pllr1, mckr;
- uint32_t fmr;
-#if defined(EFC1)
- uint32_t fmr1;
-#endif
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAMS70 || SAME70)
- (sleep_mode == SAM_PM_SMODE_WAIT_FAST) ?
- pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_STANDBY) :
- pmc_set_flash_in_wait_mode(PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN);
-#endif
- cpu_irq_disable();
- b_is_sleep_clock_used = true;
-
-#if (SAM4C || SAM4CM || SAM4CP)
- /* Backup the sub-system 1 status and stop sub-system 1 */
- uint32_t cpclk_backup = PMC->PMC_SCSR &
- (PMC_SCSR_CPCK | PMC_SCSR_CPBMCK);
- PMC->PMC_SCDR = cpclk_backup | PMC_SCDR_CPKEY_PASSWD;
-#endif
- pmc_save_clock_settings(&mor, &pllr0, &pllr1, &mckr, &fmr,
-#if defined(EFC1)
- &fmr1,
-#endif
- (sleep_mode == SAM_PM_SMODE_WAIT));
-
- /* Enter wait mode */
- cpu_irq_enable();
-
- pmc_enable_waitmode();
-
- cpu_irq_disable();
- pmc_restore_clock_setting(mor, pllr0, pllr1, mckr, fmr
-#if defined(EFC1)
- , fmr1
-#endif
- );
-
-#if (SAM4C || SAM4CM || SAM4CP)
- /* Restore the sub-system 1 */
- PMC->PMC_SCER = cpclk_backup | PMC_SCER_CPKEY_PASSWD;
-#endif
- b_is_sleep_clock_used = false;
- if (callback_clocks_restored) {
- callback_clocks_restored();
- callback_clocks_restored = NULL;
- }
- cpu_irq_enable();
-
- break;
- }
-#if (!(SAMG51 || SAMG53 || SAMG54))
- case SAM_PM_SMODE_BACKUP:
- SCB->SCR |= SCR_SLEEPDEEP;
-#if (SAM4S || SAM4E || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG55 || SAMV71 || SAMV70 || SAMS70 || SAME70)
- SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF_STOP_VREG;
- cpu_irq_enable();
- __WFI() ;
-#else
- cpu_irq_enable();
- __WFE() ;
-#endif
- break;
-#endif
- }
-}
-
-bool pmc_is_wakeup_clocks_restored(void)
-{
- return !b_is_sleep_clock_used;
-}
-
-void pmc_wait_wakeup_clocks_restore(
- pmc_callback_wakeup_clocks_restored_t callback)
-{
- if (b_is_sleep_clock_used) {
- cpu_irq_disable();
- callback_clocks_restored = callback;
- } else if (callback) {
- callback();
- }
-}
-
-#endif
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/drivers/pmc/sleep.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/drivers/pmc/sleep.h
deleted file mode 100644
index 868c57f..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/drivers/pmc/sleep.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/**
- * \file
- *
- * \brief Sleep mode access
- *
- * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef SLEEP_H
-#define SLEEP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <compiler.h>
-
-/**
- * \defgroup sleep_group Power Manager (PM)
- *
- * This is a stub on the SAM Power Manager Control (PMC) for the sleepmgr
- * service.
- *
- * \note To minimize the code overhead, these functions do not feature
- * interrupt-protected access since they are likely to be called inside
- * interrupt handlers or in applications where such protection is not
- * necessary. If such protection is needed, it must be ensured by the calling
- * code.
- *
- * @{
- */
-
-#if defined(__DOXYGEN__)
-/**
- * \brief Sets the MCU in the specified sleep mode
- * \param sleep_mode Sleep mode to set.
- */
-#endif
-/* SAM3,SAM4,SAMG,SAMV,SAME and SAMS series */
-#if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \
- SAM4CM || SAM4CP || SAMG || SAMV71 || SAME70 || SAMS70)
-# define SAM_PM_SMODE_ACTIVE 0 /**< Active */
-# define SAM_PM_SMODE_SLEEP_WFE 1 /**< Wait for Events */
-# define SAM_PM_SMODE_SLEEP_WFI 2 /**< Wait for Interrupts */
-# define SAM_PM_SMODE_WAIT_FAST 3 /**< Wait Mode, startup fast (in 3ms) */
-# define SAM_PM_SMODE_WAIT 4 /**< Wait Mode */
-#if (!(SAMG51 || SAMG53 || SAMG54))
-# define SAM_PM_SMODE_BACKUP 5 /**< Backup Mode */
-#endif
-
-/** (SCR) Sleep deep bit */
-#define SCR_SLEEPDEEP (0x1 << 2)
-
-/**
- * Clocks restored callback function type.
- * Registered by routine pmc_wait_wakeup_clocks_restore()
- * Callback called when all clocks are restored.
- */
-typedef void (*pmc_callback_wakeup_clocks_restored_t) (void);
-
-/**
- * Enter sleep mode
- * \param sleep_mode Sleep mode to enter
- */
-void pmc_sleep(int sleep_mode);
-
-/**
- * Check if clocks are restored after wakeup
- * (For WAIT mode. In WAIT mode, clocks are switched to FASTRC.
- * After wakeup clocks should be restored, before that some of the
- * ISR should not be served, otherwise there may be timing or clock issue.)
- */
-bool pmc_is_wakeup_clocks_restored(void);
-
-/**
- * \return true if start waiting
- */
-void pmc_wait_wakeup_clocks_restore(
- pmc_callback_wakeup_clocks_restored_t callback);
-
-#endif
-
-//! @}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SLEEP_H */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/acc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/acc.h
deleted file mode 100644
index 9b87664..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/acc.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_ACC_COMPONENT_
-#define _SAMS70_ACC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_ACC Analog Comparator Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Acc hardware registers */
-typedef struct {
- __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */
- __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */
- __I uint32_t Reserved1[7];
- __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */
- __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */
- __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */
- __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */
- __I uint32_t Reserved2[24];
- __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */
- __I uint32_t Reserved3[19];
- __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */
- __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */
-} Acc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
-#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */
-/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
-#define ACC_MR_SELMINUS_Pos 0
-#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */
-#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos)))
-#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */
-#define ACC_MR_SELMINUS_ADVREFP (0x1u << 0) /**< \brief (ACC_MR) Select ADVREFP */
-#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */
-#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */
-#define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AFE0_AD0 */
-#define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AFE0_AD1 */
-#define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AFE0_AD2 */
-#define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AFE0_AD3 */
-#define ACC_MR_SELPLUS_Pos 4
-#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */
-#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos)))
-#define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AFE0_AD0 */
-#define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AFE0_AD1 */
-#define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AFE0_AD2 */
-#define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AFE0_AD3 */
-#define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AFE0_AD4 */
-#define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AFE0_AD5 */
-#define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) /**< \brief (ACC_MR) Select AFE1_AD0 */
-#define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) /**< \brief (ACC_MR) Select AFE1_AD1 */
-#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */
-#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */
-#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */
-#define ACC_MR_EDGETYP_Pos 9
-#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */
-#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos)))
-#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */
-#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */
-#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */
-#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */
-#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */
-#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */
-#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */
-#define ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */
-#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */
-#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */
-#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */
-#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */
-/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
-#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */
-/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
-#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */
-/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
-#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */
-/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
-#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */
-#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */
-#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */
-/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
-#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */
-#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */
-#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */
-#define ACC_ACR_HYST_Pos 1
-#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */
-#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))
-/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */
-#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */
-#define ACC_WPMR_WPKEY_Pos 8
-#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */
-#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))
-#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
-/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */
-#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */
-
-/*@}*/
-
-
-#endif /* _SAMS70_ACC_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/aes.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/aes.h
deleted file mode 100644
index 963f22a..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/aes.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_AES_COMPONENT_
-#define _SAMS70_AES_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */
-/* ============================================================================= */
-/** \addtogroup SAMS70_AES Advanced Encryption Standard */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Aes hardware registers */
-typedef struct {
- __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */
- __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */
- __I uint32_t Reserved1[2];
- __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */
- __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */
- __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */
- __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */
- __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */
- __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */
- __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */
- __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */
- __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */
- __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */
- __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */
- __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */
- __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */
- __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H Word Register */
-} Aes;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */
-#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */
-#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */
-/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */
-#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */
-#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */
-#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */
-#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */
-#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. */
-#define AES_MR_PROCDLY_Pos 4
-#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */
-#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)))
-#define AES_MR_SMOD_Pos 8
-#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */
-#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos)))
-#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */
-#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */
-#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */
-#define AES_MR_KEYSIZE_Pos 10
-#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */
-#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos)))
-#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */
-#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */
-#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */
-#define AES_MR_OPMOD_Pos 12
-#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */
-#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos)))
-#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */
-#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */
-#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */
-#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */
-#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */
-#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */
-#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */
-#define AES_MR_CFBS_Pos 16
-#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */
-#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos)))
-#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */
-#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */
-#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */
-#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */
-#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */
-#define AES_MR_CKEY_Pos 20
-#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Key */
-#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)))
-#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE the first time that AES_MR is programmed. For subsequent programming of the AES_MR, any value can be written, including that of 0xE.Always reads as 0. */
-/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */
-#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */
-#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */
-#define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */
-/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */
-#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */
-#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */
-#define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */
-/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */
-#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */
-#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */
-#define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */
-/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */
-#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */
-#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */
-#define AES_ISR_URAT_Pos 12
-#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */
-#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */
-#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */
-#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */
-#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */
-#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */
-#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */
-#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */
-/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */
-#define AES_KEYWR_KEYW_Pos 0
-#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */
-#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)))
-/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */
-#define AES_IDATAR_IDATA_Pos 0
-#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */
-#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)))
-/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */
-#define AES_ODATAR_ODATA_Pos 0
-#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */
-/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */
-#define AES_IVR_IV_Pos 0
-#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */
-#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)))
-/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */
-#define AES_AADLENR_AADLEN_Pos 0
-#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */
-#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)))
-/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */
-#define AES_CLENR_CLEN_Pos 0
-#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */
-#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)))
-/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */
-#define AES_GHASHR_GHASH_Pos 0
-#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */
-#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)))
-/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */
-#define AES_TAGR_TAG_Pos 0
-#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */
-/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */
-#define AES_CTRR_CTR_Pos 0
-#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */
-/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */
-#define AES_GCMHR_H_Pos 0
-#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */
-#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)))
-
-/*@}*/
-
-
-#endif /* _SAMS70_AES_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/afec.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/afec.h
deleted file mode 100644
index f8ee47e..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/afec.h
+++ /dev/null
@@ -1,498 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_AFEC_COMPONENT_
-#define _SAMS70_AFEC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Analog Front-End Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_AFEC Analog Front-End Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Afec hardware registers */
-typedef struct {
- __O uint32_t AFEC_CR; /**< \brief (Afec Offset: 0x00) AFEC Control Register */
- __IO uint32_t AFEC_MR; /**< \brief (Afec Offset: 0x04) AFEC Mode Register */
- __IO uint32_t AFEC_EMR; /**< \brief (Afec Offset: 0x08) AFEC Extended Mode Register */
- __IO uint32_t AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register */
- __IO uint32_t AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) AFEC Channel Sequence 2 Register */
- __O uint32_t AFEC_CHER; /**< \brief (Afec Offset: 0x14) AFEC Channel Enable Register */
- __O uint32_t AFEC_CHDR; /**< \brief (Afec Offset: 0x18) AFEC Channel Disable Register */
- __I uint32_t AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) AFEC Channel Status Register */
- __I uint32_t AFEC_LCDR; /**< \brief (Afec Offset: 0x20) AFEC Last Converted Data Register */
- __O uint32_t AFEC_IER; /**< \brief (Afec Offset: 0x24) AFEC Interrupt Enable Register */
- __O uint32_t AFEC_IDR; /**< \brief (Afec Offset: 0x28) AFEC Interrupt Disable Register */
- __I uint32_t AFEC_IMR; /**< \brief (Afec Offset: 0x2C) AFEC Interrupt Mask Register */
- __I uint32_t AFEC_ISR; /**< \brief (Afec Offset: 0x30) AFEC Interrupt Status Register */
- __I uint32_t Reserved1[6];
- __I uint32_t AFEC_OVER; /**< \brief (Afec Offset: 0x4C) AFEC Overrun Status Register */
- __IO uint32_t AFEC_CWR; /**< \brief (Afec Offset: 0x50) AFEC Compare Window Register */
- __IO uint32_t AFEC_CGR; /**< \brief (Afec Offset: 0x54) AFEC Channel Gain Register */
- __I uint32_t Reserved2[2];
- __IO uint32_t AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) AFEC Channel Differential Register */
- __IO uint32_t AFEC_CSELR; /**< \brief (Afec Offset: 0x64) AFEC Channel Selection Register */
- __I uint32_t AFEC_CDR; /**< \brief (Afec Offset: 0x68) AFEC Channel Data Register */
- __IO uint32_t AFEC_COCR; /**< \brief (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register */
- __IO uint32_t AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register */
- __IO uint32_t AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) AFEC Temperature Compare Window Register */
- __I uint32_t Reserved3[7];
- __IO uint32_t AFEC_ACR; /**< \brief (Afec Offset: 0x94) AFEC Analog Control Register */
- __I uint32_t Reserved4[2];
- __IO uint32_t AFEC_SHMR; /**< \brief (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register */
- __I uint32_t Reserved5[11];
- __IO uint32_t AFEC_COSR; /**< \brief (Afec Offset: 0xD0) AFEC Correction Select Register */
- __IO uint32_t AFEC_CVR; /**< \brief (Afec Offset: 0xD4) AFEC Correction Values Register */
- __IO uint32_t AFEC_CECR; /**< \brief (Afec Offset: 0xD8) AFEC Channel Error Correction Register */
- __I uint32_t Reserved6[2];
- __IO uint32_t AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) AFEC Write Protection Mode Register */
- __I uint32_t AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) AFEC Write Protection Status Register */
-} Afec;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */
-#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */
-#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */
-/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */
-#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */
-#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
-#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */
-#define AFEC_MR_TRGSEL_Pos 1
-#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */
-#define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos)))
-#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */
-#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */
-#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */
-#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */
-#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */
-#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */
-#define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) /**< \brief (AFEC_MR) Analog Comparator */
-#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */
-#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */
-#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */
-#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake-up */
-#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */
-#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */
-#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */
-#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal mode */
-#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run mode: Never wait for any trigger. */
-#define AFEC_MR_PRESCAL_Pos 8
-#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */
-#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos)))
-#define AFEC_MR_STARTUP_Pos 16
-#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start-up Time */
-#define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos)))
-#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFE clock */
-#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFE clock */
-#define AFEC_MR_ONE (0x1u << 23) /**< \brief (AFEC_MR) One */
-#define AFEC_MR_TRACKTIM_Pos 24
-#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */
-#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos)))
-#define AFEC_MR_TRANSFER_Pos 28
-#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */
-#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos)))
-#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Enable */
-#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */
-#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */
-/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */
-#define AFEC_EMR_CMPMODE_Pos 0
-#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */
-#define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos)))
-#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
-#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
-#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */
-#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */
-#define AFEC_EMR_CMPSEL_Pos 3
-#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */
-#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos)))
-#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */
-#define AFEC_EMR_CMPFILTER_Pos 12
-#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */
-#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos)))
-#define AFEC_EMR_RES_Pos 16
-#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */
-#define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos)))
-#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */
-#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */
-#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */
-#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */
-#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */
-#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR */
-#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */
-#define AFEC_EMR_SIGNMODE_Pos 28
-#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) /**< \brief (AFEC_EMR) Sign Mode */
-#define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos)))
-#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */
-#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */
-#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) /**< \brief (AFEC_EMR) All channels: Unsigned conversions. */
-#define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) /**< \brief (AFEC_EMR) All channels: Signed conversions. */
-/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */
-#define AFEC_SEQ1R_USCH0_Pos 0
-#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */
-#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos)))
-#define AFEC_SEQ1R_USCH1_Pos 4
-#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */
-#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos)))
-#define AFEC_SEQ1R_USCH2_Pos 8
-#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */
-#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos)))
-#define AFEC_SEQ1R_USCH3_Pos 12
-#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */
-#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos)))
-#define AFEC_SEQ1R_USCH4_Pos 16
-#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */
-#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos)))
-#define AFEC_SEQ1R_USCH5_Pos 20
-#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */
-#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos)))
-#define AFEC_SEQ1R_USCH6_Pos 24
-#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */
-#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos)))
-#define AFEC_SEQ1R_USCH7_Pos 28
-#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */
-#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos)))
-/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */
-#define AFEC_SEQ2R_USCH8_Pos 0
-#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */
-#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos)))
-#define AFEC_SEQ2R_USCH9_Pos 4
-#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */
-#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos)))
-#define AFEC_SEQ2R_USCH10_Pos 8
-#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */
-#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos)))
-#define AFEC_SEQ2R_USCH11_Pos 12
-#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */
-#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos)))
-#define AFEC_SEQ2R_USCH12_Pos 16
-#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */
-#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos)))
-#define AFEC_SEQ2R_USCH13_Pos 20
-#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */
-#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos)))
-#define AFEC_SEQ2R_USCH14_Pos 24
-#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */
-#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos)))
-#define AFEC_SEQ2R_USCH15_Pos 28
-#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */
-#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos)))
-/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */
-#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */
-#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */
-#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */
-#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */
-#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */
-#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */
-#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */
-#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */
-#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */
-#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */
-#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */
-#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */
-/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */
-#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */
-#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */
-#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */
-#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */
-#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */
-#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */
-#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */
-#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */
-#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */
-#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */
-#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */
-#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */
-/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */
-#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */
-#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */
-#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */
-#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */
-#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */
-#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */
-#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */
-#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */
-#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */
-#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */
-#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */
-#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */
-/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */
-#define AFEC_LCDR_LDATA_Pos 0
-#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */
-#define AFEC_LCDR_CHNB_Pos 24
-#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */
-/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */
-#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */
-#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */
-#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */
-#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */
-#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */
-#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */
-#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */
-#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */
-#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */
-#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */
-#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */
-#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */
-#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */
-#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */
-#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable */
-#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */
-/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */
-#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */
-#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */
-#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */
-#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */
-#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */
-#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */
-#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */
-#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */
-#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */
-#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */
-#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */
-#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */
-#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */
-#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */
-#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */
-#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */
-/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */
-#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */
-#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */
-#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */
-#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */
-#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */
-#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */
-#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */
-#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */
-#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */
-#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */
-#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */
-#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */
-#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */
-#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */
-#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */
-#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */
-/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */
-#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) */
-#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) */
-#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) */
-#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) */
-#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change (cleared on read) */
-/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */
-#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */
-#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */
-#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */
-#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */
-#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */
-#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */
-#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */
-#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */
-#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */
-#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */
-#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */
-#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */
-/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */
-#define AFEC_CWR_LOWTHRES_Pos 0
-#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */
-#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos)))
-#define AFEC_CWR_HIGHTHRES_Pos 16
-#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */
-#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos)))
-/* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */
-#define AFEC_CGR_GAIN0_Pos 0
-#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for Channel 0 */
-#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos)))
-#define AFEC_CGR_GAIN1_Pos 2
-#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for Channel 1 */
-#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos)))
-#define AFEC_CGR_GAIN2_Pos 4
-#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for Channel 2 */
-#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos)))
-#define AFEC_CGR_GAIN3_Pos 6
-#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for Channel 3 */
-#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos)))
-#define AFEC_CGR_GAIN4_Pos 8
-#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for Channel 4 */
-#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos)))
-#define AFEC_CGR_GAIN5_Pos 10
-#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for Channel 5 */
-#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos)))
-#define AFEC_CGR_GAIN6_Pos 12
-#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for Channel 6 */
-#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos)))
-#define AFEC_CGR_GAIN7_Pos 14
-#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for Channel 7 */
-#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos)))
-#define AFEC_CGR_GAIN8_Pos 16
-#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for Channel 8 */
-#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos)))
-#define AFEC_CGR_GAIN9_Pos 18
-#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for Channel 9 */
-#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos)))
-#define AFEC_CGR_GAIN10_Pos 20
-#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for Channel 10 */
-#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos)))
-#define AFEC_CGR_GAIN11_Pos 22
-#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for Channel 11 */
-#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos)))
-/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */
-#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */
-#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */
-#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */
-#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */
-#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */
-#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */
-#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */
-#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */
-#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */
-#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */
-#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */
-#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */
-/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */
-#define AFEC_CSELR_CSEL_Pos 0
-#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */
-#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos)))
-/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */
-#define AFEC_CDR_DATA_Pos 0
-#define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */
-/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */
-#define AFEC_COCR_AOFF_Pos 0
-#define AFEC_COCR_AOFF_Msk (0xfffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */
-#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos)))
-/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */
-#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode */
-#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4
-#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */
-#define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos)))
-#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */
-#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */
-#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */
-#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */
-/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */
-#define AFEC_TEMPCWR_TLOWTHRES_Pos 0
-#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */
-#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos)))
-#define AFEC_TEMPCWR_THIGHTHRES_Pos 16
-#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */
-#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos)))
-/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */
-#define AFEC_ACR_PGA0EN (0x1u << 2) /**< \brief (AFEC_ACR) PGA0 Enable */
-#define AFEC_ACR_PGA1EN (0x1u << 3) /**< \brief (AFEC_ACR) PGA1 Enable */
-#define AFEC_ACR_IBCTL_Pos 8
-#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFE Bias Current Control */
-#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos)))
-/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */
-#define AFEC_SHMR_DUAL0 (0x1u << 0) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 0 */
-#define AFEC_SHMR_DUAL1 (0x1u << 1) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 1 */
-#define AFEC_SHMR_DUAL2 (0x1u << 2) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 2 */
-#define AFEC_SHMR_DUAL3 (0x1u << 3) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 3 */
-#define AFEC_SHMR_DUAL4 (0x1u << 4) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 4 */
-#define AFEC_SHMR_DUAL5 (0x1u << 5) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 5 */
-#define AFEC_SHMR_DUAL6 (0x1u << 6) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 6 */
-#define AFEC_SHMR_DUAL7 (0x1u << 7) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 7 */
-#define AFEC_SHMR_DUAL8 (0x1u << 8) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 8 */
-#define AFEC_SHMR_DUAL9 (0x1u << 9) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 9 */
-#define AFEC_SHMR_DUAL10 (0x1u << 10) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 10 */
-#define AFEC_SHMR_DUAL11 (0x1u << 11) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 11 */
-/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */
-#define AFEC_COSR_CSEL (0x1u << 0) /**< \brief (AFEC_COSR) Sample & Hold unit Correction Select */
-/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */
-#define AFEC_CVR_OFFSETCORR_Pos 0
-#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) /**< \brief (AFEC_CVR) Offset Correction */
-#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos)))
-#define AFEC_CVR_GAINCORR_Pos 16
-#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) /**< \brief (AFEC_CVR) Gain Correction */
-#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos)))
-/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */
-#define AFEC_CECR_ECORR0 (0x1u << 0) /**< \brief (AFEC_CECR) Error Correction Enable for channel 0 */
-#define AFEC_CECR_ECORR1 (0x1u << 1) /**< \brief (AFEC_CECR) Error Correction Enable for channel 1 */
-#define AFEC_CECR_ECORR2 (0x1u << 2) /**< \brief (AFEC_CECR) Error Correction Enable for channel 2 */
-#define AFEC_CECR_ECORR3 (0x1u << 3) /**< \brief (AFEC_CECR) Error Correction Enable for channel 3 */
-#define AFEC_CECR_ECORR4 (0x1u << 4) /**< \brief (AFEC_CECR) Error Correction Enable for channel 4 */
-#define AFEC_CECR_ECORR5 (0x1u << 5) /**< \brief (AFEC_CECR) Error Correction Enable for channel 5 */
-#define AFEC_CECR_ECORR6 (0x1u << 6) /**< \brief (AFEC_CECR) Error Correction Enable for channel 6 */
-#define AFEC_CECR_ECORR7 (0x1u << 7) /**< \brief (AFEC_CECR) Error Correction Enable for channel 7 */
-#define AFEC_CECR_ECORR8 (0x1u << 8) /**< \brief (AFEC_CECR) Error Correction Enable for channel 8 */
-#define AFEC_CECR_ECORR9 (0x1u << 9) /**< \brief (AFEC_CECR) Error Correction Enable for channel 9 */
-#define AFEC_CECR_ECORR10 (0x1u << 10) /**< \brief (AFEC_CECR) Error Correction Enable for channel 10 */
-#define AFEC_CECR_ECORR11 (0x1u << 11) /**< \brief (AFEC_CECR) Error Correction Enable for channel 11 */
-/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */
-#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protection Enable */
-#define AFEC_WPMR_WPKEY_Pos 8
-#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */
-#define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos)))
-#define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
-/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */
-#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */
-#define AFEC_WPSR_WPVSRC_Pos 8
-#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_AFEC_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/chipid.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/chipid.h
deleted file mode 100644
index 57f14ab..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/chipid.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_CHIPID_COMPONENT_
-#define _SAMS70_CHIPID_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Chip Identifier */
-/* ============================================================================= */
-/** \addtogroup SAMS70_CHIPID Chip Identifier */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Chipid hardware registers */
-typedef struct {
- __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
- __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
-} Chipid;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
-#define CHIPID_CIDR_VERSION_Pos 0
-#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
-#define CHIPID_CIDR_EPROC_Pos 5
-#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
-#define CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) /**< \brief (CHIPID_CIDR) Cortex-M7 */
-#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
-#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
-#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
-#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
-#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
-#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
-#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
-#define CHIPID_CIDR_NVPSIZ_Pos 8
-#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
-#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
-#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */
-#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_Pos 12
-#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
-#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
-#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */
-#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_Pos 16
-#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
-#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */
-#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */
-#define CHIPID_CIDR_ARCH_Pos 20
-#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
-#define CHIPID_CIDR_ARCH_SAME70 (0x10u << 20) /**< \brief (CHIPID_CIDR) SAM E70 */
-#define CHIPID_CIDR_ARCH_SAMS70 (0x11u << 20) /**< \brief (CHIPID_CIDR) SAM S70 */
-#define CHIPID_CIDR_ARCH_SAMV71 (0x12u << 20) /**< \brief (CHIPID_CIDR) SAM V71 */
-#define CHIPID_CIDR_ARCH_SAMV70 (0x13u << 20) /**< \brief (CHIPID_CIDR) SAM V70 */
-#define CHIPID_CIDR_NVPTYP_Pos 28
-#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
-#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
-#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
-#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
-#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */
-#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
-#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
-/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
-#define CHIPID_EXID_EXID_Pos 0
-#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
-
-/*@}*/
-
-
-#endif /* _SAMS70_CHIPID_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/dacc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/dacc.h
deleted file mode 100644
index 7aec4a9..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/dacc.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_DACC_COMPONENT_
-#define _SAMS70_DACC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_DACC Digital-to-Analog Converter Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Dacc hardware registers */
-typedef struct {
- __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */
- __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */
- __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */
- __I uint32_t Reserved1[1];
- __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */
- __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */
- __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */
- __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */
- __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */
- __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */
- __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */
- __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */
- __I uint32_t Reserved2[24];
- __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */
- __I uint32_t Reserved3[19];
- __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode register */
- __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status register */
-} Dacc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
-#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
-/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
-#define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */
-#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) Triggered by selected event */
-#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode enabled */
-#define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */
-#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) Triggered by selected event */
-#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode enabled */
-#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */
-#define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC */
-#define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces number of requests to DMA and the number of system bus accesses) */
-#define DACC_MR_REFRESH_Pos 8
-#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */
-#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos)))
-#define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */
-#define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 outputs can be separately configured */
-#define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN outputs are configured by the channel 0 value. */
-#define DACC_MR_PRESCALER_Pos 24
-#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */
-#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos)))
-/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */
-#define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */
-#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */
-#define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */
-#define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */
-#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */
-#define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */
-#define DACC_TRIGR_TRGSEL0_Pos 4
-#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */
-#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos)))
-#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) TC0 output */
-#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TC1 output */
-#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TC2 output */
-#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) PWM0 event 0 */
-#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) PWM0 event 1 */
-#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) PWM1 event 0 */
-#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) PWM1 event 1 */
-#define DACC_TRIGR_TRGSEL1_Pos 8
-#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */
-#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos)))
-#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) TC0 output */
-#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TC1 output */
-#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TC2 output */
-#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) PWM0 event 0 */
-#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) PWM0 event 1 */
-#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) PWM1 event 0 */
-#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) PWM1 event 1 */
-#define DACC_TRIGR_OSR0_Pos 16
-#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */
-#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos)))
-#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */
-#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */
-#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */
-#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */
-#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */
-#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */
-#define DACC_TRIGR_OSR1_Pos 20
-#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */
-#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos)))
-#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */
-#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */
-#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */
-#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */
-#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */
-#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */
-/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */
-#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */
-#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */
-/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */
-#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */
-#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */
-/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */
-#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */
-#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */
-#define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC ready flag */
-#define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC ready flag */
-/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */
-#define DACC_CDR_DATA0_Pos 0
-#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */
-#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos)))
-#define DACC_CDR_DATA1_Pos 16
-#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */
-#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos)))
-/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */
-#define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */
-#define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */
-#define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */
-#define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */
-#define DACC_IER_ENDTX0 (0x1u << 8) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 0 */
-#define DACC_IER_ENDTX1 (0x1u << 9) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 1 */
-#define DACC_IER_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 0 */
-#define DACC_IER_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 1 */
-/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */
-#define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */
-#define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */
-#define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */
-#define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */
-#define DACC_IDR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 0 */
-#define DACC_IDR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 1 */
-#define DACC_IDR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 0 */
-#define DACC_IDR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 1 */
-/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */
-#define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */
-#define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */
-#define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */
-#define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */
-#define DACC_IMR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 0 */
-#define DACC_IMR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 1 */
-#define DACC_IMR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 0 */
-#define DACC_IMR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 1 */
-/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */
-#define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */
-#define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */
-#define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */
-#define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */
-#define DACC_ISR_ENDTX0 (0x1u << 8) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 0 */
-#define DACC_ISR_ENDTX1 (0x1u << 9) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 1 */
-#define DACC_ISR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 0 */
-#define DACC_ISR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 1 */
-/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */
-#define DACC_ACR_IBCTLCH0_Pos 0
-#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
-#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos)))
-#define DACC_ACR_IBCTLCH1_Pos 2
-#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */
-#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos)))
-/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode register -------- */
-#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */
-#define DACC_WPMR_WPKEY_Pos 8
-#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */
-#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
-#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */
-/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status register -------- */
-#define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */
-#define DACC_WPSR_WPVSRC_Pos 8
-#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_DACC_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/efc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/efc.h
deleted file mode 100644
index e316688..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/efc.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_EFC_COMPONENT_
-#define _SAMS70_EFC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_EFC Embedded Flash Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Efc hardware registers */
-typedef struct {
- __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
- __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
- __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
- __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
- __I uint32_t Reserved1[1];
- __I uint32_t EEFC_VERSION; /**< \brief (Efc Offset: 0x14) EEFC Version Register */
- __I uint32_t Reserved2[51];
- __IO uint32_t EEFC_WPMR; /**< \brief (Efc Offset: 0xE4) Write Protection Mode Register */
-} Efc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
-#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Flash Ready Interrupt Enable */
-#define EEFC_FMR_FWS_Pos 8
-#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
-#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
-#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
-#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */
-/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
-#define EEFC_FCR_FCMD_Pos 0
-#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
-#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
-#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */
-#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */
-#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */
-#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */
-#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */
-#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */
-#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */
-#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */
-#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */
-#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */
-#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */
-#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */
-#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */
-#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */
-#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */
-#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */
-#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */
-#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */
-#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */
-#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */
-#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */
-#define EEFC_FCR_FARG_Pos 8
-#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
-#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
-#define EEFC_FCR_FKEY_Pos 24
-#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
-#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
-#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */
-/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
-#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) */
-#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) */
-#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status (cleared on read) */
-#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) */
-#define EEFC_FSR_UECCELSB (0x1u << 16) /**< \brief (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */
-#define EEFC_FSR_MECCELSB (0x1u << 17) /**< \brief (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */
-#define EEFC_FSR_UECCEMSB (0x1u << 18) /**< \brief (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */
-#define EEFC_FSR_MECCEMSB (0x1u << 19) /**< \brief (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */
-/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
-#define EEFC_FRR_FVALUE_Pos 0
-#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
-/* -------- EEFC_VERSION : (EFC Offset: 0x14) EEFC Version Register -------- */
-#define EEFC_VERSION_VERSION_Pos 0
-#define EEFC_VERSION_VERSION_Msk (0xfffu << EEFC_VERSION_VERSION_Pos) /**< \brief (EEFC_VERSION) Version of the Hardware Module */
-#define EEFC_VERSION_MFN_Pos 16
-#define EEFC_VERSION_MFN_Msk (0x7u << EEFC_VERSION_MFN_Pos) /**< \brief (EEFC_VERSION) Metal Fix Number */
-/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */
-#define EEFC_WPMR_WPEN (0x1u << 0) /**< \brief (EEFC_WPMR) Write Protection Enable */
-#define EEFC_WPMR_WPKEY_Pos 8
-#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) /**< \brief (EEFC_WPMR) Write Protection Key */
-#define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos)))
-#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) /**< \brief (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */
-
-/*@}*/
-
-
-#endif /* _SAMS70_EFC_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/gpbr.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/gpbr.h
deleted file mode 100644
index 21de664..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/gpbr.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_GPBR_COMPONENT_
-#define _SAMS70_GPBR_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */
-/* ============================================================================= */
-/** \addtogroup SAMS70_GPBR General Purpose Backup Registers */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Gpbr hardware registers */
-typedef struct {
- __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
-} Gpbr;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
-#define SYS_GPBR_GPBR_VALUE_Pos 0
-#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */
-#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
-
-/*@}*/
-
-
-#endif /* _SAMS70_GPBR_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/hsmci.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/hsmci.h
deleted file mode 100644
index ef86451..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/hsmci.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_HSMCI_COMPONENT_
-#define _SAMS70_HSMCI_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
-/* ============================================================================= */
-/** \addtogroup SAMS70_HSMCI High Speed MultiMedia Card Interface */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Hsmci hardware registers */
-typedef struct {
- __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */
- __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */
- __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
- __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
- __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */
- __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */
- __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */
- __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
- __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */
- __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
- __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
- __I uint32_t Reserved1[2];
- __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */
- __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
- __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
- __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
- __IO uint32_t HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */
- __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */
- __I uint32_t Reserved2[35];
- __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
- __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
- __I uint32_t Reserved3[69];
- __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
-} Hsmci;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
-#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
-#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
-#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
-#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
-#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
-/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
-#define HSMCI_MR_CLKDIV_Pos 0
-#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
-#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
-#define HSMCI_MR_PWSDIV_Pos 8
-#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
-#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
-#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */
-#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */
-#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
-#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
-#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */
-/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
-#define HSMCI_DTOR_DTOCYC_Pos 0
-#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
-#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
-#define HSMCI_DTOR_DTOMUL_Pos 4
-#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
-#define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos)))
-#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
-#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
-#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
-#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
-#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
-#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
-#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
-#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
-/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
-#define HSMCI_SDCR_SDCSEL_Pos 0
-#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
-#define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos)))
-#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
-#define HSMCI_SDCR_SDCBUS_Pos 6
-#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
-#define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos)))
-#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
-#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bits */
-#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bits */
-/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
-#define HSMCI_ARGR_ARG_Pos 0
-#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
-#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
-/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
-#define HSMCI_CMDR_CMDNB_Pos 0
-#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
-#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
-#define HSMCI_CMDR_RSPTYP_Pos 6
-#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
-#define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos)))
-#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response */
-#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response */
-#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response */
-#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
-#define HSMCI_CMDR_SPCMD_Pos 8
-#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
-#define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos)))
-#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
-#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
-#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
-#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
-#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
-#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
-#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
-#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
-#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
-#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
-#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
-#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
-#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
-#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
-#define HSMCI_CMDR_TRCMD_Pos 16
-#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
-#define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos)))
-#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
-#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
-#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
-#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
-#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
-#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
-#define HSMCI_CMDR_TRTYP_Pos 19
-#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
-#define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos)))
-#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */
-#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */
-#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
-#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
-#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
-#define HSMCI_CMDR_IOSPCMD_Pos 24
-#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
-#define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos)))
-#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
-#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
-#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
-#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
-#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
-#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
-#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge */
-/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
-#define HSMCI_BLKR_BCNT_Pos 0
-#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
-#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos)))
-#define HSMCI_BLKR_BLKLEN_Pos 16
-#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
-#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
-/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
-#define HSMCI_CSTOR_CSTOCYC_Pos 0
-#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
-#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
-#define HSMCI_CSTOR_CSTOMUL_Pos 4
-#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
-#define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos)))
-#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
-#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
-#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
-#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
-#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
-#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
-#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
-#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
-/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
-#define HSMCI_RSPR_RSP_Pos 0
-#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
-/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
-#define HSMCI_RDR_DATA_Pos 0
-#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
-/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
-#define HSMCI_TDR_DATA_Pos 0
-#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
-#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
-/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
-#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) */
-#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) */
-#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) */
-#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended (cleared on read) */
-#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) */
-#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
-#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) */
-#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
-#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) */
-#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) */
-#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) */
-#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) */
-#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) */
-#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) */
-#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error (cleared on read) */
-#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error (cleared on read) */
-#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error (cleared on read) */
-#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error (cleared on read) */
-#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
-#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
-#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) */
-#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) */
-#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */
-#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */
-/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
-#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
-#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
-#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
-#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
-#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
-#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
-#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */
-#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
-#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
-#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
-#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
-#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
-#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
-#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
-#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
-#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
-#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
-#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */
-#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
-#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
-#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
-#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
-#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
-#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
-/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
-#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
-#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
-#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
-#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
-#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
-#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
-#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */
-#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
-#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
-#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
-#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
-#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
-#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
-#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
-#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
-#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
-#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
-#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */
-#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
-#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
-#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
-#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
-#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
-#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
-/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
-#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
-#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
-#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
-#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
-#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
-#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
-#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */
-#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
-#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
-#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
-#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
-#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
-#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
-#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
-#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
-#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
-#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
-#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */
-#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
-#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
-#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
-#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
-#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
-#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
-/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
-#define HSMCI_DMA_CHKSIZE_Pos 4
-#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */
-#define HSMCI_DMA_CHKSIZE(value) ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos)))
-#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */
-#define HSMCI_DMA_CHKSIZE_2 (0x1u << 4) /**< \brief (HSMCI_DMA) 2 data available */
-#define HSMCI_DMA_CHKSIZE_4 (0x2u << 4) /**< \brief (HSMCI_DMA) 4 data available */
-#define HSMCI_DMA_CHKSIZE_8 (0x3u << 4) /**< \brief (HSMCI_DMA) 8 data available */
-#define HSMCI_DMA_CHKSIZE_16 (0x4u << 4) /**< \brief (HSMCI_DMA) 16 data available */
-#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */
-/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
-#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
-#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
-#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
-#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
-/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
-#define HSMCI_WPMR_WPEN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protect Enable */
-#define HSMCI_WPMR_WPKEY_Pos 8
-#define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos) /**< \brief (HSMCI_WPMR) Write Protect Key */
-#define HSMCI_WPMR_WPKEY(value) ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos)))
-#define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8) /**< \brief (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
-/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
-#define HSMCI_WPSR_WPVS (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
-#define HSMCI_WPSR_WPVSRC_Pos 8
-#define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Source */
-/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
-#define HSMCI_FIFO_DATA_Pos 0
-#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */
-#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))
-
-/*@}*/
-
-
-#endif /* _SAMS70_HSMCI_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/icm.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/icm.h
deleted file mode 100644
index f4c7a1e..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/icm.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_ICM_COMPONENT_
-#define _SAMS70_ICM_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Integrity Check Monitor */
-/* ============================================================================= */
-/** \addtogroup SAMS70_ICM Integrity Check Monitor */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Icm hardware registers */
-typedef struct {
- __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */
- __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */
- __O uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */
- __I uint32_t Reserved1[1];
- __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */
- __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */
- __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */
- __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */
- __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */
- __I uint32_t Reserved2[3];
- __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */
- __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */
- __O uint32_t ICM_UIHVAL[8]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */
-} Icm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */
-#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */
-#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */
-#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */
-#define ICM_CFG_BBC_Pos 4
-#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */
-#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)))
-#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */
-#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */
-#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */
-#define ICM_CFG_UALGO_Pos 13
-#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */
-#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)))
-#define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */
-#define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */
-#define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */
-#define ICM_CFG_HAPROT_Pos 16
-#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */
-#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos)))
-#define ICM_CFG_DAPROT_Pos 24
-#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */
-#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos)))
-/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */
-#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */
-#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */
-#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */
-#define ICM_CTRL_REHASH_Pos 4
-#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */
-#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)))
-#define ICM_CTRL_RMDIS_Pos 8
-#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */
-#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)))
-#define ICM_CTRL_RMEN_Pos 12
-#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */
-#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)))
-/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */
-#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */
-#define ICM_SR_RAWRMDIS_Pos 8
-#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */
-#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)))
-#define ICM_SR_RMDIS_Pos 12
-#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */
-#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)))
-/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */
-#define ICM_IER_RHC_Pos 0
-#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */
-#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)))
-#define ICM_IER_RDM_Pos 4
-#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */
-#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)))
-#define ICM_IER_RBE_Pos 8
-#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */
-#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)))
-#define ICM_IER_RWC_Pos 12
-#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */
-#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)))
-#define ICM_IER_REC_Pos 16
-#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */
-#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)))
-#define ICM_IER_RSU_Pos 20
-#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */
-#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)))
-#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */
-/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */
-#define ICM_IDR_RHC_Pos 0
-#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */
-#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)))
-#define ICM_IDR_RDM_Pos 4
-#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */
-#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)))
-#define ICM_IDR_RBE_Pos 8
-#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */
-#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)))
-#define ICM_IDR_RWC_Pos 12
-#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */
-#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)))
-#define ICM_IDR_REC_Pos 16
-#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */
-#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)))
-#define ICM_IDR_RSU_Pos 20
-#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */
-#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)))
-#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */
-/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */
-#define ICM_IMR_RHC_Pos 0
-#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */
-#define ICM_IMR_RDM_Pos 4
-#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */
-#define ICM_IMR_RBE_Pos 8
-#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */
-#define ICM_IMR_RWC_Pos 12
-#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */
-#define ICM_IMR_REC_Pos 16
-#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */
-#define ICM_IMR_RSU_Pos 20
-#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */
-#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */
-/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */
-#define ICM_ISR_RHC_Pos 0
-#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */
-#define ICM_ISR_RDM_Pos 4
-#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */
-#define ICM_ISR_RBE_Pos 8
-#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */
-#define ICM_ISR_RWC_Pos 12
-#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */
-#define ICM_ISR_REC_Pos 16
-#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */
-#define ICM_ISR_RSU_Pos 20
-#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */
-#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */
-/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */
-#define ICM_UASR_URAT_Pos 0
-#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */
-#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */
-#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */
-#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */
-#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */
-#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */
-/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */
-#define ICM_DSCR_DASA_Pos 6
-#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */
-#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)))
-/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */
-#define ICM_HASH_HASA_Pos 7
-#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */
-#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)))
-/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */
-#define ICM_UIHVAL_VAL_Pos 0
-#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[8]) Initial Hash Value */
-#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)))
-
-/*@}*/
-
-
-#endif /* _SAMS70_ICM_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/isi.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/isi.h
deleted file mode 100644
index 1ceb845..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/isi.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_ISI_COMPONENT_
-#define _SAMS70_ISI_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Image Sensor Interface */
-/* ============================================================================= */
-/** \addtogroup SAMS70_ISI Image Sensor Interface */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Isi hardware registers */
-typedef struct {
- __IO uint32_t ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */
- __IO uint32_t ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */
- __IO uint32_t ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */
- __IO uint32_t ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */
- __IO uint32_t ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */
- __IO uint32_t ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */
- __IO uint32_t ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */
- __IO uint32_t ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */
- __IO uint32_t ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */
- __O uint32_t ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */
- __I uint32_t ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */
- __O uint32_t ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */
- __O uint32_t ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */
- __I uint32_t ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */
- __O uint32_t ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */
- __O uint32_t ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */
- __I uint32_t ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */
- __IO uint32_t ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */
- __IO uint32_t ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */
- __IO uint32_t ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */
- __IO uint32_t ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */
- __IO uint32_t ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */
- __IO uint32_t ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */
- __I uint32_t Reserved1[34];
- __IO uint32_t ISI_WPMR; /**< \brief (Isi Offset: 0xE4) Write Protection Mode Register */
- __I uint32_t ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */
-} Isi;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */
-#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */
-#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */
-#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */
-#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */
-#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */
-#define ISI_CFG1_FRATE_Pos 8
-#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */
-#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos)))
-#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */
-#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */
-#define ISI_CFG1_THMASK_Pos 13
-#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */
-#define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos)))
-#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */
-#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */
-#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */
-#define ISI_CFG1_SLD_Pos 16
-#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */
-#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos)))
-#define ISI_CFG1_SFD_Pos 24
-#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */
-#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos)))
-/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */
-#define ISI_CFG2_IM_VSIZE_Pos 0
-#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] */
-#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos)))
-#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) Grayscale Pixel Format Mode */
-#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode */
-#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) Grayscale Mode Format Enable */
-#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) RGB Format Swap Mode */
-#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */
-#define ISI_CFG2_IM_HSIZE_Pos 16
-#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */
-#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos)))
-#define ISI_CFG2_YCC_SWAP_Pos 28
-#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) YCrCb Format Swap Mode */
-#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos)))
-#define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28) /**< \brief (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */
-#define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28) /**< \brief (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */
-#define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */
-#define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */
-#define ISI_CFG2_RGB_CFG_Pos 30
-#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) RGB Pixel Mapping Configuration */
-#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos)))
-#define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30) /**< \brief (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */
-#define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30) /**< \brief (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */
-#define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */
-#define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */
-/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */
-#define ISI_PSIZE_PREV_VSIZE_Pos 0
-#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */
-#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos)))
-#define ISI_PSIZE_PREV_HSIZE_Pos 16
-#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */
-#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos)))
-/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */
-#define ISI_PDECF_DEC_FACTOR_Pos 0
-#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */
-#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos)))
-/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */
-#define ISI_Y2R_SET0_C0_Pos 0
-#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */
-#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos)))
-#define ISI_Y2R_SET0_C1_Pos 8
-#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */
-#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos)))
-#define ISI_Y2R_SET0_C2_Pos 16
-#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */
-#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos)))
-#define ISI_Y2R_SET0_C3_Pos 24
-#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */
-#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos)))
-/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */
-#define ISI_Y2R_SET1_C4_Pos 0
-#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */
-#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos)))
-#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */
-#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */
-#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */
-/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */
-#define ISI_R2Y_SET0_C0_Pos 0
-#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */
-#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos)))
-#define ISI_R2Y_SET0_C1_Pos 8
-#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */
-#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos)))
-#define ISI_R2Y_SET0_C2_Pos 16
-#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */
-#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos)))
-#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */
-/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */
-#define ISI_R2Y_SET1_C3_Pos 0
-#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */
-#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos)))
-#define ISI_R2Y_SET1_C4_Pos 8
-#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */
-#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos)))
-#define ISI_R2Y_SET1_C5_Pos 16
-#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */
-#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos)))
-#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */
-/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */
-#define ISI_R2Y_SET2_C6_Pos 0
-#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */
-#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos)))
-#define ISI_R2Y_SET2_C7_Pos 8
-#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */
-#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos)))
-#define ISI_R2Y_SET2_C8_Pos 16
-#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */
-#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos)))
-#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */
-/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */
-#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */
-#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */
-#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */
-#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */
-/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */
-#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) Module Enable */
-#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated (cleared on read) */
-#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated (cleared on read) */
-#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request */
-#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization (cleared on read) */
-#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) */
-#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) */
-#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress */
-#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow (cleared on read) */
-#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow (cleared on read) */
-#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error (cleared on read) */
-#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun (cleared on read) */
-/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */
-#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */
-#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */
-#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */
-#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */
-#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */
-#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */
-#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */
-#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */
-#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */
-/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */
-#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */
-#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */
-#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */
-#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */
-#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */
-#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */
-#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */
-#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */
-#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */
-/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */
-#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */
-#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */
-#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */
-#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Completed */
-#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Completed */
-#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) Preview FIFO Overflow */
-#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) Codec FIFO Overflow */
-#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */
-#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */
-/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */
-#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */
-#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */
-/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */
-#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) Preview Channel Disable Request */
-#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) Codec Channel Disable Request */
-/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */
-#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) Preview DMA Channel Status */
-#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) Code DMA Channel Status */
-/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */
-#define ISI_DMA_P_ADDR_P_ADDR_Pos 2
-#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address */
-#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos)))
-/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */
-#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit */
-#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit */
-#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */
-#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) Preview Transfer Done */
-/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */
-#define ISI_DMA_P_DSCR_P_DSCR_Pos 2
-#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address */
-#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos)))
-/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */
-#define ISI_DMA_C_ADDR_C_ADDR_Pos 2
-#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address */
-#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos)))
-/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */
-#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit */
-#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit */
-#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done Flag Control */
-#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) Codec Transfer Done */
-/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */
-#define ISI_DMA_C_DSCR_C_DSCR_Pos 2
-#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address */
-#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos)))
-/* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */
-#define ISI_WPMR_WPEN (0x1u << 0) /**< \brief (ISI_WPMR) Write Protection Enable */
-#define ISI_WPMR_WPKEY_Pos 8
-#define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos) /**< \brief (ISI_WPMR) Write Protection Key Password */
-#define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos)))
-#define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8) /**< \brief (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
-/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */
-#define ISI_WPSR_WPVS (0x1u << 0) /**< \brief (ISI_WPSR) Write Protection Violation Status */
-#define ISI_WPSR_WPVSRC_Pos 8
-#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_ISI_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/matrix.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/matrix.h
deleted file mode 100644
index 8bb7f21..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/matrix.h
+++ /dev/null
@@ -1,476 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_MATRIX_COMPONENT_
-#define _SAMS70_MATRIX_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */
-/* ============================================================================= */
-/** \addtogroup SAMS70_MATRIX AHB Bus Matrix */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Matrix hardware registers */
-typedef struct {
- __IO uint32_t MATRIX_MCFG0; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register 0 */
- __IO uint32_t MATRIX_MCFG1; /**< \brief (Matrix Offset: 0x0004) Master Configuration Register 1 */
- __IO uint32_t MATRIX_MCFG2; /**< \brief (Matrix Offset: 0x0008) Master Configuration Register 2 */
- __IO uint32_t MATRIX_MCFG3; /**< \brief (Matrix Offset: 0x000C) Master Configuration Register 3 */
- __IO uint32_t MATRIX_MCFG4; /**< \brief (Matrix Offset: 0x0010) Master Configuration Register 4 */
- __IO uint32_t MATRIX_MCFG5; /**< \brief (Matrix Offset: 0x0014) Master Configuration Register 5 */
- __IO uint32_t MATRIX_MCFG6; /**< \brief (Matrix Offset: 0x0018) Master Configuration Register 6 */
- __I uint32_t Reserved1[1];
- __IO uint32_t MATRIX_MCFG8; /**< \brief (Matrix Offset: 0x0020) Master Configuration Register 8 */
- __I uint32_t Reserved2[7];
- __IO uint32_t MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
- __I uint32_t Reserved3[7];
- __IO uint32_t MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
- __IO uint32_t MATRIX_PRBS0; /**< \brief (Matrix Offset: 0x0084) Priority Register B for Slave 0 */
- __IO uint32_t MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
- __IO uint32_t MATRIX_PRBS1; /**< \brief (Matrix Offset: 0x008C) Priority Register B for Slave 1 */
- __IO uint32_t MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
- __IO uint32_t MATRIX_PRBS2; /**< \brief (Matrix Offset: 0x0094) Priority Register B for Slave 2 */
- __IO uint32_t MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
- __IO uint32_t MATRIX_PRBS3; /**< \brief (Matrix Offset: 0x009C) Priority Register B for Slave 3 */
- __IO uint32_t MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
- __IO uint32_t MATRIX_PRBS4; /**< \brief (Matrix Offset: 0x00A4) Priority Register B for Slave 4 */
- __IO uint32_t MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */
- __IO uint32_t MATRIX_PRBS5; /**< \brief (Matrix Offset: 0x00AC) Priority Register B for Slave 5 */
- __IO uint32_t MATRIX_PRAS6; /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */
- __IO uint32_t MATRIX_PRBS6; /**< \brief (Matrix Offset: 0x00B4) Priority Register B for Slave 6 */
- __IO uint32_t MATRIX_PRAS7; /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */
- __IO uint32_t MATRIX_PRBS7; /**< \brief (Matrix Offset: 0x00BC) Priority Register B for Slave 7 */
- __IO uint32_t MATRIX_PRAS8; /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */
- __IO uint32_t MATRIX_PRBS8; /**< \brief (Matrix Offset: 0x00C4) Priority Register B for Slave 8 */
- __I uint32_t Reserved4[14];
- __IO uint32_t MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */
- __I uint32_t Reserved5[4];
- __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration Register */
- __I uint32_t Reserved6[3];
- __IO uint32_t CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register */
- __I uint32_t Reserved7[47];
- __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register */
- __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protection Status Register */
-} Matrix;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0000) Master Configuration Register 0 -------- */
-#define MATRIX_MCFG0_ULBT_Pos 0
-#define MATRIX_MCFG0_ULBT_Msk (0x7u << MATRIX_MCFG0_ULBT_Pos) /**< \brief (MATRIX_MCFG0) Undefined Length Burst Type */
-#define MATRIX_MCFG0_ULBT(value) ((MATRIX_MCFG0_ULBT_Msk & ((value) << MATRIX_MCFG0_ULBT_Pos)))
-#define MATRIX_MCFG0_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG0) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG0_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG0) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG0_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG0) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG0_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG0) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG0_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG0) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG0_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG0) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG0_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG0) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG0_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG0) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_MCFG1 : (MATRIX Offset: 0x0004) Master Configuration Register 1 -------- */
-#define MATRIX_MCFG1_ULBT_Pos 0
-#define MATRIX_MCFG1_ULBT_Msk (0x7u << MATRIX_MCFG1_ULBT_Pos) /**< \brief (MATRIX_MCFG1) Undefined Length Burst Type */
-#define MATRIX_MCFG1_ULBT(value) ((MATRIX_MCFG1_ULBT_Msk & ((value) << MATRIX_MCFG1_ULBT_Pos)))
-#define MATRIX_MCFG1_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG1) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG1_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG1) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG1_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG1) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG1_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG1) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG1_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG1) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG1_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG1) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG1_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG1) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG1_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG1) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_MCFG2 : (MATRIX Offset: 0x0008) Master Configuration Register 2 -------- */
-#define MATRIX_MCFG2_ULBT_Pos 0
-#define MATRIX_MCFG2_ULBT_Msk (0x7u << MATRIX_MCFG2_ULBT_Pos) /**< \brief (MATRIX_MCFG2) Undefined Length Burst Type */
-#define MATRIX_MCFG2_ULBT(value) ((MATRIX_MCFG2_ULBT_Msk & ((value) << MATRIX_MCFG2_ULBT_Pos)))
-#define MATRIX_MCFG2_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG2) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG2_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG2) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG2_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG2) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG2_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG2) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG2_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG2) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG2_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG2) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG2_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG2) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG2_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG2) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_MCFG3 : (MATRIX Offset: 0x000C) Master Configuration Register 3 -------- */
-#define MATRIX_MCFG3_ULBT_Pos 0
-#define MATRIX_MCFG3_ULBT_Msk (0x7u << MATRIX_MCFG3_ULBT_Pos) /**< \brief (MATRIX_MCFG3) Undefined Length Burst Type */
-#define MATRIX_MCFG3_ULBT(value) ((MATRIX_MCFG3_ULBT_Msk & ((value) << MATRIX_MCFG3_ULBT_Pos)))
-#define MATRIX_MCFG3_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG3) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG3_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG3) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG3_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG3) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG3_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG3) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG3_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG3) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG3_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG3) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG3_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG3) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG3_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG3) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_MCFG4 : (MATRIX Offset: 0x0010) Master Configuration Register 4 -------- */
-#define MATRIX_MCFG4_ULBT_Pos 0
-#define MATRIX_MCFG4_ULBT_Msk (0x7u << MATRIX_MCFG4_ULBT_Pos) /**< \brief (MATRIX_MCFG4) Undefined Length Burst Type */
-#define MATRIX_MCFG4_ULBT(value) ((MATRIX_MCFG4_ULBT_Msk & ((value) << MATRIX_MCFG4_ULBT_Pos)))
-#define MATRIX_MCFG4_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG4) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG4_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG4) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG4_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG4) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG4_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG4) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG4_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG4) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG4_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG4) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG4_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG4) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG4_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG4) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_MCFG5 : (MATRIX Offset: 0x0014) Master Configuration Register 5 -------- */
-#define MATRIX_MCFG5_ULBT_Pos 0
-#define MATRIX_MCFG5_ULBT_Msk (0x7u << MATRIX_MCFG5_ULBT_Pos) /**< \brief (MATRIX_MCFG5) Undefined Length Burst Type */
-#define MATRIX_MCFG5_ULBT(value) ((MATRIX_MCFG5_ULBT_Msk & ((value) << MATRIX_MCFG5_ULBT_Pos)))
-#define MATRIX_MCFG5_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG5) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG5_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG5) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG5_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG5) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG5_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG5) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG5_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG5) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG5_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG5) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG5_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG5) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG5_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG5) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_MCFG6 : (MATRIX Offset: 0x0018) Master Configuration Register 6 -------- */
-#define MATRIX_MCFG6_ULBT_Pos 0
-#define MATRIX_MCFG6_ULBT_Msk (0x7u << MATRIX_MCFG6_ULBT_Pos) /**< \brief (MATRIX_MCFG6) Undefined Length Burst Type */
-#define MATRIX_MCFG6_ULBT(value) ((MATRIX_MCFG6_ULBT_Msk & ((value) << MATRIX_MCFG6_ULBT_Pos)))
-#define MATRIX_MCFG6_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG6) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG6_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG6) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG6_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG6) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG6_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG6) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG6_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG6) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG6_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG6) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG6_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG6) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG6_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG6) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_MCFG8 : (MATRIX Offset: 0x0020) Master Configuration Register 8 -------- */
-#define MATRIX_MCFG8_ULBT_Pos 0
-#define MATRIX_MCFG8_ULBT_Msk (0x7u << MATRIX_MCFG8_ULBT_Pos) /**< \brief (MATRIX_MCFG8) Undefined Length Burst Type */
-#define MATRIX_MCFG8_ULBT(value) ((MATRIX_MCFG8_ULBT_Msk & ((value) << MATRIX_MCFG8_ULBT_Pos)))
-#define MATRIX_MCFG8_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG8) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
-#define MATRIX_MCFG8_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG8) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
-#define MATRIX_MCFG8_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG8) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
-#define MATRIX_MCFG8_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG8) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
-#define MATRIX_MCFG8_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG8) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
-#define MATRIX_MCFG8_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG8) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
-#define MATRIX_MCFG8_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG8) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
-#define MATRIX_MCFG8_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG8) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
-/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
-#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
-#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Bus Grant Duration for Masters */
-#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
-#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
-#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */
-#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
-#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG[9]) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
-#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG[9]) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
-#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
-#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
-#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */
-#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
-/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
-#define MATRIX_PRAS0_M0PR_Pos 0
-#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
-#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
-#define MATRIX_PRAS0_M1PR_Pos 4
-#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
-#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
-#define MATRIX_PRAS0_M2PR_Pos 8
-#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
-#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
-#define MATRIX_PRAS0_M3PR_Pos 12
-#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
-#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
-#define MATRIX_PRAS0_M4PR_Pos 16
-#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
-#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
-#define MATRIX_PRAS0_M5PR_Pos 20
-#define MATRIX_PRAS0_M5PR_Msk (0x3u << MATRIX_PRAS0_M5PR_Pos) /**< \brief (MATRIX_PRAS0) Master 5 Priority */
-#define MATRIX_PRAS0_M5PR(value) ((MATRIX_PRAS0_M5PR_Msk & ((value) << MATRIX_PRAS0_M5PR_Pos)))
-#define MATRIX_PRAS0_M6PR_Pos 24
-#define MATRIX_PRAS0_M6PR_Msk (0x3u << MATRIX_PRAS0_M6PR_Pos) /**< \brief (MATRIX_PRAS0) Master 6 Priority */
-#define MATRIX_PRAS0_M6PR(value) ((MATRIX_PRAS0_M6PR_Msk & ((value) << MATRIX_PRAS0_M6PR_Pos)))
-/* -------- MATRIX_PRBS0 : (MATRIX Offset: 0x0084) Priority Register B for Slave 0 -------- */
-#define MATRIX_PRBS0_M8PR_Pos 0
-#define MATRIX_PRBS0_M8PR_Msk (0x3u << MATRIX_PRBS0_M8PR_Pos) /**< \brief (MATRIX_PRBS0) Master 8 Priority */
-#define MATRIX_PRBS0_M8PR(value) ((MATRIX_PRBS0_M8PR_Msk & ((value) << MATRIX_PRBS0_M8PR_Pos)))
-/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
-#define MATRIX_PRAS1_M0PR_Pos 0
-#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
-#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
-#define MATRIX_PRAS1_M1PR_Pos 4
-#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
-#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
-#define MATRIX_PRAS1_M2PR_Pos 8
-#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
-#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
-#define MATRIX_PRAS1_M3PR_Pos 12
-#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
-#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
-#define MATRIX_PRAS1_M4PR_Pos 16
-#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
-#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
-#define MATRIX_PRAS1_M5PR_Pos 20
-#define MATRIX_PRAS1_M5PR_Msk (0x3u << MATRIX_PRAS1_M5PR_Pos) /**< \brief (MATRIX_PRAS1) Master 5 Priority */
-#define MATRIX_PRAS1_M5PR(value) ((MATRIX_PRAS1_M5PR_Msk & ((value) << MATRIX_PRAS1_M5PR_Pos)))
-#define MATRIX_PRAS1_M6PR_Pos 24
-#define MATRIX_PRAS1_M6PR_Msk (0x3u << MATRIX_PRAS1_M6PR_Pos) /**< \brief (MATRIX_PRAS1) Master 6 Priority */
-#define MATRIX_PRAS1_M6PR(value) ((MATRIX_PRAS1_M6PR_Msk & ((value) << MATRIX_PRAS1_M6PR_Pos)))
-/* -------- MATRIX_PRBS1 : (MATRIX Offset: 0x008C) Priority Register B for Slave 1 -------- */
-#define MATRIX_PRBS1_M8PR_Pos 0
-#define MATRIX_PRBS1_M8PR_Msk (0x3u << MATRIX_PRBS1_M8PR_Pos) /**< \brief (MATRIX_PRBS1) Master 8 Priority */
-#define MATRIX_PRBS1_M8PR(value) ((MATRIX_PRBS1_M8PR_Msk & ((value) << MATRIX_PRBS1_M8PR_Pos)))
-/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
-#define MATRIX_PRAS2_M0PR_Pos 0
-#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
-#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
-#define MATRIX_PRAS2_M1PR_Pos 4
-#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
-#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
-#define MATRIX_PRAS2_M2PR_Pos 8
-#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
-#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
-#define MATRIX_PRAS2_M3PR_Pos 12
-#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
-#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
-#define MATRIX_PRAS2_M4PR_Pos 16
-#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
-#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
-#define MATRIX_PRAS2_M5PR_Pos 20
-#define MATRIX_PRAS2_M5PR_Msk (0x3u << MATRIX_PRAS2_M5PR_Pos) /**< \brief (MATRIX_PRAS2) Master 5 Priority */
-#define MATRIX_PRAS2_M5PR(value) ((MATRIX_PRAS2_M5PR_Msk & ((value) << MATRIX_PRAS2_M5PR_Pos)))
-#define MATRIX_PRAS2_M6PR_Pos 24
-#define MATRIX_PRAS2_M6PR_Msk (0x3u << MATRIX_PRAS2_M6PR_Pos) /**< \brief (MATRIX_PRAS2) Master 6 Priority */
-#define MATRIX_PRAS2_M6PR(value) ((MATRIX_PRAS2_M6PR_Msk & ((value) << MATRIX_PRAS2_M6PR_Pos)))
-/* -------- MATRIX_PRBS2 : (MATRIX Offset: 0x0094) Priority Register B for Slave 2 -------- */
-#define MATRIX_PRBS2_M8PR_Pos 0
-#define MATRIX_PRBS2_M8PR_Msk (0x3u << MATRIX_PRBS2_M8PR_Pos) /**< \brief (MATRIX_PRBS2) Master 8 Priority */
-#define MATRIX_PRBS2_M8PR(value) ((MATRIX_PRBS2_M8PR_Msk & ((value) << MATRIX_PRBS2_M8PR_Pos)))
-/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
-#define MATRIX_PRAS3_M0PR_Pos 0
-#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
-#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
-#define MATRIX_PRAS3_M1PR_Pos 4
-#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
-#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
-#define MATRIX_PRAS3_M2PR_Pos 8
-#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
-#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
-#define MATRIX_PRAS3_M3PR_Pos 12
-#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
-#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
-#define MATRIX_PRAS3_M4PR_Pos 16
-#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
-#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
-#define MATRIX_PRAS3_M5PR_Pos 20
-#define MATRIX_PRAS3_M5PR_Msk (0x3u << MATRIX_PRAS3_M5PR_Pos) /**< \brief (MATRIX_PRAS3) Master 5 Priority */
-#define MATRIX_PRAS3_M5PR(value) ((MATRIX_PRAS3_M5PR_Msk & ((value) << MATRIX_PRAS3_M5PR_Pos)))
-#define MATRIX_PRAS3_M6PR_Pos 24
-#define MATRIX_PRAS3_M6PR_Msk (0x3u << MATRIX_PRAS3_M6PR_Pos) /**< \brief (MATRIX_PRAS3) Master 6 Priority */
-#define MATRIX_PRAS3_M6PR(value) ((MATRIX_PRAS3_M6PR_Msk & ((value) << MATRIX_PRAS3_M6PR_Pos)))
-/* -------- MATRIX_PRBS3 : (MATRIX Offset: 0x009C) Priority Register B for Slave 3 -------- */
-#define MATRIX_PRBS3_M8PR_Pos 0
-#define MATRIX_PRBS3_M8PR_Msk (0x3u << MATRIX_PRBS3_M8PR_Pos) /**< \brief (MATRIX_PRBS3) Master 8 Priority */
-#define MATRIX_PRBS3_M8PR(value) ((MATRIX_PRBS3_M8PR_Msk & ((value) << MATRIX_PRBS3_M8PR_Pos)))
-/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
-#define MATRIX_PRAS4_M0PR_Pos 0
-#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
-#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
-#define MATRIX_PRAS4_M1PR_Pos 4
-#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
-#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
-#define MATRIX_PRAS4_M2PR_Pos 8
-#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
-#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
-#define MATRIX_PRAS4_M3PR_Pos 12
-#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
-#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
-#define MATRIX_PRAS4_M4PR_Pos 16
-#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
-#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
-#define MATRIX_PRAS4_M5PR_Pos 20
-#define MATRIX_PRAS4_M5PR_Msk (0x3u << MATRIX_PRAS4_M5PR_Pos) /**< \brief (MATRIX_PRAS4) Master 5 Priority */
-#define MATRIX_PRAS4_M5PR(value) ((MATRIX_PRAS4_M5PR_Msk & ((value) << MATRIX_PRAS4_M5PR_Pos)))
-#define MATRIX_PRAS4_M6PR_Pos 24
-#define MATRIX_PRAS4_M6PR_Msk (0x3u << MATRIX_PRAS4_M6PR_Pos) /**< \brief (MATRIX_PRAS4) Master 6 Priority */
-#define MATRIX_PRAS4_M6PR(value) ((MATRIX_PRAS4_M6PR_Msk & ((value) << MATRIX_PRAS4_M6PR_Pos)))
-/* -------- MATRIX_PRBS4 : (MATRIX Offset: 0x00A4) Priority Register B for Slave 4 -------- */
-#define MATRIX_PRBS4_M8PR_Pos 0
-#define MATRIX_PRBS4_M8PR_Msk (0x3u << MATRIX_PRBS4_M8PR_Pos) /**< \brief (MATRIX_PRBS4) Master 8 Priority */
-#define MATRIX_PRBS4_M8PR(value) ((MATRIX_PRBS4_M8PR_Msk & ((value) << MATRIX_PRBS4_M8PR_Pos)))
-/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */
-#define MATRIX_PRAS5_M0PR_Pos 0
-#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */
-#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))
-#define MATRIX_PRAS5_M1PR_Pos 4
-#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */
-#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))
-#define MATRIX_PRAS5_M2PR_Pos 8
-#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */
-#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))
-#define MATRIX_PRAS5_M3PR_Pos 12
-#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */
-#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))
-#define MATRIX_PRAS5_M4PR_Pos 16
-#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */
-#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))
-#define MATRIX_PRAS5_M5PR_Pos 20
-#define MATRIX_PRAS5_M5PR_Msk (0x3u << MATRIX_PRAS5_M5PR_Pos) /**< \brief (MATRIX_PRAS5) Master 5 Priority */
-#define MATRIX_PRAS5_M5PR(value) ((MATRIX_PRAS5_M5PR_Msk & ((value) << MATRIX_PRAS5_M5PR_Pos)))
-#define MATRIX_PRAS5_M6PR_Pos 24
-#define MATRIX_PRAS5_M6PR_Msk (0x3u << MATRIX_PRAS5_M6PR_Pos) /**< \brief (MATRIX_PRAS5) Master 6 Priority */
-#define MATRIX_PRAS5_M6PR(value) ((MATRIX_PRAS5_M6PR_Msk & ((value) << MATRIX_PRAS5_M6PR_Pos)))
-/* -------- MATRIX_PRBS5 : (MATRIX Offset: 0x00AC) Priority Register B for Slave 5 -------- */
-#define MATRIX_PRBS5_M8PR_Pos 0
-#define MATRIX_PRBS5_M8PR_Msk (0x3u << MATRIX_PRBS5_M8PR_Pos) /**< \brief (MATRIX_PRBS5) Master 8 Priority */
-#define MATRIX_PRBS5_M8PR(value) ((MATRIX_PRBS5_M8PR_Msk & ((value) << MATRIX_PRBS5_M8PR_Pos)))
-/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */
-#define MATRIX_PRAS6_M0PR_Pos 0
-#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */
-#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos)))
-#define MATRIX_PRAS6_M1PR_Pos 4
-#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */
-#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos)))
-#define MATRIX_PRAS6_M2PR_Pos 8
-#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */
-#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos)))
-#define MATRIX_PRAS6_M3PR_Pos 12
-#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */
-#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos)))
-#define MATRIX_PRAS6_M4PR_Pos 16
-#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */
-#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos)))
-#define MATRIX_PRAS6_M5PR_Pos 20
-#define MATRIX_PRAS6_M5PR_Msk (0x3u << MATRIX_PRAS6_M5PR_Pos) /**< \brief (MATRIX_PRAS6) Master 5 Priority */
-#define MATRIX_PRAS6_M5PR(value) ((MATRIX_PRAS6_M5PR_Msk & ((value) << MATRIX_PRAS6_M5PR_Pos)))
-#define MATRIX_PRAS6_M6PR_Pos 24
-#define MATRIX_PRAS6_M6PR_Msk (0x3u << MATRIX_PRAS6_M6PR_Pos) /**< \brief (MATRIX_PRAS6) Master 6 Priority */
-#define MATRIX_PRAS6_M6PR(value) ((MATRIX_PRAS6_M6PR_Msk & ((value) << MATRIX_PRAS6_M6PR_Pos)))
-/* -------- MATRIX_PRBS6 : (MATRIX Offset: 0x00B4) Priority Register B for Slave 6 -------- */
-#define MATRIX_PRBS6_M8PR_Pos 0
-#define MATRIX_PRBS6_M8PR_Msk (0x3u << MATRIX_PRBS6_M8PR_Pos) /**< \brief (MATRIX_PRBS6) Master 8 Priority */
-#define MATRIX_PRBS6_M8PR(value) ((MATRIX_PRBS6_M8PR_Msk & ((value) << MATRIX_PRBS6_M8PR_Pos)))
-/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */
-#define MATRIX_PRAS7_M0PR_Pos 0
-#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */
-#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos)))
-#define MATRIX_PRAS7_M1PR_Pos 4
-#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */
-#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos)))
-#define MATRIX_PRAS7_M2PR_Pos 8
-#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */
-#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos)))
-#define MATRIX_PRAS7_M3PR_Pos 12
-#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */
-#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos)))
-#define MATRIX_PRAS7_M4PR_Pos 16
-#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */
-#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos)))
-#define MATRIX_PRAS7_M5PR_Pos 20
-#define MATRIX_PRAS7_M5PR_Msk (0x3u << MATRIX_PRAS7_M5PR_Pos) /**< \brief (MATRIX_PRAS7) Master 5 Priority */
-#define MATRIX_PRAS7_M5PR(value) ((MATRIX_PRAS7_M5PR_Msk & ((value) << MATRIX_PRAS7_M5PR_Pos)))
-#define MATRIX_PRAS7_M6PR_Pos 24
-#define MATRIX_PRAS7_M6PR_Msk (0x3u << MATRIX_PRAS7_M6PR_Pos) /**< \brief (MATRIX_PRAS7) Master 6 Priority */
-#define MATRIX_PRAS7_M6PR(value) ((MATRIX_PRAS7_M6PR_Msk & ((value) << MATRIX_PRAS7_M6PR_Pos)))
-/* -------- MATRIX_PRBS7 : (MATRIX Offset: 0x00BC) Priority Register B for Slave 7 -------- */
-#define MATRIX_PRBS7_M8PR_Pos 0
-#define MATRIX_PRBS7_M8PR_Msk (0x3u << MATRIX_PRBS7_M8PR_Pos) /**< \brief (MATRIX_PRBS7) Master 8 Priority */
-#define MATRIX_PRBS7_M8PR(value) ((MATRIX_PRBS7_M8PR_Msk & ((value) << MATRIX_PRBS7_M8PR_Pos)))
-/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */
-#define MATRIX_PRAS8_M0PR_Pos 0
-#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */
-#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos)))
-#define MATRIX_PRAS8_M1PR_Pos 4
-#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */
-#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos)))
-#define MATRIX_PRAS8_M2PR_Pos 8
-#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */
-#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos)))
-#define MATRIX_PRAS8_M3PR_Pos 12
-#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */
-#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos)))
-#define MATRIX_PRAS8_M4PR_Pos 16
-#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */
-#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos)))
-#define MATRIX_PRAS8_M5PR_Pos 20
-#define MATRIX_PRAS8_M5PR_Msk (0x3u << MATRIX_PRAS8_M5PR_Pos) /**< \brief (MATRIX_PRAS8) Master 5 Priority */
-#define MATRIX_PRAS8_M5PR(value) ((MATRIX_PRAS8_M5PR_Msk & ((value) << MATRIX_PRAS8_M5PR_Pos)))
-#define MATRIX_PRAS8_M6PR_Pos 24
-#define MATRIX_PRAS8_M6PR_Msk (0x3u << MATRIX_PRAS8_M6PR_Pos) /**< \brief (MATRIX_PRAS8) Master 6 Priority */
-#define MATRIX_PRAS8_M6PR(value) ((MATRIX_PRAS8_M6PR_Msk & ((value) << MATRIX_PRAS8_M6PR_Pos)))
-/* -------- MATRIX_PRBS8 : (MATRIX Offset: 0x00C4) Priority Register B for Slave 8 -------- */
-#define MATRIX_PRBS8_M8PR_Pos 0
-#define MATRIX_PRBS8_M8PR_Msk (0x3u << MATRIX_PRBS8_M8PR_Pos) /**< \brief (MATRIX_PRBS8) Master 8 Priority */
-#define MATRIX_PRBS8_M8PR(value) ((MATRIX_PRBS8_M8PR_Msk & ((value) << MATRIX_PRBS8_M8PR_Pos)))
-/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
-#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 */
-#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 */
-#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 */
-#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 */
-#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 */
-#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 */
-#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 */
-#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 8 */
-/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration Register -------- */
-#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */
-#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */
-#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */
-#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */
-#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */
-/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */
-#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */
-#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */
-#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */
-#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */
-#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) /**< \brief (CCFG_SMCNFCS) SDRAM Enable */
-/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */
-#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */
-#define MATRIX_WPMR_WPKEY_Pos 8
-#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key */
-#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
-#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
-/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */
-#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */
-#define MATRIX_WPSR_WPVSRC_Pos 8
-#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_MATRIX_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/pio.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/pio.h
deleted file mode 100644
index 94bc5c2..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/pio.h
+++ /dev/null
@@ -1,1629 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PIO_COMPONENT_
-#define _SAMS70_PIO_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_PIO Parallel Input/Output Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Pio hardware registers */
-typedef struct {
- __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */
- __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */
- __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */
- __I uint32_t Reserved1[1];
- __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */
- __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */
- __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */
- __I uint32_t Reserved2[1];
- __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */
- __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */
- __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */
- __I uint32_t Reserved3[1];
- __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */
- __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */
- __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */
- __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */
- __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */
- __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */
- __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */
- __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */
- __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */
- __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */
- __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */
- __I uint32_t Reserved4[1];
- __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */
- __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */
- __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */
- __I uint32_t Reserved5[1];
- __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */
- __I uint32_t Reserved6[2];
- __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */
- __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */
- __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */
- __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */
- __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */
- __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */
- __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */
- __I uint32_t Reserved7[1];
- __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */
- __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */
- __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */
- __I uint32_t Reserved8[1];
- __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */
- __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */
- __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */
- __I uint32_t Reserved9[1];
- __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */
- __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */
- __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */
- __I uint32_t Reserved10[1];
- __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */
- __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register */
- __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */
- __I uint32_t Reserved11[1];
- __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */
- __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */
- __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */
- __I uint32_t Reserved12[5];
- __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */
- __I uint32_t Reserved13[5];
- __IO uint32_t PIO_DRIVER; /**< \brief (Pio Offset: 0x0118) I/O Drive Register */
- __I uint32_t Reserved14[13];
- __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x0150) Parallel Capture Mode Register */
- __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x0154) Parallel Capture Interrupt Enable Register */
- __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x0158) Parallel Capture Interrupt Disable Register */
- __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x015C) Parallel Capture Interrupt Mask Register */
- __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x0160) Parallel Capture Interrupt Status Register */
- __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x0164) Parallel Capture Reception Holding Register */
-} Pio;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */
-#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */
-#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */
-/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */
-#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */
-#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */
-/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */
-#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */
-#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */
-/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */
-#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */
-#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */
-/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */
-#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */
-#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */
-/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */
-#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */
-#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */
-/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */
-#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */
-#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */
-/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */
-#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */
-#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */
-/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */
-#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filter Status */
-#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filter Status */
-/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */
-#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */
-#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */
-/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */
-#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */
-#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */
-/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */
-#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */
-#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */
-/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */
-#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */
-#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */
-/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */
-#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */
-/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */
-#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */
-/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */
-#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */
-/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */
-#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */
-/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */
-#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-drive Enable */
-#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-drive Enable */
-/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */
-#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-drive Disable */
-#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-drive Disable */
-/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */
-#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-drive Status */
-#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-drive Status */
-/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */
-#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */
-#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */
-/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */
-#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */
-#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */
-/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */
-#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */
-#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */
-/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */
-#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */
-/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */
-#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */
-/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */
-#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */
-/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */
-#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */
-/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */
-#define PIO_SCDR_DIV_Pos 0
-#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */
-#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos)))
-/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */
-#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */
-/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */
-#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */
-#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */
-/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */
-#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */
-#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */
-/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */
-#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */
-#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */
-/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */
-#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */
-#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */
-/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */
-#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */
-#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */
-/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */
-#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */
-/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */
-#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */
-/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */
-#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) IO Line Index */
-#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) IO Line Index */
-/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */
-#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */
-/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */
-#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */
-#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */
-/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */
-#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */
-/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */
-#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */
-/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/High-Level Select Register -------- */
-#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */
-/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */
-#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */
-/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */
-#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */
-#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */
-/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */
-#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */
-#define PIO_WPMR_WPKEY_Pos 8
-#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */
-#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos)))
-#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
-/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */
-#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */
-#define PIO_WPSR_WPVSRC_Pos 8
-#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */
-/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */
-#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */
-/* -------- PIO_PCMR : (PIO Offset: 0x0150) Parallel Capture Mode Register -------- */
-#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */
-#define PIO_PCMR_DSIZE_Pos 4
-#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */
-#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos)))
-#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */
-#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */
-#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */
-#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */
-#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */
-#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */
-/* -------- PIO_PCIER : (PIO Offset: 0x0154) Parallel Capture Interrupt Enable Register -------- */
-#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */
-#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */
-#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */
-#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */
-/* -------- PIO_PCIDR : (PIO Offset: 0x0158) Parallel Capture Interrupt Disable Register -------- */
-#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */
-#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */
-#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */
-#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */
-/* -------- PIO_PCIMR : (PIO Offset: 0x015C) Parallel Capture Interrupt Mask Register -------- */
-#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */
-#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */
-#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */
-#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */
-/* -------- PIO_PCISR : (PIO Offset: 0x0160) Parallel Capture Interrupt Status Register -------- */
-#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */
-#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error */
-/* -------- PIO_PCRHR : (PIO Offset: 0x0164) Parallel Capture Reception Holding Register -------- */
-#define PIO_PCRHR_RDATA_Pos 0
-#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data */
-
-/*@}*/
-
-
-#endif /* _SAMS70_PIO_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/pmc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/pmc.h
deleted file mode 100644
index 0c973cf..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/pmc.h
+++ /dev/null
@@ -1,736 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PMC_COMPONENT_
-#define _SAMS70_PMC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Power Management Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_PMC Power Management Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Pmc hardware registers */
-typedef struct {
- __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
- __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
- __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
- __I uint32_t Reserved1[1];
- __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */
- __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */
- __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */
- __IO uint32_t CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */
- __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
- __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
- __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */
- __I uint32_t Reserved2[1];
- __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
- __I uint32_t Reserved3[1];
- __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */
- __I uint32_t Reserved4[1];
- __IO uint32_t PMC_PCK[7]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
- __I uint32_t Reserved5[1];
- __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
- __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
- __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */
- __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
- __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
- __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
- __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
- __I uint32_t Reserved6[26];
- __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */
- __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */
- __I uint32_t Reserved7[5];
- __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */
- __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */
- __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */
- __IO uint32_t PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */
- __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */
- __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x0114) SleepWalking Enable Register 0 */
- __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x0118) SleepWalking Disable Register 0 */
- __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x011C) SleepWalking Status Register 0 */
- __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0 */
- __I uint32_t Reserved8[4];
- __O uint32_t PMC_SLPWK_ER1; /**< \brief (Pmc Offset: 0x0134) SleepWalking Enable Register 1 */
- __O uint32_t PMC_SLPWK_DR1; /**< \brief (Pmc Offset: 0x0138) SleepWalking Disable Register 1 */
- __I uint32_t PMC_SLPWK_SR1; /**< \brief (Pmc Offset: 0x013C) SleepWalking Status Register 1 */
- __I uint32_t PMC_SLPWK_ASR1; /**< \brief (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1 */
- __I uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register */
-} Pmc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
-#define PMC_SCER_USBCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB FS Clock */
-#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
-#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
-#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
-#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */
-#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */
-#define PMC_SCER_PCK5 (0x1u << 13) /**< \brief (PMC_SCER) Programmable Clock 5 Output Enable */
-#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */
-/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
-#define PMC_SCDR_USBCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB FS Clock */
-#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
-#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
-#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
-#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */
-#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */
-#define PMC_SCDR_PCK5 (0x1u << 13) /**< \brief (PMC_SCDR) Programmable Clock 5 Output Disable */
-#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */
-/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
-#define PMC_SCSR_USBCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB FS Clock Status */
-#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
-#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
-#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
-#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */
-#define PMC_SCSR_PCK4 (0x1u << 12) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */
-#define PMC_SCSR_PCK5 (0x1u << 13) /**< \brief (PMC_SCSR) Programmable Clock 5 Output Status */
-#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */
-/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
-#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */
-#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */
-#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */
-#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */
-#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */
-#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */
-#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */
-#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */
-#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */
-#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */
-#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */
-#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */
-#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */
-#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */
-#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */
-#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */
-#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */
-#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */
-#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */
-#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */
-#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */
-#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */
-#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */
-#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */
-#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */
-/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
-#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */
-#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */
-#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */
-#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */
-#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */
-#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */
-#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */
-#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */
-#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */
-#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */
-#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */
-#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */
-#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */
-#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */
-#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */
-#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */
-#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */
-#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */
-#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */
-#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */
-#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */
-#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */
-#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */
-#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */
-#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */
-/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
-#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */
-#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */
-#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */
-#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */
-#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */
-#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */
-#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */
-#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */
-#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */
-#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */
-#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */
-#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */
-#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */
-#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */
-#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */
-#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */
-#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */
-#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */
-#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */
-#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */
-#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */
-#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */
-#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */
-#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */
-#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */
-/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
-#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */
-#define CKGR_UCKR_UPLLCOUNT_Pos 20
-#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */
-#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
-/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
-#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
-#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
-#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command (Write-only) */
-#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
-#define CKGR_MOR_MOSCRCF_Pos 4
-#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
-#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)))
-#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 4 MHz (default) */
-#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 8 MHz */
-#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 12 MHz */
-#define CKGR_MOR_MOSCXTST_Pos 8
-#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
-#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
-#define CKGR_MOR_KEY_Pos 16
-#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */
-#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
-#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */
-#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
-#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
-#define CKGR_MOR_XT32KFME (0x1u << 26) /**< \brief (CKGR_MOR) Slow Crystal Oscillator Frequency Monitoring Enable */
-/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
-#define CKGR_MCFR_MAINF_Pos 0
-#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
-#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos)))
-#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready */
-#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */
-#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */
-/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
-#define CKGR_PLLAR_DIVA_Pos 0
-#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) PLLA Front End Divider */
-#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
-#define CKGR_PLLAR_DIVA_0 (0x0u << 0) /**< \brief (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */
-#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /**< \brief (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */
-#define CKGR_PLLAR_PLLACOUNT_Pos 8
-#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
-#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
-#define CKGR_PLLAR_MULA_Pos 16
-#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
-#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
-#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */
-/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
-#define PMC_MCKR_CSS_Pos 0
-#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
-#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)))
-#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
-#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
-#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */
-#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) Divided UPLL Clock is selected */
-#define PMC_MCKR_PRES_Pos 4
-#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
-#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)))
-#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
-#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
-#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
-#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
-#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
-#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
-#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
-#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
-#define PMC_MCKR_MDIV_Pos 8
-#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */
-#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos)))
-#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */
-#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */
-#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */
-#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */
-#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */
-/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */
-#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */
-#define PMC_USB_USBDIV_Pos 8
-#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */
-#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos)))
-/* -------- PMC_PCK[7] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
-#define PMC_PCK_CSS_Pos 0
-#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[7]) Master Clock Source Selection */
-#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)))
-#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[7]) Slow Clock is selected */
-#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[7]) Main Clock is selected */
-#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[7]) PLLA Clock is selected */
-#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[7]) Divided UPLL Clock is selected */
-#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[7]) Master Clock is selected */
-#define PMC_PCK_PRES_Pos 4
-#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[7]) Programmable Clock Prescaler */
-#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
-/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
-#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
-#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */
-#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
-#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */
-#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
-#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
-#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
-#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */
-#define PMC_IER_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable */
-#define PMC_IER_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable */
-#define PMC_IER_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable */
-#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
-#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
-#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
-#define PMC_IER_XT32KERR (0x1u << 21) /**< \brief (PMC_IER) Slow Crystal Oscillator Error Interrupt Enable */
-/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
-#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
-#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */
-#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
-#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */
-#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
-#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
-#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
-#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */
-#define PMC_IDR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable */
-#define PMC_IDR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable */
-#define PMC_IDR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable */
-#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
-#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
-#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
-#define PMC_IDR_XT32KERR (0x1u << 21) /**< \brief (PMC_IDR) Slow Crystal Oscillator Error Interrupt Disable */
-/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
-#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main Crystal Oscillator Status */
-#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */
-#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
-#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */
-#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
-#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */
-#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
-#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
-#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
-#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
-#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
-#define PMC_SR_XT32KERR (0x1u << 21) /**< \brief (PMC_SR) Slow Crystal Oscillator Error */
-/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
-#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
-#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */
-#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
-#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */
-#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
-#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
-#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
-#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
-#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
-#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
-#define PMC_IMR_XT32KERR (0x1u << 21) /**< \brief (PMC_IMR) Slow Crystal Oscillator Error Interrupt Mask */
-/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
-#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
-#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
-#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
-#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
-#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
-#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
-#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
-#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
-#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
-#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
-#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
-#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
-#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
-#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
-#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
-#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
-#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
-#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
-#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
-#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */
-#define PMC_FSMR_FLPM_Pos 21
-#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */
-#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos)))
-#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */
-#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */
-#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) Idle mode */
-#define PMC_FSMR_FFLPM (0x1u << 23) /**< \brief (PMC_FSMR) Force Flash Low-power Mode */
-/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
-#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */
-#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 1 */
-#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 2 */
-#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 3 */
-#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 4 */
-#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 5 */
-#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 6 */
-#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 7 */
-#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 8 */
-#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 9 */
-#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 10 */
-#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 11 */
-#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 12 */
-#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 13 */
-#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 14 */
-#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 15 */
-/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
-#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
-/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */
-#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */
-#define PMC_WPMR_WPKEY_Pos 8
-#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */
-#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
-#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
-/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */
-#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */
-#define PMC_WPSR_WPVSRC_Pos 8
-#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */
-/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */
-#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */
-#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */
-#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */
-#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */
-#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */
-#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */
-#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */
-#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */
-#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */
-#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */
-#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */
-#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */
-#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */
-#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */
-#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */
-#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */
-#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */
-#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */
-#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */
-#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */
-#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */
-#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */
-#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */
-#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */
-#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */
-/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */
-#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */
-#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */
-#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */
-#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */
-#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */
-#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */
-#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */
-#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */
-#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */
-#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */
-#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */
-#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */
-#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */
-#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */
-#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */
-#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */
-#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */
-#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */
-#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */
-#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */
-#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */
-#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */
-#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */
-#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */
-#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */
-/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */
-#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */
-#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */
-#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */
-#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */
-#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */
-#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */
-#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */
-#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */
-#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */
-#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */
-#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */
-#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */
-#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */
-#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */
-#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */
-#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */
-#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */
-#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */
-#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */
-#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */
-#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */
-#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */
-#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */
-#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */
-#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */
-/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */
-#define PMC_PCR_PID_Pos 0
-#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */
-#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos)))
-#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */
-#define PMC_PCR_DIV_Pos 16
-#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */
-#define PMC_PCR_DIV(value) ((PMC_PCR_DIV_Msk & ((value) << PMC_PCR_DIV_Pos)))
-#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */
-#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */
-#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */
-#define PMC_PCR_DIV_PERIPH_DIV8_MCK (0x3u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/8 */
-#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */
-/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
-#define PMC_OCR_CAL4_Pos 0
-#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */
-#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
-#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */
-#define PMC_OCR_CAL8_Pos 8
-#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */
-#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
-#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */
-#define PMC_OCR_CAL12_Pos 16
-#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */
-#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
-#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */
-/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */
-#define PMC_SLPWK_ER0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable */
-#define PMC_SLPWK_ER0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable */
-/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */
-#define PMC_SLPWK_DR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable */
-#define PMC_SLPWK_DR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable */
-/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */
-#define PMC_SLPWK_SR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status */
-#define PMC_SLPWK_SR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status */
-/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */
-#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR0) Peripheral 7 Activity Status */
-#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */
-#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */
-#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */
-#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */
-#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */
-#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */
-#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */
-#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */
-#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */
-#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */
-#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */
-#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */
-#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */
-#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */
-#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */
-#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */
-#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */
-#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */
-#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */
-#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */
-#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */
-#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */
-#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ASR0) Peripheral 30 Activity Status */
-#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ASR0) Peripheral 31 Activity Status */
-/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */
-#define PMC_SLPWK_ER1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable */
-#define PMC_SLPWK_ER1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable */
-/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */
-#define PMC_SLPWK_DR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable */
-#define PMC_SLPWK_DR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable */
-/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */
-#define PMC_SLPWK_SR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status */
-#define PMC_SLPWK_SR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status */
-/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */
-#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ASR1) Peripheral 32 Activity Status */
-#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ASR1) Peripheral 33 Activity Status */
-#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ASR1) Peripheral 34 Activity Status */
-#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ASR1) Peripheral 35 Activity Status */
-#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ASR1) Peripheral 37 Activity Status */
-#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR1) Peripheral 39 Activity Status */
-#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR1) Peripheral 40 Activity Status */
-#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR1) Peripheral 41 Activity Status */
-#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR1) Peripheral 42 Activity Status */
-#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR1) Peripheral 43 Activity Status */
-#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR1) Peripheral 44 Activity Status */
-#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR1) Peripheral 45 Activity Status */
-#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR1) Peripheral 46 Activity Status */
-#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR1) Peripheral 47 Activity Status */
-#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR1) Peripheral 48 Activity Status */
-#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR1) Peripheral 49 Activity Status */
-#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR1) Peripheral 50 Activity Status */
-#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR1) Peripheral 51 Activity Status */
-#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR1) Peripheral 52 Activity Status */
-#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR1) Peripheral 53 Activity Status */
-#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR1) Peripheral 56 Activity Status */
-#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR1) Peripheral 57 Activity Status */
-#define PMC_SLPWK_ASR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR1) Peripheral 58 Activity Status */
-#define PMC_SLPWK_ASR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR1) Peripheral 59 Activity Status */
-#define PMC_SLPWK_ASR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR1) Peripheral 60 Activity Status */
-/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */
-#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */
-
-/*@}*/
-
-
-#endif /* _SAMS70_PMC_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/pwm.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/pwm.h
deleted file mode 100644
index fb3c8fb..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/pwm.h
+++ /dev/null
@@ -1,715 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PWM_COMPONENT_
-#define _SAMS70_PWM_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_PWM Pulse Width Modulation Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief PwmCh_num hardware registers */
-typedef struct {
- __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
- __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
- __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
- __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
- __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
- __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
- __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
- __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
-} PwmCh_num;
-/** \brief PwmCmp hardware registers */
-typedef struct {
- __IO uint32_t PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
- __O uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
- __IO uint32_t PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
- __O uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
-} PwmCmp;
-/** \brief Pwm hardware registers */
-#define PWMCMP_NUMBER 8
-#define PWMCH_NUM_NUMBER 4
-typedef struct {
- __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
- __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
- __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
- __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
- __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
- __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
- __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
- __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
- __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
- __O uint32_t PWM_DMAR; /**< \brief (Pwm Offset: 0x24) PWM DMA Register */
- __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
- __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
- __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
- __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
- __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
- __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
- __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
- __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
- __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
- __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
- __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
- __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
- __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
- __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
- __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
- __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
- __IO uint32_t PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */
- __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
- __I uint32_t Reserved1[3];
- __IO uint32_t PWM_ELMR[8]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
- __I uint32_t Reserved2[1];
- __IO uint32_t PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */
- __O uint32_t PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */
- __I uint32_t Reserved3[2];
- __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */
- __I uint32_t Reserved4[3];
- __IO uint32_t PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */
- __I uint32_t Reserved5[8];
- __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */
- __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */
- __I uint32_t Reserved6[17];
- PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
- __I uint32_t Reserved7[20];
- PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
- __I uint32_t Reserved8[96];
- __O uint32_t PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */
- __I uint32_t Reserved9[7];
- __O uint32_t PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */
- __I uint32_t Reserved10[2];
- __IO uint32_t PWM_ETRG1; /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */
- __IO uint32_t PWM_LEBR1; /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */
- __I uint32_t Reserved11[3];
- __O uint32_t PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */
- __I uint32_t Reserved12[2];
- __IO uint32_t PWM_ETRG2; /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */
- __IO uint32_t PWM_LEBR2; /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */
- __I uint32_t Reserved13[3];
- __O uint32_t PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */
- __I uint32_t Reserved14[2];
- __IO uint32_t PWM_ETRG3; /**< \brief (Pwm Offset: 0x46C) PWM External Trigger Register (trg_num = 3) */
- __IO uint32_t PWM_LEBR3; /**< \brief (Pwm Offset: 0x470) PWM Leading-Edge Blanking Register (trg_num = 3) */
- __I uint32_t Reserved15[6];
- __IO uint32_t PWM_ETRG4; /**< \brief (Pwm Offset: 0x48C) PWM External Trigger Register (trg_num = 4) */
- __IO uint32_t PWM_LEBR4; /**< \brief (Pwm Offset: 0x490) PWM Leading-Edge Blanking Register (trg_num = 4) */
-} Pwm;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
-#define PWM_CLK_DIVA_Pos 0
-#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA Divide Factor */
-#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
-#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) /**< \brief (PWM_CLK) CLKA clock is turned off */
-#define PWM_CLK_DIVA_PREA (0x1u << 0) /**< \brief (PWM_CLK) CLKA clock is clock selected by PREA */
-#define PWM_CLK_PREA_Pos 8
-#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA Source Clock Selection */
-#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
-#define PWM_CLK_PREA_CLK (0x0u << 8) /**< \brief (PWM_CLK) Peripheral clock */
-#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) /**< \brief (PWM_CLK) Peripheral clock/2 */
-#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) /**< \brief (PWM_CLK) Peripheral clock/4 */
-#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) /**< \brief (PWM_CLK) Peripheral clock/8 */
-#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) /**< \brief (PWM_CLK) Peripheral clock/16 */
-#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) /**< \brief (PWM_CLK) Peripheral clock/32 */
-#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) /**< \brief (PWM_CLK) Peripheral clock/64 */
-#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) /**< \brief (PWM_CLK) Peripheral clock/128 */
-#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) /**< \brief (PWM_CLK) Peripheral clock/256 */
-#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) /**< \brief (PWM_CLK) Peripheral clock/512 */
-#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) /**< \brief (PWM_CLK) Peripheral clock/1024 */
-#define PWM_CLK_DIVB_Pos 16
-#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKB Divide Factor */
-#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
-#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) /**< \brief (PWM_CLK) CLKB clock is turned off */
-#define PWM_CLK_DIVB_PREB (0x1u << 16) /**< \brief (PWM_CLK) CLKB clock is clock selected by PREB */
-#define PWM_CLK_PREB_Pos 24
-#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKB Source Clock Selection */
-#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
-#define PWM_CLK_PREB_CLK (0x0u << 24) /**< \brief (PWM_CLK) Peripheral clock */
-#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) /**< \brief (PWM_CLK) Peripheral clock/2 */
-#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) /**< \brief (PWM_CLK) Peripheral clock/4 */
-#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) /**< \brief (PWM_CLK) Peripheral clock/8 */
-#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) /**< \brief (PWM_CLK) Peripheral clock/16 */
-#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) /**< \brief (PWM_CLK) Peripheral clock/32 */
-#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) /**< \brief (PWM_CLK) Peripheral clock/64 */
-#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) /**< \brief (PWM_CLK) Peripheral clock/128 */
-#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) /**< \brief (PWM_CLK) Peripheral clock/256 */
-#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) /**< \brief (PWM_CLK) Peripheral clock/512 */
-#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) /**< \brief (PWM_CLK) Peripheral clock/1024 */
-/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
-#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
-#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
-#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
-#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
-/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
-#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
-#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
-#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
-#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
-/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
-#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
-#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
-#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
-#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
-/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
-#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
-#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
-#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
-#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
-#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
-#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
-#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
-#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
-/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
-#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
-#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
-#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
-#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
-#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
-#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
-#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
-#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
-/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
-#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
-#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
-#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
-#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
-#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
-#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
-#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
-#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
-/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
-#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
-#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
-#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
-#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
-#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
-#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
-#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
-#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
-/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
-#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
-#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
-#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
-#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
-#define PWM_SCM_UPDM_Pos 16
-#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
-#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos)))
-#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
-#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
-#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA and automatic update of synchronous channels */
-#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Transfer Request Mode */
-#define PWM_SCM_PTRCS_Pos 21
-#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Transfer Request Comparison Selection */
-#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
-/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */
-#define PWM_DMAR_DMADUTY_Pos 0
-#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */
-#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos)))
-/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
-#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
-/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
-#define PWM_SCUP_UPR_Pos 0
-#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
-#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
-#define PWM_SCUP_UPRCNT_Pos 4
-#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
-#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
-/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
-#define PWM_SCUPUPD_UPRUPD_Pos 0
-#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
-#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
-/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
-#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
-#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
-#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
-#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
-#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
-#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
-#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
-#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
-#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
-#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
-#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
-#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
-#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
-#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
-#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
-#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
-#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
-#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
-/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
-#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
-#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
-#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
-#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
-#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
-#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
-#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
-#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
-#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
-#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
-#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
-#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
-#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
-#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
-#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
-#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
-#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
-#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
-/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
-#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
-#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
-#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
-#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
-#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
-#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
-#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
-#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
-#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
-#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
-#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
-#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
-#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
-#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
-#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
-#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
-#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
-#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
-/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
-#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
-#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
-#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
-#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
-#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
-#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
-#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
-#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
-#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
-#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
-#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
-#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
-#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
-#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
-#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
-#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
-#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
-#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
-/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
-#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
-#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
-#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
-#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
-#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
-#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
-#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
-#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
-/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
-#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
-#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
-#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
-#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
-#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
-#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
-#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
-#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
-/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
-#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
-#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
-#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
-#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
-#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
-#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
-#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
-#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
-/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
-#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
-#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
-#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
-#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
-#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
-#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
-#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
-#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
-/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
-#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
-#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
-#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
-#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
-#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
-#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
-#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
-#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
-/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
-#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
-#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
-#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
-#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
-#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
-#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
-#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
-#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
-/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
-#define PWM_FMR_FPOL_Pos 0
-#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */
-#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
-#define PWM_FMR_FMOD_Pos 8
-#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */
-#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
-#define PWM_FMR_FFIL_Pos 16
-#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */
-#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
-/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
-#define PWM_FSR_FIV_Pos 0
-#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */
-#define PWM_FSR_FS_Pos 8
-#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */
-/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
-#define PWM_FCR_FCLR_Pos 0
-#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */
-#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
-/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */
-#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */
-#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */
-#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */
-#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */
-#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */
-#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */
-#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */
-#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */
-/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
-#define PWM_FPE_FPE0_Pos 0
-#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */
-#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
-#define PWM_FPE_FPE1_Pos 8
-#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */
-#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
-#define PWM_FPE_FPE2_Pos 16
-#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */
-#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
-#define PWM_FPE_FPE3_Pos 24
-#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */
-#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
-/* -------- PWM_ELMR[8] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
-#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[8]) Comparison 0 Selection */
-#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[8]) Comparison 1 Selection */
-#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[8]) Comparison 2 Selection */
-#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[8]) Comparison 3 Selection */
-#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[8]) Comparison 4 Selection */
-#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[8]) Comparison 5 Selection */
-#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[8]) Comparison 6 Selection */
-#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[8]) Comparison 7 Selection */
-/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */
-#define PWM_SSPR_SPRD_Pos 0
-#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */
-#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos)))
-#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */
-/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */
-#define PWM_SSPUP_SPRDUP_Pos 0
-#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */
-#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos)))
-/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */
-#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */
-#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */
-#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */
-#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */
-/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */
-#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */
-#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */
-#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */
-#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */
-#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */
-#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */
-#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */
-#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */
-/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */
-#define PWM_WPCR_WPCMD_Pos 0
-#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */
-#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
-#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */
-#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */
-#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */
-#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */
-#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */
-#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */
-#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */
-#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */
-#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */
-#define PWM_WPCR_WPKEY_Pos 8
-#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */
-#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
-#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */
-/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */
-#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
-#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
-#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
-#define PWM_WPSR_WPVSRC_Pos 16
-#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
-/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
-#define PWM_CMPV_CV_Pos 0
-#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
-#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
-#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
-/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
-#define PWM_CMPVUPD_CVUPD_Pos 0
-#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
-#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
-#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
-/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
-#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
-#define PWM_CMPM_CTR_Pos 4
-#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
-#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
-#define PWM_CMPM_CPR_Pos 8
-#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
-#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
-#define PWM_CMPM_CPRCNT_Pos 12
-#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
-#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
-#define PWM_CMPM_CUPR_Pos 16
-#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
-#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
-#define PWM_CMPM_CUPRCNT_Pos 20
-#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
-#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
-/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
-#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
-#define PWM_CMPMUPD_CTRUPD_Pos 4
-#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
-#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
-#define PWM_CMPMUPD_CPRUPD_Pos 8
-#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
-#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
-#define PWM_CMPMUPD_CUPRUPD_Pos 16
-#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
-#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
-/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
-#define PWM_CMR_CPRE_Pos 0
-#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
-#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos)))
-#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Peripheral clock */
-#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Peripheral clock/2 */
-#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Peripheral clock/4 */
-#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Peripheral clock/8 */
-#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Peripheral clock/16 */
-#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Peripheral clock/32 */
-#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Peripheral clock/64 */
-#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Peripheral clock/128 */
-#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Peripheral clock/256 */
-#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Peripheral clock/512 */
-#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Peripheral clock/1024 */
-#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
-#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
-#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
-#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
-#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
-#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */
-#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */
-#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */
-#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
-#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
-#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
-#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */
-/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
-#define PWM_CDTY_CDTY_Pos 0
-#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
-#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
-/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
-#define PWM_CDTYUPD_CDTYUPD_Pos 0
-#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
-#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
-/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
-#define PWM_CPRD_CPRD_Pos 0
-#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
-#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
-/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
-#define PWM_CPRDUPD_CPRDUPD_Pos 0
-#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
-#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
-/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
-#define PWM_CCNT_CNT_Pos 0
-#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
-/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
-#define PWM_DT_DTH_Pos 0
-#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
-#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
-#define PWM_DT_DTL_Pos 16
-#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
-#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
-/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
-#define PWM_DTUPD_DTHUPD_Pos 0
-#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
-#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
-#define PWM_DTUPD_DTLUPD_Pos 16
-#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
-#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
-/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */
-#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */
-#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */
-/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */
-#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */
-#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */
-/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */
-#define PWM_ETRG1_MAXCNT_Pos 0
-#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */
-#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos)))
-#define PWM_ETRG1_TRGMODE_Pos 24
-#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */
-#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos)))
-#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */
-#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */
-#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */
-#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */
-#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */
-#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */
-#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */
-#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */
-#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */
-#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */
-/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */
-#define PWM_LEBR1_LEBDELAY_Pos 0
-#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */
-#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos)))
-#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */
-#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */
-#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */
-#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */
-/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */
-#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */
-#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */
-/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */
-#define PWM_ETRG2_MAXCNT_Pos 0
-#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */
-#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos)))
-#define PWM_ETRG2_TRGMODE_Pos 24
-#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */
-#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos)))
-#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */
-#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */
-#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */
-#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */
-#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */
-#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */
-#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */
-#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */
-#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */
-#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */
-/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */
-#define PWM_LEBR2_LEBDELAY_Pos 0
-#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */
-#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos)))
-#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */
-#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */
-#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */
-#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */
-/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */
-#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */
-#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */
-/* -------- PWM_ETRG3 : (PWM Offset: 0x46C) PWM External Trigger Register (trg_num = 3) -------- */
-#define PWM_ETRG3_MAXCNT_Pos 0
-#define PWM_ETRG3_MAXCNT_Msk (0xffffffu << PWM_ETRG3_MAXCNT_Pos) /**< \brief (PWM_ETRG3) Maximum Counter value */
-#define PWM_ETRG3_MAXCNT(value) ((PWM_ETRG3_MAXCNT_Msk & ((value) << PWM_ETRG3_MAXCNT_Pos)))
-#define PWM_ETRG3_TRGMODE_Pos 24
-#define PWM_ETRG3_TRGMODE_Msk (0x3u << PWM_ETRG3_TRGMODE_Pos) /**< \brief (PWM_ETRG3) External Trigger Mode */
-#define PWM_ETRG3_TRGMODE(value) ((PWM_ETRG3_TRGMODE_Msk & ((value) << PWM_ETRG3_TRGMODE_Pos)))
-#define PWM_ETRG3_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG3) External trigger is not enabled. */
-#define PWM_ETRG3_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG3) External PWM Reset Mode */
-#define PWM_ETRG3_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG3) External PWM Start Mode */
-#define PWM_ETRG3_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG3) Cycle-by-cycle Duty Mode */
-#define PWM_ETRG3_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG3) Edge Selection */
-#define PWM_ETRG3_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG3) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */
-#define PWM_ETRG3_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG3) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */
-#define PWM_ETRG3_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG3) Filtered input */
-#define PWM_ETRG3_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG3) Trigger Source */
-#define PWM_ETRG3_RFEN (0x1u << 31) /**< \brief (PWM_ETRG3) Recoverable Fault Enable */
-/* -------- PWM_LEBR3 : (PWM Offset: 0x470) PWM Leading-Edge Blanking Register (trg_num = 3) -------- */
-#define PWM_LEBR3_LEBDELAY_Pos 0
-#define PWM_LEBR3_LEBDELAY_Msk (0x7fu << PWM_LEBR3_LEBDELAY_Pos) /**< \brief (PWM_LEBR3) Leading-Edge Blanking Delay for TRGINx */
-#define PWM_LEBR3_LEBDELAY(value) ((PWM_LEBR3_LEBDELAY_Msk & ((value) << PWM_LEBR3_LEBDELAY_Pos)))
-#define PWM_LEBR3_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR3) PWML Falling Edge Enable */
-#define PWM_LEBR3_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR3) PWML Rising Edge Enable */
-#define PWM_LEBR3_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR3) PWMH Falling Edge Enable */
-#define PWM_LEBR3_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR3) PWMH Rising Edge Enable */
-/* -------- PWM_ETRG4 : (PWM Offset: 0x48C) PWM External Trigger Register (trg_num = 4) -------- */
-#define PWM_ETRG4_MAXCNT_Pos 0
-#define PWM_ETRG4_MAXCNT_Msk (0xffffffu << PWM_ETRG4_MAXCNT_Pos) /**< \brief (PWM_ETRG4) Maximum Counter value */
-#define PWM_ETRG4_MAXCNT(value) ((PWM_ETRG4_MAXCNT_Msk & ((value) << PWM_ETRG4_MAXCNT_Pos)))
-#define PWM_ETRG4_TRGMODE_Pos 24
-#define PWM_ETRG4_TRGMODE_Msk (0x3u << PWM_ETRG4_TRGMODE_Pos) /**< \brief (PWM_ETRG4) External Trigger Mode */
-#define PWM_ETRG4_TRGMODE(value) ((PWM_ETRG4_TRGMODE_Msk & ((value) << PWM_ETRG4_TRGMODE_Pos)))
-#define PWM_ETRG4_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG4) External trigger is not enabled. */
-#define PWM_ETRG4_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG4) External PWM Reset Mode */
-#define PWM_ETRG4_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG4) External PWM Start Mode */
-#define PWM_ETRG4_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG4) Cycle-by-cycle Duty Mode */
-#define PWM_ETRG4_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG4) Edge Selection */
-#define PWM_ETRG4_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG4) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */
-#define PWM_ETRG4_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG4) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */
-#define PWM_ETRG4_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG4) Filtered input */
-#define PWM_ETRG4_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG4) Trigger Source */
-#define PWM_ETRG4_RFEN (0x1u << 31) /**< \brief (PWM_ETRG4) Recoverable Fault Enable */
-/* -------- PWM_LEBR4 : (PWM Offset: 0x490) PWM Leading-Edge Blanking Register (trg_num = 4) -------- */
-#define PWM_LEBR4_LEBDELAY_Pos 0
-#define PWM_LEBR4_LEBDELAY_Msk (0x7fu << PWM_LEBR4_LEBDELAY_Pos) /**< \brief (PWM_LEBR4) Leading-Edge Blanking Delay for TRGINx */
-#define PWM_LEBR4_LEBDELAY(value) ((PWM_LEBR4_LEBDELAY_Msk & ((value) << PWM_LEBR4_LEBDELAY_Pos)))
-#define PWM_LEBR4_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR4) PWML Falling Edge Enable */
-#define PWM_LEBR4_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR4) PWML Rising Edge Enable */
-#define PWM_LEBR4_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR4) PWMH Falling Edge Enable */
-#define PWM_LEBR4_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR4) PWMH Rising Edge Enable */
-
-/*@}*/
-
-
-#endif /* _SAMS70_PWM_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/qspi.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/qspi.h
deleted file mode 100644
index 6600ba3..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/qspi.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_QSPI_COMPONENT_
-#define _SAMS70_QSPI_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */
-/* ============================================================================= */
-/** \addtogroup SAMS70_QSPI Quad Serial Peripheral Interface */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Qspi hardware registers */
-typedef struct {
- __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */
- __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */
- __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */
- __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */
- __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */
- __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */
- __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */
- __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */
- __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */
- __I uint32_t Reserved1[3];
- __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */
- __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */
- __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */
- __I uint32_t Reserved2[1];
- __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */
- __O uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */
- __I uint32_t Reserved3[39];
- __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */
- __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */
-} Qspi;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */
-#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */
-#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */
-#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */
-#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */
-/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */
-#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */
-#define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */
-#define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */
-#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */
-#define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */
-#define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */
-#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */
-#define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */
-#define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */
-#define QSPI_MR_CSMODE_Pos 4
-#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */
-#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos)))
-#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */
-#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */
-#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */
-#define QSPI_MR_NBBITS_Pos 8
-#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */
-#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos)))
-#define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */
-#define QSPI_MR_NBBITS_9_BIT (0x1u << 8) /**< \brief (QSPI_MR) 9 bits for transfer */
-#define QSPI_MR_NBBITS_10_BIT (0x2u << 8) /**< \brief (QSPI_MR) 10 bits for transfer */
-#define QSPI_MR_NBBITS_11_BIT (0x3u << 8) /**< \brief (QSPI_MR) 11 bits for transfer */
-#define QSPI_MR_NBBITS_12_BIT (0x4u << 8) /**< \brief (QSPI_MR) 12 bits for transfer */
-#define QSPI_MR_NBBITS_13_BIT (0x5u << 8) /**< \brief (QSPI_MR) 13 bits for transfer */
-#define QSPI_MR_NBBITS_14_BIT (0x6u << 8) /**< \brief (QSPI_MR) 14 bits for transfer */
-#define QSPI_MR_NBBITS_15_BIT (0x7u << 8) /**< \brief (QSPI_MR) 15 bits for transfer */
-#define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */
-#define QSPI_MR_DLYBCT_Pos 16
-#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */
-#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos)))
-#define QSPI_MR_DLYCS_Pos 24
-#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */
-#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos)))
-/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */
-#define QSPI_RDR_RD_Pos 0
-#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */
-/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */
-#define QSPI_TDR_TD_Pos 0
-#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */
-#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos)))
-/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */
-#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full */
-#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty */
-#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty */
-#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status */
-#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */
-#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */
-#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */
-#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */
-/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */
-#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */
-#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */
-#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */
-#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */
-#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */
-#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */
-#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */
-/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */
-#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */
-#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */
-#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */
-#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */
-#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */
-#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */
-#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */
-/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */
-#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */
-#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */
-#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */
-#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */
-#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */
-#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */
-#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */
-/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */
-#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */
-#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */
-#define QSPI_SCR_SCBR_Pos 8
-#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */
-#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos)))
-#define QSPI_SCR_DLYBS_Pos 16
-#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */
-#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos)))
-/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */
-#define QSPI_IAR_ADDR_Pos 0
-#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */
-#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos)))
-/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */
-#define QSPI_ICR_INST_Pos 0
-#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */
-#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos)))
-#define QSPI_ICR_OPT_Pos 16
-#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */
-#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos)))
-/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */
-#define QSPI_IFR_WIDTH_Pos 0
-#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */
-#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos)))
-#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */
-#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */
-#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */
-#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */
-#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */
-#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */
-#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */
-#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */
-#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */
-#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */
-#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */
-#define QSPI_IFR_OPTL_Pos 8
-#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */
-#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos)))
-#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */
-#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */
-#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */
-#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */
-#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */
-#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */
-#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */
-#define QSPI_IFR_TFRTYP_Pos 12
-#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */
-#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos)))
-#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */
-#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */
-#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */
-#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */
-#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */
-#define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */
-#define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */
-#define QSPI_IFR_NBDUM_Pos 16
-#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */
-#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos)))
-/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */
-#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */
-#define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */
-#define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */
-#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */
-/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */
-#define QSPI_SKR_USRK_Pos 0
-#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */
-#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos)))
-/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */
-#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */
-#define QSPI_WPMR_WPKEY_Pos 8
-#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */
-#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos)))
-#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
-/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */
-#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */
-#define QSPI_WPSR_WPVSRC_Pos 8
-#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_QSPI_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/rstc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/rstc.h
deleted file mode 100644
index 592f50d..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/rstc.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RSTC_COMPONENT_
-#define _SAMS70_RSTC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Reset Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_RSTC Reset Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Rstc hardware registers */
-typedef struct {
- __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
- __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
- __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
-} Rstc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
-#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
-#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
-#define RSTC_CR_KEY_Pos 24
-#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */
-#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
-#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */
-/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
-#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
-#define RSTC_SR_RSTTYP_Pos 8
-#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
-#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */
-#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */
-#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */
-#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */
-#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */
-#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
-#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
-/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
-#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
-#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
-#define RSTC_MR_ERSTL_Pos 8
-#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
-#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
-#define RSTC_MR_KEY_Pos 24
-#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */
-#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
-#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */
-
-/*@}*/
-
-
-#endif /* _SAMS70_RSTC_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/rswdt.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/rswdt.h
deleted file mode 100644
index 09694f4..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/rswdt.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RSWDT_COMPONENT_
-#define _SAMS70_RSWDT_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */
-/* ============================================================================= */
-/** \addtogroup SAMS70_RSWDT Reinforced Safety Watchdog Timer */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Rswdt hardware registers */
-typedef struct {
- __O uint32_t RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */
- __IO uint32_t RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */
- __I uint32_t RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */
-} Rswdt;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */
-#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */
-#define RSWDT_CR_KEY_Pos 24
-#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */
-#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos)))
-#define RSWDT_CR_KEY_PASSWD (0xC4u << 24) /**< \brief (RSWDT_CR) Writing any other value in this field aborts the write operation. */
-/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */
-#define RSWDT_MR_WDV_Pos 0
-#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */
-#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos)))
-#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */
-#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */
-#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */
-#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */
-#define RSWDT_MR_ALLONES_Pos 16
-#define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) /**< \brief (RSWDT_MR) Must Always Be Written with 0xFFF */
-#define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos)))
-#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */
-#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */
-/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */
-#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */
-
-/*@}*/
-
-
-#endif /* _SAMS70_RSWDT_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/rtc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/rtc.h
deleted file mode 100644
index 2456bde..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/rtc.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RTC_COMPONENT_
-#define _SAMS70_RTC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Real-time Clock */
-/* ============================================================================= */
-/** \addtogroup SAMS70_RTC Real-time Clock */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Rtc hardware registers */
-typedef struct {
- __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */
- __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */
- __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */
- __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */
- __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
- __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
- __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */
- __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
- __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
- __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
- __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
- __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
-} Rtc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
-#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
-#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
-#define RTC_CR_TIMEVSEL_Pos 8
-#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
-#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos)))
-#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
-#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
-#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
-#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
-#define RTC_CR_CALEVSEL_Pos 16
-#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
-#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos)))
-#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
-#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
-#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
-/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
-#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
-#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */
-#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */
-#define RTC_MR_CORRECTION_Pos 8
-#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */
-#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)))
-#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */
-#define RTC_MR_OUT0_Pos 16
-#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */
-#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos)))
-#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */
-#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */
-#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */
-#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */
-#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */
-#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) Output toggles when alarm flag rises */
-#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */
-#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) Duty cycle programmable pulse */
-#define RTC_MR_OUT1_Pos 20
-#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */
-#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos)))
-#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */
-#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */
-#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */
-#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */
-#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */
-#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) Output toggles when alarm flag rises */
-#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */
-#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) Duty cycle programmable pulse */
-#define RTC_MR_THIGH_Pos 24
-#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */
-#define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos)))
-#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */
-#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */
-#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */
-#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */
-#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */
-#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */
-#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */
-#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */
-#define RTC_MR_TPERIOD_Pos 28
-#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */
-#define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos)))
-#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */
-#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */
-#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */
-#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */
-/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
-#define RTC_TIMR_SEC_Pos 0
-#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
-#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
-#define RTC_TIMR_MIN_Pos 8
-#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
-#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
-#define RTC_TIMR_HOUR_Pos 16
-#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
-#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
-#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
-/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
-#define RTC_CALR_CENT_Pos 0
-#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
-#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
-#define RTC_CALR_YEAR_Pos 8
-#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
-#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
-#define RTC_CALR_MONTH_Pos 16
-#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
-#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
-#define RTC_CALR_DAY_Pos 21
-#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
-#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
-#define RTC_CALR_DATE_Pos 24
-#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
-#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
-/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
-#define RTC_TIMALR_SEC_Pos 0
-#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
-#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
-#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
-#define RTC_TIMALR_MIN_Pos 8
-#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
-#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
-#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
-#define RTC_TIMALR_HOUR_Pos 16
-#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
-#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
-#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
-#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
-/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
-#define RTC_CALALR_MONTH_Pos 16
-#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
-#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
-#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
-#define RTC_CALALR_DATE_Pos 24
-#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
-#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
-#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
-/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
-#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
-#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */
-#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */
-#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
-#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */
-#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */
-#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
-#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */
-#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */
-#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
-#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */
-#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */
-#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
-#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */
-#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */
-#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */
-#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */
-#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */
-/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
-#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
-#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
-#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
-#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
-#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
-#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */
-/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
-#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
-#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
-#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
-#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
-#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
-#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */
-/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
-#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
-#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
-#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
-#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
-#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
-#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */
-/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
-#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
-#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
-#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
-#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
-#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
-#define RTC_IMR_TDERR (0x1u << 5) /**< \brief (RTC_IMR) Time and/or Date Error Mask */
-/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
-#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
-#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
-#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
-#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
-
-/*@}*/
-
-
-#endif /* _SAMS70_RTC_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/rtt.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/rtt.h
deleted file mode 100644
index d9c76c5..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/rtt.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RTT_COMPONENT_
-#define _SAMS70_RTT_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Real-time Timer */
-/* ============================================================================= */
-/** \addtogroup SAMS70_RTT Real-time Timer */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Rtt hardware registers */
-typedef struct {
- __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
- __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
- __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
- __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
-} Rtt;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
-#define RTT_MR_RTPRES_Pos 0
-#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
-#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
-#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
-#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
-#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
-#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */
-#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */
-/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
-#define RTT_AR_ALMV_Pos 0
-#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
-#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
-/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
-#define RTT_VR_CRTV_Pos 0
-#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
-/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
-#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status (cleared on read) */
-#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status (cleared on read) */
-
-/*@}*/
-
-
-#endif /* _SAMS70_RTT_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/sdramc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/sdramc.h
deleted file mode 100644
index 126e9ca..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/sdramc.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SDRAMC_COMPONENT_
-#define _SAMS70_SDRAMC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR SDRAM Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_SDRAMC SDRAM Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Sdramc hardware registers */
-typedef struct {
- __IO uint32_t SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */
- __IO uint32_t SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */
- __IO uint32_t SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */
- __I uint32_t Reserved1[1];
- __IO uint32_t SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */
- __O uint32_t SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */
- __O uint32_t SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */
- __I uint32_t SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */
- __I uint32_t SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */
- __IO uint32_t SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */
- __IO uint32_t SDRAMC_CFR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */
- __IO uint32_t SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register */
- __O uint32_t SDRAMC_OCMS_KEY1; /**< \brief (Sdramc Offset: 0x30) SDRAMC OCMS KEY1 Register */
- __O uint32_t SDRAMC_OCMS_KEY2; /**< \brief (Sdramc Offset: 0x34) SDRAMC OCMS KEY2 Register */
-} Sdramc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */
-#define SDRAMC_MR_MODE_Pos 0
-#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */
-#define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos)))
-#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */
-#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
-#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
-#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */
-#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */
-#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */
-#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */
-/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */
-#define SDRAMC_TR_COUNT_Pos 0
-#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */
-#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos)))
-/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */
-#define SDRAMC_CR_NC_Pos 0
-#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */
-#define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos)))
-#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */
-#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */
-#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */
-#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */
-#define SDRAMC_CR_NR_Pos 2
-#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */
-#define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos)))
-#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */
-#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */
-#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */
-#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */
-#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */
-#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */
-#define SDRAMC_CR_CAS_Pos 5
-#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */
-#define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos)))
-#define SDRAMC_CR_CAS_LATENCY1 (0x0u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */
-#define SDRAMC_CR_CAS_LATENCY2 (0x1u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */
-#define SDRAMC_CR_CAS_LATENCY3 (0x2u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */
-#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */
-#define SDRAMC_CR_TWR_Pos 8
-#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */
-#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos)))
-#define SDRAMC_CR_TRC_TRFC_Pos 12
-#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */
-#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos)))
-#define SDRAMC_CR_TRP_Pos 16
-#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */
-#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos)))
-#define SDRAMC_CR_TRCD_Pos 20
-#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */
-#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos)))
-#define SDRAMC_CR_TRAS_Pos 24
-#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */
-#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos)))
-#define SDRAMC_CR_TXSR_Pos 28
-#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */
-#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos)))
-/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */
-#define SDRAMC_LPR_LPCB_Pos 0
-#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */
-#define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos)))
-#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */
-#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */
-#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */
-#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */
-#define SDRAMC_LPR_PASR_Pos 4
-#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */
-#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos)))
-#define SDRAMC_LPR_TCSR_Pos 8
-#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */
-#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos)))
-#define SDRAMC_LPR_DS_Pos 10
-#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */
-#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos)))
-#define SDRAMC_LPR_TIMEOUT_Pos 12
-#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled */
-#define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos)))
-#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. */
-#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */
-#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */
-/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */
-#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */
-/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */
-#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */
-/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */
-#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */
-/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */
-#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status (cleared on read) */
-/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */
-#define SDRAMC_MDR_MD_Pos 0
-#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */
-#define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos)))
-#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */
-#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */
-/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */
-#define SDRAMC_CFR1_TMRD_Pos 0
-#define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos) /**< \brief (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command */
-#define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos)))
-#define SDRAMC_CFR1_UNAL (0x1u << 8) /**< \brief (SDRAMC_CFR1) Support Unaligned Access */
-#define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is not supported. */
-#define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is supported. */
-/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */
-#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */
-/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */
-#define SDRAMC_OCMS_KEY1_KEY1_Pos 0
-#define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< \brief (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 */
-#define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos)))
-/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */
-#define SDRAMC_OCMS_KEY2_KEY2_Pos 0
-#define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< \brief (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 */
-#define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos)))
-
-/*@}*/
-
-
-#endif /* _SAMS70_SDRAMC_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/smc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/smc.h
deleted file mode 100644
index 04954ec..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/smc.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SMC_COMPONENT_
-#define _SAMS70_SMC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Static Memory Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_SMC Static Memory Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief SmcCs_number hardware registers */
-typedef struct {
- __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
- __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
- __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
- __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC MODE Register */
-} SmcCs_number;
-/** \brief Smc hardware registers */
-#define SMCCS_NUMBER_NUMBER 4
-typedef struct {
- SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */
- __I uint32_t Reserved1[16];
- __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */
- __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */
- __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */
- __I uint32_t Reserved2[22];
- __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protection Mode Register */
- __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protection Status Register */
-} Smc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
-#define SMC_SETUP_NWE_SETUP_Pos 0
-#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
-#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
-#define SMC_SETUP_NCS_WR_SETUP_Pos 8
-#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */
-#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
-#define SMC_SETUP_NRD_SETUP_Pos 16
-#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
-#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
-#define SMC_SETUP_NCS_RD_SETUP_Pos 24
-#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */
-#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
-/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
-#define SMC_PULSE_NWE_PULSE_Pos 0
-#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
-#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
-#define SMC_PULSE_NCS_WR_PULSE_Pos 8
-#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
-#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
-#define SMC_PULSE_NRD_PULSE_Pos 16
-#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
-#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
-#define SMC_PULSE_NCS_RD_PULSE_Pos 24
-#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
-#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
-/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
-#define SMC_CYCLE_NWE_CYCLE_Pos 0
-#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
-#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
-#define SMC_CYCLE_NRD_CYCLE_Pos 16
-#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
-#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
-/* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */
-#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) Read Mode */
-#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) Write Mode */
-#define SMC_MODE_EXNW_MODE_Pos 4
-#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
-#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos)))
-#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
-#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
-#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
-#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */
-#define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8) /**< \brief (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */
-#define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8) /**< \brief (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */
-#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */
-#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit Data Bus */
-#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit Data Bus */
-#define SMC_MODE_TDF_CYCLES_Pos 16
-#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
-#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
-#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
-#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */
-#define SMC_MODE_PS_Pos 28
-#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */
-#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos)))
-#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */
-#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */
-#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */
-#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */
-/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */
-#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
-/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */
-#define SMC_KEY1_KEY1_Pos 0
-#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
-#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
-/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */
-#define SMC_KEY2_KEY2_Pos 0
-#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
-#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
-/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */
-#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */
-#define SMC_WPMR_WPKEY_Pos 8
-#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protection Key */
-#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))
-#define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8) /**< \brief (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
-/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */
-#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */
-#define SMC_WPSR_WPVSRC_Pos 8
-#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_SMC_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/spi.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/spi.h
deleted file mode 100644
index 0faef2c..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/spi.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SPI_COMPONENT_
-#define _SAMS70_SPI_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
-/* ============================================================================= */
-/** \addtogroup SAMS70_SPI Serial Peripheral Interface */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Spi hardware registers */
-typedef struct {
- __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */
- __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */
- __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */
- __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
- __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */
- __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
- __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
- __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
- __I uint32_t Reserved1[4];
- __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */
- __I uint32_t Reserved2[41];
- __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Mode Register */
- __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
-} Spi;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
-#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
-#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
-#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
-#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
-/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
-#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
-#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
-#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
-#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
-#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
-#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
-#define SPI_MR_PCS_Pos 16
-#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
-#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
-#define SPI_MR_DLYBCS_Pos 24
-#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
-#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
-/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
-#define SPI_RDR_RD_Pos 0
-#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
-#define SPI_RDR_PCS_Pos 16
-#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
-/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
-#define SPI_TDR_TD_Pos 0
-#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
-#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
-#define SPI_TDR_PCS_Pos 16
-#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
-#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
-#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */
-#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */
-#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */
-#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */
-#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */
-#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */
-#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) */
-#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
-#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
-#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
-#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
-#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
-#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
-#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
-#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
-#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
-#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
-#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
-#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
-#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
-#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
-/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
-#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
-#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
-#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
-#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
-#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
-#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
-#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
-/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
-#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
-#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
-#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
-#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */
-#define SPI_CSR_BITS_Pos 4
-#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
-#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos)))
-#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
-#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
-#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
-#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
-#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
-#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
-#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
-#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
-#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
-#define SPI_CSR_SCBR_Pos 8
-#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Bit Rate */
-#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
-#define SPI_CSR_DLYBS_Pos 16
-#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
-#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
-#define SPI_CSR_DLYBCT_Pos 24
-#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
-#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
-/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */
-#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */
-#define SPI_WPMR_WPKEY_Pos 8
-#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */
-#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos)))
-#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
-/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
-#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */
-#define SPI_WPSR_WPVSRC_Pos 8
-#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_SPI_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/ssc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/ssc.h
deleted file mode 100644
index 904716c..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/ssc.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SSC_COMPONENT_
-#define _SAMS70_SSC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_SSC Synchronous Serial Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Ssc hardware registers */
-typedef struct {
- __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */
- __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
- __I uint32_t Reserved1[2];
- __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
- __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
- __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
- __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
- __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
- __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
- __I uint32_t Reserved2[2];
- __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
- __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
- __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
- __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
- __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */
- __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
- __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
- __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
- __I uint32_t Reserved3[37];
- __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protection Mode Register */
- __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protection Status Register */
-} Ssc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
-#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
-#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
-#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
-#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
-#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
-/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
-#define SSC_CMR_DIV_Pos 0
-#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
-#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
-/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
-#define SSC_RCMR_CKS_Pos 0
-#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
-#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos)))
-#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
-#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
-#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
-#define SSC_RCMR_CKO_Pos 2
-#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
-#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos)))
-#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */
-#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */
-#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */
-#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
-#define SSC_RCMR_CKG_Pos 6
-#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
-#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos)))
-#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */
-#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */
-#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */
-#define SSC_RCMR_START_Pos 8
-#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
-#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos)))
-#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
-#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
-#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
-#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
-#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
-#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
-#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
-#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
-#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
-#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
-#define SSC_RCMR_STTDLY_Pos 16
-#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
-#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
-#define SSC_RCMR_PERIOD_Pos 24
-#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
-#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
-/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
-#define SSC_RFMR_DATLEN_Pos 0
-#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
-#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
-#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
-#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
-#define SSC_RFMR_DATNB_Pos 8
-#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
-#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
-#define SSC_RFMR_FSLEN_Pos 16
-#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
-#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
-#define SSC_RFMR_FSOS_Pos 20
-#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
-#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos)))
-#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */
-#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */
-#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */
-#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */
-#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */
-#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */
-#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
-#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
-#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
-#define SSC_RFMR_FSLEN_EXT_Pos 28
-#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
-#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
-/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
-#define SSC_TCMR_CKS_Pos 0
-#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
-#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos)))
-#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
-#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */
-#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */
-#define SSC_TCMR_CKO_Pos 2
-#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
-#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos)))
-#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */
-#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */
-#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */
-#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
-#define SSC_TCMR_CKG_Pos 6
-#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
-#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos)))
-#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */
-#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
-#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
-#define SSC_TCMR_START_Pos 8
-#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
-#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos)))
-#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */
-#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
-#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
-#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
-#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
-#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
-#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
-#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
-#define SSC_TCMR_STTDLY_Pos 16
-#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
-#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
-#define SSC_TCMR_PERIOD_Pos 24
-#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
-#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
-/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
-#define SSC_TFMR_DATLEN_Pos 0
-#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
-#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
-#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
-#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
-#define SSC_TFMR_DATNB_Pos 8
-#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per Frame */
-#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
-#define SSC_TFMR_FSLEN_Pos 16
-#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
-#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
-#define SSC_TFMR_FSOS_Pos 20
-#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
-#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos)))
-#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, TF pin is an input */
-#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, TF pin is an output */
-#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, TF pin is an output */
-#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
-#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
-#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
-#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
-#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
-#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
-#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
-#define SSC_TFMR_FSLEN_EXT_Pos 28
-#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
-#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
-/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
-#define SSC_RHR_RDAT_Pos 0
-#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
-/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
-#define SSC_THR_TDAT_Pos 0
-#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
-#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
-/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
-#define SSC_RSHR_RSDAT_Pos 0
-#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
-/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
-#define SSC_TSHR_TSDAT_Pos 0
-#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
-#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
-/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
-#define SSC_RC0R_CP0_Pos 0
-#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
-#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
-/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
-#define SSC_RC1R_CP1_Pos 0
-#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
-#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
-/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
-#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
-#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
-#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
-#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
-#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
-#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
-#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
-#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
-#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
-#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
-/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
-#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
-#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
-#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
-#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
-#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
-#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
-#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
-#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
-/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
-#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
-#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
-#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
-#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
-#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
-#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
-#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
-#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
-/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
-#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
-#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
-#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
-#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
-#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
-#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
-#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
-#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
-/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */
-#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protection Enable */
-#define SSC_WPMR_WPKEY_Pos 8
-#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protection Key */
-#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
-#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
-/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */
-#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protection Violation Status */
-#define SSC_WPSR_WPVSRC_Pos 8
-#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_SSC_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/supc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/supc.h
deleted file mode 100644
index 6e10ef4..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/supc.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SUPC_COMPONENT_
-#define _SAMS70_SUPC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Supply Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_SUPC Supply Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Supc hardware registers */
-typedef struct {
- __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
- __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
- __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
- __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */
- __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */
- __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
-} Supc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
-#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
-#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */
-#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */
-#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
-#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */
-#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */
-#define SUPC_CR_KEY_Pos 24
-#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
-#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
-#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation. */
-/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
-#define SUPC_SMMR_SMTH_Pos 0
-#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
-#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos)))
-#define SUPC_SMMR_SMSMPL_Pos 8
-#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
-#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos)))
-#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
-#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
-#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
-#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
-#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
-#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
-#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */
-#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
-#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
-#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */
-#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */
-/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
-#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
-#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */
-#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
-#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
-#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */
-#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */
-#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator Enable */
-#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */
-#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is used. */
-#define SUPC_MR_BKUPRETON (0x1u << 17) /**< \brief (SUPC_MR) SRAM On In Backup Mode */
-#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
-#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */
-#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */
-#define SUPC_MR_KEY_Pos 24
-#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
-#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
-#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation. */
-/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */
-#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */
-#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */
-#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */
-#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */
-#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */
-#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */
-#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */
-#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */
-#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */
-#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP0 */
-#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */
-#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */
-#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP1 */
-#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */
-#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */
-#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low-power Debouncer Clear */
-#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */
-#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */
-#define SUPC_WUMR_WKUPDBC_Pos 12
-#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */
-#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos)))
-#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
-#define SUPC_WUMR_WKUPDBC_3_SLCK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_32_SLCK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_512_SLCK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_4096_SLCK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
-#define SUPC_WUMR_WKUPDBC_32768_SLCK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
-#define SUPC_WUMR_LPDBC_Pos 16
-#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low-power Debouncer Period */
-#define SUPC_WUMR_LPDBC(value) ((SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos)))
-#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low-power debouncers. */
-#define SUPC_WUMR_LPDBC_2_RTCOUT (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */
-#define SUPC_WUMR_LPDBC_3_RTCOUT (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */
-#define SUPC_WUMR_LPDBC_4_RTCOUT (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */
-#define SUPC_WUMR_LPDBC_5_RTCOUT (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */
-#define SUPC_WUMR_LPDBC_6_RTCOUT (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */
-#define SUPC_WUMR_LPDBC_7_RTCOUT (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */
-#define SUPC_WUMR_LPDBC_8_RTCOUT (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */
-/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */
-#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 0 */
-#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 1 */
-#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 2 */
-#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 3 */
-#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 4 */
-#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 5 */
-#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 6 */
-#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 7 */
-#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 8 */
-#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 9 */
-#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 10 */
-#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 11 */
-#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 12 */
-#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 13 */
-#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */
-#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 0 */
-#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 1 */
-#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 2 */
-#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 3 */
-#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 4 */
-#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 5 */
-#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 6 */
-#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 7 */
-#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 8 */
-#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 9 */
-#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 10 */
-#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 11 */
-#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 12 */
-#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 13 */
-#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */
-#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */
-/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
-#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status (cleared on read) */
-#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) */
-#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status (cleared on read) */
-#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */
-#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
-#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status (cleared on read) */
-#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
-#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
-#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status (cleared on read) */
-#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */
-#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */
-#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
-#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */
-#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */
-#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
-#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */
-#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */
-#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) */
-#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) */
-#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */
-#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */
-#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */
-
-/*@}*/
-
-
-#endif /* _SAMS70_SUPC_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/tc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/tc.h
deleted file mode 100644
index 5969e8a..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/tc.h
+++ /dev/null
@@ -1,361 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TC_COMPONENT_
-#define _SAMS70_TC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Timer Counter */
-/* ============================================================================= */
-/** \addtogroup SAMS70_TC Timer Counter */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief TcChannel hardware registers */
-typedef struct {
- __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
- __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
- __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
- __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */
- __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */
- __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */
- __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */
- __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */
- __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */
- __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
- __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
- __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
- __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */
- __I uint32_t Reserved1[3];
-} TcChannel;
-/** \brief Tc hardware registers */
-#define TCCHANNEL_NUMBER 3
-typedef struct {
- TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
- __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */
- __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */
- __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
- __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
- __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
- __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
- __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */
- __I uint32_t Reserved1[2];
- __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */
-} Tc;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
-#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
-#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
-#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
-/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
-#define TC_CMR_TCCLKS_Pos 0
-#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
-#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos)))
-#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */
-#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */
-#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */
-#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */
-#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */
-#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
-#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
-#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
-#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
-#define TC_CMR_BURST_Pos 4
-#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
-#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos)))
-#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
-#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
-#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
-#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
-#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
-#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
-#define TC_CMR_ETRGEDG_Pos 8
-#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
-#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos)))
-#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
-#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
-#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
-#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
-#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
-#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
-#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
-#define TC_CMR_LDRA_Pos 16
-#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
-#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos)))
-#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
-#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
-#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
-#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
-#define TC_CMR_LDRB_Pos 18
-#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
-#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos)))
-#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
-#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
-#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
-#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
-#define TC_CMR_SBSMPLR_Pos 20
-#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */
-#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos)))
-#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */
-#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */
-#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */
-#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */
-#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */
-#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
-#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
-#define TC_CMR_EEVTEDG_Pos 8
-#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
-#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos)))
-#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
-#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
-#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
-#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
-#define TC_CMR_EEVT_Pos 10
-#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
-#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos)))
-#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
-#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
-#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
-#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
-#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
-#define TC_CMR_WAVSEL_Pos 13
-#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
-#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos)))
-#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
-#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
-#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
-#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
-#define TC_CMR_ACPA_Pos 16
-#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
-#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos)))
-#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
-#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
-#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
-#define TC_CMR_ACPC_Pos 18
-#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
-#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos)))
-#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
-#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
-#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
-#define TC_CMR_AEEVT_Pos 20
-#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
-#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos)))
-#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
-#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
-#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
-#define TC_CMR_ASWTRG_Pos 22
-#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
-#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos)))
-#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
-#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
-#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
-#define TC_CMR_BCPB_Pos 24
-#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
-#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos)))
-#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
-#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
-#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
-#define TC_CMR_BCPC_Pos 26
-#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
-#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos)))
-#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
-#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
-#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
-#define TC_CMR_BEEVT_Pos 28
-#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
-#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos)))
-#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
-#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
-#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
-#define TC_CMR_BSWTRG_Pos 30
-#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
-#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos)))
-#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
-#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
-#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
-#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
-/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
-#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
-#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */
-/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */
-#define TC_RAB_RAB_Pos 0
-#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */
-/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
-#define TC_CV_CV_Pos 0
-#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
-/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
-#define TC_RA_RA_Pos 0
-#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
-#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
-/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
-#define TC_RB_RB_Pos 0
-#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
-#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
-/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
-#define TC_RC_RC_Pos 0
-#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
-#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
-/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
-#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */
-#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */
-#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */
-#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */
-#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */
-#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */
-#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */
-#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */
-#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
-#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
-#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
-/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
-#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
-#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
-#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
-#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
-#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
-#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
-#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
-#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
-/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
-#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
-#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
-#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
-#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
-#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
-#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
-#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
-#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
-/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
-#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
-#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
-#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
-#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
-#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
-#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
-#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
-#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
-/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */
-#define TC_EMR_TRIGSRCA_Pos 0
-#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */
-#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos)))
-#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */
-#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */
-#define TC_EMR_TRIGSRCB_Pos 4
-#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */
-#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos)))
-#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */
-#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven internally by PWMx */
-#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */
-/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
-#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
-/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
-#define TC_BMR_TC0XC0S_Pos 0
-#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
-#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos)))
-#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
-#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
-#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
-#define TC_BMR_TC1XC1S_Pos 2
-#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
-#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos)))
-#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
-#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
-#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
-#define TC_BMR_TC2XC2S_Pos 4
-#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
-#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos)))
-#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
-#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */
-#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
-#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */
-#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */
-#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */
-#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */
-#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */
-#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */
-#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */
-#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */
-#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */
-#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */
-#define TC_BMR_MAXFILT_Pos 20
-#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */
-#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
-/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
-#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */
-#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */
-#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */
-/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
-#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */
-#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */
-#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */
-/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
-#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */
-#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */
-#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */
-/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
-#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */
-#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */
-#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */
-#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
-/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */
-#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */
-#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */
-/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */
-#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */
-#define TC_WPMR_WPKEY_Pos 8
-#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */
-#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
-#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
-
-/*@}*/
-
-
-#endif /* _SAMS70_TC_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/trng.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/trng.h
deleted file mode 100644
index 5b785aa..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/trng.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TRNG_COMPONENT_
-#define _SAMS70_TRNG_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR True Random Number Generator */
-/* ============================================================================= */
-/** \addtogroup SAMS70_TRNG True Random Number Generator */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Trng hardware registers */
-typedef struct {
- __O uint32_t TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */
- __I uint32_t Reserved1[3];
- __O uint32_t TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */
- __O uint32_t TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */
- __I uint32_t TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */
- __I uint32_t TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */
- __I uint32_t Reserved2[12];
- __I uint32_t TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */
-} Trng;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */
-#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */
-#define TRNG_CR_KEY_Pos 8
-#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key. */
-#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos)))
-#define TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */
-/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */
-#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */
-/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */
-#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */
-/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */
-#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */
-/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */
-#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */
-/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */
-#define TRNG_ODATA_ODATA_Pos 0
-#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */
-
-/*@}*/
-
-
-#endif /* _SAMS70_TRNG_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/twihs.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/twihs.h
deleted file mode 100644
index 366650f..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/twihs.h
+++ /dev/null
@@ -1,265 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TWIHS_COMPONENT_
-#define _SAMS70_TWIHS_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */
-/* ============================================================================= */
-/** \addtogroup SAMS70_TWIHS Two-wire Interface High Speed */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Twihs hardware registers */
-typedef struct {
- __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */
- __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */
- __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */
- __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */
- __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */
- __I uint32_t Reserved1[3];
- __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */
- __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */
- __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */
- __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */
- __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */
- __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */
- __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */
- __I uint32_t Reserved2[2];
- __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */
- __I uint32_t Reserved3[1];
- __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */
- __I uint32_t Reserved4[37];
- __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */
- __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */
-} Twihs;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */
-#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */
-#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */
-#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */
-#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */
-#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */
-#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */
-#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */
-#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */
-#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */
-#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */
-#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */
-#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */
-#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */
-#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */
-#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */
-#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */
-/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */
-#define TWIHS_MMR_IADRSZ_Pos 8
-#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */
-#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos)))
-#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */
-#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */
-#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */
-#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */
-#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */
-#define TWIHS_MMR_DADR_Pos 16
-#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */
-#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos)))
-/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */
-#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */
-#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */
-#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */
-#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */
-#define TWIHS_SMR_MASK_Pos 8
-#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */
-#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos)))
-#define TWIHS_SMR_SADR_Pos 16
-#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */
-#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos)))
-#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */
-#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */
-#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */
-#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */
-/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */
-#define TWIHS_IADR_IADR_Pos 0
-#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */
-#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos)))
-/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */
-#define TWIHS_CWGR_CLDIV_Pos 0
-#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */
-#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos)))
-#define TWIHS_CWGR_CHDIV_Pos 8
-#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */
-#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos)))
-#define TWIHS_CWGR_CKDIV_Pos 16
-#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */
-#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos)))
-#define TWIHS_CWGR_HOLD_Pos 24
-#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */
-#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos)))
-/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */
-#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */
-#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */
-#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */
-#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */
-#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */
-#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */
-#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */
-#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */
-#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */
-#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */
-#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */
-#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */
-#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */
-#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */
-#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */
-#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */
-#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */
-#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL line value */
-#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA line value */
-/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */
-#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */
-#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */
-#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */
-#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */
-#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */
-#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */
-#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */
-#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */
-#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */
-#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */
-#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */
-#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */
-#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */
-#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */
-#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */
-#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */
-/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */
-#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */
-#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */
-#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */
-#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */
-#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */
-#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */
-#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */
-#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */
-#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */
-#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */
-#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */
-#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */
-#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */
-#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */
-#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */
-#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */
-/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */
-#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */
-#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */
-#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */
-#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */
-#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */
-#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */
-#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */
-#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */
-#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */
-#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */
-#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */
-#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */
-#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */
-#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */
-#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */
-#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */
-/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */
-#define TWIHS_RHR_RXDATA_Pos 0
-#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */
-/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */
-#define TWIHS_THR_TXDATA_Pos 0
-#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */
-#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos)))
-/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */
-#define TWIHS_SMBTR_PRESC_Pos 0
-#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */
-#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos)))
-#define TWIHS_SMBTR_TLOWS_Pos 8
-#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */
-#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos)))
-#define TWIHS_SMBTR_TLOWM_Pos 16
-#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */
-#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos)))
-#define TWIHS_SMBTR_THMAX_Pos 24
-#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */
-#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos)))
-/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */
-#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */
-#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */
-#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */
-#define TWIHS_FILTR_THRES_Pos 8
-#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */
-#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos)))
-/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */
-#define TWIHS_SWMR_SADR1_Pos 0
-#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */
-#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos)))
-#define TWIHS_SWMR_SADR2_Pos 8
-#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */
-#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos)))
-#define TWIHS_SWMR_SADR3_Pos 16
-#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */
-#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos)))
-#define TWIHS_SWMR_DATAM_Pos 24
-#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */
-#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos)))
-/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */
-#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */
-#define TWIHS_WPMR_WPKEY_Pos 8
-#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */
-#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos)))
-#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */
-/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */
-#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */
-#define TWIHS_WPSR_WPVSRC_Pos 8
-#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_TWIHS_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/uart.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/uart.h
deleted file mode 100644
index 0e54542..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/uart.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UART_COMPONENT_
-#define _SAMS70_UART_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
-/* ============================================================================= */
-/** \addtogroup SAMS70_UART Universal Asynchronous Receiver Transmitter */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Uart hardware registers */
-typedef struct {
- __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */
- __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */
- __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
- __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
- __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
- __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */
- __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
- __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
- __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
- __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */
- __I uint32_t Reserved1[47];
- __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */
-} Uart;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
-#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
-#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
-#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
-#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
-#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
-#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
-#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */
-#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */
-/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
-#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */
-#define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */
-#define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */
-#define UART_MR_PAR_Pos 9
-#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
-#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos)))
-#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */
-#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */
-#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
-#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
-#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
-#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */
-#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */
-#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */
-#define UART_MR_CHMODE_Pos 14
-#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
-#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos)))
-#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */
-#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */
-#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */
-#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */
-/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
-#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
-#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
-#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
-#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
-#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
-#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
-#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */
-/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
-#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
-#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
-#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
-#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
-#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
-#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
-#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */
-/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
-#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
-#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
-#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
-#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
-#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
-#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
-#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */
-/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
-#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
-#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
-#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
-#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
-#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
-#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
-#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */
-/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
-#define UART_RHR_RXCHR_Pos 0
-#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
-/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
-#define UART_THR_TXCHR_Pos 0
-#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
-#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
-/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
-#define UART_BRGR_CD_Pos 0
-#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
-#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
-/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */
-#define UART_CMPR_VAL1_Pos 0
-#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */
-#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos)))
-#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */
-#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */
-#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */
-#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */
-#define UART_CMPR_VAL2_Pos 16
-#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */
-#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos)))
-/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */
-#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */
-#define UART_WPMR_WPKEY_Pos 8
-#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */
-#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos)))
-#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */
-
-/*@}*/
-
-
-#endif /* _SAMS70_UART_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/usart.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/usart.h
deleted file mode 100644
index 9d4ce79..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/usart.h
+++ /dev/null
@@ -1,432 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_USART_COMPONENT_
-#define _SAMS70_USART_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
-/* ============================================================================= */
-/** \addtogroup SAMS70_USART Universal Synchronous Asynchronous Receiver Transmitter */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Usart hardware registers */
-typedef struct {
- __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */
- __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */
- __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
- __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
- __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
- __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */
- __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */
- __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */
- __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
- __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
- __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
- __I uint32_t Reserved1[9];
- __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */
- __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */
- __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */
- __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */
- __IO uint32_t US_LONMR; /**< \brief (Usart Offset: 0x0060) LON Mode Register */
- __IO uint32_t US_LONPR; /**< \brief (Usart Offset: 0x0064) LON Preamble Register */
- __IO uint32_t US_LONDL; /**< \brief (Usart Offset: 0x0068) LON Data Length Register */
- __IO uint32_t US_LONL2HDR; /**< \brief (Usart Offset: 0x006C) LON L2HDR Register */
- __I uint32_t US_LONBL; /**< \brief (Usart Offset: 0x0070) LON Backlog Register */
- __IO uint32_t US_LONB1TX; /**< \brief (Usart Offset: 0x0074) LON Beta1 Tx Register */
- __IO uint32_t US_LONB1RX; /**< \brief (Usart Offset: 0x0078) LON Beta1 Rx Register */
- __IO uint32_t US_LONPRIO; /**< \brief (Usart Offset: 0x007C) LON Priority Register */
- __IO uint32_t US_IDTTX; /**< \brief (Usart Offset: 0x0080) LON IDT Tx Register */
- __IO uint32_t US_IDTRX; /**< \brief (Usart Offset: 0x0084) LON IDT Rx Register */
- __IO uint32_t US_ICDIFF; /**< \brief (Usart Offset: 0x0088) IC DIFF Register */
- __I uint32_t Reserved2[22];
- __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */
- __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */
-} Usart;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
-#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
-#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
-#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
-#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
-#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
-#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
-#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
-#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
-#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
-#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received */
-#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
-#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Start Time-out Immediately */
-#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Pin Control */
-#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Pin Control */
-#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */
-#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */
-#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
-#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
-/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
-#define US_MR_USART_MODE_Pos 0
-#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */
-#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos)))
-#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
-#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
-#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
-#define US_MR_USART_MODE_LON (0x9u << 0) /**< \brief (US_MR) LON */
-#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master */
-#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
-#define US_MR_USCLKS_Pos 4
-#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
-#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos)))
-#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */
-#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock divided (DIV=DIV=8) is selected */
-#define US_MR_USCLKS_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */
-#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial clock (SCK) is selected */
-#define US_MR_CHRL_Pos 6
-#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */
-#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos)))
-#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
-#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
-#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
-#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
-#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
-#define US_MR_PAR_Pos 9
-#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
-#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos)))
-#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
-#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
-#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
-#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
-#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
-#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
-#define US_MR_NBSTOP_Pos 12
-#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
-#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos)))
-#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
-#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
-#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
-#define US_MR_CHMODE_Pos 14
-#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
-#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos)))
-#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */
-#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
-#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
-#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
-#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
-#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
-#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
-#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
-#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */
-#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
-#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
-#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
-#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
-#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
-#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */
-/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
-#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
-#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
-#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
-#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
-#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
-#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
-#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
-#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
-#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
-#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
-#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */
-#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */
-#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */
-#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */
-#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */
-#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */
-#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */
-#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */
-#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */
-#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */
-#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */
-#define US_IER_LSFE (0x1u << 6) /**< \brief (US_IER) LON Short Frame Error Interrupt Enable */
-#define US_IER_LCRCE (0x1u << 7) /**< \brief (US_IER) LON CRC Error Interrupt Enable */
-#define US_IER_LTXD (0x1u << 24) /**< \brief (US_IER) LON Transmission Done Interrupt Enable */
-#define US_IER_LCOL (0x1u << 25) /**< \brief (US_IER) LON Collision Interrupt Enable */
-#define US_IER_LFET (0x1u << 26) /**< \brief (US_IER) LON Frame Early Termination Interrupt Enable */
-#define US_IER_LRXD (0x1u << 27) /**< \brief (US_IER) LON Reception Done Interrupt Enable */
-#define US_IER_LBLOVFE (0x1u << 28) /**< \brief (US_IER) LON Backlog Overflow Error Interrupt Enable */
-/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
-#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
-#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
-#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
-#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */
-#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
-#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
-#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
-#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
-#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
-#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
-#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */
-#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */
-#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */
-#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */
-#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */
-#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */
-#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */
-#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */
-#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */
-#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */
-#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */
-#define US_IDR_LSFE (0x1u << 6) /**< \brief (US_IDR) LON Short Frame Error Interrupt Disable */
-#define US_IDR_LCRCE (0x1u << 7) /**< \brief (US_IDR) LON CRC Error Interrupt Disable */
-#define US_IDR_LTXD (0x1u << 24) /**< \brief (US_IDR) LON Transmission Done Interrupt Disable */
-#define US_IDR_LCOL (0x1u << 25) /**< \brief (US_IDR) LON Collision Interrupt Disable */
-#define US_IDR_LFET (0x1u << 26) /**< \brief (US_IDR) LON Frame Early Termination Interrupt Disable */
-#define US_IDR_LRXD (0x1u << 27) /**< \brief (US_IDR) LON Reception Done Interrupt Disable */
-#define US_IDR_LBLOVFE (0x1u << 28) /**< \brief (US_IDR) LON Backlog Overflow Error Interrupt Disable */
-/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
-#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
-#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
-#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
-#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
-#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
-#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
-#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
-#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
-#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
-#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
-#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */
-#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */
-#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */
-#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */
-#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */
-#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */
-#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */
-#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */
-#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */
-#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */
-#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */
-#define US_IMR_LSFE (0x1u << 6) /**< \brief (US_IMR) LON Short Frame Error Interrupt Mask */
-#define US_IMR_LCRCE (0x1u << 7) /**< \brief (US_IMR) LON CRC Error Interrupt Mask */
-#define US_IMR_LTXD (0x1u << 24) /**< \brief (US_IMR) LON Transmission Done Interrupt Mask */
-#define US_IMR_LCOL (0x1u << 25) /**< \brief (US_IMR) LON Collision Interrupt Mask */
-#define US_IMR_LFET (0x1u << 26) /**< \brief (US_IMR) LON Frame Early Termination Interrupt Mask */
-#define US_IMR_LRXD (0x1u << 27) /**< \brief (US_IMR) LON Reception Done Interrupt Mask */
-#define US_IMR_LBLOVFE (0x1u << 28) /**< \brief (US_IMR) LON Backlog Overflow Error Interrupt Mask */
-/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
-#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (cleared by reading US_RHR) */
-#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (cleared by writing US_THR) */
-#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) */
-#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (cleared by writing US_THR) */
-#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag (cleared on read) */
-#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
-#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) */
-#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */
-#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LSFE (0x1u << 6) /**< \brief (US_CSR) LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LCRCE (0x1u << 7) /**< \brief (US_CSR) LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LTXD (0x1u << 24) /**< \brief (US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LCOL (0x1u << 25) /**< \brief (US_CSR) LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LFET (0x1u << 26) /**< \brief (US_CSR) LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LRXD (0x1u << 27) /**< \brief (US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) */
-#define US_CSR_LBLOVFE (0x1u << 28) /**< \brief (US_CSR) LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) */
-/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */
-#define US_RHR_RXCHR_Pos 0
-#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
-#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
-/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */
-#define US_THR_TXCHR_Pos 0
-#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
-#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
-#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */
-/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
-#define US_BRGR_CD_Pos 0
-#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
-#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
-#define US_BRGR_FP_Pos 16
-#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
-#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
-/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
-#define US_RTOR_TO_Pos 0
-#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
-#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
-/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
-#define US_TTGR_TG_Pos 0
-#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
-#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
-#define US_TTGR_PCYCLE_Pos 0
-#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos) /**< \brief (US_TTGR) LON PCYCLE Length */
-#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos)))
-/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */
-#define US_MAN_TX_PL_Pos 0
-#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
-#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
-#define US_MAN_TX_PP_Pos 8
-#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
-#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos)))
-#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
-#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
-#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
-#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
-#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
-#define US_MAN_RX_PL_Pos 16
-#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
-#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
-#define US_MAN_RX_PP_Pos 24
-#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
-#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos)))
-#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
-#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
-#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
-#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
-#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
-#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */
-#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */
-#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) */
-/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */
-#define US_LINMR_NACT_Pos 0
-#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */
-#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos)))
-#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */
-#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */
-#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */
-#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */
-#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */
-#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */
-#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */
-#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */
-#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */
-#define US_LINMR_DLC_Pos 8
-#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */
-#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos)))
-#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */
-#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */
-/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */
-#define US_LINIR_IDCHR_Pos 0
-#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */
-#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos)))
-/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */
-#define US_LINBRR_LINCD_Pos 0
-#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */
-#define US_LINBRR_LINFP_Pos 16
-#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */
-/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */
-#define US_LONMR_COMMT (0x1u << 0) /**< \brief (US_LONMR) LON comm_type Parameter Value */
-#define US_LONMR_COLDET (0x1u << 1) /**< \brief (US_LONMR) LON Collision Detection Feature */
-#define US_LONMR_TCOL (0x1u << 2) /**< \brief (US_LONMR) Terminate Frame upon Collision Notification */
-#define US_LONMR_CDTAIL (0x1u << 3) /**< \brief (US_LONMR) LON Collision Detection on Frame Tail */
-#define US_LONMR_DMAM (0x1u << 4) /**< \brief (US_LONMR) LON DMA Mode */
-#define US_LONMR_LCDS (0x1u << 5) /**< \brief (US_LONMR) LON Collision Detection Source */
-#define US_LONMR_EOFS_Pos 16
-#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos) /**< \brief (US_LONMR) End of Frame Condition Size */
-#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos)))
-/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */
-#define US_LONPR_LONPL_Pos 0
-#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos) /**< \brief (US_LONPR) LON Preamble Length */
-#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos)))
-/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */
-#define US_LONDL_LONDL_Pos 0
-#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos) /**< \brief (US_LONDL) LON Data Length */
-#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos)))
-/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */
-#define US_LONL2HDR_BLI_Pos 0
-#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos) /**< \brief (US_LONL2HDR) LON Backlog Increment */
-#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos)))
-#define US_LONL2HDR_ALTP (0x1u << 6) /**< \brief (US_LONL2HDR) LON Alternate Path Bit */
-#define US_LONL2HDR_PB (0x1u << 7) /**< \brief (US_LONL2HDR) LON Priority Bit */
-/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */
-#define US_LONBL_LONBL_Pos 0
-#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos) /**< \brief (US_LONBL) LON Node Backlog Value */
-/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */
-#define US_LONB1TX_BETA1TX_Pos 0
-#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos) /**< \brief (US_LONB1TX) LON Beta1 Length after Transmission */
-#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos)))
-/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */
-#define US_LONB1RX_BETA1RX_Pos 0
-#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos) /**< \brief (US_LONB1RX) LON Beta1 Length after Reception */
-#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos)))
-/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */
-#define US_LONPRIO_PSNB_Pos 0
-#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos) /**< \brief (US_LONPRIO) LON Priority Slot Number */
-#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos)))
-#define US_LONPRIO_NPS_Pos 8
-#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos) /**< \brief (US_LONPRIO) LON Node Priority Slot */
-#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos)))
-/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */
-#define US_IDTTX_IDTTX_Pos 0
-#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos) /**< \brief (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) */
-#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos)))
-/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */
-#define US_IDTRX_IDTRX_Pos 0
-#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos) /**< \brief (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) */
-#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos)))
-/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */
-#define US_ICDIFF_ICDIFF_Pos 0
-#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos) /**< \brief (US_ICDIFF) IC Differentiator Number */
-#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos)))
-/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */
-#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */
-#define US_WPMR_WPKEY_Pos 8
-#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */
-#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
-#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
-/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */
-#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */
-#define US_WPSR_WPVSRC_Pos 8
-#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */
-
-/*@}*/
-
-
-#endif /* _SAMS70_USART_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/usbhs.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/usbhs.h
deleted file mode 100644
index 0391a17..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/usbhs.h
+++ /dev/null
@@ -1,975 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_USBHS_COMPONENT_
-#define _SAMS70_USBHS_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR USB High-Speed Interface */
-/* ============================================================================= */
-/** \addtogroup SAMS70_USBHS USB High-Speed Interface */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief UsbhsDevdma hardware registers */
-typedef struct {
- __IO uint32_t USBHS_DEVDMANXTDSC; /**< \brief (UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */
- __IO uint32_t USBHS_DEVDMAADDRESS; /**< \brief (UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register */
- __IO uint32_t USBHS_DEVDMACONTROL; /**< \brief (UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register */
- __IO uint32_t USBHS_DEVDMASTATUS; /**< \brief (UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register */
-} UsbhsDevdma;
-/** \brief UsbhsHstdma hardware registers */
-typedef struct {
- __IO uint32_t USBHS_HSTDMANXTDSC; /**< \brief (UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */
- __IO uint32_t USBHS_HSTDMAADDRESS; /**< \brief (UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register */
- __IO uint32_t USBHS_HSTDMACONTROL; /**< \brief (UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register */
- __IO uint32_t USBHS_HSTDMASTATUS; /**< \brief (UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register */
-} UsbhsHstdma;
-/** \brief Usbhs hardware registers */
-#define USBHSDEVDMA_NUMBER 7
-#define USBHSHSTDMA_NUMBER 7
-typedef struct {
- __IO uint32_t USBHS_DEVCTRL; /**< \brief (Usbhs Offset: 0x0000) Device General Control Register */
- __I uint32_t USBHS_DEVISR; /**< \brief (Usbhs Offset: 0x0004) Device Global Interrupt Status Register */
- __O uint32_t USBHS_DEVICR; /**< \brief (Usbhs Offset: 0x0008) Device Global Interrupt Clear Register */
- __O uint32_t USBHS_DEVIFR; /**< \brief (Usbhs Offset: 0x000C) Device Global Interrupt Set Register */
- __I uint32_t USBHS_DEVIMR; /**< \brief (Usbhs Offset: 0x0010) Device Global Interrupt Mask Register */
- __O uint32_t USBHS_DEVIDR; /**< \brief (Usbhs Offset: 0x0014) Device Global Interrupt Disable Register */
- __O uint32_t USBHS_DEVIER; /**< \brief (Usbhs Offset: 0x0018) Device Global Interrupt Enable Register */
- __IO uint32_t USBHS_DEVEPT; /**< \brief (Usbhs Offset: 0x001C) Device Endpoint Register */
- __I uint32_t USBHS_DEVFNUM; /**< \brief (Usbhs Offset: 0x0020) Device Frame Number Register */
- __I uint32_t Reserved1[55];
- __IO uint32_t USBHS_DEVEPTCFG[10]; /**< \brief (Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */
- __I uint32_t Reserved2[2];
- __I uint32_t USBHS_DEVEPTISR[10]; /**< \brief (Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0) */
- __I uint32_t Reserved3[2];
- __O uint32_t USBHS_DEVEPTICR[10]; /**< \brief (Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0) */
- __I uint32_t Reserved4[2];
- __O uint32_t USBHS_DEVEPTIFR[10]; /**< \brief (Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0) */
- __I uint32_t Reserved5[2];
- __I uint32_t USBHS_DEVEPTIMR[10]; /**< \brief (Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */
- __I uint32_t Reserved6[2];
- __O uint32_t USBHS_DEVEPTIER[10]; /**< \brief (Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */
- __I uint32_t Reserved7[2];
- __O uint32_t USBHS_DEVEPTIDR[10]; /**< \brief (Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0) */
- __I uint32_t Reserved8[50];
- UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x310) n = 1 .. 7 */
- __I uint32_t Reserved9[32];
- __IO uint32_t USBHS_HSTCTRL; /**< \brief (Usbhs Offset: 0x0400) Host General Control Register */
- __I uint32_t USBHS_HSTISR; /**< \brief (Usbhs Offset: 0x0404) Host Global Interrupt Status Register */
- __O uint32_t USBHS_HSTICR; /**< \brief (Usbhs Offset: 0x0408) Host Global Interrupt Clear Register */
- __O uint32_t USBHS_HSTIFR; /**< \brief (Usbhs Offset: 0x040C) Host Global Interrupt Set Register */
- __I uint32_t USBHS_HSTIMR; /**< \brief (Usbhs Offset: 0x0410) Host Global Interrupt Mask Register */
- __O uint32_t USBHS_HSTIDR; /**< \brief (Usbhs Offset: 0x0414) Host Global Interrupt Disable Register */
- __O uint32_t USBHS_HSTIER; /**< \brief (Usbhs Offset: 0x0418) Host Global Interrupt Enable Register */
- __IO uint32_t USBHS_HSTPIP; /**< \brief (Usbhs Offset: 0x0041C) Host Pipe Register */
- __IO uint32_t USBHS_HSTFNUM; /**< \brief (Usbhs Offset: 0x0420) Host Frame Number Register */
- __IO uint32_t USBHS_HSTADDR1; /**< \brief (Usbhs Offset: 0x0424) Host Address 1 Register */
- __IO uint32_t USBHS_HSTADDR2; /**< \brief (Usbhs Offset: 0x0428) Host Address 2 Register */
- __IO uint32_t USBHS_HSTADDR3; /**< \brief (Usbhs Offset: 0x042C) Host Address 3 Register */
- __I uint32_t Reserved10[52];
- __IO uint32_t USBHS_HSTPIPCFG[10]; /**< \brief (Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0) */
- __I uint32_t Reserved11[2];
- __I uint32_t USBHS_HSTPIPISR[10]; /**< \brief (Usbhs Offset: 0x530) Host Pipe Status Register (n = 0) */
- __I uint32_t Reserved12[2];
- __O uint32_t USBHS_HSTPIPICR[10]; /**< \brief (Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0) */
- __I uint32_t Reserved13[2];
- __O uint32_t USBHS_HSTPIPIFR[10]; /**< \brief (Usbhs Offset: 0x590) Host Pipe Set Register (n = 0) */
- __I uint32_t Reserved14[2];
- __I uint32_t USBHS_HSTPIPIMR[10]; /**< \brief (Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */
- __I uint32_t Reserved15[2];
- __O uint32_t USBHS_HSTPIPIER[10]; /**< \brief (Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */
- __I uint32_t Reserved16[2];
- __O uint32_t USBHS_HSTPIPIDR[10]; /**< \brief (Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0) */
- __I uint32_t Reserved17[2];
- __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< \brief (Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0) */
- __I uint32_t Reserved18[2];
- __IO uint32_t USBHS_HSTPIPERR[10]; /**< \brief (Usbhs Offset: 0x680) Host Pipe Error Register (n = 0) */
- __I uint32_t Reserved19[26];
- UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x710) n = 1 .. 7 */
- __I uint32_t Reserved20[32];
- __IO uint32_t USBHS_CTRL; /**< \brief (Usbhs Offset: 0x0800) General Control Register */
- __I uint32_t USBHS_SR; /**< \brief (Usbhs Offset: 0x0804) General Status Register */
- __O uint32_t USBHS_SCR; /**< \brief (Usbhs Offset: 0x0808) General Status Clear Register */
- __O uint32_t USBHS_SFR; /**< \brief (Usbhs Offset: 0x080C) General Status Set Register */
- __IO uint32_t USBHS_TSTA1; /**< \brief (Usbhs Offset: 0x0810) General Test A1 Register */
- __IO uint32_t USBHS_TSTA2; /**< \brief (Usbhs Offset: 0x0814) General Test A2 Register */
- __I uint32_t USBHS_VERSION; /**< \brief (Usbhs Offset: 0x0818) General Version Register */
- __I uint32_t Reserved21[4];
- __I uint32_t USBHS_FSM; /**< \brief (Usbhs Offset: 0x082C) General Finite State Machine Register */
-} Usbhs;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */
-#define USBHS_DEVCTRL_UADD_Pos 0
-#define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos) /**< \brief (USBHS_DEVCTRL) USB Address */
-#define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos)))
-#define USBHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (USBHS_DEVCTRL) Address Enable */
-#define USBHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (USBHS_DEVCTRL) Detach */
-#define USBHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (USBHS_DEVCTRL) Remote Wake-Up */
-#define USBHS_DEVCTRL_SPDCONF_Pos 10
-#define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos) /**< \brief (USBHS_DEVCTRL) Mode Configuration */
-#define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos)))
-#define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */
-#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */
-#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (USBHS_DEVCTRL) Forced high speed. */
-#define USBHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */
-#define USBHS_DEVCTRL_LS (0x1u << 12) /**< \brief (USBHS_DEVCTRL) Low-Speed Mode Force */
-#define USBHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (USBHS_DEVCTRL) Test mode J */
-#define USBHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (USBHS_DEVCTRL) Test mode K */
-#define USBHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (USBHS_DEVCTRL) Test packet mode */
-#define USBHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (USBHS_DEVCTRL) Specific Operational mode */
-/* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */
-#define USBHS_DEVISR_SUSP (0x1u << 0) /**< \brief (USBHS_DEVISR) Suspend Interrupt */
-#define USBHS_DEVISR_MSOF (0x1u << 1) /**< \brief (USBHS_DEVISR) Micro Start of Frame Interrupt */
-#define USBHS_DEVISR_SOF (0x1u << 2) /**< \brief (USBHS_DEVISR) Start of Frame Interrupt */
-#define USBHS_DEVISR_EORST (0x1u << 3) /**< \brief (USBHS_DEVISR) End of Reset Interrupt */
-#define USBHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (USBHS_DEVISR) Wake-Up Interrupt */
-#define USBHS_DEVISR_EORSM (0x1u << 5) /**< \brief (USBHS_DEVISR) End of Resume Interrupt */
-#define USBHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (USBHS_DEVISR) Upstream Resume Interrupt */
-#define USBHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVISR) Endpoint 0 Interrupt */
-#define USBHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVISR) Endpoint 1 Interrupt */
-#define USBHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVISR) Endpoint 2 Interrupt */
-#define USBHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVISR) Endpoint 3 Interrupt */
-#define USBHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVISR) Endpoint 4 Interrupt */
-#define USBHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVISR) Endpoint 5 Interrupt */
-#define USBHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVISR) Endpoint 6 Interrupt */
-#define USBHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVISR) Endpoint 7 Interrupt */
-#define USBHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVISR) Endpoint 8 Interrupt */
-#define USBHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVISR) Endpoint 9 Interrupt */
-#define USBHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVISR) Endpoint 10 Interrupt */
-#define USBHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVISR) Endpoint 11 Interrupt */
-#define USBHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVISR) DMA Channel 1 Interrupt */
-#define USBHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVISR) DMA Channel 2 Interrupt */
-#define USBHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVISR) DMA Channel 3 Interrupt */
-#define USBHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVISR) DMA Channel 4 Interrupt */
-#define USBHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVISR) DMA Channel 5 Interrupt */
-#define USBHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVISR) DMA Channel 6 Interrupt */
-#define USBHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVISR) DMA Channel 7 Interrupt */
-/* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */
-#define USBHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (USBHS_DEVICR) Suspend Interrupt Clear */
-#define USBHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (USBHS_DEVICR) Micro Start of Frame Interrupt Clear */
-#define USBHS_DEVICR_SOFC (0x1u << 2) /**< \brief (USBHS_DEVICR) Start of Frame Interrupt Clear */
-#define USBHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (USBHS_DEVICR) End of Reset Interrupt Clear */
-#define USBHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (USBHS_DEVICR) Wake-Up Interrupt Clear */
-#define USBHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (USBHS_DEVICR) End of Resume Interrupt Clear */
-#define USBHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (USBHS_DEVICR) Upstream Resume Interrupt Clear */
-/* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */
-#define USBHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (USBHS_DEVIFR) Suspend Interrupt Set */
-#define USBHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (USBHS_DEVIFR) Micro Start of Frame Interrupt Set */
-#define USBHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (USBHS_DEVIFR) Start of Frame Interrupt Set */
-#define USBHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (USBHS_DEVIFR) End of Reset Interrupt Set */
-#define USBHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (USBHS_DEVIFR) Wake-Up Interrupt Set */
-#define USBHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (USBHS_DEVIFR) End of Resume Interrupt Set */
-#define USBHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (USBHS_DEVIFR) Upstream Resume Interrupt Set */
-#define USBHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIFR) DMA Channel 1 Interrupt Set */
-#define USBHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIFR) DMA Channel 2 Interrupt Set */
-#define USBHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIFR) DMA Channel 3 Interrupt Set */
-#define USBHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIFR) DMA Channel 4 Interrupt Set */
-#define USBHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIFR) DMA Channel 5 Interrupt Set */
-#define USBHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIFR) DMA Channel 6 Interrupt Set */
-#define USBHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIFR) DMA Channel 7 Interrupt Set */
-/* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */
-#define USBHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (USBHS_DEVIMR) Suspend Interrupt Mask */
-#define USBHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask */
-#define USBHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (USBHS_DEVIMR) Start of Frame Interrupt Mask */
-#define USBHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (USBHS_DEVIMR) End of Reset Interrupt Mask */
-#define USBHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (USBHS_DEVIMR) Wake-Up Interrupt Mask */
-#define USBHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (USBHS_DEVIMR) End of Resume Interrupt Mask */
-#define USBHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (USBHS_DEVIMR) Upstream Resume Interrupt Mask */
-#define USBHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIMR) Endpoint 0 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIMR) Endpoint 1 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIMR) Endpoint 2 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIMR) Endpoint 3 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIMR) Endpoint 4 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIMR) Endpoint 5 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIMR) Endpoint 6 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIMR) Endpoint 7 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIMR) Endpoint 8 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIMR) Endpoint 9 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIMR) Endpoint 10 Interrupt Mask */
-#define USBHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIMR) Endpoint 11 Interrupt Mask */
-#define USBHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask */
-#define USBHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask */
-#define USBHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask */
-#define USBHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask */
-#define USBHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask */
-#define USBHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask */
-#define USBHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask */
-/* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */
-#define USBHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (USBHS_DEVIDR) Suspend Interrupt Disable */
-#define USBHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable */
-#define USBHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (USBHS_DEVIDR) Start of Frame Interrupt Disable */
-#define USBHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (USBHS_DEVIDR) End of Reset Interrupt Disable */
-#define USBHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (USBHS_DEVIDR) Wake-Up Interrupt Disable */
-#define USBHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (USBHS_DEVIDR) End of Resume Interrupt Disable */
-#define USBHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (USBHS_DEVIDR) Upstream Resume Interrupt Disable */
-#define USBHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIDR) Endpoint 0 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIDR) Endpoint 1 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIDR) Endpoint 2 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIDR) Endpoint 3 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIDR) Endpoint 4 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIDR) Endpoint 5 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIDR) Endpoint 6 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIDR) Endpoint 7 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIDR) Endpoint 8 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIDR) Endpoint 9 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIDR) Endpoint 10 Interrupt Disable */
-#define USBHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIDR) Endpoint 11 Interrupt Disable */
-#define USBHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable */
-#define USBHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable */
-#define USBHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable */
-#define USBHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable */
-#define USBHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable */
-#define USBHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable */
-#define USBHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable */
-/* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */
-#define USBHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (USBHS_DEVIER) Suspend Interrupt Enable */
-#define USBHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (USBHS_DEVIER) Micro Start of Frame Interrupt Enable */
-#define USBHS_DEVIER_SOFES (0x1u << 2) /**< \brief (USBHS_DEVIER) Start of Frame Interrupt Enable */
-#define USBHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (USBHS_DEVIER) End of Reset Interrupt Enable */
-#define USBHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (USBHS_DEVIER) Wake-Up Interrupt Enable */
-#define USBHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (USBHS_DEVIER) End of Resume Interrupt Enable */
-#define USBHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (USBHS_DEVIER) Upstream Resume Interrupt Enable */
-#define USBHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIER) Endpoint 0 Interrupt Enable */
-#define USBHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIER) Endpoint 1 Interrupt Enable */
-#define USBHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIER) Endpoint 2 Interrupt Enable */
-#define USBHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIER) Endpoint 3 Interrupt Enable */
-#define USBHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIER) Endpoint 4 Interrupt Enable */
-#define USBHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIER) Endpoint 5 Interrupt Enable */
-#define USBHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIER) Endpoint 6 Interrupt Enable */
-#define USBHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIER) Endpoint 7 Interrupt Enable */
-#define USBHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIER) Endpoint 8 Interrupt Enable */
-#define USBHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIER) Endpoint 9 Interrupt Enable */
-#define USBHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIER) Endpoint 10 Interrupt Enable */
-#define USBHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIER) Endpoint 11 Interrupt Enable */
-#define USBHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIER) DMA Channel 1 Interrupt Enable */
-#define USBHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIER) DMA Channel 2 Interrupt Enable */
-#define USBHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIER) DMA Channel 3 Interrupt Enable */
-#define USBHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIER) DMA Channel 4 Interrupt Enable */
-#define USBHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIER) DMA Channel 5 Interrupt Enable */
-#define USBHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIER) DMA Channel 6 Interrupt Enable */
-#define USBHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIER) DMA Channel 7 Interrupt Enable */
-/* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */
-#define USBHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (USBHS_DEVEPT) Endpoint 0 Enable */
-#define USBHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (USBHS_DEVEPT) Endpoint 1 Enable */
-#define USBHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (USBHS_DEVEPT) Endpoint 2 Enable */
-#define USBHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (USBHS_DEVEPT) Endpoint 3 Enable */
-#define USBHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (USBHS_DEVEPT) Endpoint 4 Enable */
-#define USBHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (USBHS_DEVEPT) Endpoint 5 Enable */
-#define USBHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (USBHS_DEVEPT) Endpoint 6 Enable */
-#define USBHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (USBHS_DEVEPT) Endpoint 7 Enable */
-#define USBHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (USBHS_DEVEPT) Endpoint 8 Enable */
-#define USBHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (USBHS_DEVEPT) Endpoint 0 Reset */
-#define USBHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (USBHS_DEVEPT) Endpoint 1 Reset */
-#define USBHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (USBHS_DEVEPT) Endpoint 2 Reset */
-#define USBHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (USBHS_DEVEPT) Endpoint 3 Reset */
-#define USBHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (USBHS_DEVEPT) Endpoint 4 Reset */
-#define USBHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (USBHS_DEVEPT) Endpoint 5 Reset */
-#define USBHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (USBHS_DEVEPT) Endpoint 6 Reset */
-#define USBHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (USBHS_DEVEPT) Endpoint 7 Reset */
-#define USBHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (USBHS_DEVEPT) Endpoint 8 Reset */
-/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */
-#define USBHS_DEVFNUM_MFNUM_Pos 0
-#define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos) /**< \brief (USBHS_DEVFNUM) Micro Frame Number */
-#define USBHS_DEVFNUM_FNUM_Pos 3
-#define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos) /**< \brief (USBHS_DEVFNUM) Frame Number */
-#define USBHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (USBHS_DEVFNUM) Frame Number CRC Error */
-/* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */
-#define USBHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate */
-#define USBHS_DEVEPTCFG_EPBK_Pos 2
-#define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Banks */
-#define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos)))
-#define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Single-bank endpoint */
-#define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Double-bank endpoint */
-#define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Triple-bank endpoint */
-#define USBHS_DEVEPTCFG_EPSIZE_Pos 4
-#define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Size */
-#define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos)))
-#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 8 bytes */
-#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 16 bytes */
-#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 32 bytes */
-#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 64 bytes */
-#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 128 bytes */
-#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 256 bytes */
-#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 512 bytes */
-#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 1024 bytes */
-#define USBHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Direction */
-#define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is OUT. */
-#define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */
-#define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (USBHS_DEVEPTCFG[10]) Automatic Switch */
-#define USBHS_DEVEPTCFG_EPTYPE_Pos 11
-#define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Type */
-#define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos)))
-#define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Control */
-#define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Isochronous */
-#define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Bulk */
-#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Interrupt */
-#define USBHS_DEVEPTCFG_NBTRANS_Pos 13
-#define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint */
-#define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos)))
-#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */
-#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe. */
-#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank. */
-#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank. */
-/* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */
-#define USBHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */
-#define USBHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (USBHS_DEVEPTISR[10]) Received OUT Data Interrupt */
-#define USBHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Received SETUP Interrupt */
-#define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) NAKed OUT Interrupt */
-#define USBHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) NAKed IN Interrupt */
-#define USBHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (USBHS_DEVEPTISR[10]) Overflow Interrupt */
-#define USBHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) STALLed Interrupt */
-#define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (USBHS_DEVEPTISR[10]) Short Packet Interrupt */
-#define USBHS_DEVEPTISR_DTSEQ_Pos 8
-#define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Data Toggle Sequence */
-#define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data0 toggle sequence */
-#define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data1 toggle sequence */
-#define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */
-#define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */
-#define USBHS_DEVEPTISR_NBUSYBK_Pos 12
-#define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Number of Busy Banks */
-#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 0 busy bank (all banks free) */
-#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 1 busy bank */
-#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 2 busy banks */
-#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 3 busy banks */
-#define USBHS_DEVEPTISR_CURRBK_Pos 14
-#define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Current Bank */
-#define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank0 */
-#define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank1 */
-#define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank2 */
-#define USBHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (USBHS_DEVEPTISR[10]) Read/Write Allowed */
-#define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (USBHS_DEVEPTISR[10]) Control Direction */
-#define USBHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (USBHS_DEVEPTISR[10]) Configuration OK Status */
-#define USBHS_DEVEPTISR_BYCT_Pos 20
-#define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Byte Count */
-#define USBHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Underflow Interrupt */
-#define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt */
-#define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */
-#define USBHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) CRC Error Interrupt */
-#define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */
-/* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */
-#define USBHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */
-#define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */
-#define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */
-#define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */
-#define USBHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */
-#define USBHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_DEVEPTICR[10]) Overflow Interrupt Clear */
-#define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) STALLed Interrupt Clear */
-#define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear */
-#define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Underflow Interrupt Clear */
-#define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear */
-#define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */
-#define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear */
-/* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */
-#define USBHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */
-#define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */
-#define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */
-#define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */
-#define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */
-#define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_DEVEPTIFR[10]) Overflow Interrupt Set */
-#define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) STALLed Interrupt Set */
-#define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set */
-#define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */
-#define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Underflow Interrupt Set */
-#define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set */
-#define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */
-#define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set */
-/* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */
-#define USBHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */
-#define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt */
-#define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Received SETUP Interrupt */
-#define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt */
-#define USBHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed IN Interrupt */
-#define USBHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (USBHS_DEVEPTIMR[10]) Overflow Interrupt */
-#define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) STALLed Interrupt */
-#define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (USBHS_DEVEPTIMR[10]) Short Packet Interrupt */
-#define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */
-#define USBHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (USBHS_DEVEPTIMR[10]) Kill IN Bank */
-#define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_DEVEPTIMR[10]) FIFO Control */
-#define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */
-#define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (USBHS_DEVEPTIMR[10]) NYET Token Disable */
-#define USBHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_DEVEPTIMR[10]) Reset Data Toggle */
-#define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (USBHS_DEVEPTIMR[10]) STALL Request */
-#define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Underflow Interrupt */
-#define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */
-#define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */
-#define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) CRC Error Interrupt */
-#define USBHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (USBHS_DEVEPTIMR[10]) MData Interrupt */
-#define USBHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (USBHS_DEVEPTIMR[10]) DataX Interrupt */
-#define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (USBHS_DEVEPTIMR[10]) Transaction Error Interrupt */
-/* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */
-#define USBHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */
-#define USBHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */
-#define USBHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */
-#define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */
-#define USBHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */
-#define USBHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (USBHS_DEVEPTIER[10]) Overflow Interrupt Enable */
-#define USBHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) STALLed Interrupt Enable */
-#define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable */
-#define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */
-#define USBHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (USBHS_DEVEPTIER[10]) Kill IN Bank */
-#define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (USBHS_DEVEPTIER[10]) FIFO Control */
-#define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */
-#define USBHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (USBHS_DEVEPTIER[10]) NYET Token Disable Enable */
-#define USBHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_DEVEPTIER[10]) Reset Data Toggle Enable */
-#define USBHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (USBHS_DEVEPTIER[10]) STALL Request Enable */
-#define USBHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Underflow Interrupt Enable */
-#define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */
-#define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */
-#define USBHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable */
-#define USBHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (USBHS_DEVEPTIER[10]) MData Interrupt Enable */
-#define USBHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (USBHS_DEVEPTIER[10]) DataX Interrupt Enable */
-#define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */
-/* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */
-#define USBHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */
-#define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */
-#define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */
-#define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */
-#define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */
-#define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear */
-#define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear */
-#define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */
-#define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */
-#define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_DEVEPTIDR[10]) FIFO Control Clear */
-#define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */
-#define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (USBHS_DEVEPTIDR[10]) NYET Token Disable Clear */
-#define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (USBHS_DEVEPTIDR[10]) STALL Request Clear */
-#define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear */
-#define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */
-#define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */
-#define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */
-#define USBHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (USBHS_DEVEPTIDR[10]) MData Interrupt Clear */
-#define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (USBHS_DEVEPTIDR[10]) DataX Interrupt Clear */
-#define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */
-/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */
-#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0
-#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_DEVDMANXTDSC) Next Descriptor Address */
-#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))
-/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */
-#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0
-#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_DEVDMAADDRESS) Buffer Address */
-#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)))
-/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */
-#define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMACONTROL) Channel Enable Command */
-#define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */
-#define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) */
-#define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Enable Control */
-#define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable */
-#define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable */
-#define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */
-#define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_DEVDMACONTROL) Burst Lock Enable */
-#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16
-#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */
-#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))
-/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */
-#define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMASTATUS) Channel Enable Status */
-#define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_DEVDMASTATUS) Channel Active Status */
-#define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Transfer Status */
-#define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Buffer Status */
-#define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_DEVDMASTATUS) Descriptor Loaded Status */
-#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16
-#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_DEVDMASTATUS) Buffer Byte Count */
-#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)))
-/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */
-#define USBHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (USBHS_HSTCTRL) Start of Frame Generation Enable */
-#define USBHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (USBHS_HSTCTRL) Send USB Reset */
-#define USBHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (USBHS_HSTCTRL) Send USB Resume */
-#define USBHS_HSTCTRL_SPDCONF_Pos 12
-#define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos) /**< \brief (USBHS_HSTCTRL) Mode Configuration */
-#define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos)))
-#define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */
-#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */
-#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (USBHS_HSTCTRL) Forced high speed. */
-#define USBHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */
-/* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */
-#define USBHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (USBHS_HSTISR) Device Connection Interrupt */
-#define USBHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (USBHS_HSTISR) Device Disconnection Interrupt */
-#define USBHS_HSTISR_RSTI (0x1u << 2) /**< \brief (USBHS_HSTISR) USB Reset Sent Interrupt */
-#define USBHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (USBHS_HSTISR) Downstream Resume Sent Interrupt */
-#define USBHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (USBHS_HSTISR) Upstream Resume Received Interrupt */
-#define USBHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (USBHS_HSTISR) Host Start of Frame Interrupt */
-#define USBHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (USBHS_HSTISR) Host Wake-Up Interrupt */
-#define USBHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTISR) Pipe 0 Interrupt */
-#define USBHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTISR) Pipe 1 Interrupt */
-#define USBHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTISR) Pipe 2 Interrupt */
-#define USBHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTISR) Pipe 3 Interrupt */
-#define USBHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTISR) Pipe 4 Interrupt */
-#define USBHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTISR) Pipe 5 Interrupt */
-#define USBHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTISR) Pipe 6 Interrupt */
-#define USBHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTISR) Pipe 7 Interrupt */
-#define USBHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTISR) Pipe 8 Interrupt */
-#define USBHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTISR) Pipe 9 Interrupt */
-#define USBHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTISR) Pipe 10 Interrupt */
-#define USBHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTISR) Pipe 11 Interrupt */
-#define USBHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTISR) DMA Channel 1 Interrupt */
-#define USBHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTISR) DMA Channel 2 Interrupt */
-#define USBHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTISR) DMA Channel 3 Interrupt */
-#define USBHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTISR) DMA Channel 4 Interrupt */
-#define USBHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTISR) DMA Channel 5 Interrupt */
-#define USBHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTISR) DMA Channel 6 Interrupt */
-#define USBHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTISR) DMA Channel 7 Interrupt */
-/* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */
-#define USBHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (USBHS_HSTICR) Device Connection Interrupt Clear */
-#define USBHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (USBHS_HSTICR) Device Disconnection Interrupt Clear */
-#define USBHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (USBHS_HSTICR) USB Reset Sent Interrupt Clear */
-#define USBHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear */
-#define USBHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (USBHS_HSTICR) Upstream Resume Received Interrupt Clear */
-#define USBHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (USBHS_HSTICR) Host Start of Frame Interrupt Clear */
-#define USBHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (USBHS_HSTICR) Host Wake-Up Interrupt Clear */
-/* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */
-#define USBHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (USBHS_HSTIFR) Device Connection Interrupt Set */
-#define USBHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (USBHS_HSTIFR) Device Disconnection Interrupt Set */
-#define USBHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (USBHS_HSTIFR) USB Reset Sent Interrupt Set */
-#define USBHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set */
-#define USBHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (USBHS_HSTIFR) Upstream Resume Received Interrupt Set */
-#define USBHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (USBHS_HSTIFR) Host Start of Frame Interrupt Set */
-#define USBHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (USBHS_HSTIFR) Host Wake-Up Interrupt Set */
-#define USBHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIFR) DMA Channel 1 Interrupt Set */
-#define USBHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIFR) DMA Channel 2 Interrupt Set */
-#define USBHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIFR) DMA Channel 3 Interrupt Set */
-#define USBHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIFR) DMA Channel 4 Interrupt Set */
-#define USBHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIFR) DMA Channel 5 Interrupt Set */
-#define USBHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIFR) DMA Channel 6 Interrupt Set */
-#define USBHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIFR) DMA Channel 7 Interrupt Set */
-/* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */
-#define USBHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (USBHS_HSTIMR) Device Connection Interrupt Enable */
-#define USBHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (USBHS_HSTIMR) Device Disconnection Interrupt Enable */
-#define USBHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (USBHS_HSTIMR) USB Reset Sent Interrupt Enable */
-#define USBHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable */
-#define USBHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable */
-#define USBHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (USBHS_HSTIMR) Host Start of Frame Interrupt Enable */
-#define USBHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (USBHS_HSTIMR) Host Wake-Up Interrupt Enable */
-#define USBHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIMR) Pipe 0 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIMR) Pipe 1 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIMR) Pipe 2 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIMR) Pipe 3 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIMR) Pipe 4 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIMR) Pipe 5 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIMR) Pipe 6 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIMR) Pipe 7 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIMR) Pipe 8 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIMR) Pipe 9 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIMR) Pipe 10 Interrupt Enable */
-#define USBHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIMR) Pipe 11 Interrupt Enable */
-#define USBHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable */
-#define USBHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable */
-#define USBHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable */
-#define USBHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable */
-#define USBHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable */
-#define USBHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable */
-#define USBHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable */
-/* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */
-#define USBHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (USBHS_HSTIDR) Device Connection Interrupt Disable */
-#define USBHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (USBHS_HSTIDR) Device Disconnection Interrupt Disable */
-#define USBHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (USBHS_HSTIDR) USB Reset Sent Interrupt Disable */
-#define USBHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable */
-#define USBHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable */
-#define USBHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (USBHS_HSTIDR) Host Start of Frame Interrupt Disable */
-#define USBHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (USBHS_HSTIDR) Host Wake-Up Interrupt Disable */
-#define USBHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIDR) Pipe 0 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIDR) Pipe 1 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIDR) Pipe 2 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIDR) Pipe 3 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIDR) Pipe 4 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIDR) Pipe 5 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIDR) Pipe 6 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIDR) Pipe 7 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIDR) Pipe 8 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIDR) Pipe 9 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIDR) Pipe 10 Interrupt Disable */
-#define USBHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIDR) Pipe 11 Interrupt Disable */
-#define USBHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable */
-#define USBHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable */
-#define USBHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable */
-#define USBHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable */
-#define USBHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable */
-#define USBHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable */
-#define USBHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable */
-/* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */
-#define USBHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (USBHS_HSTIER) Device Connection Interrupt Enable */
-#define USBHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (USBHS_HSTIER) Device Disconnection Interrupt Enable */
-#define USBHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (USBHS_HSTIER) USB Reset Sent Interrupt Enable */
-#define USBHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable */
-#define USBHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (USBHS_HSTIER) Upstream Resume Received Interrupt Enable */
-#define USBHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (USBHS_HSTIER) Host Start of Frame Interrupt Enable */
-#define USBHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (USBHS_HSTIER) Host Wake-Up Interrupt Enable */
-#define USBHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIER) Pipe 0 Interrupt Enable */
-#define USBHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIER) Pipe 1 Interrupt Enable */
-#define USBHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIER) Pipe 2 Interrupt Enable */
-#define USBHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIER) Pipe 3 Interrupt Enable */
-#define USBHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIER) Pipe 4 Interrupt Enable */
-#define USBHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIER) Pipe 5 Interrupt Enable */
-#define USBHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIER) Pipe 6 Interrupt Enable */
-#define USBHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIER) Pipe 7 Interrupt Enable */
-#define USBHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIER) Pipe 8 Interrupt Enable */
-#define USBHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIER) Pipe 9 Interrupt Enable */
-#define USBHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIER) Pipe 10 Interrupt Enable */
-#define USBHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIER) Pipe 11 Interrupt Enable */
-#define USBHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIER) DMA Channel 1 Interrupt Enable */
-#define USBHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIER) DMA Channel 2 Interrupt Enable */
-#define USBHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIER) DMA Channel 3 Interrupt Enable */
-#define USBHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIER) DMA Channel 4 Interrupt Enable */
-#define USBHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIER) DMA Channel 5 Interrupt Enable */
-#define USBHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIER) DMA Channel 6 Interrupt Enable */
-#define USBHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIER) DMA Channel 7 Interrupt Enable */
-/* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */
-#define USBHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (USBHS_HSTPIP) Pipe 0 Enable */
-#define USBHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (USBHS_HSTPIP) Pipe 1 Enable */
-#define USBHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (USBHS_HSTPIP) Pipe 2 Enable */
-#define USBHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (USBHS_HSTPIP) Pipe 3 Enable */
-#define USBHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (USBHS_HSTPIP) Pipe 4 Enable */
-#define USBHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (USBHS_HSTPIP) Pipe 5 Enable */
-#define USBHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (USBHS_HSTPIP) Pipe 6 Enable */
-#define USBHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (USBHS_HSTPIP) Pipe 7 Enable */
-#define USBHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (USBHS_HSTPIP) Pipe 8 Enable */
-#define USBHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (USBHS_HSTPIP) Pipe 0 Reset */
-#define USBHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (USBHS_HSTPIP) Pipe 1 Reset */
-#define USBHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (USBHS_HSTPIP) Pipe 2 Reset */
-#define USBHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (USBHS_HSTPIP) Pipe 3 Reset */
-#define USBHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (USBHS_HSTPIP) Pipe 4 Reset */
-#define USBHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (USBHS_HSTPIP) Pipe 5 Reset */
-#define USBHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (USBHS_HSTPIP) Pipe 6 Reset */
-#define USBHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (USBHS_HSTPIP) Pipe 7 Reset */
-#define USBHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (USBHS_HSTPIP) Pipe 8 Reset */
-/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */
-#define USBHS_HSTFNUM_MFNUM_Pos 0
-#define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos) /**< \brief (USBHS_HSTFNUM) Micro Frame Number */
-#define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos)))
-#define USBHS_HSTFNUM_FNUM_Pos 3
-#define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos) /**< \brief (USBHS_HSTFNUM) Frame Number */
-#define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos)))
-#define USBHS_HSTFNUM_FLENHIGH_Pos 16
-#define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (USBHS_HSTFNUM) Frame Length */
-#define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos)))
-/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */
-#define USBHS_HSTADDR1_HSTADDRP0_Pos 0
-#define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */
-#define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos)))
-#define USBHS_HSTADDR1_HSTADDRP1_Pos 8
-#define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */
-#define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos)))
-#define USBHS_HSTADDR1_HSTADDRP2_Pos 16
-#define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */
-#define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos)))
-#define USBHS_HSTADDR1_HSTADDRP3_Pos 24
-#define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */
-#define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos)))
-/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */
-#define USBHS_HSTADDR2_HSTADDRP4_Pos 0
-#define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */
-#define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos)))
-#define USBHS_HSTADDR2_HSTADDRP5_Pos 8
-#define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */
-#define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos)))
-#define USBHS_HSTADDR2_HSTADDRP6_Pos 16
-#define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */
-#define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos)))
-#define USBHS_HSTADDR2_HSTADDRP7_Pos 24
-#define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */
-#define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos)))
-/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */
-#define USBHS_HSTADDR3_HSTADDRP8_Pos 0
-#define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */
-#define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos)))
-#define USBHS_HSTADDR3_HSTADDRP9_Pos 8
-#define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */
-#define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos)))
-/* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */
-#define USBHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Memory Allocate */
-#define USBHS_HSTPIPCFG_PBK_Pos 2
-#define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Banks */
-#define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos)))
-#define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Single-bank pipe */
-#define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Double-bank pipe */
-#define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Triple-bank pipe */
-#define USBHS_HSTPIPCFG_PSIZE_Pos 4
-#define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Size */
-#define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos)))
-#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 8 bytes */
-#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 16 bytes */
-#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 32 bytes */
-#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 64 bytes */
-#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 128 bytes */
-#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 256 bytes */
-#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 512 bytes */
-#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 1024 bytes */
-#define USBHS_HSTPIPCFG_PTOKEN_Pos 8
-#define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Token */
-#define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos)))
-#define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) SETUP */
-#define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) IN */
-#define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) OUT */
-#define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (USBHS_HSTPIPCFG[10]) Automatic Switch */
-#define USBHS_HSTPIPCFG_PTYPE_Pos 12
-#define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Type */
-#define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos)))
-#define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Control */
-#define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Isochronous */
-#define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Bulk */
-#define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Interrupt */
-#define USBHS_HSTPIPCFG_PEPNUM_Pos 16
-#define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Endpoint Number */
-#define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos)))
-#define USBHS_HSTPIPCFG_INTFRQ_Pos 24
-#define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */
-#define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos)))
-#define USBHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (USBHS_HSTPIPCFG[10]) Ping Enable */
-#define USBHS_HSTPIPCFG_BINTERVAL_Pos 24
-#define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction */
-#define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos)))
-/* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */
-#define USBHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (USBHS_HSTPIPISR[10]) Received IN Data Interrupt */
-#define USBHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */
-#define USBHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */
-#define USBHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Error Interrupt */
-#define USBHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (USBHS_HSTPIPISR[10]) NAKed Interrupt */
-#define USBHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (USBHS_HSTPIPISR[10]) Overflow Interrupt */
-#define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) Received STALLed Interrupt */
-#define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (USBHS_HSTPIPISR[10]) Short Packet Interrupt */
-#define USBHS_HSTPIPISR_DTSEQ_Pos 8
-#define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Data Toggle Sequence */
-#define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data0 toggle sequence */
-#define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data1 toggle sequence */
-#define USBHS_HSTPIPISR_NBUSYBK_Pos 12
-#define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Number of Busy Banks */
-#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 0 busy bank (all banks free) */
-#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 1 busy bank */
-#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 2 busy banks */
-#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 3 busy banks */
-#define USBHS_HSTPIPISR_CURRBK_Pos 14
-#define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Current Bank */
-#define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank0 */
-#define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank1 */
-#define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank2 */
-#define USBHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (USBHS_HSTPIPISR[10]) Read/Write Allowed */
-#define USBHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (USBHS_HSTPIPISR[10]) Configuration OK Status */
-#define USBHS_HSTPIPISR_PBYCT_Pos 20
-#define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Byte Count */
-#define USBHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Underflow Interrupt */
-#define USBHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) CRC Error Interrupt */
-/* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */
-#define USBHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */
-#define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */
-#define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */
-#define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (USBHS_HSTPIPICR[10]) NAKed Interrupt Clear */
-#define USBHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_HSTPIPICR[10]) Overflow Interrupt Clear */
-#define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */
-#define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear */
-#define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Underflow Interrupt Clear */
-#define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear */
-/* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */
-#define USBHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */
-#define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */
-#define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */
-#define USBHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */
-#define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (USBHS_HSTPIPIFR[10]) NAKed Interrupt Set */
-#define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_HSTPIPIFR[10]) Overflow Interrupt Set */
-#define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */
-#define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set */
-#define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_HSTPIPIFR[10]) Number of Busy Banks Set */
-#define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Underflow Interrupt Set */
-#define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set */
-/* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */
-#define USBHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */
-#define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */
-#define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */
-#define USBHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */
-#define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable */
-#define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable */
-#define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */
-#define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */
-#define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */
-#define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_HSTPIPIMR[10]) FIFO Control */
-#define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */
-#define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Freeze */
-#define USBHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_HSTPIPIMR[10]) Reset Data Toggle */
-#define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable */
-#define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */
-/* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */
-#define USBHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */
-#define USBHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */
-#define USBHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */
-#define USBHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */
-#define USBHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (USBHS_HSTPIPIER[10]) NAKed Interrupt Enable */
-#define USBHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (USBHS_HSTPIPIER[10]) Overflow Interrupt Enable */
-#define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */
-#define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable */
-#define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_HSTPIPIER[10]) Number of Busy Banks Enable */
-#define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */
-#define USBHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Freeze Enable */
-#define USBHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_HSTPIPIER[10]) Reset Data Toggle Enable */
-#define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Underflow Interrupt Enable */
-#define USBHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable */
-/* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */
-#define USBHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */
-#define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */
-#define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */
-#define USBHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */
-#define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable */
-#define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable */
-#define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */
-#define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */
-#define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable */
-#define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_HSTPIPIDR[10]) FIFO Control Disable */
-#define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */
-#define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Freeze Disable */
-#define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable */
-#define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */
-/* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */
-#define USBHS_HSTPIPINRQ_INRQ_Pos 0
-#define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze */
-#define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos)))
-#define USBHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Mode */
-/* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */
-#define USBHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (USBHS_HSTPIPERR[10]) Data Toggle Error */
-#define USBHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */
-#define USBHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */
-#define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (USBHS_HSTPIPERR[10]) Time-Out Error */
-#define USBHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (USBHS_HSTPIPERR[10]) CRC16 Error */
-#define USBHS_HSTPIPERR_COUNTER_Pos 5
-#define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos) /**< \brief (USBHS_HSTPIPERR[10]) Error Counter */
-#define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos)))
-/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */
-#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0
-#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_HSTDMANXTDSC) Next Descriptor Address */
-#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))
-/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */
-#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0
-#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_HSTDMAADDRESS) Buffer Address */
-#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)))
-/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */
-#define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMACONTROL) Channel Enable Command */
-#define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */
-#define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) */
-#define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Enable Control */
-#define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable */
-#define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable */
-#define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */
-#define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_HSTDMACONTROL) Burst Lock Enable */
-#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16
-#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */
-#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))
-/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */
-#define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMASTATUS) Channel Enable Status */
-#define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_HSTDMASTATUS) Channel Active Status */
-#define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Transfer Status */
-#define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Buffer Status */
-#define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_HSTDMASTATUS) Descriptor Loaded Status */
-#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16
-#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_HSTDMASTATUS) Buffer Byte Count */
-#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)))
-/* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */
-#define USBHS_CTRL_RDERRE (0x1u << 4) /**< \brief (USBHS_CTRL) Remote Device Connection Error Interrupt Enable */
-#define USBHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (USBHS_CTRL) Freeze USB Clock */
-#define USBHS_CTRL_USBE (0x1u << 15) /**< \brief (USBHS_CTRL) USBHS Enable */
-#define USBHS_CTRL_UIMOD (0x1u << 25) /**< \brief (USBHS_CTRL) USBHS Mode */
-#define USBHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (USBHS_CTRL) The module is in USB Host mode. */
-#define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (USBHS_CTRL) The module is in USB Device mode. */
-/* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */
-#define USBHS_SR_RDERRI (0x1u << 4) /**< \brief (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) */
-#define USBHS_SR_VBUSRQ (0x1u << 9) /**< \brief (USBHS_SR) VBus Request (Host mode only) */
-#define USBHS_SR_SPEED_Pos 12
-#define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos) /**< \brief (USBHS_SR) Speed Status (Device mode only) */
-#define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (USBHS_SR) Full-Speed mode */
-#define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (USBHS_SR) High-Speed mode */
-#define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (USBHS_SR) Low-Speed mode */
-#define USBHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (USBHS_SR) UTMI Clock Usable */
-/* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */
-#define USBHS_SCR_RDERRIC (0x1u << 4) /**< \brief (USBHS_SCR) Remote Device Connection Error Interrupt Clear */
-#define USBHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (USBHS_SCR) VBus Request Clear */
-/* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */
-#define USBHS_SFR_RDERRIS (0x1u << 4) /**< \brief (USBHS_SFR) Remote Device Connection Error Interrupt Set */
-#define USBHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (USBHS_SFR) VBus Request Set */
-/* -------- USBHS_TSTA1 : (USBHS Offset: 0x0810) General Test A1 Register -------- */
-#define USBHS_TSTA1_CounterA_Pos 0
-#define USBHS_TSTA1_CounterA_Msk (0x7fffu << USBHS_TSTA1_CounterA_Pos) /**< \brief (USBHS_TSTA1) Counter A */
-#define USBHS_TSTA1_CounterA(value) ((USBHS_TSTA1_CounterA_Msk & ((value) << USBHS_TSTA1_CounterA_Pos)))
-#define USBHS_TSTA1_LoadCntA (0x1u << 15) /**< \brief (USBHS_TSTA1) Load CounterA */
-#define USBHS_TSTA1_CounterB_Pos 16
-#define USBHS_TSTA1_CounterB_Msk (0x3fu << USBHS_TSTA1_CounterB_Pos) /**< \brief (USBHS_TSTA1) Counter B */
-#define USBHS_TSTA1_CounterB(value) ((USBHS_TSTA1_CounterB_Msk & ((value) << USBHS_TSTA1_CounterB_Pos)))
-#define USBHS_TSTA1_LoadCntB (0x1u << 23) /**< \brief (USBHS_TSTA1) Load CounterB */
-#define USBHS_TSTA1_SOFCntMa1_Pos 24
-#define USBHS_TSTA1_SOFCntMa1_Msk (0x7fu << USBHS_TSTA1_SOFCntMa1_Pos) /**< \brief (USBHS_TSTA1) SOF Counter Max */
-#define USBHS_TSTA1_SOFCntMa1(value) ((USBHS_TSTA1_SOFCntMa1_Msk & ((value) << USBHS_TSTA1_SOFCntMa1_Pos)))
-#define USBHS_TSTA1_LoadSOFCnt (0x1u << 31) /**< \brief (USBHS_TSTA1) Load SOF Counter */
-/* -------- USBHS_TSTA2 : (USBHS Offset: 0x0814) General Test A2 Register -------- */
-#define USBHS_TSTA2_FullDetachEn (0x1u << 0) /**< \brief (USBHS_TSTA2) Full Detach Enable */
-#define USBHS_TSTA2_HSSerialMode (0x1u << 1) /**< \brief (USBHS_TSTA2) HS Serial Mode */
-#define USBHS_TSTA2_LoopBackMode (0x1u << 2) /**< \brief (USBHS_TSTA2) Loop-back Mode */
-#define USBHS_TSTA2_DisableGatedClock (0x1u << 3) /**< \brief (USBHS_TSTA2) Disable Gated Clock */
-#define USBHS_TSTA2_ForceSuspendMTo1 (0x1u << 4) /**< \brief (USBHS_TSTA2) Force SuspendM to 1 */
-#define USBHS_TSTA2_ByPassDpll (0x1u << 5) /**< \brief (USBHS_TSTA2) Bypass DPLL */
-#define USBHS_TSTA2_HostHSDisconnectDisable (0x1u << 6) /**< \brief (USBHS_TSTA2) Host HS Disconnect Disable */
-#define USBHS_TSTA2_ForceHSRst_50ms (0x1u << 7) /**< \brief (USBHS_TSTA2) Force HS Reset to 50 ms */
-#define USBHS_TSTA2_RemovePUWhenTX (0x1u << 9) /**< \brief (USBHS_TSTA2) Remove Pull-up When TX */
-/* -------- USBHS_VERSION : (USBHS Offset: 0x0818) General Version Register -------- */
-#define USBHS_VERSION_VERSION_Pos 0
-#define USBHS_VERSION_VERSION_Msk (0xfffu << USBHS_VERSION_VERSION_Pos) /**< \brief (USBHS_VERSION) Version Number */
-#define USBHS_VERSION_MFN_Pos 16
-#define USBHS_VERSION_MFN_Msk (0xfu << USBHS_VERSION_MFN_Pos) /**< \brief (USBHS_VERSION) Metal Fix Number */
-/* -------- USBHS_FSM : (USBHS Offset: 0x082C) General Finite State Machine Register -------- */
-#define USBHS_FSM_DRDSTATE_Pos 0
-#define USBHS_FSM_DRDSTATE_Msk (0xfu << USBHS_FSM_DRDSTATE_Pos) /**< \brief (USBHS_FSM) Dual Role Device State */
-#define USBHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (USBHS_FSM) This is the start state for A-devices (when the ID pin is 0) */
-#define USBHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */
-#define USBHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */
-#define USBHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (USBHS_FSM) In this state, the A-device that operates in Host mode is operational. */
-#define USBHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (USBHS_FSM) The A-device operating as a host is in the Suspend mode. */
-#define USBHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (USBHS_FSM) The A-device operates as a peripheral. */
-#define USBHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */
-#define USBHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */
-#define USBHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */
-#define USBHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (USBHS_FSM) This is the start state for B-device (when the ID pin is 1). */
-#define USBHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the peripheral. */
-#define USBHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (USBHS_FSM) In this state, the B-device is in Suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */
-#define USBHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us)) before becoming Host. */
-#define USBHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */
-#define USBHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the Host. */
-#define USBHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (USBHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */
-
-/*@}*/
-
-
-#endif /* _SAMS70_USBHS_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/utmi.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/utmi.h
deleted file mode 100644
index aa847f6..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/utmi.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UTMI_COMPONENT_
-#define _SAMS70_UTMI_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR USB Transmitter Interface Macrocell */
-/* ============================================================================= */
-/** \addtogroup SAMS70_UTMI USB Transmitter Interface Macrocell */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Utmi hardware registers */
-typedef struct {
- __I uint32_t Reserved1[4];
- __IO uint32_t UTMI_OHCIICR; /**< \brief (Utmi Offset: 0x10) OHCI Interrupt Configuration Register */
- __I uint32_t Reserved2[7];
- __IO uint32_t UTMI_CKTRIM; /**< \brief (Utmi Offset: 0x30) UTMI Clock Trimming Register */
-} Utmi;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) OHCI Interrupt Configuration Register -------- */
-#define UTMI_OHCIICR_RES0 (0x1u << 0) /**< \brief (UTMI_OHCIICR) USB PORTx Reset */
-#define UTMI_OHCIICR_ARIE (0x1u << 4) /**< \brief (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */
-#define UTMI_OHCIICR_APPSTART (0x1u << 5) /**< \brief (UTMI_OHCIICR) Reserved */
-#define UTMI_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (UTMI_OHCIICR) USB Device Pull-up Disable */
-/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) UTMI Clock Trimming Register -------- */
-#define UTMI_CKTRIM_FREQ_Pos 0
-#define UTMI_CKTRIM_FREQ_Msk (0x3u << UTMI_CKTRIM_FREQ_Pos) /**< \brief (UTMI_CKTRIM) UTMI Reference Clock Frequency */
-#define UTMI_CKTRIM_FREQ(value) ((UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos)))
-#define UTMI_CKTRIM_FREQ_XTAL12 (0x0u << 0) /**< \brief (UTMI_CKTRIM) 12 MHz reference clock */
-#define UTMI_CKTRIM_FREQ_XTAL16 (0x1u << 0) /**< \brief (UTMI_CKTRIM) 16 MHz reference clock */
-
-/*@}*/
-
-
-#endif /* _SAMS70_UTMI_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/wdt.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/wdt.h
deleted file mode 100644
index b8f749b..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/wdt.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_WDT_COMPONENT_
-#define _SAMS70_WDT_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Watchdog Timer */
-/* ============================================================================= */
-/** \addtogroup SAMS70_WDT Watchdog Timer */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief Wdt hardware registers */
-typedef struct {
- __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
- __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
- __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
-} Wdt;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
-#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
-#define WDT_CR_KEY_Pos 24
-#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
-#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
-#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */
-/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
-#define WDT_MR_WDV_Pos 0
-#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
-#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
-#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
-#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
-#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
-#define WDT_MR_WDD_Pos 16
-#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
-#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
-#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
-#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
-/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
-#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */
-#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */
-
-/*@}*/
-
-
-#endif /* _SAMS70_WDT_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/xdmac.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/xdmac.h
deleted file mode 100644
index 942e270..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/component/xdmac.h
+++ /dev/null
@@ -1,634 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_XDMAC_COMPONENT_
-#define _SAMS70_XDMAC_COMPONENT_
-
-/* ============================================================================= */
-/** SOFTWARE API DEFINITION FOR Extensible DMA Controller */
-/* ============================================================================= */
-/** \addtogroup SAMS70_XDMAC Extensible DMA Controller */
-/*@{*/
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-/** \brief XdmacChid hardware registers */
-typedef struct {
- __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */
- __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */
- __O uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */
- __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */
- __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */
- __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */
- __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */
- __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */
- __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */
- __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */
- __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */
- __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */
- __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */
- __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */
- __I uint32_t Reserved1[2];
-} XdmacChid;
-/** \brief Xdmac hardware registers */
-#define XDMACCHID_NUMBER 24
-typedef struct {
- __IO uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */
- __I uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */
- __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */
- __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */
- __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */
- __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */
- __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */
- __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */
- __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */
- __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */
- __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */
- __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */
- __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */
- __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */
- __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */
- __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */
- __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */
- __I uint32_t Reserved1[3];
- XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 23 */
-} Xdmac;
-#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */
-#define XDMAC_GTYPE_NB_CH_Pos 0
-#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */
-#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos)))
-#define XDMAC_GTYPE_FIFO_SZ_Pos 5
-#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */
-#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos)))
-#define XDMAC_GTYPE_NB_REQ_Pos 16
-#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */
-#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos)))
-/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */
-#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */
-#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */
-#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */
-#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */
-#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilo byte Enable */
-/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */
-#define XDMAC_GWAC_PW0_Pos 0
-#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */
-#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos)))
-#define XDMAC_GWAC_PW1_Pos 4
-#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */
-#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos)))
-#define XDMAC_GWAC_PW2_Pos 8
-#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */
-#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos)))
-#define XDMAC_GWAC_PW3_Pos 12
-#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */
-#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos)))
-/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */
-#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */
-#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */
-#define XDMAC_GIE_IE2 (0x1u << 2) /**< \brief (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit */
-#define XDMAC_GIE_IE3 (0x1u << 3) /**< \brief (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit */
-#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */
-#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */
-#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */
-#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */
-#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */
-#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */
-#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */
-#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */
-#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */
-#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */
-#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */
-#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */
-#define XDMAC_GIE_IE16 (0x1u << 16) /**< \brief (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit */
-#define XDMAC_GIE_IE17 (0x1u << 17) /**< \brief (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit */
-#define XDMAC_GIE_IE18 (0x1u << 18) /**< \brief (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit */
-#define XDMAC_GIE_IE19 (0x1u << 19) /**< \brief (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit */
-#define XDMAC_GIE_IE20 (0x1u << 20) /**< \brief (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit */
-#define XDMAC_GIE_IE21 (0x1u << 21) /**< \brief (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit */
-#define XDMAC_GIE_IE22 (0x1u << 22) /**< \brief (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit */
-#define XDMAC_GIE_IE23 (0x1u << 23) /**< \brief (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit */
-/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */
-#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */
-#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */
-#define XDMAC_GID_ID2 (0x1u << 2) /**< \brief (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit */
-#define XDMAC_GID_ID3 (0x1u << 3) /**< \brief (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit */
-#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */
-#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */
-#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */
-#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */
-#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */
-#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */
-#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */
-#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */
-#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */
-#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */
-#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */
-#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */
-#define XDMAC_GID_ID16 (0x1u << 16) /**< \brief (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit */
-#define XDMAC_GID_ID17 (0x1u << 17) /**< \brief (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit */
-#define XDMAC_GID_ID18 (0x1u << 18) /**< \brief (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit */
-#define XDMAC_GID_ID19 (0x1u << 19) /**< \brief (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit */
-#define XDMAC_GID_ID20 (0x1u << 20) /**< \brief (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit */
-#define XDMAC_GID_ID21 (0x1u << 21) /**< \brief (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit */
-#define XDMAC_GID_ID22 (0x1u << 22) /**< \brief (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit */
-#define XDMAC_GID_ID23 (0x1u << 23) /**< \brief (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit */
-/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */
-#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */
-#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */
-#define XDMAC_GIM_IM2 (0x1u << 2) /**< \brief (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit */
-#define XDMAC_GIM_IM3 (0x1u << 3) /**< \brief (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit */
-#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */
-#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */
-#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */
-#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */
-#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */
-#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */
-#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */
-#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */
-#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */
-#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */
-#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */
-#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */
-#define XDMAC_GIM_IM16 (0x1u << 16) /**< \brief (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit */
-#define XDMAC_GIM_IM17 (0x1u << 17) /**< \brief (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit */
-#define XDMAC_GIM_IM18 (0x1u << 18) /**< \brief (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit */
-#define XDMAC_GIM_IM19 (0x1u << 19) /**< \brief (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit */
-#define XDMAC_GIM_IM20 (0x1u << 20) /**< \brief (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit */
-#define XDMAC_GIM_IM21 (0x1u << 21) /**< \brief (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit */
-#define XDMAC_GIM_IM22 (0x1u << 22) /**< \brief (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit */
-#define XDMAC_GIM_IM23 (0x1u << 23) /**< \brief (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit */
-/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */
-#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */
-#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */
-#define XDMAC_GIS_IS2 (0x1u << 2) /**< \brief (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit */
-#define XDMAC_GIS_IS3 (0x1u << 3) /**< \brief (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit */
-#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */
-#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */
-#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */
-#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */
-#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */
-#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */
-#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */
-#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */
-#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */
-#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */
-#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */
-#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */
-#define XDMAC_GIS_IS16 (0x1u << 16) /**< \brief (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit */
-#define XDMAC_GIS_IS17 (0x1u << 17) /**< \brief (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit */
-#define XDMAC_GIS_IS18 (0x1u << 18) /**< \brief (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit */
-#define XDMAC_GIS_IS19 (0x1u << 19) /**< \brief (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit */
-#define XDMAC_GIS_IS20 (0x1u << 20) /**< \brief (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit */
-#define XDMAC_GIS_IS21 (0x1u << 21) /**< \brief (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit */
-#define XDMAC_GIS_IS22 (0x1u << 22) /**< \brief (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit */
-#define XDMAC_GIS_IS23 (0x1u << 23) /**< \brief (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit */
-/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */
-#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */
-#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */
-#define XDMAC_GE_EN2 (0x1u << 2) /**< \brief (XDMAC_GE) XDMAC Channel 2 Enable Bit */
-#define XDMAC_GE_EN3 (0x1u << 3) /**< \brief (XDMAC_GE) XDMAC Channel 3 Enable Bit */
-#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */
-#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */
-#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */
-#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */
-#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */
-#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */
-#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */
-#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */
-#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */
-#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */
-#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */
-#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */
-#define XDMAC_GE_EN16 (0x1u << 16) /**< \brief (XDMAC_GE) XDMAC Channel 16 Enable Bit */
-#define XDMAC_GE_EN17 (0x1u << 17) /**< \brief (XDMAC_GE) XDMAC Channel 17 Enable Bit */
-#define XDMAC_GE_EN18 (0x1u << 18) /**< \brief (XDMAC_GE) XDMAC Channel 18 Enable Bit */
-#define XDMAC_GE_EN19 (0x1u << 19) /**< \brief (XDMAC_GE) XDMAC Channel 19 Enable Bit */
-#define XDMAC_GE_EN20 (0x1u << 20) /**< \brief (XDMAC_GE) XDMAC Channel 20 Enable Bit */
-#define XDMAC_GE_EN21 (0x1u << 21) /**< \brief (XDMAC_GE) XDMAC Channel 21 Enable Bit */
-#define XDMAC_GE_EN22 (0x1u << 22) /**< \brief (XDMAC_GE) XDMAC Channel 22 Enable Bit */
-#define XDMAC_GE_EN23 (0x1u << 23) /**< \brief (XDMAC_GE) XDMAC Channel 23 Enable Bit */
-/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */
-#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */
-#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */
-#define XDMAC_GD_DI2 (0x1u << 2) /**< \brief (XDMAC_GD) XDMAC Channel 2 Disable Bit */
-#define XDMAC_GD_DI3 (0x1u << 3) /**< \brief (XDMAC_GD) XDMAC Channel 3 Disable Bit */
-#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */
-#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */
-#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */
-#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */
-#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */
-#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */
-#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */
-#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */
-#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */
-#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */
-#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */
-#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */
-#define XDMAC_GD_DI16 (0x1u << 16) /**< \brief (XDMAC_GD) XDMAC Channel 16 Disable Bit */
-#define XDMAC_GD_DI17 (0x1u << 17) /**< \brief (XDMAC_GD) XDMAC Channel 17 Disable Bit */
-#define XDMAC_GD_DI18 (0x1u << 18) /**< \brief (XDMAC_GD) XDMAC Channel 18 Disable Bit */
-#define XDMAC_GD_DI19 (0x1u << 19) /**< \brief (XDMAC_GD) XDMAC Channel 19 Disable Bit */
-#define XDMAC_GD_DI20 (0x1u << 20) /**< \brief (XDMAC_GD) XDMAC Channel 20 Disable Bit */
-#define XDMAC_GD_DI21 (0x1u << 21) /**< \brief (XDMAC_GD) XDMAC Channel 21 Disable Bit */
-#define XDMAC_GD_DI22 (0x1u << 22) /**< \brief (XDMAC_GD) XDMAC Channel 22 Disable Bit */
-#define XDMAC_GD_DI23 (0x1u << 23) /**< \brief (XDMAC_GD) XDMAC Channel 23 Disable Bit */
-/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */
-#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */
-#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */
-#define XDMAC_GS_ST2 (0x1u << 2) /**< \brief (XDMAC_GS) XDMAC Channel 2 Status Bit */
-#define XDMAC_GS_ST3 (0x1u << 3) /**< \brief (XDMAC_GS) XDMAC Channel 3 Status Bit */
-#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */
-#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */
-#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */
-#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */
-#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */
-#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */
-#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */
-#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */
-#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */
-#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */
-#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */
-#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */
-#define XDMAC_GS_ST16 (0x1u << 16) /**< \brief (XDMAC_GS) XDMAC Channel 16 Status Bit */
-#define XDMAC_GS_ST17 (0x1u << 17) /**< \brief (XDMAC_GS) XDMAC Channel 17 Status Bit */
-#define XDMAC_GS_ST18 (0x1u << 18) /**< \brief (XDMAC_GS) XDMAC Channel 18 Status Bit */
-#define XDMAC_GS_ST19 (0x1u << 19) /**< \brief (XDMAC_GS) XDMAC Channel 19 Status Bit */
-#define XDMAC_GS_ST20 (0x1u << 20) /**< \brief (XDMAC_GS) XDMAC Channel 20 Status Bit */
-#define XDMAC_GS_ST21 (0x1u << 21) /**< \brief (XDMAC_GS) XDMAC Channel 21 Status Bit */
-#define XDMAC_GS_ST22 (0x1u << 22) /**< \brief (XDMAC_GS) XDMAC Channel 22 Status Bit */
-#define XDMAC_GS_ST23 (0x1u << 23) /**< \brief (XDMAC_GS) XDMAC Channel 23 Status Bit */
-/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */
-#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */
-#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */
-#define XDMAC_GRS_RS2 (0x1u << 2) /**< \brief (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit */
-#define XDMAC_GRS_RS3 (0x1u << 3) /**< \brief (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit */
-#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */
-#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */
-#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */
-#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */
-#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */
-#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */
-#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */
-#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */
-#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */
-#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */
-#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */
-#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */
-#define XDMAC_GRS_RS16 (0x1u << 16) /**< \brief (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit */
-#define XDMAC_GRS_RS17 (0x1u << 17) /**< \brief (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit */
-#define XDMAC_GRS_RS18 (0x1u << 18) /**< \brief (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit */
-#define XDMAC_GRS_RS19 (0x1u << 19) /**< \brief (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit */
-#define XDMAC_GRS_RS20 (0x1u << 20) /**< \brief (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit */
-#define XDMAC_GRS_RS21 (0x1u << 21) /**< \brief (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit */
-#define XDMAC_GRS_RS22 (0x1u << 22) /**< \brief (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit */
-#define XDMAC_GRS_RS23 (0x1u << 23) /**< \brief (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit */
-/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */
-#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */
-#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */
-#define XDMAC_GWS_WS2 (0x1u << 2) /**< \brief (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit */
-#define XDMAC_GWS_WS3 (0x1u << 3) /**< \brief (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit */
-#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */
-#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */
-#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */
-#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */
-#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */
-#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */
-#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */
-#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */
-#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */
-#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */
-#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */
-#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */
-#define XDMAC_GWS_WS16 (0x1u << 16) /**< \brief (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit */
-#define XDMAC_GWS_WS17 (0x1u << 17) /**< \brief (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit */
-#define XDMAC_GWS_WS18 (0x1u << 18) /**< \brief (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit */
-#define XDMAC_GWS_WS19 (0x1u << 19) /**< \brief (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit */
-#define XDMAC_GWS_WS20 (0x1u << 20) /**< \brief (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit */
-#define XDMAC_GWS_WS21 (0x1u << 21) /**< \brief (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit */
-#define XDMAC_GWS_WS22 (0x1u << 22) /**< \brief (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit */
-#define XDMAC_GWS_WS23 (0x1u << 23) /**< \brief (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit */
-/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */
-#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS2 (0x1u << 2) /**< \brief (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS3 (0x1u << 3) /**< \brief (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS16 (0x1u << 16) /**< \brief (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS17 (0x1u << 17) /**< \brief (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS18 (0x1u << 18) /**< \brief (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS19 (0x1u << 19) /**< \brief (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS20 (0x1u << 20) /**< \brief (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS21 (0x1u << 21) /**< \brief (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS22 (0x1u << 22) /**< \brief (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit */
-#define XDMAC_GRWS_RWS23 (0x1u << 23) /**< \brief (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit */
-/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */
-#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR2 (0x1u << 2) /**< \brief (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR3 (0x1u << 3) /**< \brief (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR16 (0x1u << 16) /**< \brief (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR17 (0x1u << 17) /**< \brief (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR18 (0x1u << 18) /**< \brief (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR19 (0x1u << 19) /**< \brief (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR20 (0x1u << 20) /**< \brief (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR21 (0x1u << 21) /**< \brief (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR22 (0x1u << 22) /**< \brief (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit */
-#define XDMAC_GRWR_RWR23 (0x1u << 23) /**< \brief (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit */
-/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */
-#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */
-#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */
-#define XDMAC_GSWR_SWREQ2 (0x1u << 2) /**< \brief (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit */
-#define XDMAC_GSWR_SWREQ3 (0x1u << 3) /**< \brief (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit */
-#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */
-#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */
-#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */
-#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */
-#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */
-#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */
-#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */
-#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */
-#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */
-#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */
-#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */
-#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */
-#define XDMAC_GSWR_SWREQ16 (0x1u << 16) /**< \brief (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit */
-#define XDMAC_GSWR_SWREQ17 (0x1u << 17) /**< \brief (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit */
-#define XDMAC_GSWR_SWREQ18 (0x1u << 18) /**< \brief (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit */
-#define XDMAC_GSWR_SWREQ19 (0x1u << 19) /**< \brief (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit */
-#define XDMAC_GSWR_SWREQ20 (0x1u << 20) /**< \brief (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit */
-#define XDMAC_GSWR_SWREQ21 (0x1u << 21) /**< \brief (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit */
-#define XDMAC_GSWR_SWREQ22 (0x1u << 22) /**< \brief (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit */
-#define XDMAC_GSWR_SWREQ23 (0x1u << 23) /**< \brief (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit */
-/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */
-#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS2 (0x1u << 2) /**< \brief (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS3 (0x1u << 3) /**< \brief (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS16 (0x1u << 16) /**< \brief (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS17 (0x1u << 17) /**< \brief (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS18 (0x1u << 18) /**< \brief (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS19 (0x1u << 19) /**< \brief (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS20 (0x1u << 20) /**< \brief (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS21 (0x1u << 21) /**< \brief (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS22 (0x1u << 22) /**< \brief (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit */
-#define XDMAC_GSWS_SWRS23 (0x1u << 23) /**< \brief (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit */
-/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */
-#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF2 (0x1u << 2) /**< \brief (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF3 (0x1u << 3) /**< \brief (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF16 (0x1u << 16) /**< \brief (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF17 (0x1u << 17) /**< \brief (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF18 (0x1u << 18) /**< \brief (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF19 (0x1u << 19) /**< \brief (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF20 (0x1u << 20) /**< \brief (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF21 (0x1u << 21) /**< \brief (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF22 (0x1u << 22) /**< \brief (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit */
-#define XDMAC_GSWF_SWF23 (0x1u << 23) /**< \brief (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit */
-/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */
-#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */
-#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */
-#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */
-#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */
-#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */
-#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */
-#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */
-/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */
-#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */
-#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */
-#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */
-#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */
-#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */
-#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */
-#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */
-/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */
-#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */
-#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */
-#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */
-#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */
-#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */
-#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */
-#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */
-/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */
-#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */
-#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */
-#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */
-#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */
-#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */
-#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */
-#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */
-/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */
-#define XDMAC_CSA_SA_Pos 0
-#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */
-#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos)))
-/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */
-#define XDMAC_CDA_DA_Pos 0
-#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */
-#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos)))
-/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */
-#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */
-#define XDMAC_CNDA_NDA_Pos 2
-#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */
-#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos)))
-/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */
-#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */
-#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled */
-#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled */
-#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */
-#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */
-#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */
-#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */
-#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */
-#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */
-#define XDMAC_CNDC_NDVIEW_Pos 3
-#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */
-#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos)))
-#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */
-#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */
-#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */
-#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */
-/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */
-#define XDMAC_CUBC_UBLEN_Pos 0
-#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */
-#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos)))
-/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */
-#define XDMAC_CBC_BLEN_Pos 0
-#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */
-#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos)))
-/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */
-#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */
-#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */
-#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */
-#define XDMAC_CC_MBSIZE_Pos 1
-#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */
-#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos)))
-#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */
-#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */
-#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */
-#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */
-#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */
-#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer */
-#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer */
-#define XDMAC_CC_PROT (0x1u << 5) /**< \brief (XDMAC_CC) Channel x Protection */
-#define XDMAC_CC_PROT_SEC (0x0u << 5) /**< \brief (XDMAC_CC) Channel is secured */
-#define XDMAC_CC_PROT_UNSEC (0x1u << 5) /**< \brief (XDMAC_CC) Channel is unsecured */
-#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */
-#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */
-#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */
-#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */
-#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated */
-#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */
-#define XDMAC_CC_CSIZE_Pos 8
-#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */
-#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos)))
-#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */
-#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */
-#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */
-#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */
-#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */
-#define XDMAC_CC_DWIDTH_Pos 11
-#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */
-#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos)))
-#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */
-#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */
-#define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */
-#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */
-#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0 */
-#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1 */
-#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */
-#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0 */
-#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1 */
-#define XDMAC_CC_SAM_Pos 16
-#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */
-#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos)))
-#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */
-#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */
-#define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */
-#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */
-#define XDMAC_CC_DAM_Pos 18
-#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */
-#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos)))
-#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */
-#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */
-#define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */
-#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */
-#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */
-#define XDMAC_CC_INITD_TERMINATED (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */
-#define XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */
-#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */
-#define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */
-#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */
-#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */
-#define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */
-#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */
-#define XDMAC_CC_PERID_Pos 24
-#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Identifier */
-#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos)))
-/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */
-#define XDMAC_CDS_MSP_SDS_MSP_Pos 0
-#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */
-#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos)))
-#define XDMAC_CDS_MSP_DDS_MSP_Pos 16
-#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */
-#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos)))
-/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */
-#define XDMAC_CSUS_SUBS_Pos 0
-#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */
-#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos)))
-/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */
-#define XDMAC_CDUS_DUBS_Pos 0
-#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */
-#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos)))
-
-/*@}*/
-
-
-#endif /* _SAMS70_XDMAC_COMPONENT_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/acc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/acc.h
deleted file mode 100644
index 5fab150..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/acc.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_ACC_INSTANCE_
-#define _SAMS70_ACC_INSTANCE_
-
-/* ========== Register definition for ACC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_ACC_CR (0x40044000U) /**< \brief (ACC) Control Register */
- #define REG_ACC_MR (0x40044004U) /**< \brief (ACC) Mode Register */
- #define REG_ACC_IER (0x40044024U) /**< \brief (ACC) Interrupt Enable Register */
- #define REG_ACC_IDR (0x40044028U) /**< \brief (ACC) Interrupt Disable Register */
- #define REG_ACC_IMR (0x4004402CU) /**< \brief (ACC) Interrupt Mask Register */
- #define REG_ACC_ISR (0x40044030U) /**< \brief (ACC) Interrupt Status Register */
- #define REG_ACC_ACR (0x40044094U) /**< \brief (ACC) Analog Control Register */
- #define REG_ACC_WPMR (0x400440E4U) /**< \brief (ACC) Write Protection Mode Register */
- #define REG_ACC_WPSR (0x400440E8U) /**< \brief (ACC) Write Protection Status Register */
-#else
- #define REG_ACC_CR (*(__O uint32_t*)0x40044000U) /**< \brief (ACC) Control Register */
- #define REG_ACC_MR (*(__IO uint32_t*)0x40044004U) /**< \brief (ACC) Mode Register */
- #define REG_ACC_IER (*(__O uint32_t*)0x40044024U) /**< \brief (ACC) Interrupt Enable Register */
- #define REG_ACC_IDR (*(__O uint32_t*)0x40044028U) /**< \brief (ACC) Interrupt Disable Register */
- #define REG_ACC_IMR (*(__I uint32_t*)0x4004402CU) /**< \brief (ACC) Interrupt Mask Register */
- #define REG_ACC_ISR (*(__I uint32_t*)0x40044030U) /**< \brief (ACC) Interrupt Status Register */
- #define REG_ACC_ACR (*(__IO uint32_t*)0x40044094U) /**< \brief (ACC) Analog Control Register */
- #define REG_ACC_WPMR (*(__IO uint32_t*)0x400440E4U) /**< \brief (ACC) Write Protection Mode Register */
- #define REG_ACC_WPSR (*(__I uint32_t*)0x400440E8U) /**< \brief (ACC) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_ACC_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/aes.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/aes.h
deleted file mode 100644
index 5a9a067..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/aes.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_AES_INSTANCE_
-#define _SAMS70_AES_INSTANCE_
-
-/* ========== Register definition for AES peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_AES_CR (0x4006C000U) /**< \brief (AES) Control Register */
- #define REG_AES_MR (0x4006C004U) /**< \brief (AES) Mode Register */
- #define REG_AES_IER (0x4006C010U) /**< \brief (AES) Interrupt Enable Register */
- #define REG_AES_IDR (0x4006C014U) /**< \brief (AES) Interrupt Disable Register */
- #define REG_AES_IMR (0x4006C018U) /**< \brief (AES) Interrupt Mask Register */
- #define REG_AES_ISR (0x4006C01CU) /**< \brief (AES) Interrupt Status Register */
- #define REG_AES_KEYWR (0x4006C020U) /**< \brief (AES) Key Word Register */
- #define REG_AES_IDATAR (0x4006C040U) /**< \brief (AES) Input Data Register */
- #define REG_AES_ODATAR (0x4006C050U) /**< \brief (AES) Output Data Register */
- #define REG_AES_IVR (0x4006C060U) /**< \brief (AES) Initialization Vector Register */
- #define REG_AES_AADLENR (0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */
- #define REG_AES_CLENR (0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */
- #define REG_AES_GHASHR (0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */
- #define REG_AES_TAGR (0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */
- #define REG_AES_CTRR (0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */
- #define REG_AES_GCMHR (0x4006C09CU) /**< \brief (AES) GCM H Word Register */
-#else
- #define REG_AES_CR (*(__O uint32_t*)0x4006C000U) /**< \brief (AES) Control Register */
- #define REG_AES_MR (*(__IO uint32_t*)0x4006C004U) /**< \brief (AES) Mode Register */
- #define REG_AES_IER (*(__O uint32_t*)0x4006C010U) /**< \brief (AES) Interrupt Enable Register */
- #define REG_AES_IDR (*(__O uint32_t*)0x4006C014U) /**< \brief (AES) Interrupt Disable Register */
- #define REG_AES_IMR (*(__I uint32_t*)0x4006C018U) /**< \brief (AES) Interrupt Mask Register */
- #define REG_AES_ISR (*(__I uint32_t*)0x4006C01CU) /**< \brief (AES) Interrupt Status Register */
- #define REG_AES_KEYWR (*(__O uint32_t*)0x4006C020U) /**< \brief (AES) Key Word Register */
- #define REG_AES_IDATAR (*(__O uint32_t*)0x4006C040U) /**< \brief (AES) Input Data Register */
- #define REG_AES_ODATAR (*(__I uint32_t*)0x4006C050U) /**< \brief (AES) Output Data Register */
- #define REG_AES_IVR (*(__O uint32_t*)0x4006C060U) /**< \brief (AES) Initialization Vector Register */
- #define REG_AES_AADLENR (*(__IO uint32_t*)0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */
- #define REG_AES_CLENR (*(__IO uint32_t*)0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */
- #define REG_AES_GHASHR (*(__IO uint32_t*)0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */
- #define REG_AES_TAGR (*(__I uint32_t*)0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */
- #define REG_AES_CTRR (*(__I uint32_t*)0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */
- #define REG_AES_GCMHR (*(__IO uint32_t*)0x4006C09CU) /**< \brief (AES) GCM H Word Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_AES_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/afec0.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/afec0.h
deleted file mode 100644
index ac8498a..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/afec0.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_AFEC0_INSTANCE_
-#define _SAMS70_AFEC0_INSTANCE_
-
-/* ========== Register definition for AFEC0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_AFEC0_CR (0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */
- #define REG_AFEC0_MR (0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */
- #define REG_AFEC0_EMR (0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */
- #define REG_AFEC0_SEQ1R (0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */
- #define REG_AFEC0_SEQ2R (0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */
- #define REG_AFEC0_CHER (0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */
- #define REG_AFEC0_CHDR (0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */
- #define REG_AFEC0_CHSR (0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */
- #define REG_AFEC0_LCDR (0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */
- #define REG_AFEC0_IER (0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */
- #define REG_AFEC0_IDR (0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */
- #define REG_AFEC0_IMR (0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */
- #define REG_AFEC0_ISR (0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */
- #define REG_AFEC0_OVER (0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */
- #define REG_AFEC0_CWR (0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */
- #define REG_AFEC0_CGR (0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain Register */
- #define REG_AFEC0_DIFFR (0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */
- #define REG_AFEC0_CSELR (0x4003C064U) /**< \brief (AFEC0) AFEC Channel Selection Register */
- #define REG_AFEC0_CDR (0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */
- #define REG_AFEC0_COCR (0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */
- #define REG_AFEC0_TEMPMR (0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */
- #define REG_AFEC0_TEMPCWR (0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */
- #define REG_AFEC0_ACR (0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */
- #define REG_AFEC0_SHMR (0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */
- #define REG_AFEC0_COSR (0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */
- #define REG_AFEC0_CVR (0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */
- #define REG_AFEC0_CECR (0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */
- #define REG_AFEC0_WPMR (0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */
- #define REG_AFEC0_WPSR (0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */
-#else
- #define REG_AFEC0_CR (*(__O uint32_t*)0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */
- #define REG_AFEC0_MR (*(__IO uint32_t*)0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */
- #define REG_AFEC0_EMR (*(__IO uint32_t*)0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */
- #define REG_AFEC0_SEQ1R (*(__IO uint32_t*)0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */
- #define REG_AFEC0_SEQ2R (*(__IO uint32_t*)0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */
- #define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */
- #define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */
- #define REG_AFEC0_CHSR (*(__I uint32_t*)0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */
- #define REG_AFEC0_LCDR (*(__I uint32_t*)0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */
- #define REG_AFEC0_IER (*(__O uint32_t*)0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */
- #define REG_AFEC0_IDR (*(__O uint32_t*)0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */
- #define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */
- #define REG_AFEC0_ISR (*(__I uint32_t*)0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */
- #define REG_AFEC0_OVER (*(__I uint32_t*)0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */
- #define REG_AFEC0_CWR (*(__IO uint32_t*)0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */
- #define REG_AFEC0_CGR (*(__IO uint32_t*)0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain Register */
- #define REG_AFEC0_DIFFR (*(__IO uint32_t*)0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */
- #define REG_AFEC0_CSELR (*(__IO uint32_t*)0x4003C064U) /**< \brief (AFEC0) AFEC Channel Selection Register */
- #define REG_AFEC0_CDR (*(__I uint32_t*)0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */
- #define REG_AFEC0_COCR (*(__IO uint32_t*)0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */
- #define REG_AFEC0_TEMPMR (*(__IO uint32_t*)0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */
- #define REG_AFEC0_TEMPCWR (*(__IO uint32_t*)0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */
- #define REG_AFEC0_ACR (*(__IO uint32_t*)0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */
- #define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */
- #define REG_AFEC0_COSR (*(__IO uint32_t*)0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */
- #define REG_AFEC0_CVR (*(__IO uint32_t*)0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */
- #define REG_AFEC0_CECR (*(__IO uint32_t*)0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */
- #define REG_AFEC0_WPMR (*(__IO uint32_t*)0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */
- #define REG_AFEC0_WPSR (*(__I uint32_t*)0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_AFEC0_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/afec1.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/afec1.h
deleted file mode 100644
index 461f201..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/afec1.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_AFEC1_INSTANCE_
-#define _SAMS70_AFEC1_INSTANCE_
-
-/* ========== Register definition for AFEC1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_AFEC1_CR (0x40064000U) /**< \brief (AFEC1) AFEC Control Register */
- #define REG_AFEC1_MR (0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */
- #define REG_AFEC1_EMR (0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */
- #define REG_AFEC1_SEQ1R (0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */
- #define REG_AFEC1_SEQ2R (0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */
- #define REG_AFEC1_CHER (0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */
- #define REG_AFEC1_CHDR (0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */
- #define REG_AFEC1_CHSR (0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */
- #define REG_AFEC1_LCDR (0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */
- #define REG_AFEC1_IER (0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */
- #define REG_AFEC1_IDR (0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */
- #define REG_AFEC1_IMR (0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */
- #define REG_AFEC1_ISR (0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */
- #define REG_AFEC1_OVER (0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */
- #define REG_AFEC1_CWR (0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */
- #define REG_AFEC1_CGR (0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */
- #define REG_AFEC1_DIFFR (0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */
- #define REG_AFEC1_CSELR (0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */
- #define REG_AFEC1_CDR (0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */
- #define REG_AFEC1_COCR (0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */
- #define REG_AFEC1_TEMPMR (0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */
- #define REG_AFEC1_TEMPCWR (0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */
- #define REG_AFEC1_ACR (0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */
- #define REG_AFEC1_SHMR (0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */
- #define REG_AFEC1_COSR (0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */
- #define REG_AFEC1_CVR (0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */
- #define REG_AFEC1_CECR (0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */
- #define REG_AFEC1_WPMR (0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */
- #define REG_AFEC1_WPSR (0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */
-#else
- #define REG_AFEC1_CR (*(__O uint32_t*)0x40064000U) /**< \brief (AFEC1) AFEC Control Register */
- #define REG_AFEC1_MR (*(__IO uint32_t*)0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */
- #define REG_AFEC1_EMR (*(__IO uint32_t*)0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */
- #define REG_AFEC1_SEQ1R (*(__IO uint32_t*)0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */
- #define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */
- #define REG_AFEC1_CHER (*(__O uint32_t*)0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */
- #define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */
- #define REG_AFEC1_CHSR (*(__I uint32_t*)0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */
- #define REG_AFEC1_LCDR (*(__I uint32_t*)0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */
- #define REG_AFEC1_IER (*(__O uint32_t*)0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */
- #define REG_AFEC1_IDR (*(__O uint32_t*)0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */
- #define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */
- #define REG_AFEC1_ISR (*(__I uint32_t*)0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */
- #define REG_AFEC1_OVER (*(__I uint32_t*)0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */
- #define REG_AFEC1_CWR (*(__IO uint32_t*)0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */
- #define REG_AFEC1_CGR (*(__IO uint32_t*)0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */
- #define REG_AFEC1_DIFFR (*(__IO uint32_t*)0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */
- #define REG_AFEC1_CSELR (*(__IO uint32_t*)0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */
- #define REG_AFEC1_CDR (*(__I uint32_t*)0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */
- #define REG_AFEC1_COCR (*(__IO uint32_t*)0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */
- #define REG_AFEC1_TEMPMR (*(__IO uint32_t*)0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */
- #define REG_AFEC1_TEMPCWR (*(__IO uint32_t*)0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */
- #define REG_AFEC1_ACR (*(__IO uint32_t*)0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */
- #define REG_AFEC1_SHMR (*(__IO uint32_t*)0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */
- #define REG_AFEC1_COSR (*(__IO uint32_t*)0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */
- #define REG_AFEC1_CVR (*(__IO uint32_t*)0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */
- #define REG_AFEC1_CECR (*(__IO uint32_t*)0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */
- #define REG_AFEC1_WPMR (*(__IO uint32_t*)0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */
- #define REG_AFEC1_WPSR (*(__I uint32_t*)0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_AFEC1_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/chipid.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/chipid.h
deleted file mode 100644
index 722773b..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/chipid.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_CHIPID_INSTANCE_
-#define _SAMS70_CHIPID_INSTANCE_
-
-/* ========== Register definition for CHIPID peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_CHIPID_CIDR (0x400E0940U) /**< \brief (CHIPID) Chip ID Register */
- #define REG_CHIPID_EXID (0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */
-#else
- #define REG_CHIPID_CIDR (*(__I uint32_t*)0x400E0940U) /**< \brief (CHIPID) Chip ID Register */
- #define REG_CHIPID_EXID (*(__I uint32_t*)0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_CHIPID_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/dacc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/dacc.h
deleted file mode 100644
index f92fe6d..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/dacc.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_DACC_INSTANCE_
-#define _SAMS70_DACC_INSTANCE_
-
-/* ========== Register definition for DACC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_DACC_CR (0x40040000U) /**< \brief (DACC) Control Register */
- #define REG_DACC_MR (0x40040004U) /**< \brief (DACC) Mode Register */
- #define REG_DACC_TRIGR (0x40040008U) /**< \brief (DACC) Trigger Register */
- #define REG_DACC_CHER (0x40040010U) /**< \brief (DACC) Channel Enable Register */
- #define REG_DACC_CHDR (0x40040014U) /**< \brief (DACC) Channel Disable Register */
- #define REG_DACC_CHSR (0x40040018U) /**< \brief (DACC) Channel Status Register */
- #define REG_DACC_CDR (0x4004001CU) /**< \brief (DACC) Conversion Data Register */
- #define REG_DACC_IER (0x40040024U) /**< \brief (DACC) Interrupt Enable Register */
- #define REG_DACC_IDR (0x40040028U) /**< \brief (DACC) Interrupt Disable Register */
- #define REG_DACC_IMR (0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */
- #define REG_DACC_ISR (0x40040030U) /**< \brief (DACC) Interrupt Status Register */
- #define REG_DACC_ACR (0x40040094U) /**< \brief (DACC) Analog Current Register */
- #define REG_DACC_WPMR (0x400400E4U) /**< \brief (DACC) Write Protection Mode register */
- #define REG_DACC_WPSR (0x400400E8U) /**< \brief (DACC) Write Protection Status register */
-#else
- #define REG_DACC_CR (*(__O uint32_t*)0x40040000U) /**< \brief (DACC) Control Register */
- #define REG_DACC_MR (*(__IO uint32_t*)0x40040004U) /**< \brief (DACC) Mode Register */
- #define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) /**< \brief (DACC) Trigger Register */
- #define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) /**< \brief (DACC) Channel Enable Register */
- #define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) /**< \brief (DACC) Channel Disable Register */
- #define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) /**< \brief (DACC) Channel Status Register */
- #define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) /**< \brief (DACC) Conversion Data Register */
- #define REG_DACC_IER (*(__O uint32_t*)0x40040024U) /**< \brief (DACC) Interrupt Enable Register */
- #define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) /**< \brief (DACC) Interrupt Disable Register */
- #define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */
- #define REG_DACC_ISR (*(__I uint32_t*)0x40040030U) /**< \brief (DACC) Interrupt Status Register */
- #define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) /**< \brief (DACC) Analog Current Register */
- #define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< \brief (DACC) Write Protection Mode register */
- #define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< \brief (DACC) Write Protection Status register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_DACC_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/efc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/efc.h
deleted file mode 100644
index e86fafc..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/efc.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_EFC_INSTANCE_
-#define _SAMS70_EFC_INSTANCE_
-
-/* ========== Register definition for EFC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_EFC_FMR (0x400E0C00U) /**< \brief (EFC) EEFC Flash Mode Register */
- #define REG_EFC_FCR (0x400E0C04U) /**< \brief (EFC) EEFC Flash Command Register */
- #define REG_EFC_FSR (0x400E0C08U) /**< \brief (EFC) EEFC Flash Status Register */
- #define REG_EFC_FRR (0x400E0C0CU) /**< \brief (EFC) EEFC Flash Result Register */
- #define REG_EFC_VERSION (0x400E0C14U) /**< \brief (EFC) EEFC Version Register */
- #define REG_EFC_WPMR (0x400E0CE4U) /**< \brief (EFC) Write Protection Mode Register */
-#else
- #define REG_EFC_FMR (*(__IO uint32_t*)0x400E0C00U) /**< \brief (EFC) EEFC Flash Mode Register */
- #define REG_EFC_FCR (*(__O uint32_t*)0x400E0C04U) /**< \brief (EFC) EEFC Flash Command Register */
- #define REG_EFC_FSR (*(__I uint32_t*)0x400E0C08U) /**< \brief (EFC) EEFC Flash Status Register */
- #define REG_EFC_FRR (*(__I uint32_t*)0x400E0C0CU) /**< \brief (EFC) EEFC Flash Result Register */
- #define REG_EFC_VERSION (*(__I uint32_t*)0x400E0C14U) /**< \brief (EFC) EEFC Version Register */
- #define REG_EFC_WPMR (*(__IO uint32_t*)0x400E0CE4U) /**< \brief (EFC) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_EFC_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/gpbr.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/gpbr.h
deleted file mode 100644
index 49de2e9..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/gpbr.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_GPBR_INSTANCE_
-#define _SAMS70_GPBR_INSTANCE_
-
-/* ========== Register definition for GPBR peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_GPBR_GPBR (0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */
-#else
- #define REG_GPBR_GPBR (*(__IO uint32_t*)0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_GPBR_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/hsmci.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/hsmci.h
deleted file mode 100644
index 3fc54b7..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/hsmci.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_HSMCI_INSTANCE_
-#define _SAMS70_HSMCI_INSTANCE_
-
-/* ========== Register definition for HSMCI peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */
- #define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */
- #define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
- #define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
- #define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */
- #define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */
- #define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */
- #define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
- #define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */
- #define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */
- #define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
- #define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */
- #define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
- #define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
- #define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
- #define REG_HSMCI_DMA (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
- #define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */
- #define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
- #define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
- #define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
-#else
- #define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< \brief (HSMCI) Control Register */
- #define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< \brief (HSMCI) Mode Register */
- #define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
- #define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
- #define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< \brief (HSMCI) Argument Register */
- #define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< \brief (HSMCI) Command Register */
- #define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< \brief (HSMCI) Block Register */
- #define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
- #define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< \brief (HSMCI) Response Register */
- #define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */
- #define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
- #define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< \brief (HSMCI) Status Register */
- #define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
- #define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
- #define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
- #define REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
- #define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< \brief (HSMCI) Configuration Register */
- #define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
- #define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
- #define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_HSMCI_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/icm.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/icm.h
deleted file mode 100644
index d3f9fb7..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/icm.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_ICM_INSTANCE_
-#define _SAMS70_ICM_INSTANCE_
-
-/* ========== Register definition for ICM peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_ICM_CFG (0x40048000U) /**< \brief (ICM) Configuration Register */
- #define REG_ICM_CTRL (0x40048004U) /**< \brief (ICM) Control Register */
- #define REG_ICM_SR (0x40048008U) /**< \brief (ICM) Status Register */
- #define REG_ICM_IER (0x40048010U) /**< \brief (ICM) Interrupt Enable Register */
- #define REG_ICM_IDR (0x40048014U) /**< \brief (ICM) Interrupt Disable Register */
- #define REG_ICM_IMR (0x40048018U) /**< \brief (ICM) Interrupt Mask Register */
- #define REG_ICM_ISR (0x4004801CU) /**< \brief (ICM) Interrupt Status Register */
- #define REG_ICM_UASR (0x40048020U) /**< \brief (ICM) Undefined Access Status Register */
- #define REG_ICM_DSCR (0x40048030U) /**< \brief (ICM) Region Descriptor Area Start Address Register */
- #define REG_ICM_HASH (0x40048034U) /**< \brief (ICM) Region Hash Area Start Address Register */
- #define REG_ICM_UIHVAL (0x40048038U) /**< \brief (ICM) User Initial Hash Value 0 Register */
-#else
- #define REG_ICM_CFG (*(__IO uint32_t*)0x40048000U) /**< \brief (ICM) Configuration Register */
- #define REG_ICM_CTRL (*(__O uint32_t*)0x40048004U) /**< \brief (ICM) Control Register */
- #define REG_ICM_SR (*(__O uint32_t*)0x40048008U) /**< \brief (ICM) Status Register */
- #define REG_ICM_IER (*(__O uint32_t*)0x40048010U) /**< \brief (ICM) Interrupt Enable Register */
- #define REG_ICM_IDR (*(__O uint32_t*)0x40048014U) /**< \brief (ICM) Interrupt Disable Register */
- #define REG_ICM_IMR (*(__I uint32_t*)0x40048018U) /**< \brief (ICM) Interrupt Mask Register */
- #define REG_ICM_ISR (*(__I uint32_t*)0x4004801CU) /**< \brief (ICM) Interrupt Status Register */
- #define REG_ICM_UASR (*(__I uint32_t*)0x40048020U) /**< \brief (ICM) Undefined Access Status Register */
- #define REG_ICM_DSCR (*(__IO uint32_t*)0x40048030U) /**< \brief (ICM) Region Descriptor Area Start Address Register */
- #define REG_ICM_HASH (*(__IO uint32_t*)0x40048034U) /**< \brief (ICM) Region Hash Area Start Address Register */
- #define REG_ICM_UIHVAL (*(__O uint32_t*)0x40048038U) /**< \brief (ICM) User Initial Hash Value 0 Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_ICM_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/isi.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/isi.h
deleted file mode 100644
index 731415d..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/isi.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_ISI_INSTANCE_
-#define _SAMS70_ISI_INSTANCE_
-
-/* ========== Register definition for ISI peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_ISI_CFG1 (0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */
- #define REG_ISI_CFG2 (0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */
- #define REG_ISI_PSIZE (0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */
- #define REG_ISI_PDECF (0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */
- #define REG_ISI_Y2R_SET0 (0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */
- #define REG_ISI_Y2R_SET1 (0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */
- #define REG_ISI_R2Y_SET0 (0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */
- #define REG_ISI_R2Y_SET1 (0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */
- #define REG_ISI_R2Y_SET2 (0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */
- #define REG_ISI_CR (0x4004C024U) /**< \brief (ISI) ISI Control Register */
- #define REG_ISI_SR (0x4004C028U) /**< \brief (ISI) ISI Status Register */
- #define REG_ISI_IER (0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */
- #define REG_ISI_IDR (0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */
- #define REG_ISI_IMR (0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */
- #define REG_ISI_DMA_CHER (0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */
- #define REG_ISI_DMA_CHDR (0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */
- #define REG_ISI_DMA_CHSR (0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */
- #define REG_ISI_DMA_P_ADDR (0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */
- #define REG_ISI_DMA_P_CTRL (0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */
- #define REG_ISI_DMA_P_DSCR (0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */
- #define REG_ISI_DMA_C_ADDR (0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */
- #define REG_ISI_DMA_C_CTRL (0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */
- #define REG_ISI_DMA_C_DSCR (0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */
- #define REG_ISI_WPMR (0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */
- #define REG_ISI_WPSR (0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */
-#else
- #define REG_ISI_CFG1 (*(__IO uint32_t*)0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */
- #define REG_ISI_CFG2 (*(__IO uint32_t*)0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */
- #define REG_ISI_PSIZE (*(__IO uint32_t*)0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */
- #define REG_ISI_PDECF (*(__IO uint32_t*)0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */
- #define REG_ISI_Y2R_SET0 (*(__IO uint32_t*)0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */
- #define REG_ISI_Y2R_SET1 (*(__IO uint32_t*)0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */
- #define REG_ISI_R2Y_SET0 (*(__IO uint32_t*)0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */
- #define REG_ISI_R2Y_SET1 (*(__IO uint32_t*)0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */
- #define REG_ISI_R2Y_SET2 (*(__IO uint32_t*)0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */
- #define REG_ISI_CR (*(__O uint32_t*)0x4004C024U) /**< \brief (ISI) ISI Control Register */
- #define REG_ISI_SR (*(__I uint32_t*)0x4004C028U) /**< \brief (ISI) ISI Status Register */
- #define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */
- #define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */
- #define REG_ISI_IMR (*(__I uint32_t*)0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */
- #define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */
- #define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */
- #define REG_ISI_DMA_CHSR (*(__I uint32_t*)0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */
- #define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */
- #define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */
- #define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */
- #define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */
- #define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */
- #define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */
- #define REG_ISI_WPMR (*(__IO uint32_t*)0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */
- #define REG_ISI_WPSR (*(__I uint32_t*)0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_ISI_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/matrix.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/matrix.h
deleted file mode 100644
index 4e78d0f..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/matrix.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_MATRIX_INSTANCE_
-#define _SAMS70_MATRIX_INSTANCE_
-
-/* ========== Register definition for MATRIX peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_MATRIX_MCFG0 (0x40088000U) /**< \brief (MATRIX) Master Configuration Register 0 */
- #define REG_MATRIX_MCFG1 (0x40088004U) /**< \brief (MATRIX) Master Configuration Register 1 */
- #define REG_MATRIX_MCFG2 (0x40088008U) /**< \brief (MATRIX) Master Configuration Register 2 */
- #define REG_MATRIX_MCFG3 (0x4008800CU) /**< \brief (MATRIX) Master Configuration Register 3 */
- #define REG_MATRIX_MCFG4 (0x40088010U) /**< \brief (MATRIX) Master Configuration Register 4 */
- #define REG_MATRIX_MCFG5 (0x40088014U) /**< \brief (MATRIX) Master Configuration Register 5 */
- #define REG_MATRIX_MCFG6 (0x40088018U) /**< \brief (MATRIX) Master Configuration Register 6 */
- #define REG_MATRIX_MCFG8 (0x40088020U) /**< \brief (MATRIX) Master Configuration Register 8 */
- #define REG_MATRIX_SCFG (0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */
- #define REG_MATRIX_PRAS0 (0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
- #define REG_MATRIX_PRBS0 (0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
- #define REG_MATRIX_PRAS1 (0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
- #define REG_MATRIX_PRBS1 (0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
- #define REG_MATRIX_PRAS2 (0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
- #define REG_MATRIX_PRBS2 (0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
- #define REG_MATRIX_PRAS3 (0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
- #define REG_MATRIX_PRBS3 (0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
- #define REG_MATRIX_PRAS4 (0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
- #define REG_MATRIX_PRBS4 (0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
- #define REG_MATRIX_PRAS5 (0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
- #define REG_MATRIX_PRBS5 (0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
- #define REG_MATRIX_PRAS6 (0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
- #define REG_MATRIX_PRBS6 (0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
- #define REG_MATRIX_PRAS7 (0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
- #define REG_MATRIX_PRBS7 (0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
- #define REG_MATRIX_PRAS8 (0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
- #define REG_MATRIX_PRBS8 (0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
- #define REG_MATRIX_MRCR (0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */
- #define REG_CCFG_SYSIO (0x40088114U) /**< \brief (MATRIX) System I/O Configuration Register */
- #define REG_CCFG_SMCNFCS (0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */
- #define REG_MATRIX_WPMR (0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */
- #define REG_MATRIX_WPSR (0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */
-#else
- #define REG_MATRIX_MCFG0 (*(__IO uint32_t*)0x40088000U) /**< \brief (MATRIX) Master Configuration Register 0 */
- #define REG_MATRIX_MCFG1 (*(__IO uint32_t*)0x40088004U) /**< \brief (MATRIX) Master Configuration Register 1 */
- #define REG_MATRIX_MCFG2 (*(__IO uint32_t*)0x40088008U) /**< \brief (MATRIX) Master Configuration Register 2 */
- #define REG_MATRIX_MCFG3 (*(__IO uint32_t*)0x4008800CU) /**< \brief (MATRIX) Master Configuration Register 3 */
- #define REG_MATRIX_MCFG4 (*(__IO uint32_t*)0x40088010U) /**< \brief (MATRIX) Master Configuration Register 4 */
- #define REG_MATRIX_MCFG5 (*(__IO uint32_t*)0x40088014U) /**< \brief (MATRIX) Master Configuration Register 5 */
- #define REG_MATRIX_MCFG6 (*(__IO uint32_t*)0x40088018U) /**< \brief (MATRIX) Master Configuration Register 6 */
- #define REG_MATRIX_MCFG8 (*(__IO uint32_t*)0x40088020U) /**< \brief (MATRIX) Master Configuration Register 8 */
- #define REG_MATRIX_SCFG (*(__IO uint32_t*)0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */
- #define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
- #define REG_MATRIX_PRBS0 (*(__IO uint32_t*)0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
- #define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
- #define REG_MATRIX_PRBS1 (*(__IO uint32_t*)0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
- #define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
- #define REG_MATRIX_PRBS2 (*(__IO uint32_t*)0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
- #define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
- #define REG_MATRIX_PRBS3 (*(__IO uint32_t*)0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
- #define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
- #define REG_MATRIX_PRBS4 (*(__IO uint32_t*)0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
- #define REG_MATRIX_PRAS5 (*(__IO uint32_t*)0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
- #define REG_MATRIX_PRBS5 (*(__IO uint32_t*)0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
- #define REG_MATRIX_PRAS6 (*(__IO uint32_t*)0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
- #define REG_MATRIX_PRBS6 (*(__IO uint32_t*)0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
- #define REG_MATRIX_PRAS7 (*(__IO uint32_t*)0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
- #define REG_MATRIX_PRBS7 (*(__IO uint32_t*)0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
- #define REG_MATRIX_PRAS8 (*(__IO uint32_t*)0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
- #define REG_MATRIX_PRBS8 (*(__IO uint32_t*)0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
- #define REG_MATRIX_MRCR (*(__IO uint32_t*)0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */
- #define REG_CCFG_SYSIO (*(__IO uint32_t*)0x40088114U) /**< \brief (MATRIX) System I/O Configuration Register */
- #define REG_CCFG_SMCNFCS (*(__IO uint32_t*)0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */
- #define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */
- #define REG_MATRIX_WPSR (*(__I uint32_t*)0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_MATRIX_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pioa.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pioa.h
deleted file mode 100644
index edacbb8..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pioa.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PIOA_INSTANCE_
-#define _SAMS70_PIOA_INSTANCE_
-
-/* ========== Register definition for PIOA peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
- #define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
- #define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
- #define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
- #define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
- #define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
- #define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
- #define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
- #define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
- #define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
- #define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
- #define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
- #define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
- #define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
- #define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
- #define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
- #define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
- #define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
- #define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
- #define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
- #define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
- #define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
- #define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
- #define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
- #define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
- #define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
- #define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
- #define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
- #define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
- #define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
- #define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
- #define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
- #define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
- #define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
- #define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
- #define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */
- #define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
- #define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
- #define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
- #define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
- #define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */
- #define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */
- #define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
- #define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
- #define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */
- #define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */
- #define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
- #define REG_PIOA_DRIVER (0x400E0F18U) /**< \brief (PIOA) PIO I/O Drive Register */
- #define REG_PIOA_KER (0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */
- #define REG_PIOA_KRCR (0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */
- #define REG_PIOA_KDR (0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */
- #define REG_PIOA_KIER (0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */
- #define REG_PIOA_KIDR (0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */
- #define REG_PIOA_KIMR (0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */
- #define REG_PIOA_KSR (0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */
- #define REG_PIOA_KKPR (0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */
- #define REG_PIOA_KKRR (0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */
- #define REG_PIOA_PCMR (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
- #define REG_PIOA_PCIER (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
- #define REG_PIOA_PCIDR (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
- #define REG_PIOA_PCIMR (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
- #define REG_PIOA_PCISR (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
- #define REG_PIOA_PCRHR (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
-#else
- #define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
- #define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
- #define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
- #define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
- #define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
- #define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
- #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
- #define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
- #define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
- #define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
- #define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
- #define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
- #define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
- #define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
- #define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
- #define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
- #define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
- #define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
- #define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
- #define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
- #define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
- #define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
- #define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
- #define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
- #define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
- #define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
- #define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
- #define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
- #define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
- #define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
- #define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
- #define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
- #define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
- #define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
- #define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
- #define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */
- #define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
- #define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
- #define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
- #define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
- #define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */
- #define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */
- #define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
- #define REG_PIOA_LOCKSR (*(__I uint32_t*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
- #define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */
- #define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */
- #define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
- #define REG_PIOA_DRIVER (*(__IO uint32_t*)0x400E0F18U) /**< \brief (PIOA) PIO I/O Drive Register */
- #define REG_PIOA_KER (*(__IO uint32_t*)0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */
- #define REG_PIOA_KRCR (*(__IO uint32_t*)0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */
- #define REG_PIOA_KDR (*(__IO uint32_t*)0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */
- #define REG_PIOA_KIER (*(__O uint32_t*)0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */
- #define REG_PIOA_KIDR (*(__O uint32_t*)0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */
- #define REG_PIOA_KIMR (*(__I uint32_t*)0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */
- #define REG_PIOA_KSR (*(__I uint32_t*)0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */
- #define REG_PIOA_KKPR (*(__I uint32_t*)0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */
- #define REG_PIOA_KKRR (*(__I uint32_t*)0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */
- #define REG_PIOA_PCMR (*(__IO uint32_t*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
- #define REG_PIOA_PCIER (*(__O uint32_t*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
- #define REG_PIOA_PCIDR (*(__O uint32_t*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
- #define REG_PIOA_PCIMR (*(__I uint32_t*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
- #define REG_PIOA_PCISR (*(__I uint32_t*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
- #define REG_PIOA_PCRHR (*(__I uint32_t*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PIOA_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/piob.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/piob.h
deleted file mode 100644
index 11cd590..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/piob.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PIOB_INSTANCE_
-#define _SAMS70_PIOB_INSTANCE_
-
-/* ========== Register definition for PIOB peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
- #define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
- #define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
- #define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
- #define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
- #define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */
- #define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
- #define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
- #define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
- #define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
- #define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
- #define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
- #define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
- #define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
- #define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
- #define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
- #define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
- #define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
- #define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
- #define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
- #define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
- #define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
- #define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
- #define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
- #define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
- #define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
- #define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
- #define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
- #define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
- #define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
- #define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
- #define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
- #define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
- #define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
- #define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
- #define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */
- #define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
- #define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
- #define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
- #define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
- #define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */
- #define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */
- #define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
- #define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */
- #define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */
- #define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */
- #define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
- #define REG_PIOB_DRIVER (0x400E1118U) /**< \brief (PIOB) PIO I/O Drive Register */
- #define REG_PIOB_KER (0x400E1120U) /**< \brief (PIOB) Keypad Controller Enable Register */
- #define REG_PIOB_KRCR (0x400E1124U) /**< \brief (PIOB) Keypad Controller Row Column Register */
- #define REG_PIOB_KDR (0x400E1128U) /**< \brief (PIOB) Keypad Controller Debouncing Register */
- #define REG_PIOB_KIER (0x400E1130U) /**< \brief (PIOB) Keypad Controller Interrupt Enable Register */
- #define REG_PIOB_KIDR (0x400E1134U) /**< \brief (PIOB) Keypad Controller Interrupt Disable Register */
- #define REG_PIOB_KIMR (0x400E1138U) /**< \brief (PIOB) Keypad Controller Interrupt Mask Register */
- #define REG_PIOB_KSR (0x400E113CU) /**< \brief (PIOB) Keypad Controller Status Register */
- #define REG_PIOB_KKPR (0x400E1140U) /**< \brief (PIOB) Keypad Controller Key Press Register */
- #define REG_PIOB_KKRR (0x400E1144U) /**< \brief (PIOB) Keypad Controller Key Release Register */
- #define REG_PIOB_PCMR (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
- #define REG_PIOB_PCIER (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
- #define REG_PIOB_PCIDR (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
- #define REG_PIOB_PCIMR (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
- #define REG_PIOB_PCISR (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
- #define REG_PIOB_PCRHR (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
-#else
- #define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
- #define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
- #define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
- #define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
- #define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
- #define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
- #define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
- #define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
- #define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
- #define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
- #define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
- #define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
- #define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
- #define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
- #define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
- #define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
- #define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
- #define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
- #define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
- #define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
- #define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
- #define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
- #define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
- #define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
- #define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
- #define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
- #define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
- #define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
- #define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
- #define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
- #define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
- #define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
- #define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
- #define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
- #define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
- #define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */
- #define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
- #define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
- #define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
- #define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
- #define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */
- #define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */
- #define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
- #define REG_PIOB_LOCKSR (*(__I uint32_t*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
- #define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */
- #define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */
- #define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
- #define REG_PIOB_DRIVER (*(__IO uint32_t*)0x400E1118U) /**< \brief (PIOB) PIO I/O Drive Register */
- #define REG_PIOB_KER (*(__IO uint32_t*)0x400E1120U) /**< \brief (PIOB) Keypad Controller Enable Register */
- #define REG_PIOB_KRCR (*(__IO uint32_t*)0x400E1124U) /**< \brief (PIOB) Keypad Controller Row Column Register */
- #define REG_PIOB_KDR (*(__IO uint32_t*)0x400E1128U) /**< \brief (PIOB) Keypad Controller Debouncing Register */
- #define REG_PIOB_KIER (*(__O uint32_t*)0x400E1130U) /**< \brief (PIOB) Keypad Controller Interrupt Enable Register */
- #define REG_PIOB_KIDR (*(__O uint32_t*)0x400E1134U) /**< \brief (PIOB) Keypad Controller Interrupt Disable Register */
- #define REG_PIOB_KIMR (*(__I uint32_t*)0x400E1138U) /**< \brief (PIOB) Keypad Controller Interrupt Mask Register */
- #define REG_PIOB_KSR (*(__I uint32_t*)0x400E113CU) /**< \brief (PIOB) Keypad Controller Status Register */
- #define REG_PIOB_KKPR (*(__I uint32_t*)0x400E1140U) /**< \brief (PIOB) Keypad Controller Key Press Register */
- #define REG_PIOB_KKRR (*(__I uint32_t*)0x400E1144U) /**< \brief (PIOB) Keypad Controller Key Release Register */
- #define REG_PIOB_PCMR (*(__IO uint32_t*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
- #define REG_PIOB_PCIER (*(__O uint32_t*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
- #define REG_PIOB_PCIDR (*(__O uint32_t*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
- #define REG_PIOB_PCIMR (*(__I uint32_t*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
- #define REG_PIOB_PCISR (*(__I uint32_t*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
- #define REG_PIOB_PCRHR (*(__I uint32_t*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PIOB_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pioc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pioc.h
deleted file mode 100644
index 6d0d928..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pioc.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PIOC_INSTANCE_
-#define _SAMS70_PIOC_INSTANCE_
-
-/* ========== Register definition for PIOC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
- #define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
- #define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */
- #define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */
- #define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */
- #define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */
- #define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
- #define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
- #define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
- #define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
- #define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
- #define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
- #define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
- #define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
- #define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
- #define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
- #define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
- #define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
- #define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
- #define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
- #define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
- #define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
- #define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
- #define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
- #define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
- #define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
- #define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
- #define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
- #define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
- #define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
- #define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
- #define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
- #define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
- #define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
- #define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
- #define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disable Register */
- #define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
- #define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
- #define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */
- #define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
- #define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low-Level Select Register */
- #define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/High-Level Select Register */
- #define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
- #define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */
- #define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protection Mode Register */
- #define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protection Status Register */
- #define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
- #define REG_PIOC_DRIVER (0x400E1318U) /**< \brief (PIOC) PIO I/O Drive Register */
- #define REG_PIOC_KER (0x400E1320U) /**< \brief (PIOC) Keypad Controller Enable Register */
- #define REG_PIOC_KRCR (0x400E1324U) /**< \brief (PIOC) Keypad Controller Row Column Register */
- #define REG_PIOC_KDR (0x400E1328U) /**< \brief (PIOC) Keypad Controller Debouncing Register */
- #define REG_PIOC_KIER (0x400E1330U) /**< \brief (PIOC) Keypad Controller Interrupt Enable Register */
- #define REG_PIOC_KIDR (0x400E1334U) /**< \brief (PIOC) Keypad Controller Interrupt Disable Register */
- #define REG_PIOC_KIMR (0x400E1338U) /**< \brief (PIOC) Keypad Controller Interrupt Mask Register */
- #define REG_PIOC_KSR (0x400E133CU) /**< \brief (PIOC) Keypad Controller Status Register */
- #define REG_PIOC_KKPR (0x400E1340U) /**< \brief (PIOC) Keypad Controller Key Press Register */
- #define REG_PIOC_KKRR (0x400E1344U) /**< \brief (PIOC) Keypad Controller Key Release Register */
- #define REG_PIOC_PCMR (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
- #define REG_PIOC_PCIER (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
- #define REG_PIOC_PCIDR (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
- #define REG_PIOC_PCIMR (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
- #define REG_PIOC_PCISR (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
- #define REG_PIOC_PCRHR (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
-#else
- #define REG_PIOC_PER (*(__O uint32_t*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
- #define REG_PIOC_PDR (*(__O uint32_t*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
- #define REG_PIOC_PSR (*(__I uint32_t*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */
- #define REG_PIOC_OER (*(__O uint32_t*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */
- #define REG_PIOC_ODR (*(__O uint32_t*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */
- #define REG_PIOC_OSR (*(__I uint32_t*)0x400E1218U) /**< \brief (PIOC) Output Status Register */
- #define REG_PIOC_IFER (*(__O uint32_t*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
- #define REG_PIOC_IFDR (*(__O uint32_t*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
- #define REG_PIOC_IFSR (*(__I uint32_t*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
- #define REG_PIOC_SODR (*(__O uint32_t*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
- #define REG_PIOC_CODR (*(__O uint32_t*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
- #define REG_PIOC_ODSR (*(__IO uint32_t*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
- #define REG_PIOC_PDSR (*(__I uint32_t*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
- #define REG_PIOC_IER (*(__O uint32_t*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
- #define REG_PIOC_IDR (*(__O uint32_t*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
- #define REG_PIOC_IMR (*(__I uint32_t*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
- #define REG_PIOC_ISR (*(__I uint32_t*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
- #define REG_PIOC_MDER (*(__O uint32_t*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
- #define REG_PIOC_MDDR (*(__O uint32_t*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
- #define REG_PIOC_MDSR (*(__I uint32_t*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
- #define REG_PIOC_PUDR (*(__O uint32_t*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
- #define REG_PIOC_PUER (*(__O uint32_t*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
- #define REG_PIOC_PUSR (*(__I uint32_t*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
- #define REG_PIOC_ABCDSR (*(__IO uint32_t*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
- #define REG_PIOC_IFSCDR (*(__O uint32_t*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
- #define REG_PIOC_IFSCER (*(__O uint32_t*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
- #define REG_PIOC_IFSCSR (*(__I uint32_t*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
- #define REG_PIOC_SCDR (*(__IO uint32_t*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
- #define REG_PIOC_PPDDR (*(__O uint32_t*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
- #define REG_PIOC_PPDER (*(__O uint32_t*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
- #define REG_PIOC_PPDSR (*(__I uint32_t*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
- #define REG_PIOC_OWER (*(__O uint32_t*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
- #define REG_PIOC_OWDR (*(__O uint32_t*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
- #define REG_PIOC_OWSR (*(__I uint32_t*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
- #define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
- #define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disable Register */
- #define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
- #define REG_PIOC_ESR (*(__O uint32_t*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
- #define REG_PIOC_LSR (*(__O uint32_t*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */
- #define REG_PIOC_ELSR (*(__I uint32_t*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
- #define REG_PIOC_FELLSR (*(__O uint32_t*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low-Level Select Register */
- #define REG_PIOC_REHLSR (*(__O uint32_t*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/High-Level Select Register */
- #define REG_PIOC_FRLHSR (*(__I uint32_t*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
- #define REG_PIOC_LOCKSR (*(__I uint32_t*)0x400E12E0U) /**< \brief (PIOC) Lock Status */
- #define REG_PIOC_WPMR (*(__IO uint32_t*)0x400E12E4U) /**< \brief (PIOC) Write Protection Mode Register */
- #define REG_PIOC_WPSR (*(__I uint32_t*)0x400E12E8U) /**< \brief (PIOC) Write Protection Status Register */
- #define REG_PIOC_SCHMITT (*(__IO uint32_t*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
- #define REG_PIOC_DRIVER (*(__IO uint32_t*)0x400E1318U) /**< \brief (PIOC) PIO I/O Drive Register */
- #define REG_PIOC_KER (*(__IO uint32_t*)0x400E1320U) /**< \brief (PIOC) Keypad Controller Enable Register */
- #define REG_PIOC_KRCR (*(__IO uint32_t*)0x400E1324U) /**< \brief (PIOC) Keypad Controller Row Column Register */
- #define REG_PIOC_KDR (*(__IO uint32_t*)0x400E1328U) /**< \brief (PIOC) Keypad Controller Debouncing Register */
- #define REG_PIOC_KIER (*(__O uint32_t*)0x400E1330U) /**< \brief (PIOC) Keypad Controller Interrupt Enable Register */
- #define REG_PIOC_KIDR (*(__O uint32_t*)0x400E1334U) /**< \brief (PIOC) Keypad Controller Interrupt Disable Register */
- #define REG_PIOC_KIMR (*(__I uint32_t*)0x400E1338U) /**< \brief (PIOC) Keypad Controller Interrupt Mask Register */
- #define REG_PIOC_KSR (*(__I uint32_t*)0x400E133CU) /**< \brief (PIOC) Keypad Controller Status Register */
- #define REG_PIOC_KKPR (*(__I uint32_t*)0x400E1340U) /**< \brief (PIOC) Keypad Controller Key Press Register */
- #define REG_PIOC_KKRR (*(__I uint32_t*)0x400E1344U) /**< \brief (PIOC) Keypad Controller Key Release Register */
- #define REG_PIOC_PCMR (*(__IO uint32_t*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
- #define REG_PIOC_PCIER (*(__O uint32_t*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
- #define REG_PIOC_PCIDR (*(__O uint32_t*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
- #define REG_PIOC_PCIMR (*(__I uint32_t*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
- #define REG_PIOC_PCISR (*(__I uint32_t*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
- #define REG_PIOC_PCRHR (*(__I uint32_t*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PIOC_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/piod.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/piod.h
deleted file mode 100644
index 46d6f11..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/piod.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PIOD_INSTANCE_
-#define _SAMS70_PIOD_INSTANCE_
-
-/* ========== Register definition for PIOD peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PIOD_PER (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
- #define REG_PIOD_PDR (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
- #define REG_PIOD_PSR (0x400E1408U) /**< \brief (PIOD) PIO Status Register */
- #define REG_PIOD_OER (0x400E1410U) /**< \brief (PIOD) Output Enable Register */
- #define REG_PIOD_ODR (0x400E1414U) /**< \brief (PIOD) Output Disable Register */
- #define REG_PIOD_OSR (0x400E1418U) /**< \brief (PIOD) Output Status Register */
- #define REG_PIOD_IFER (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
- #define REG_PIOD_IFDR (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
- #define REG_PIOD_IFSR (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
- #define REG_PIOD_SODR (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
- #define REG_PIOD_CODR (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
- #define REG_PIOD_ODSR (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
- #define REG_PIOD_PDSR (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
- #define REG_PIOD_IER (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
- #define REG_PIOD_IDR (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
- #define REG_PIOD_IMR (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
- #define REG_PIOD_ISR (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
- #define REG_PIOD_MDER (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
- #define REG_PIOD_MDDR (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
- #define REG_PIOD_MDSR (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
- #define REG_PIOD_PUDR (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
- #define REG_PIOD_PUER (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
- #define REG_PIOD_PUSR (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
- #define REG_PIOD_ABCDSR (0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */
- #define REG_PIOD_IFSCDR (0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */
- #define REG_PIOD_IFSCER (0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */
- #define REG_PIOD_IFSCSR (0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */
- #define REG_PIOD_SCDR (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
- #define REG_PIOD_PPDDR (0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */
- #define REG_PIOD_PPDER (0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */
- #define REG_PIOD_PPDSR (0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */
- #define REG_PIOD_OWER (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
- #define REG_PIOD_OWDR (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
- #define REG_PIOD_OWSR (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
- #define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
- #define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disable Register */
- #define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
- #define REG_PIOD_ESR (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
- #define REG_PIOD_LSR (0x400E14C4U) /**< \brief (PIOD) Level Select Register */
- #define REG_PIOD_ELSR (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
- #define REG_PIOD_FELLSR (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low-Level Select Register */
- #define REG_PIOD_REHLSR (0x400E14D4U) /**< \brief (PIOD) Rising Edge/High-Level Select Register */
- #define REG_PIOD_FRLHSR (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
- #define REG_PIOD_LOCKSR (0x400E14E0U) /**< \brief (PIOD) Lock Status */
- #define REG_PIOD_WPMR (0x400E14E4U) /**< \brief (PIOD) Write Protection Mode Register */
- #define REG_PIOD_WPSR (0x400E14E8U) /**< \brief (PIOD) Write Protection Status Register */
- #define REG_PIOD_SCHMITT (0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */
- #define REG_PIOD_DRIVER (0x400E1518U) /**< \brief (PIOD) PIO I/O Drive Register */
- #define REG_PIOD_KER (0x400E1520U) /**< \brief (PIOD) Keypad Controller Enable Register */
- #define REG_PIOD_KRCR (0x400E1524U) /**< \brief (PIOD) Keypad Controller Row Column Register */
- #define REG_PIOD_KDR (0x400E1528U) /**< \brief (PIOD) Keypad Controller Debouncing Register */
- #define REG_PIOD_KIER (0x400E1530U) /**< \brief (PIOD) Keypad Controller Interrupt Enable Register */
- #define REG_PIOD_KIDR (0x400E1534U) /**< \brief (PIOD) Keypad Controller Interrupt Disable Register */
- #define REG_PIOD_KIMR (0x400E1538U) /**< \brief (PIOD) Keypad Controller Interrupt Mask Register */
- #define REG_PIOD_KSR (0x400E153CU) /**< \brief (PIOD) Keypad Controller Status Register */
- #define REG_PIOD_KKPR (0x400E1540U) /**< \brief (PIOD) Keypad Controller Key Press Register */
- #define REG_PIOD_KKRR (0x400E1544U) /**< \brief (PIOD) Keypad Controller Key Release Register */
- #define REG_PIOD_PCMR (0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */
- #define REG_PIOD_PCIER (0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */
- #define REG_PIOD_PCIDR (0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */
- #define REG_PIOD_PCIMR (0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */
- #define REG_PIOD_PCISR (0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */
- #define REG_PIOD_PCRHR (0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */
-#else
- #define REG_PIOD_PER (*(__O uint32_t*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
- #define REG_PIOD_PDR (*(__O uint32_t*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
- #define REG_PIOD_PSR (*(__I uint32_t*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */
- #define REG_PIOD_OER (*(__O uint32_t*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */
- #define REG_PIOD_ODR (*(__O uint32_t*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */
- #define REG_PIOD_OSR (*(__I uint32_t*)0x400E1418U) /**< \brief (PIOD) Output Status Register */
- #define REG_PIOD_IFER (*(__O uint32_t*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
- #define REG_PIOD_IFDR (*(__O uint32_t*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
- #define REG_PIOD_IFSR (*(__I uint32_t*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
- #define REG_PIOD_SODR (*(__O uint32_t*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
- #define REG_PIOD_CODR (*(__O uint32_t*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
- #define REG_PIOD_ODSR (*(__IO uint32_t*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
- #define REG_PIOD_PDSR (*(__I uint32_t*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
- #define REG_PIOD_IER (*(__O uint32_t*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
- #define REG_PIOD_IDR (*(__O uint32_t*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
- #define REG_PIOD_IMR (*(__I uint32_t*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
- #define REG_PIOD_ISR (*(__I uint32_t*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
- #define REG_PIOD_MDER (*(__O uint32_t*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
- #define REG_PIOD_MDDR (*(__O uint32_t*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
- #define REG_PIOD_MDSR (*(__I uint32_t*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
- #define REG_PIOD_PUDR (*(__O uint32_t*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
- #define REG_PIOD_PUER (*(__O uint32_t*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
- #define REG_PIOD_PUSR (*(__I uint32_t*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
- #define REG_PIOD_ABCDSR (*(__IO uint32_t*)0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */
- #define REG_PIOD_IFSCDR (*(__O uint32_t*)0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */
- #define REG_PIOD_IFSCER (*(__O uint32_t*)0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */
- #define REG_PIOD_IFSCSR (*(__I uint32_t*)0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */
- #define REG_PIOD_SCDR (*(__IO uint32_t*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
- #define REG_PIOD_PPDDR (*(__O uint32_t*)0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */
- #define REG_PIOD_PPDER (*(__O uint32_t*)0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */
- #define REG_PIOD_PPDSR (*(__I uint32_t*)0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */
- #define REG_PIOD_OWER (*(__O uint32_t*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
- #define REG_PIOD_OWDR (*(__O uint32_t*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
- #define REG_PIOD_OWSR (*(__I uint32_t*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
- #define REG_PIOD_AIMER (*(__O uint32_t*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
- #define REG_PIOD_AIMDR (*(__O uint32_t*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disable Register */
- #define REG_PIOD_AIMMR (*(__I uint32_t*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
- #define REG_PIOD_ESR (*(__O uint32_t*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
- #define REG_PIOD_LSR (*(__O uint32_t*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */
- #define REG_PIOD_ELSR (*(__I uint32_t*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
- #define REG_PIOD_FELLSR (*(__O uint32_t*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low-Level Select Register */
- #define REG_PIOD_REHLSR (*(__O uint32_t*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/High-Level Select Register */
- #define REG_PIOD_FRLHSR (*(__I uint32_t*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
- #define REG_PIOD_LOCKSR (*(__I uint32_t*)0x400E14E0U) /**< \brief (PIOD) Lock Status */
- #define REG_PIOD_WPMR (*(__IO uint32_t*)0x400E14E4U) /**< \brief (PIOD) Write Protection Mode Register */
- #define REG_PIOD_WPSR (*(__I uint32_t*)0x400E14E8U) /**< \brief (PIOD) Write Protection Status Register */
- #define REG_PIOD_SCHMITT (*(__IO uint32_t*)0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */
- #define REG_PIOD_DRIVER (*(__IO uint32_t*)0x400E1518U) /**< \brief (PIOD) PIO I/O Drive Register */
- #define REG_PIOD_KER (*(__IO uint32_t*)0x400E1520U) /**< \brief (PIOD) Keypad Controller Enable Register */
- #define REG_PIOD_KRCR (*(__IO uint32_t*)0x400E1524U) /**< \brief (PIOD) Keypad Controller Row Column Register */
- #define REG_PIOD_KDR (*(__IO uint32_t*)0x400E1528U) /**< \brief (PIOD) Keypad Controller Debouncing Register */
- #define REG_PIOD_KIER (*(__O uint32_t*)0x400E1530U) /**< \brief (PIOD) Keypad Controller Interrupt Enable Register */
- #define REG_PIOD_KIDR (*(__O uint32_t*)0x400E1534U) /**< \brief (PIOD) Keypad Controller Interrupt Disable Register */
- #define REG_PIOD_KIMR (*(__I uint32_t*)0x400E1538U) /**< \brief (PIOD) Keypad Controller Interrupt Mask Register */
- #define REG_PIOD_KSR (*(__I uint32_t*)0x400E153CU) /**< \brief (PIOD) Keypad Controller Status Register */
- #define REG_PIOD_KKPR (*(__I uint32_t*)0x400E1540U) /**< \brief (PIOD) Keypad Controller Key Press Register */
- #define REG_PIOD_KKRR (*(__I uint32_t*)0x400E1544U) /**< \brief (PIOD) Keypad Controller Key Release Register */
- #define REG_PIOD_PCMR (*(__IO uint32_t*)0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */
- #define REG_PIOD_PCIER (*(__O uint32_t*)0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */
- #define REG_PIOD_PCIDR (*(__O uint32_t*)0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */
- #define REG_PIOD_PCIMR (*(__I uint32_t*)0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */
- #define REG_PIOD_PCISR (*(__I uint32_t*)0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */
- #define REG_PIOD_PCRHR (*(__I uint32_t*)0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PIOD_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pioe.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pioe.h
deleted file mode 100644
index 4f44c5d..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pioe.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PIOE_INSTANCE_
-#define _SAMS70_PIOE_INSTANCE_
-
-/* ========== Register definition for PIOE peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PIOE_PER (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
- #define REG_PIOE_PDR (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
- #define REG_PIOE_PSR (0x400E1608U) /**< \brief (PIOE) PIO Status Register */
- #define REG_PIOE_OER (0x400E1610U) /**< \brief (PIOE) Output Enable Register */
- #define REG_PIOE_ODR (0x400E1614U) /**< \brief (PIOE) Output Disable Register */
- #define REG_PIOE_OSR (0x400E1618U) /**< \brief (PIOE) Output Status Register */
- #define REG_PIOE_IFER (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
- #define REG_PIOE_IFDR (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
- #define REG_PIOE_IFSR (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
- #define REG_PIOE_SODR (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
- #define REG_PIOE_CODR (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
- #define REG_PIOE_ODSR (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
- #define REG_PIOE_PDSR (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
- #define REG_PIOE_IER (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
- #define REG_PIOE_IDR (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
- #define REG_PIOE_IMR (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
- #define REG_PIOE_ISR (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
- #define REG_PIOE_MDER (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
- #define REG_PIOE_MDDR (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
- #define REG_PIOE_MDSR (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
- #define REG_PIOE_PUDR (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
- #define REG_PIOE_PUER (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
- #define REG_PIOE_PUSR (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
- #define REG_PIOE_ABCDSR (0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */
- #define REG_PIOE_IFSCDR (0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */
- #define REG_PIOE_IFSCER (0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */
- #define REG_PIOE_IFSCSR (0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */
- #define REG_PIOE_SCDR (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
- #define REG_PIOE_PPDDR (0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */
- #define REG_PIOE_PPDER (0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */
- #define REG_PIOE_PPDSR (0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */
- #define REG_PIOE_OWER (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
- #define REG_PIOE_OWDR (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
- #define REG_PIOE_OWSR (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
- #define REG_PIOE_AIMER (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
- #define REG_PIOE_AIMDR (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */
- #define REG_PIOE_AIMMR (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
- #define REG_PIOE_ESR (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
- #define REG_PIOE_LSR (0x400E16C4U) /**< \brief (PIOE) Level Select Register */
- #define REG_PIOE_ELSR (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
- #define REG_PIOE_FELLSR (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */
- #define REG_PIOE_REHLSR (0x400E16D4U) /**< \brief (PIOE) Rising Edge/High-Level Select Register */
- #define REG_PIOE_FRLHSR (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
- #define REG_PIOE_LOCKSR (0x400E16E0U) /**< \brief (PIOE) Lock Status */
- #define REG_PIOE_WPMR (0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */
- #define REG_PIOE_WPSR (0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */
- #define REG_PIOE_SCHMITT (0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */
- #define REG_PIOE_DRIVER (0x400E1718U) /**< \brief (PIOE) PIO I/O Drive Register */
- #define REG_PIOE_KER (0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */
- #define REG_PIOE_KRCR (0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */
- #define REG_PIOE_KDR (0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */
- #define REG_PIOE_KIER (0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */
- #define REG_PIOE_KIDR (0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */
- #define REG_PIOE_KIMR (0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */
- #define REG_PIOE_KSR (0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */
- #define REG_PIOE_KKPR (0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */
- #define REG_PIOE_KKRR (0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */
- #define REG_PIOE_PCMR (0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */
- #define REG_PIOE_PCIER (0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */
- #define REG_PIOE_PCIDR (0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */
- #define REG_PIOE_PCIMR (0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */
- #define REG_PIOE_PCISR (0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */
- #define REG_PIOE_PCRHR (0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */
-#else
- #define REG_PIOE_PER (*(__O uint32_t*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
- #define REG_PIOE_PDR (*(__O uint32_t*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
- #define REG_PIOE_PSR (*(__I uint32_t*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */
- #define REG_PIOE_OER (*(__O uint32_t*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */
- #define REG_PIOE_ODR (*(__O uint32_t*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */
- #define REG_PIOE_OSR (*(__I uint32_t*)0x400E1618U) /**< \brief (PIOE) Output Status Register */
- #define REG_PIOE_IFER (*(__O uint32_t*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
- #define REG_PIOE_IFDR (*(__O uint32_t*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
- #define REG_PIOE_IFSR (*(__I uint32_t*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
- #define REG_PIOE_SODR (*(__O uint32_t*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
- #define REG_PIOE_CODR (*(__O uint32_t*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
- #define REG_PIOE_ODSR (*(__IO uint32_t*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
- #define REG_PIOE_PDSR (*(__I uint32_t*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
- #define REG_PIOE_IER (*(__O uint32_t*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
- #define REG_PIOE_IDR (*(__O uint32_t*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
- #define REG_PIOE_IMR (*(__I uint32_t*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
- #define REG_PIOE_ISR (*(__I uint32_t*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
- #define REG_PIOE_MDER (*(__O uint32_t*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
- #define REG_PIOE_MDDR (*(__O uint32_t*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
- #define REG_PIOE_MDSR (*(__I uint32_t*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
- #define REG_PIOE_PUDR (*(__O uint32_t*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
- #define REG_PIOE_PUER (*(__O uint32_t*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
- #define REG_PIOE_PUSR (*(__I uint32_t*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
- #define REG_PIOE_ABCDSR (*(__IO uint32_t*)0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */
- #define REG_PIOE_IFSCDR (*(__O uint32_t*)0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */
- #define REG_PIOE_IFSCER (*(__O uint32_t*)0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */
- #define REG_PIOE_IFSCSR (*(__I uint32_t*)0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */
- #define REG_PIOE_SCDR (*(__IO uint32_t*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
- #define REG_PIOE_PPDDR (*(__O uint32_t*)0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */
- #define REG_PIOE_PPDER (*(__O uint32_t*)0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */
- #define REG_PIOE_PPDSR (*(__I uint32_t*)0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */
- #define REG_PIOE_OWER (*(__O uint32_t*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
- #define REG_PIOE_OWDR (*(__O uint32_t*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
- #define REG_PIOE_OWSR (*(__I uint32_t*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
- #define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
- #define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */
- #define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
- #define REG_PIOE_ESR (*(__O uint32_t*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
- #define REG_PIOE_LSR (*(__O uint32_t*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */
- #define REG_PIOE_ELSR (*(__I uint32_t*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
- #define REG_PIOE_FELLSR (*(__O uint32_t*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */
- #define REG_PIOE_REHLSR (*(__O uint32_t*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/High-Level Select Register */
- #define REG_PIOE_FRLHSR (*(__I uint32_t*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
- #define REG_PIOE_LOCKSR (*(__I uint32_t*)0x400E16E0U) /**< \brief (PIOE) Lock Status */
- #define REG_PIOE_WPMR (*(__IO uint32_t*)0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */
- #define REG_PIOE_WPSR (*(__I uint32_t*)0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */
- #define REG_PIOE_SCHMITT (*(__IO uint32_t*)0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */
- #define REG_PIOE_DRIVER (*(__IO uint32_t*)0x400E1718U) /**< \brief (PIOE) PIO I/O Drive Register */
- #define REG_PIOE_KER (*(__IO uint32_t*)0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */
- #define REG_PIOE_KRCR (*(__IO uint32_t*)0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */
- #define REG_PIOE_KDR (*(__IO uint32_t*)0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */
- #define REG_PIOE_KIER (*(__O uint32_t*)0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */
- #define REG_PIOE_KIDR (*(__O uint32_t*)0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */
- #define REG_PIOE_KIMR (*(__I uint32_t*)0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */
- #define REG_PIOE_KSR (*(__I uint32_t*)0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */
- #define REG_PIOE_KKPR (*(__I uint32_t*)0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */
- #define REG_PIOE_KKRR (*(__I uint32_t*)0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */
- #define REG_PIOE_PCMR (*(__IO uint32_t*)0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */
- #define REG_PIOE_PCIER (*(__O uint32_t*)0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */
- #define REG_PIOE_PCIDR (*(__O uint32_t*)0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */
- #define REG_PIOE_PCIMR (*(__I uint32_t*)0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */
- #define REG_PIOE_PCISR (*(__I uint32_t*)0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */
- #define REG_PIOE_PCRHR (*(__I uint32_t*)0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PIOE_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pmc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pmc.h
deleted file mode 100644
index 2a2ade3..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pmc.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PMC_INSTANCE_
-#define _SAMS70_PMC_INSTANCE_
-
-/* ========== Register definition for PMC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PMC_SCER (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */
- #define REG_PMC_SCDR (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */
- #define REG_PMC_SCSR (0x400E0608U) /**< \brief (PMC) System Clock Status Register */
- #define REG_PMC_PCER0 (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
- #define REG_PMC_PCDR0 (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
- #define REG_PMC_PCSR0 (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
- #define REG_CKGR_UCKR (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */
- #define REG_CKGR_MOR (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */
- #define REG_CKGR_MCFR (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */
- #define REG_CKGR_PLLAR (0x400E0628U) /**< \brief (PMC) PLLA Register */
- #define REG_PMC_MCKR (0x400E0630U) /**< \brief (PMC) Master Clock Register */
- #define REG_PMC_USB (0x400E0638U) /**< \brief (PMC) USB Clock Register */
- #define REG_PMC_PCK (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */
- #define REG_PMC_IER (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */
- #define REG_PMC_IDR (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */
- #define REG_PMC_SR (0x400E0668U) /**< \brief (PMC) Status Register */
- #define REG_PMC_IMR (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */
- #define REG_PMC_FSMR (0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */
- #define REG_PMC_FSPR (0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */
- #define REG_PMC_FOCR (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */
- #define REG_PMC_WPMR (0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */
- #define REG_PMC_WPSR (0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */
- #define REG_PMC_PCER1 (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
- #define REG_PMC_PCDR1 (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
- #define REG_PMC_PCSR1 (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
- #define REG_PMC_PCR (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */
- #define REG_PMC_OCR (0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */
- #define REG_PMC_SLPWK_ER0 (0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */
- #define REG_PMC_SLPWK_DR0 (0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */
- #define REG_PMC_SLPWK_SR0 (0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */
- #define REG_PMC_SLPWK_ASR0 (0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */
- #define REG_PMC_SLPWK_ER1 (0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */
- #define REG_PMC_SLPWK_DR1 (0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */
- #define REG_PMC_SLPWK_SR1 (0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */
- #define REG_PMC_SLPWK_ASR1 (0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */
- #define REG_PMC_SLPWK_AIPR (0x400E0744U) /**< \brief (PMC) SleepWalking Activity In Progress Register */
-#else
- #define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */
- #define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */
- #define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */
- #define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
- #define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
- #define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
- #define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */
- #define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */
- #define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */
- #define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U) /**< \brief (PMC) PLLA Register */
- #define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U) /**< \brief (PMC) Master Clock Register */
- #define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U) /**< \brief (PMC) USB Clock Register */
- #define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */
- #define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */
- #define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */
- #define REG_PMC_SR (*(__I uint32_t*)0x400E0668U) /**< \brief (PMC) Status Register */
- #define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */
- #define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */
- #define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */
- #define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */
- #define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */
- #define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */
- #define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
- #define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
- #define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
- #define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */
- #define REG_PMC_OCR (*(__IO uint32_t*)0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */
- #define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */
- #define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */
- #define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */
- #define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */
- #define REG_PMC_SLPWK_ER1 (*(__O uint32_t*)0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */
- #define REG_PMC_SLPWK_DR1 (*(__O uint32_t*)0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */
- #define REG_PMC_SLPWK_SR1 (*(__I uint32_t*)0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */
- #define REG_PMC_SLPWK_ASR1 (*(__I uint32_t*)0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */
- #define REG_PMC_SLPWK_AIPR (*(__I uint32_t*)0x400E0744U) /**< \brief (PMC) SleepWalking Activity In Progress Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PMC_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pwm0.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pwm0.h
deleted file mode 100644
index 908e462..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pwm0.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PWM0_INSTANCE_
-#define _SAMS70_PWM0_INSTANCE_
-
-/* ========== Register definition for PWM0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PWM0_CLK (0x40020000U) /**< \brief (PWM0) PWM Clock Register */
- #define REG_PWM0_ENA (0x40020004U) /**< \brief (PWM0) PWM Enable Register */
- #define REG_PWM0_DIS (0x40020008U) /**< \brief (PWM0) PWM Disable Register */
- #define REG_PWM0_SR (0x4002000CU) /**< \brief (PWM0) PWM Status Register */
- #define REG_PWM0_IER1 (0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */
- #define REG_PWM0_IDR1 (0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */
- #define REG_PWM0_IMR1 (0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */
- #define REG_PWM0_ISR1 (0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */
- #define REG_PWM0_SCM (0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */
- #define REG_PWM0_DMAR (0x40020024U) /**< \brief (PWM0) PWM DMA Register */
- #define REG_PWM0_SCUC (0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */
- #define REG_PWM0_SCUP (0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */
- #define REG_PWM0_SCUPUPD (0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */
- #define REG_PWM0_IER2 (0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */
- #define REG_PWM0_IDR2 (0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */
- #define REG_PWM0_IMR2 (0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */
- #define REG_PWM0_ISR2 (0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */
- #define REG_PWM0_OOV (0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */
- #define REG_PWM0_OS (0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */
- #define REG_PWM0_OSS (0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */
- #define REG_PWM0_OSC (0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */
- #define REG_PWM0_OSSUPD (0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */
- #define REG_PWM0_OSCUPD (0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */
- #define REG_PWM0_FMR (0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */
- #define REG_PWM0_FSR (0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */
- #define REG_PWM0_FCR (0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */
- #define REG_PWM0_FPV1 (0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */
- #define REG_PWM0_FPE (0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */
- #define REG_PWM0_ELMR (0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */
- #define REG_PWM0_SSPR (0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */
- #define REG_PWM0_SSPUP (0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */
- #define REG_PWM0_SMMR (0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */
- #define REG_PWM0_FPV2 (0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */
- #define REG_PWM0_WPCR (0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */
- #define REG_PWM0_WPSR (0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */
- #define REG_PWM0_CMPV0 (0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */
- #define REG_PWM0_CMPVUPD0 (0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */
- #define REG_PWM0_CMPM0 (0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */
- #define REG_PWM0_CMPMUPD0 (0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */
- #define REG_PWM0_CMPV1 (0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */
- #define REG_PWM0_CMPVUPD1 (0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */
- #define REG_PWM0_CMPM1 (0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */
- #define REG_PWM0_CMPMUPD1 (0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */
- #define REG_PWM0_CMPV2 (0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */
- #define REG_PWM0_CMPVUPD2 (0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */
- #define REG_PWM0_CMPM2 (0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */
- #define REG_PWM0_CMPMUPD2 (0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */
- #define REG_PWM0_CMPV3 (0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */
- #define REG_PWM0_CMPVUPD3 (0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */
- #define REG_PWM0_CMPM3 (0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */
- #define REG_PWM0_CMPMUPD3 (0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */
- #define REG_PWM0_CMPV4 (0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */
- #define REG_PWM0_CMPVUPD4 (0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */
- #define REG_PWM0_CMPM4 (0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */
- #define REG_PWM0_CMPMUPD4 (0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */
- #define REG_PWM0_CMPV5 (0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */
- #define REG_PWM0_CMPVUPD5 (0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */
- #define REG_PWM0_CMPM5 (0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */
- #define REG_PWM0_CMPMUPD5 (0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */
- #define REG_PWM0_CMPV6 (0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */
- #define REG_PWM0_CMPVUPD6 (0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */
- #define REG_PWM0_CMPM6 (0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */
- #define REG_PWM0_CMPMUPD6 (0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */
- #define REG_PWM0_CMPV7 (0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */
- #define REG_PWM0_CMPVUPD7 (0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */
- #define REG_PWM0_CMPM7 (0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */
- #define REG_PWM0_CMPMUPD7 (0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */
- #define REG_PWM0_CMR0 (0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */
- #define REG_PWM0_CDTY0 (0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */
- #define REG_PWM0_CDTYUPD0 (0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */
- #define REG_PWM0_CPRD0 (0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */
- #define REG_PWM0_CPRDUPD0 (0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */
- #define REG_PWM0_CCNT0 (0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */
- #define REG_PWM0_DT0 (0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */
- #define REG_PWM0_DTUPD0 (0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */
- #define REG_PWM0_CMR1 (0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */
- #define REG_PWM0_CDTY1 (0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */
- #define REG_PWM0_CDTYUPD1 (0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */
- #define REG_PWM0_CPRD1 (0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */
- #define REG_PWM0_CPRDUPD1 (0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */
- #define REG_PWM0_CCNT1 (0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */
- #define REG_PWM0_DT1 (0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */
- #define REG_PWM0_DTUPD1 (0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */
- #define REG_PWM0_CMR2 (0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */
- #define REG_PWM0_CDTY2 (0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */
- #define REG_PWM0_CDTYUPD2 (0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */
- #define REG_PWM0_CPRD2 (0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */
- #define REG_PWM0_CPRDUPD2 (0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */
- #define REG_PWM0_CCNT2 (0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */
- #define REG_PWM0_DT2 (0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */
- #define REG_PWM0_DTUPD2 (0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */
- #define REG_PWM0_CMR3 (0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */
- #define REG_PWM0_CDTY3 (0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */
- #define REG_PWM0_CDTYUPD3 (0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */
- #define REG_PWM0_CPRD3 (0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */
- #define REG_PWM0_CPRDUPD3 (0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */
- #define REG_PWM0_CCNT3 (0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */
- #define REG_PWM0_DT3 (0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */
- #define REG_PWM0_DTUPD3 (0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */
- #define REG_PWM0_CMUPD0 (0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */
- #define REG_PWM0_CMUPD1 (0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */
- #define REG_PWM0_ETRG1 (0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */
- #define REG_PWM0_LEBR1 (0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */
- #define REG_PWM0_CMUPD2 (0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */
- #define REG_PWM0_ETRG2 (0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */
- #define REG_PWM0_LEBR2 (0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */
- #define REG_PWM0_CMUPD3 (0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */
- #define REG_PWM0_ETRG3 (0x4002046CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 3) */
- #define REG_PWM0_LEBR3 (0x40020470U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 3) */
- #define REG_PWM0_ETRG4 (0x4002048CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 4) */
- #define REG_PWM0_LEBR4 (0x40020490U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 4) */
-#else
- #define REG_PWM0_CLK (*(__IO uint32_t*)0x40020000U) /**< \brief (PWM0) PWM Clock Register */
- #define REG_PWM0_ENA (*(__O uint32_t*)0x40020004U) /**< \brief (PWM0) PWM Enable Register */
- #define REG_PWM0_DIS (*(__O uint32_t*)0x40020008U) /**< \brief (PWM0) PWM Disable Register */
- #define REG_PWM0_SR (*(__I uint32_t*)0x4002000CU) /**< \brief (PWM0) PWM Status Register */
- #define REG_PWM0_IER1 (*(__O uint32_t*)0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */
- #define REG_PWM0_IDR1 (*(__O uint32_t*)0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */
- #define REG_PWM0_IMR1 (*(__I uint32_t*)0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */
- #define REG_PWM0_ISR1 (*(__I uint32_t*)0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */
- #define REG_PWM0_SCM (*(__IO uint32_t*)0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */
- #define REG_PWM0_DMAR (*(__O uint32_t*)0x40020024U) /**< \brief (PWM0) PWM DMA Register */
- #define REG_PWM0_SCUC (*(__IO uint32_t*)0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */
- #define REG_PWM0_SCUP (*(__IO uint32_t*)0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */
- #define REG_PWM0_SCUPUPD (*(__O uint32_t*)0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */
- #define REG_PWM0_IER2 (*(__O uint32_t*)0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */
- #define REG_PWM0_IDR2 (*(__O uint32_t*)0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */
- #define REG_PWM0_IMR2 (*(__I uint32_t*)0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */
- #define REG_PWM0_ISR2 (*(__I uint32_t*)0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */
- #define REG_PWM0_OOV (*(__IO uint32_t*)0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */
- #define REG_PWM0_OS (*(__IO uint32_t*)0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */
- #define REG_PWM0_OSS (*(__O uint32_t*)0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */
- #define REG_PWM0_OSC (*(__O uint32_t*)0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */
- #define REG_PWM0_OSSUPD (*(__O uint32_t*)0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */
- #define REG_PWM0_OSCUPD (*(__O uint32_t*)0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */
- #define REG_PWM0_FMR (*(__IO uint32_t*)0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */
- #define REG_PWM0_FSR (*(__I uint32_t*)0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */
- #define REG_PWM0_FCR (*(__O uint32_t*)0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */
- #define REG_PWM0_FPV1 (*(__IO uint32_t*)0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */
- #define REG_PWM0_FPE (*(__IO uint32_t*)0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */
- #define REG_PWM0_ELMR (*(__IO uint32_t*)0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */
- #define REG_PWM0_SSPR (*(__IO uint32_t*)0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */
- #define REG_PWM0_SSPUP (*(__O uint32_t*)0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */
- #define REG_PWM0_SMMR (*(__IO uint32_t*)0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */
- #define REG_PWM0_FPV2 (*(__IO uint32_t*)0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */
- #define REG_PWM0_WPCR (*(__O uint32_t*)0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */
- #define REG_PWM0_WPSR (*(__I uint32_t*)0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */
- #define REG_PWM0_CMPV0 (*(__IO uint32_t*)0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */
- #define REG_PWM0_CMPVUPD0 (*(__O uint32_t*)0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */
- #define REG_PWM0_CMPM0 (*(__IO uint32_t*)0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */
- #define REG_PWM0_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */
- #define REG_PWM0_CMPV1 (*(__IO uint32_t*)0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */
- #define REG_PWM0_CMPVUPD1 (*(__O uint32_t*)0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */
- #define REG_PWM0_CMPM1 (*(__IO uint32_t*)0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */
- #define REG_PWM0_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */
- #define REG_PWM0_CMPV2 (*(__IO uint32_t*)0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */
- #define REG_PWM0_CMPVUPD2 (*(__O uint32_t*)0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */
- #define REG_PWM0_CMPM2 (*(__IO uint32_t*)0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */
- #define REG_PWM0_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */
- #define REG_PWM0_CMPV3 (*(__IO uint32_t*)0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */
- #define REG_PWM0_CMPVUPD3 (*(__O uint32_t*)0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */
- #define REG_PWM0_CMPM3 (*(__IO uint32_t*)0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */
- #define REG_PWM0_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */
- #define REG_PWM0_CMPV4 (*(__IO uint32_t*)0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */
- #define REG_PWM0_CMPVUPD4 (*(__O uint32_t*)0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */
- #define REG_PWM0_CMPM4 (*(__IO uint32_t*)0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */
- #define REG_PWM0_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */
- #define REG_PWM0_CMPV5 (*(__IO uint32_t*)0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */
- #define REG_PWM0_CMPVUPD5 (*(__O uint32_t*)0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */
- #define REG_PWM0_CMPM5 (*(__IO uint32_t*)0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */
- #define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */
- #define REG_PWM0_CMPV6 (*(__IO uint32_t*)0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */
- #define REG_PWM0_CMPVUPD6 (*(__O uint32_t*)0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */
- #define REG_PWM0_CMPM6 (*(__IO uint32_t*)0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */
- #define REG_PWM0_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */
- #define REG_PWM0_CMPV7 (*(__IO uint32_t*)0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */
- #define REG_PWM0_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */
- #define REG_PWM0_CMPM7 (*(__IO uint32_t*)0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */
- #define REG_PWM0_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */
- #define REG_PWM0_CMR0 (*(__IO uint32_t*)0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */
- #define REG_PWM0_CDTY0 (*(__IO uint32_t*)0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */
- #define REG_PWM0_CDTYUPD0 (*(__O uint32_t*)0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */
- #define REG_PWM0_CPRD0 (*(__IO uint32_t*)0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */
- #define REG_PWM0_CPRDUPD0 (*(__O uint32_t*)0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */
- #define REG_PWM0_CCNT0 (*(__I uint32_t*)0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */
- #define REG_PWM0_DT0 (*(__IO uint32_t*)0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */
- #define REG_PWM0_DTUPD0 (*(__O uint32_t*)0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */
- #define REG_PWM0_CMR1 (*(__IO uint32_t*)0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */
- #define REG_PWM0_CDTY1 (*(__IO uint32_t*)0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */
- #define REG_PWM0_CDTYUPD1 (*(__O uint32_t*)0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */
- #define REG_PWM0_CPRD1 (*(__IO uint32_t*)0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */
- #define REG_PWM0_CPRDUPD1 (*(__O uint32_t*)0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */
- #define REG_PWM0_CCNT1 (*(__I uint32_t*)0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */
- #define REG_PWM0_DT1 (*(__IO uint32_t*)0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */
- #define REG_PWM0_DTUPD1 (*(__O uint32_t*)0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */
- #define REG_PWM0_CMR2 (*(__IO uint32_t*)0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */
- #define REG_PWM0_CDTY2 (*(__IO uint32_t*)0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */
- #define REG_PWM0_CDTYUPD2 (*(__O uint32_t*)0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */
- #define REG_PWM0_CPRD2 (*(__IO uint32_t*)0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */
- #define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */
- #define REG_PWM0_CCNT2 (*(__I uint32_t*)0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */
- #define REG_PWM0_DT2 (*(__IO uint32_t*)0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */
- #define REG_PWM0_DTUPD2 (*(__O uint32_t*)0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */
- #define REG_PWM0_CMR3 (*(__IO uint32_t*)0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */
- #define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */
- #define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */
- #define REG_PWM0_CPRD3 (*(__IO uint32_t*)0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */
- #define REG_PWM0_CPRDUPD3 (*(__O uint32_t*)0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */
- #define REG_PWM0_CCNT3 (*(__I uint32_t*)0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */
- #define REG_PWM0_DT3 (*(__IO uint32_t*)0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */
- #define REG_PWM0_DTUPD3 (*(__O uint32_t*)0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */
- #define REG_PWM0_CMUPD0 (*(__O uint32_t*)0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */
- #define REG_PWM0_CMUPD1 (*(__O uint32_t*)0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */
- #define REG_PWM0_ETRG1 (*(__IO uint32_t*)0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */
- #define REG_PWM0_LEBR1 (*(__IO uint32_t*)0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */
- #define REG_PWM0_CMUPD2 (*(__O uint32_t*)0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */
- #define REG_PWM0_ETRG2 (*(__IO uint32_t*)0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */
- #define REG_PWM0_LEBR2 (*(__IO uint32_t*)0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */
- #define REG_PWM0_CMUPD3 (*(__O uint32_t*)0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */
- #define REG_PWM0_ETRG3 (*(__IO uint32_t*)0x4002046CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 3) */
- #define REG_PWM0_LEBR3 (*(__IO uint32_t*)0x40020470U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 3) */
- #define REG_PWM0_ETRG4 (*(__IO uint32_t*)0x4002048CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 4) */
- #define REG_PWM0_LEBR4 (*(__IO uint32_t*)0x40020490U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 4) */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PWM0_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pwm1.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pwm1.h
deleted file mode 100644
index 0f4dcf7..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/pwm1.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_PWM1_INSTANCE_
-#define _SAMS70_PWM1_INSTANCE_
-
-/* ========== Register definition for PWM1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_PWM1_CLK (0x4005C000U) /**< \brief (PWM1) PWM Clock Register */
- #define REG_PWM1_ENA (0x4005C004U) /**< \brief (PWM1) PWM Enable Register */
- #define REG_PWM1_DIS (0x4005C008U) /**< \brief (PWM1) PWM Disable Register */
- #define REG_PWM1_SR (0x4005C00CU) /**< \brief (PWM1) PWM Status Register */
- #define REG_PWM1_IER1 (0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */
- #define REG_PWM1_IDR1 (0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */
- #define REG_PWM1_IMR1 (0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */
- #define REG_PWM1_ISR1 (0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */
- #define REG_PWM1_SCM (0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */
- #define REG_PWM1_DMAR (0x4005C024U) /**< \brief (PWM1) PWM DMA Register */
- #define REG_PWM1_SCUC (0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */
- #define REG_PWM1_SCUP (0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */
- #define REG_PWM1_SCUPUPD (0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */
- #define REG_PWM1_IER2 (0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */
- #define REG_PWM1_IDR2 (0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */
- #define REG_PWM1_IMR2 (0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */
- #define REG_PWM1_ISR2 (0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */
- #define REG_PWM1_OOV (0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */
- #define REG_PWM1_OS (0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */
- #define REG_PWM1_OSS (0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */
- #define REG_PWM1_OSC (0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */
- #define REG_PWM1_OSSUPD (0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */
- #define REG_PWM1_OSCUPD (0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */
- #define REG_PWM1_FMR (0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */
- #define REG_PWM1_FSR (0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */
- #define REG_PWM1_FCR (0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */
- #define REG_PWM1_FPV1 (0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */
- #define REG_PWM1_FPE (0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */
- #define REG_PWM1_ELMR (0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */
- #define REG_PWM1_SSPR (0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */
- #define REG_PWM1_SSPUP (0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */
- #define REG_PWM1_SMMR (0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */
- #define REG_PWM1_FPV2 (0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */
- #define REG_PWM1_WPCR (0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */
- #define REG_PWM1_WPSR (0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */
- #define REG_PWM1_CMPV0 (0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */
- #define REG_PWM1_CMPVUPD0 (0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */
- #define REG_PWM1_CMPM0 (0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */
- #define REG_PWM1_CMPMUPD0 (0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */
- #define REG_PWM1_CMPV1 (0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */
- #define REG_PWM1_CMPVUPD1 (0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */
- #define REG_PWM1_CMPM1 (0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */
- #define REG_PWM1_CMPMUPD1 (0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */
- #define REG_PWM1_CMPV2 (0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */
- #define REG_PWM1_CMPVUPD2 (0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */
- #define REG_PWM1_CMPM2 (0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */
- #define REG_PWM1_CMPMUPD2 (0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */
- #define REG_PWM1_CMPV3 (0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */
- #define REG_PWM1_CMPVUPD3 (0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */
- #define REG_PWM1_CMPM3 (0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */
- #define REG_PWM1_CMPMUPD3 (0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */
- #define REG_PWM1_CMPV4 (0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */
- #define REG_PWM1_CMPVUPD4 (0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */
- #define REG_PWM1_CMPM4 (0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */
- #define REG_PWM1_CMPMUPD4 (0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */
- #define REG_PWM1_CMPV5 (0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */
- #define REG_PWM1_CMPVUPD5 (0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */
- #define REG_PWM1_CMPM5 (0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */
- #define REG_PWM1_CMPMUPD5 (0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */
- #define REG_PWM1_CMPV6 (0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */
- #define REG_PWM1_CMPVUPD6 (0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */
- #define REG_PWM1_CMPM6 (0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */
- #define REG_PWM1_CMPMUPD6 (0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */
- #define REG_PWM1_CMPV7 (0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */
- #define REG_PWM1_CMPVUPD7 (0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */
- #define REG_PWM1_CMPM7 (0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */
- #define REG_PWM1_CMPMUPD7 (0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */
- #define REG_PWM1_CMR0 (0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */
- #define REG_PWM1_CDTY0 (0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */
- #define REG_PWM1_CDTYUPD0 (0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */
- #define REG_PWM1_CPRD0 (0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */
- #define REG_PWM1_CPRDUPD0 (0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */
- #define REG_PWM1_CCNT0 (0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */
- #define REG_PWM1_DT0 (0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */
- #define REG_PWM1_DTUPD0 (0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */
- #define REG_PWM1_CMR1 (0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */
- #define REG_PWM1_CDTY1 (0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */
- #define REG_PWM1_CDTYUPD1 (0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */
- #define REG_PWM1_CPRD1 (0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */
- #define REG_PWM1_CPRDUPD1 (0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */
- #define REG_PWM1_CCNT1 (0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */
- #define REG_PWM1_DT1 (0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */
- #define REG_PWM1_DTUPD1 (0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */
- #define REG_PWM1_CMR2 (0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */
- #define REG_PWM1_CDTY2 (0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */
- #define REG_PWM1_CDTYUPD2 (0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */
- #define REG_PWM1_CPRD2 (0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */
- #define REG_PWM1_CPRDUPD2 (0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */
- #define REG_PWM1_CCNT2 (0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */
- #define REG_PWM1_DT2 (0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */
- #define REG_PWM1_DTUPD2 (0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */
- #define REG_PWM1_CMR3 (0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */
- #define REG_PWM1_CDTY3 (0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */
- #define REG_PWM1_CDTYUPD3 (0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */
- #define REG_PWM1_CPRD3 (0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */
- #define REG_PWM1_CPRDUPD3 (0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */
- #define REG_PWM1_CCNT3 (0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */
- #define REG_PWM1_DT3 (0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */
- #define REG_PWM1_DTUPD3 (0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */
- #define REG_PWM1_CMUPD0 (0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */
- #define REG_PWM1_CMUPD1 (0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */
- #define REG_PWM1_ETRG1 (0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */
- #define REG_PWM1_LEBR1 (0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */
- #define REG_PWM1_CMUPD2 (0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */
- #define REG_PWM1_ETRG2 (0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */
- #define REG_PWM1_LEBR2 (0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */
- #define REG_PWM1_CMUPD3 (0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */
- #define REG_PWM1_ETRG3 (0x4005C46CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 3) */
- #define REG_PWM1_LEBR3 (0x4005C470U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 3) */
- #define REG_PWM1_ETRG4 (0x4005C48CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 4) */
- #define REG_PWM1_LEBR4 (0x4005C490U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 4) */
-#else
- #define REG_PWM1_CLK (*(__IO uint32_t*)0x4005C000U) /**< \brief (PWM1) PWM Clock Register */
- #define REG_PWM1_ENA (*(__O uint32_t*)0x4005C004U) /**< \brief (PWM1) PWM Enable Register */
- #define REG_PWM1_DIS (*(__O uint32_t*)0x4005C008U) /**< \brief (PWM1) PWM Disable Register */
- #define REG_PWM1_SR (*(__I uint32_t*)0x4005C00CU) /**< \brief (PWM1) PWM Status Register */
- #define REG_PWM1_IER1 (*(__O uint32_t*)0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */
- #define REG_PWM1_IDR1 (*(__O uint32_t*)0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */
- #define REG_PWM1_IMR1 (*(__I uint32_t*)0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */
- #define REG_PWM1_ISR1 (*(__I uint32_t*)0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */
- #define REG_PWM1_SCM (*(__IO uint32_t*)0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */
- #define REG_PWM1_DMAR (*(__O uint32_t*)0x4005C024U) /**< \brief (PWM1) PWM DMA Register */
- #define REG_PWM1_SCUC (*(__IO uint32_t*)0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */
- #define REG_PWM1_SCUP (*(__IO uint32_t*)0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */
- #define REG_PWM1_SCUPUPD (*(__O uint32_t*)0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */
- #define REG_PWM1_IER2 (*(__O uint32_t*)0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */
- #define REG_PWM1_IDR2 (*(__O uint32_t*)0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */
- #define REG_PWM1_IMR2 (*(__I uint32_t*)0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */
- #define REG_PWM1_ISR2 (*(__I uint32_t*)0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */
- #define REG_PWM1_OOV (*(__IO uint32_t*)0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */
- #define REG_PWM1_OS (*(__IO uint32_t*)0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */
- #define REG_PWM1_OSS (*(__O uint32_t*)0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */
- #define REG_PWM1_OSC (*(__O uint32_t*)0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */
- #define REG_PWM1_OSSUPD (*(__O uint32_t*)0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */
- #define REG_PWM1_OSCUPD (*(__O uint32_t*)0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */
- #define REG_PWM1_FMR (*(__IO uint32_t*)0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */
- #define REG_PWM1_FSR (*(__I uint32_t*)0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */
- #define REG_PWM1_FCR (*(__O uint32_t*)0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */
- #define REG_PWM1_FPV1 (*(__IO uint32_t*)0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */
- #define REG_PWM1_FPE (*(__IO uint32_t*)0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */
- #define REG_PWM1_ELMR (*(__IO uint32_t*)0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */
- #define REG_PWM1_SSPR (*(__IO uint32_t*)0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */
- #define REG_PWM1_SSPUP (*(__O uint32_t*)0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */
- #define REG_PWM1_SMMR (*(__IO uint32_t*)0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */
- #define REG_PWM1_FPV2 (*(__IO uint32_t*)0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */
- #define REG_PWM1_WPCR (*(__O uint32_t*)0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */
- #define REG_PWM1_WPSR (*(__I uint32_t*)0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */
- #define REG_PWM1_CMPV0 (*(__IO uint32_t*)0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */
- #define REG_PWM1_CMPVUPD0 (*(__O uint32_t*)0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */
- #define REG_PWM1_CMPM0 (*(__IO uint32_t*)0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */
- #define REG_PWM1_CMPMUPD0 (*(__O uint32_t*)0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */
- #define REG_PWM1_CMPV1 (*(__IO uint32_t*)0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */
- #define REG_PWM1_CMPVUPD1 (*(__O uint32_t*)0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */
- #define REG_PWM1_CMPM1 (*(__IO uint32_t*)0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */
- #define REG_PWM1_CMPMUPD1 (*(__O uint32_t*)0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */
- #define REG_PWM1_CMPV2 (*(__IO uint32_t*)0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */
- #define REG_PWM1_CMPVUPD2 (*(__O uint32_t*)0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */
- #define REG_PWM1_CMPM2 (*(__IO uint32_t*)0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */
- #define REG_PWM1_CMPMUPD2 (*(__O uint32_t*)0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */
- #define REG_PWM1_CMPV3 (*(__IO uint32_t*)0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */
- #define REG_PWM1_CMPVUPD3 (*(__O uint32_t*)0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */
- #define REG_PWM1_CMPM3 (*(__IO uint32_t*)0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */
- #define REG_PWM1_CMPMUPD3 (*(__O uint32_t*)0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */
- #define REG_PWM1_CMPV4 (*(__IO uint32_t*)0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */
- #define REG_PWM1_CMPVUPD4 (*(__O uint32_t*)0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */
- #define REG_PWM1_CMPM4 (*(__IO uint32_t*)0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */
- #define REG_PWM1_CMPMUPD4 (*(__O uint32_t*)0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */
- #define REG_PWM1_CMPV5 (*(__IO uint32_t*)0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */
- #define REG_PWM1_CMPVUPD5 (*(__O uint32_t*)0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */
- #define REG_PWM1_CMPM5 (*(__IO uint32_t*)0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */
- #define REG_PWM1_CMPMUPD5 (*(__O uint32_t*)0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */
- #define REG_PWM1_CMPV6 (*(__IO uint32_t*)0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */
- #define REG_PWM1_CMPVUPD6 (*(__O uint32_t*)0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */
- #define REG_PWM1_CMPM6 (*(__IO uint32_t*)0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */
- #define REG_PWM1_CMPMUPD6 (*(__O uint32_t*)0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */
- #define REG_PWM1_CMPV7 (*(__IO uint32_t*)0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */
- #define REG_PWM1_CMPVUPD7 (*(__O uint32_t*)0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */
- #define REG_PWM1_CMPM7 (*(__IO uint32_t*)0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */
- #define REG_PWM1_CMPMUPD7 (*(__O uint32_t*)0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */
- #define REG_PWM1_CMR0 (*(__IO uint32_t*)0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */
- #define REG_PWM1_CDTY0 (*(__IO uint32_t*)0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */
- #define REG_PWM1_CDTYUPD0 (*(__O uint32_t*)0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */
- #define REG_PWM1_CPRD0 (*(__IO uint32_t*)0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */
- #define REG_PWM1_CPRDUPD0 (*(__O uint32_t*)0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */
- #define REG_PWM1_CCNT0 (*(__I uint32_t*)0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */
- #define REG_PWM1_DT0 (*(__IO uint32_t*)0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */
- #define REG_PWM1_DTUPD0 (*(__O uint32_t*)0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */
- #define REG_PWM1_CMR1 (*(__IO uint32_t*)0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */
- #define REG_PWM1_CDTY1 (*(__IO uint32_t*)0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */
- #define REG_PWM1_CDTYUPD1 (*(__O uint32_t*)0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */
- #define REG_PWM1_CPRD1 (*(__IO uint32_t*)0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */
- #define REG_PWM1_CPRDUPD1 (*(__O uint32_t*)0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */
- #define REG_PWM1_CCNT1 (*(__I uint32_t*)0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */
- #define REG_PWM1_DT1 (*(__IO uint32_t*)0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */
- #define REG_PWM1_DTUPD1 (*(__O uint32_t*)0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */
- #define REG_PWM1_CMR2 (*(__IO uint32_t*)0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */
- #define REG_PWM1_CDTY2 (*(__IO uint32_t*)0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */
- #define REG_PWM1_CDTYUPD2 (*(__O uint32_t*)0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */
- #define REG_PWM1_CPRD2 (*(__IO uint32_t*)0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */
- #define REG_PWM1_CPRDUPD2 (*(__O uint32_t*)0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */
- #define REG_PWM1_CCNT2 (*(__I uint32_t*)0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */
- #define REG_PWM1_DT2 (*(__IO uint32_t*)0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */
- #define REG_PWM1_DTUPD2 (*(__O uint32_t*)0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */
- #define REG_PWM1_CMR3 (*(__IO uint32_t*)0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */
- #define REG_PWM1_CDTY3 (*(__IO uint32_t*)0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */
- #define REG_PWM1_CDTYUPD3 (*(__O uint32_t*)0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */
- #define REG_PWM1_CPRD3 (*(__IO uint32_t*)0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */
- #define REG_PWM1_CPRDUPD3 (*(__O uint32_t*)0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */
- #define REG_PWM1_CCNT3 (*(__I uint32_t*)0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */
- #define REG_PWM1_DT3 (*(__IO uint32_t*)0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */
- #define REG_PWM1_DTUPD3 (*(__O uint32_t*)0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */
- #define REG_PWM1_CMUPD0 (*(__O uint32_t*)0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */
- #define REG_PWM1_CMUPD1 (*(__O uint32_t*)0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */
- #define REG_PWM1_ETRG1 (*(__IO uint32_t*)0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */
- #define REG_PWM1_LEBR1 (*(__IO uint32_t*)0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */
- #define REG_PWM1_CMUPD2 (*(__O uint32_t*)0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */
- #define REG_PWM1_ETRG2 (*(__IO uint32_t*)0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */
- #define REG_PWM1_LEBR2 (*(__IO uint32_t*)0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */
- #define REG_PWM1_CMUPD3 (*(__O uint32_t*)0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */
- #define REG_PWM1_ETRG3 (*(__IO uint32_t*)0x4005C46CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 3) */
- #define REG_PWM1_LEBR3 (*(__IO uint32_t*)0x4005C470U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 3) */
- #define REG_PWM1_ETRG4 (*(__IO uint32_t*)0x4005C48CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 4) */
- #define REG_PWM1_LEBR4 (*(__IO uint32_t*)0x4005C490U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 4) */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_PWM1_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/qspi.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/qspi.h
deleted file mode 100644
index 2009f77..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/qspi.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_QSPI_INSTANCE_
-#define _SAMS70_QSPI_INSTANCE_
-
-/* ========== Register definition for QSPI peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_QSPI_CR (0x4007C000U) /**< \brief (QSPI) Control Register */
- #define REG_QSPI_MR (0x4007C004U) /**< \brief (QSPI) Mode Register */
- #define REG_QSPI_RDR (0x4007C008U) /**< \brief (QSPI) Receive Data Register */
- #define REG_QSPI_TDR (0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */
- #define REG_QSPI_SR (0x4007C010U) /**< \brief (QSPI) Status Register */
- #define REG_QSPI_IER (0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */
- #define REG_QSPI_IDR (0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */
- #define REG_QSPI_IMR (0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */
- #define REG_QSPI_SCR (0x4007C020U) /**< \brief (QSPI) Serial Clock Register */
- #define REG_QSPI_IAR (0x4007C030U) /**< \brief (QSPI) Instruction Address Register */
- #define REG_QSPI_ICR (0x4007C034U) /**< \brief (QSPI) Instruction Code Register */
- #define REG_QSPI_IFR (0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */
- #define REG_QSPI_SMR (0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */
- #define REG_QSPI_SKR (0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */
- #define REG_QSPI_WPMR (0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */
- #define REG_QSPI_WPSR (0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */
-#else
- #define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< \brief (QSPI) Control Register */
- #define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U) /**< \brief (QSPI) Mode Register */
- #define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U) /**< \brief (QSPI) Receive Data Register */
- #define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */
- #define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U) /**< \brief (QSPI) Status Register */
- #define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */
- #define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */
- #define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */
- #define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U) /**< \brief (QSPI) Serial Clock Register */
- #define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U) /**< \brief (QSPI) Instruction Address Register */
- #define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U) /**< \brief (QSPI) Instruction Code Register */
- #define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */
- #define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */
- #define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */
- #define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */
- #define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_QSPI_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/rstc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/rstc.h
deleted file mode 100644
index 8278615..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/rstc.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RSTC_INSTANCE_
-#define _SAMS70_RSTC_INSTANCE_
-
-/* ========== Register definition for RSTC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_RSTC_CR (0x400E1800U) /**< \brief (RSTC) Control Register */
- #define REG_RSTC_SR (0x400E1804U) /**< \brief (RSTC) Status Register */
- #define REG_RSTC_MR (0x400E1808U) /**< \brief (RSTC) Mode Register */
-#else
- #define REG_RSTC_CR (*(__O uint32_t*)0x400E1800U) /**< \brief (RSTC) Control Register */
- #define REG_RSTC_SR (*(__I uint32_t*)0x400E1804U) /**< \brief (RSTC) Status Register */
- #define REG_RSTC_MR (*(__IO uint32_t*)0x400E1808U) /**< \brief (RSTC) Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_RSTC_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/rswdt.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/rswdt.h
deleted file mode 100644
index 903cd16..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/rswdt.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RSWDT_INSTANCE_
-#define _SAMS70_RSWDT_INSTANCE_
-
-/* ========== Register definition for RSWDT peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_RSWDT_CR (0x400E1900U) /**< \brief (RSWDT) Control Register */
- #define REG_RSWDT_MR (0x400E1904U) /**< \brief (RSWDT) Mode Register */
- #define REG_RSWDT_SR (0x400E1908U) /**< \brief (RSWDT) Status Register */
-#else
- #define REG_RSWDT_CR (*(__O uint32_t*)0x400E1900U) /**< \brief (RSWDT) Control Register */
- #define REG_RSWDT_MR (*(__IO uint32_t*)0x400E1904U) /**< \brief (RSWDT) Mode Register */
- #define REG_RSWDT_SR (*(__I uint32_t*)0x400E1908U) /**< \brief (RSWDT) Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_RSWDT_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/rtc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/rtc.h
deleted file mode 100644
index c44c036..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/rtc.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RTC_INSTANCE_
-#define _SAMS70_RTC_INSTANCE_
-
-/* ========== Register definition for RTC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_RTC_CR (0x400E1860U) /**< \brief (RTC) Control Register */
- #define REG_RTC_MR (0x400E1864U) /**< \brief (RTC) Mode Register */
- #define REG_RTC_TIMR (0x400E1868U) /**< \brief (RTC) Time Register */
- #define REG_RTC_CALR (0x400E186CU) /**< \brief (RTC) Calendar Register */
- #define REG_RTC_TIMALR (0x400E1870U) /**< \brief (RTC) Time Alarm Register */
- #define REG_RTC_CALALR (0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */
- #define REG_RTC_SR (0x400E1878U) /**< \brief (RTC) Status Register */
- #define REG_RTC_SCCR (0x400E187CU) /**< \brief (RTC) Status Clear Command Register */
- #define REG_RTC_IER (0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */
- #define REG_RTC_IDR (0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */
- #define REG_RTC_IMR (0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */
- #define REG_RTC_VER (0x400E188CU) /**< \brief (RTC) Valid Entry Register */
-#else
- #define REG_RTC_CR (*(__IO uint32_t*)0x400E1860U) /**< \brief (RTC) Control Register */
- #define REG_RTC_MR (*(__IO uint32_t*)0x400E1864U) /**< \brief (RTC) Mode Register */
- #define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1868U) /**< \brief (RTC) Time Register */
- #define REG_RTC_CALR (*(__IO uint32_t*)0x400E186CU) /**< \brief (RTC) Calendar Register */
- #define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1870U) /**< \brief (RTC) Time Alarm Register */
- #define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */
- #define REG_RTC_SR (*(__I uint32_t*)0x400E1878U) /**< \brief (RTC) Status Register */
- #define REG_RTC_SCCR (*(__O uint32_t*)0x400E187CU) /**< \brief (RTC) Status Clear Command Register */
- #define REG_RTC_IER (*(__O uint32_t*)0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */
- #define REG_RTC_IDR (*(__O uint32_t*)0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */
- #define REG_RTC_IMR (*(__I uint32_t*)0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */
- #define REG_RTC_VER (*(__I uint32_t*)0x400E188CU) /**< \brief (RTC) Valid Entry Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_RTC_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/rtt.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/rtt.h
deleted file mode 100644
index 79b313d..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/rtt.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_RTT_INSTANCE_
-#define _SAMS70_RTT_INSTANCE_
-
-/* ========== Register definition for RTT peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_RTT_MR (0x400E1830U) /**< \brief (RTT) Mode Register */
- #define REG_RTT_AR (0x400E1834U) /**< \brief (RTT) Alarm Register */
- #define REG_RTT_VR (0x400E1838U) /**< \brief (RTT) Value Register */
- #define REG_RTT_SR (0x400E183CU) /**< \brief (RTT) Status Register */
-#else
- #define REG_RTT_MR (*(__IO uint32_t*)0x400E1830U) /**< \brief (RTT) Mode Register */
- #define REG_RTT_AR (*(__IO uint32_t*)0x400E1834U) /**< \brief (RTT) Alarm Register */
- #define REG_RTT_VR (*(__I uint32_t*)0x400E1838U) /**< \brief (RTT) Value Register */
- #define REG_RTT_SR (*(__I uint32_t*)0x400E183CU) /**< \brief (RTT) Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_RTT_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/sdramc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/sdramc.h
deleted file mode 100644
index 7febe8d..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/sdramc.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SDRAMC_INSTANCE_
-#define _SAMS70_SDRAMC_INSTANCE_
-
-/* ========== Register definition for SDRAMC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_SDRAMC_MR (0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */
- #define REG_SDRAMC_TR (0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
- #define REG_SDRAMC_CR (0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
- #define REG_SDRAMC_LPR (0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
- #define REG_SDRAMC_IER (0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
- #define REG_SDRAMC_IDR (0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
- #define REG_SDRAMC_IMR (0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
- #define REG_SDRAMC_ISR (0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
- #define REG_SDRAMC_MDR (0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
- #define REG_SDRAMC_CFR1 (0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
- #define REG_SDRAMC_OCMS (0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */
- #define REG_SDRAMC_OCMS_KEY1 (0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */
- #define REG_SDRAMC_OCMS_KEY2 (0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */
-#else
- #define REG_SDRAMC_MR (*(__IO uint32_t*)0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */
- #define REG_SDRAMC_TR (*(__IO uint32_t*)0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
- #define REG_SDRAMC_CR (*(__IO uint32_t*)0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
- #define REG_SDRAMC_LPR (*(__IO uint32_t*)0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
- #define REG_SDRAMC_IER (*(__O uint32_t*)0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
- #define REG_SDRAMC_IDR (*(__O uint32_t*)0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
- #define REG_SDRAMC_IMR (*(__I uint32_t*)0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
- #define REG_SDRAMC_ISR (*(__I uint32_t*)0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
- #define REG_SDRAMC_MDR (*(__IO uint32_t*)0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
- #define REG_SDRAMC_CFR1 (*(__IO uint32_t*)0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
- #define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */
- #define REG_SDRAMC_OCMS_KEY1 (*(__O uint32_t*)0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */
- #define REG_SDRAMC_OCMS_KEY2 (*(__O uint32_t*)0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_SDRAMC_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/smc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/smc.h
deleted file mode 100644
index e4cde22..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/smc.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SMC_INSTANCE_
-#define _SAMS70_SMC_INSTANCE_
-
-/* ========== Register definition for SMC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_SMC_SETUP0 (0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
- #define REG_SMC_PULSE0 (0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
- #define REG_SMC_CYCLE0 (0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
- #define REG_SMC_MODE0 (0x4008000CU) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */
- #define REG_SMC_SETUP1 (0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
- #define REG_SMC_PULSE1 (0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
- #define REG_SMC_CYCLE1 (0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
- #define REG_SMC_MODE1 (0x4008001CU) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */
- #define REG_SMC_SETUP2 (0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
- #define REG_SMC_PULSE2 (0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
- #define REG_SMC_CYCLE2 (0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
- #define REG_SMC_MODE2 (0x4008002CU) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */
- #define REG_SMC_SETUP3 (0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
- #define REG_SMC_PULSE3 (0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
- #define REG_SMC_CYCLE3 (0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
- #define REG_SMC_MODE3 (0x4008003CU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */
- #define REG_SMC_OCMS (0x40080080U) /**< \brief (SMC) SMC OCMS MODE Register */
- #define REG_SMC_KEY1 (0x40080084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
- #define REG_SMC_KEY2 (0x40080088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
- #define REG_SMC_WPMR (0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */
- #define REG_SMC_WPSR (0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */
-#else
- #define REG_SMC_SETUP0 (*(__IO uint32_t*)0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
- #define REG_SMC_PULSE0 (*(__IO uint32_t*)0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
- #define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
- #define REG_SMC_MODE0 (*(__IO uint32_t*)0x4008000CU) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */
- #define REG_SMC_SETUP1 (*(__IO uint32_t*)0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
- #define REG_SMC_PULSE1 (*(__IO uint32_t*)0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
- #define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
- #define REG_SMC_MODE1 (*(__IO uint32_t*)0x4008001CU) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */
- #define REG_SMC_SETUP2 (*(__IO uint32_t*)0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
- #define REG_SMC_PULSE2 (*(__IO uint32_t*)0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
- #define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
- #define REG_SMC_MODE2 (*(__IO uint32_t*)0x4008002CU) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */
- #define REG_SMC_SETUP3 (*(__IO uint32_t*)0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
- #define REG_SMC_PULSE3 (*(__IO uint32_t*)0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
- #define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
- #define REG_SMC_MODE3 (*(__IO uint32_t*)0x4008003CU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */
- #define REG_SMC_OCMS (*(__IO uint32_t*)0x40080080U) /**< \brief (SMC) SMC OCMS MODE Register */
- #define REG_SMC_KEY1 (*(__O uint32_t*)0x40080084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
- #define REG_SMC_KEY2 (*(__O uint32_t*)0x40080088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
- #define REG_SMC_WPMR (*(__IO uint32_t*)0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */
- #define REG_SMC_WPSR (*(__I uint32_t*)0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_SMC_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/spi0.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/spi0.h
deleted file mode 100644
index 5e7a8cc..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/spi0.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SPI0_INSTANCE_
-#define _SAMS70_SPI0_INSTANCE_
-
-/* ========== Register definition for SPI0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_SPI0_CR (0x40008000U) /**< \brief (SPI0) Control Register */
- #define REG_SPI0_MR (0x40008004U) /**< \brief (SPI0) Mode Register */
- #define REG_SPI0_RDR (0x40008008U) /**< \brief (SPI0) Receive Data Register */
- #define REG_SPI0_TDR (0x4000800CU) /**< \brief (SPI0) Transmit Data Register */
- #define REG_SPI0_SR (0x40008010U) /**< \brief (SPI0) Status Register */
- #define REG_SPI0_IER (0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */
- #define REG_SPI0_IDR (0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */
- #define REG_SPI0_IMR (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */
- #define REG_SPI0_CSR (0x40008030U) /**< \brief (SPI0) Chip Select Register */
- #define REG_SPI0_WPMR (0x400080E4U) /**< \brief (SPI0) Write Protection Mode Register */
- #define REG_SPI0_WPSR (0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */
-#else
- #define REG_SPI0_CR (*(__O uint32_t*)0x40008000U) /**< \brief (SPI0) Control Register */
- #define REG_SPI0_MR (*(__IO uint32_t*)0x40008004U) /**< \brief (SPI0) Mode Register */
- #define REG_SPI0_RDR (*(__I uint32_t*)0x40008008U) /**< \brief (SPI0) Receive Data Register */
- #define REG_SPI0_TDR (*(__O uint32_t*)0x4000800CU) /**< \brief (SPI0) Transmit Data Register */
- #define REG_SPI0_SR (*(__I uint32_t*)0x40008010U) /**< \brief (SPI0) Status Register */
- #define REG_SPI0_IER (*(__O uint32_t*)0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */
- #define REG_SPI0_IDR (*(__O uint32_t*)0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */
- #define REG_SPI0_IMR (*(__I uint32_t*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */
- #define REG_SPI0_CSR (*(__IO uint32_t*)0x40008030U) /**< \brief (SPI0) Chip Select Register */
- #define REG_SPI0_WPMR (*(__IO uint32_t*)0x400080E4U) /**< \brief (SPI0) Write Protection Mode Register */
- #define REG_SPI0_WPSR (*(__I uint32_t*)0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_SPI0_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/spi1.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/spi1.h
deleted file mode 100644
index dbd26f0..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/spi1.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SPI1_INSTANCE_
-#define _SAMS70_SPI1_INSTANCE_
-
-/* ========== Register definition for SPI1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_SPI1_CR (0x40058000U) /**< \brief (SPI1) Control Register */
- #define REG_SPI1_MR (0x40058004U) /**< \brief (SPI1) Mode Register */
- #define REG_SPI1_RDR (0x40058008U) /**< \brief (SPI1) Receive Data Register */
- #define REG_SPI1_TDR (0x4005800CU) /**< \brief (SPI1) Transmit Data Register */
- #define REG_SPI1_SR (0x40058010U) /**< \brief (SPI1) Status Register */
- #define REG_SPI1_IER (0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */
- #define REG_SPI1_IDR (0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */
- #define REG_SPI1_IMR (0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */
- #define REG_SPI1_CSR (0x40058030U) /**< \brief (SPI1) Chip Select Register */
- #define REG_SPI1_WPMR (0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */
- #define REG_SPI1_WPSR (0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */
-#else
- #define REG_SPI1_CR (*(__O uint32_t*)0x40058000U) /**< \brief (SPI1) Control Register */
- #define REG_SPI1_MR (*(__IO uint32_t*)0x40058004U) /**< \brief (SPI1) Mode Register */
- #define REG_SPI1_RDR (*(__I uint32_t*)0x40058008U) /**< \brief (SPI1) Receive Data Register */
- #define REG_SPI1_TDR (*(__O uint32_t*)0x4005800CU) /**< \brief (SPI1) Transmit Data Register */
- #define REG_SPI1_SR (*(__I uint32_t*)0x40058010U) /**< \brief (SPI1) Status Register */
- #define REG_SPI1_IER (*(__O uint32_t*)0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */
- #define REG_SPI1_IDR (*(__O uint32_t*)0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */
- #define REG_SPI1_IMR (*(__I uint32_t*)0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */
- #define REG_SPI1_CSR (*(__IO uint32_t*)0x40058030U) /**< \brief (SPI1) Chip Select Register */
- #define REG_SPI1_WPMR (*(__IO uint32_t*)0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */
- #define REG_SPI1_WPSR (*(__I uint32_t*)0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_SPI1_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/ssc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/ssc.h
deleted file mode 100644
index 3d55362..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/ssc.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SSC_INSTANCE_
-#define _SAMS70_SSC_INSTANCE_
-
-/* ========== Register definition for SSC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */
- #define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */
- #define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
- #define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
- #define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
- #define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
- #define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */
- #define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */
- #define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
- #define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
- #define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
- #define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
- #define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */
- #define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
- #define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
- #define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
- #define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */
- #define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protection Status Register */
-#else
- #define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< \brief (SSC) Control Register */
- #define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< \brief (SSC) Clock Mode Register */
- #define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
- #define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
- #define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
- #define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
- #define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< \brief (SSC) Receive Holding Register */
- #define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */
- #define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
- #define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
- #define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
- #define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
- #define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< \brief (SSC) Status Register */
- #define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
- #define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
- #define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
- #define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */
- #define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< \brief (SSC) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_SSC_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/supc.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/supc.h
deleted file mode 100644
index 3a8ccae..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/supc.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_SUPC_INSTANCE_
-#define _SAMS70_SUPC_INSTANCE_
-
-/* ========== Register definition for SUPC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_SUPC_CR (0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */
- #define REG_SUPC_SMMR (0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
- #define REG_SUPC_MR (0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */
- #define REG_SUPC_WUMR (0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */
- #define REG_SUPC_WUIR (0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */
- #define REG_SUPC_SR (0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */
-#else
- #define REG_SUPC_CR (*(__O uint32_t*)0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */
- #define REG_SUPC_SMMR (*(__IO uint32_t*)0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
- #define REG_SUPC_MR (*(__IO uint32_t*)0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */
- #define REG_SUPC_WUMR (*(__IO uint32_t*)0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */
- #define REG_SUPC_WUIR (*(__IO uint32_t*)0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */
- #define REG_SUPC_SR (*(__I uint32_t*)0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_SUPC_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/tc0.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/tc0.h
deleted file mode 100644
index 35b9687..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/tc0.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TC0_INSTANCE_
-#define _SAMS70_TC0_INSTANCE_
-
-/* ========== Register definition for TC0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TC0_CCR0 (0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
- #define REG_TC0_CMR0 (0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
- #define REG_TC0_SMMR0 (0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC0_RAB0 (0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */
- #define REG_TC0_CV0 (0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */
- #define REG_TC0_RA0 (0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */
- #define REG_TC0_RB0 (0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */
- #define REG_TC0_RC0 (0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */
- #define REG_TC0_SR0 (0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */
- #define REG_TC0_IER0 (0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
- #define REG_TC0_IDR0 (0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
- #define REG_TC0_IMR0 (0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
- #define REG_TC0_EMR0 (0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */
- #define REG_TC0_CCR1 (0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
- #define REG_TC0_CMR1 (0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
- #define REG_TC0_SMMR1 (0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC0_RAB1 (0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */
- #define REG_TC0_CV1 (0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */
- #define REG_TC0_RA1 (0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */
- #define REG_TC0_RB1 (0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */
- #define REG_TC0_RC1 (0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */
- #define REG_TC0_SR1 (0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */
- #define REG_TC0_IER1 (0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
- #define REG_TC0_IDR1 (0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
- #define REG_TC0_IMR1 (0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
- #define REG_TC0_EMR1 (0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */
- #define REG_TC0_CCR2 (0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
- #define REG_TC0_CMR2 (0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
- #define REG_TC0_SMMR2 (0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC0_RAB2 (0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */
- #define REG_TC0_CV2 (0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */
- #define REG_TC0_RA2 (0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */
- #define REG_TC0_RB2 (0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */
- #define REG_TC0_RC2 (0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */
- #define REG_TC0_SR2 (0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */
- #define REG_TC0_IER2 (0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
- #define REG_TC0_IDR2 (0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
- #define REG_TC0_IMR2 (0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
- #define REG_TC0_EMR2 (0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */
- #define REG_TC0_BCR (0x4000C0C0U) /**< \brief (TC0) Block Control Register */
- #define REG_TC0_BMR (0x4000C0C4U) /**< \brief (TC0) Block Mode Register */
- #define REG_TC0_QIER (0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
- #define REG_TC0_QIDR (0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
- #define REG_TC0_QIMR (0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
- #define REG_TC0_QISR (0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
- #define REG_TC0_FMR (0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */
- #define REG_TC0_WPMR (0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */
-#else
- #define REG_TC0_CCR0 (*(__O uint32_t*)0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
- #define REG_TC0_CMR0 (*(__IO uint32_t*)0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
- #define REG_TC0_SMMR0 (*(__IO uint32_t*)0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC0_RAB0 (*(__I uint32_t*)0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */
- #define REG_TC0_CV0 (*(__I uint32_t*)0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */
- #define REG_TC0_RA0 (*(__IO uint32_t*)0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */
- #define REG_TC0_RB0 (*(__IO uint32_t*)0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */
- #define REG_TC0_RC0 (*(__IO uint32_t*)0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */
- #define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */
- #define REG_TC0_IER0 (*(__O uint32_t*)0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
- #define REG_TC0_IDR0 (*(__O uint32_t*)0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
- #define REG_TC0_IMR0 (*(__I uint32_t*)0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
- #define REG_TC0_EMR0 (*(__IO uint32_t*)0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */
- #define REG_TC0_CCR1 (*(__O uint32_t*)0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
- #define REG_TC0_CMR1 (*(__IO uint32_t*)0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
- #define REG_TC0_SMMR1 (*(__IO uint32_t*)0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC0_RAB1 (*(__I uint32_t*)0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */
- #define REG_TC0_CV1 (*(__I uint32_t*)0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */
- #define REG_TC0_RA1 (*(__IO uint32_t*)0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */
- #define REG_TC0_RB1 (*(__IO uint32_t*)0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */
- #define REG_TC0_RC1 (*(__IO uint32_t*)0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */
- #define REG_TC0_SR1 (*(__I uint32_t*)0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */
- #define REG_TC0_IER1 (*(__O uint32_t*)0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
- #define REG_TC0_IDR1 (*(__O uint32_t*)0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
- #define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
- #define REG_TC0_EMR1 (*(__IO uint32_t*)0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */
- #define REG_TC0_CCR2 (*(__O uint32_t*)0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
- #define REG_TC0_CMR2 (*(__IO uint32_t*)0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
- #define REG_TC0_SMMR2 (*(__IO uint32_t*)0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC0_RAB2 (*(__I uint32_t*)0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */
- #define REG_TC0_CV2 (*(__I uint32_t*)0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */
- #define REG_TC0_RA2 (*(__IO uint32_t*)0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */
- #define REG_TC0_RB2 (*(__IO uint32_t*)0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */
- #define REG_TC0_RC2 (*(__IO uint32_t*)0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */
- #define REG_TC0_SR2 (*(__I uint32_t*)0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */
- #define REG_TC0_IER2 (*(__O uint32_t*)0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
- #define REG_TC0_IDR2 (*(__O uint32_t*)0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
- #define REG_TC0_IMR2 (*(__I uint32_t*)0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
- #define REG_TC0_EMR2 (*(__IO uint32_t*)0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */
- #define REG_TC0_BCR (*(__O uint32_t*)0x4000C0C0U) /**< \brief (TC0) Block Control Register */
- #define REG_TC0_BMR (*(__IO uint32_t*)0x4000C0C4U) /**< \brief (TC0) Block Mode Register */
- #define REG_TC0_QIER (*(__O uint32_t*)0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
- #define REG_TC0_QIDR (*(__O uint32_t*)0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
- #define REG_TC0_QIMR (*(__I uint32_t*)0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
- #define REG_TC0_QISR (*(__I uint32_t*)0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
- #define REG_TC0_FMR (*(__IO uint32_t*)0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */
- #define REG_TC0_WPMR (*(__IO uint32_t*)0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TC0_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/tc1.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/tc1.h
deleted file mode 100644
index 0f1bc18..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/tc1.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TC1_INSTANCE_
-#define _SAMS70_TC1_INSTANCE_
-
-/* ========== Register definition for TC1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TC1_CCR0 (0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
- #define REG_TC1_CMR0 (0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
- #define REG_TC1_SMMR0 (0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC1_RAB0 (0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */
- #define REG_TC1_CV0 (0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */
- #define REG_TC1_RA0 (0x40010014U) /**< \brief (TC1) Register A (channel = 0) */
- #define REG_TC1_RB0 (0x40010018U) /**< \brief (TC1) Register B (channel = 0) */
- #define REG_TC1_RC0 (0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */
- #define REG_TC1_SR0 (0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */
- #define REG_TC1_IER0 (0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
- #define REG_TC1_IDR0 (0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
- #define REG_TC1_IMR0 (0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
- #define REG_TC1_EMR0 (0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */
- #define REG_TC1_CCR1 (0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
- #define REG_TC1_CMR1 (0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
- #define REG_TC1_SMMR1 (0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC1_RAB1 (0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */
- #define REG_TC1_CV1 (0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */
- #define REG_TC1_RA1 (0x40010054U) /**< \brief (TC1) Register A (channel = 1) */
- #define REG_TC1_RB1 (0x40010058U) /**< \brief (TC1) Register B (channel = 1) */
- #define REG_TC1_RC1 (0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */
- #define REG_TC1_SR1 (0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */
- #define REG_TC1_IER1 (0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
- #define REG_TC1_IDR1 (0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
- #define REG_TC1_IMR1 (0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
- #define REG_TC1_EMR1 (0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */
- #define REG_TC1_CCR2 (0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
- #define REG_TC1_CMR2 (0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
- #define REG_TC1_SMMR2 (0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC1_RAB2 (0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */
- #define REG_TC1_CV2 (0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */
- #define REG_TC1_RA2 (0x40010094U) /**< \brief (TC1) Register A (channel = 2) */
- #define REG_TC1_RB2 (0x40010098U) /**< \brief (TC1) Register B (channel = 2) */
- #define REG_TC1_RC2 (0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */
- #define REG_TC1_SR2 (0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */
- #define REG_TC1_IER2 (0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
- #define REG_TC1_IDR2 (0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
- #define REG_TC1_IMR2 (0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
- #define REG_TC1_EMR2 (0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */
- #define REG_TC1_BCR (0x400100C0U) /**< \brief (TC1) Block Control Register */
- #define REG_TC1_BMR (0x400100C4U) /**< \brief (TC1) Block Mode Register */
- #define REG_TC1_QIER (0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
- #define REG_TC1_QIDR (0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
- #define REG_TC1_QIMR (0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
- #define REG_TC1_QISR (0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
- #define REG_TC1_FMR (0x400100D8U) /**< \brief (TC1) Fault Mode Register */
- #define REG_TC1_WPMR (0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */
-#else
- #define REG_TC1_CCR0 (*(__O uint32_t*)0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
- #define REG_TC1_CMR0 (*(__IO uint32_t*)0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
- #define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC1_RAB0 (*(__I uint32_t*)0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */
- #define REG_TC1_CV0 (*(__I uint32_t*)0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */
- #define REG_TC1_RA0 (*(__IO uint32_t*)0x40010014U) /**< \brief (TC1) Register A (channel = 0) */
- #define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< \brief (TC1) Register B (channel = 0) */
- #define REG_TC1_RC0 (*(__IO uint32_t*)0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */
- #define REG_TC1_SR0 (*(__I uint32_t*)0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */
- #define REG_TC1_IER0 (*(__O uint32_t*)0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
- #define REG_TC1_IDR0 (*(__O uint32_t*)0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
- #define REG_TC1_IMR0 (*(__I uint32_t*)0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
- #define REG_TC1_EMR0 (*(__IO uint32_t*)0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */
- #define REG_TC1_CCR1 (*(__O uint32_t*)0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
- #define REG_TC1_CMR1 (*(__IO uint32_t*)0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
- #define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC1_RAB1 (*(__I uint32_t*)0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */
- #define REG_TC1_CV1 (*(__I uint32_t*)0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */
- #define REG_TC1_RA1 (*(__IO uint32_t*)0x40010054U) /**< \brief (TC1) Register A (channel = 1) */
- #define REG_TC1_RB1 (*(__IO uint32_t*)0x40010058U) /**< \brief (TC1) Register B (channel = 1) */
- #define REG_TC1_RC1 (*(__IO uint32_t*)0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */
- #define REG_TC1_SR1 (*(__I uint32_t*)0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */
- #define REG_TC1_IER1 (*(__O uint32_t*)0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
- #define REG_TC1_IDR1 (*(__O uint32_t*)0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
- #define REG_TC1_IMR1 (*(__I uint32_t*)0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
- #define REG_TC1_EMR1 (*(__IO uint32_t*)0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */
- #define REG_TC1_CCR2 (*(__O uint32_t*)0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
- #define REG_TC1_CMR2 (*(__IO uint32_t*)0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
- #define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC1_RAB2 (*(__I uint32_t*)0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */
- #define REG_TC1_CV2 (*(__I uint32_t*)0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */
- #define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< \brief (TC1) Register A (channel = 2) */
- #define REG_TC1_RB2 (*(__IO uint32_t*)0x40010098U) /**< \brief (TC1) Register B (channel = 2) */
- #define REG_TC1_RC2 (*(__IO uint32_t*)0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */
- #define REG_TC1_SR2 (*(__I uint32_t*)0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */
- #define REG_TC1_IER2 (*(__O uint32_t*)0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
- #define REG_TC1_IDR2 (*(__O uint32_t*)0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
- #define REG_TC1_IMR2 (*(__I uint32_t*)0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
- #define REG_TC1_EMR2 (*(__IO uint32_t*)0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */
- #define REG_TC1_BCR (*(__O uint32_t*)0x400100C0U) /**< \brief (TC1) Block Control Register */
- #define REG_TC1_BMR (*(__IO uint32_t*)0x400100C4U) /**< \brief (TC1) Block Mode Register */
- #define REG_TC1_QIER (*(__O uint32_t*)0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
- #define REG_TC1_QIDR (*(__O uint32_t*)0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
- #define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
- #define REG_TC1_QISR (*(__I uint32_t*)0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
- #define REG_TC1_FMR (*(__IO uint32_t*)0x400100D8U) /**< \brief (TC1) Fault Mode Register */
- #define REG_TC1_WPMR (*(__IO uint32_t*)0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TC1_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/tc2.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/tc2.h
deleted file mode 100644
index 6a7e0b9..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/tc2.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TC2_INSTANCE_
-#define _SAMS70_TC2_INSTANCE_
-
-/* ========== Register definition for TC2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TC2_CCR0 (0x40014000U) /**< \brief (TC2) Channel Control Register (channel = 0) */
- #define REG_TC2_CMR0 (0x40014004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */
- #define REG_TC2_SMMR0 (0x40014008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC2_RAB0 (0x4001400CU) /**< \brief (TC2) Register AB (channel = 0) */
- #define REG_TC2_CV0 (0x40014010U) /**< \brief (TC2) Counter Value (channel = 0) */
- #define REG_TC2_RA0 (0x40014014U) /**< \brief (TC2) Register A (channel = 0) */
- #define REG_TC2_RB0 (0x40014018U) /**< \brief (TC2) Register B (channel = 0) */
- #define REG_TC2_RC0 (0x4001401CU) /**< \brief (TC2) Register C (channel = 0) */
- #define REG_TC2_SR0 (0x40014020U) /**< \brief (TC2) Status Register (channel = 0) */
- #define REG_TC2_IER0 (0x40014024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */
- #define REG_TC2_IDR0 (0x40014028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */
- #define REG_TC2_IMR0 (0x4001402CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */
- #define REG_TC2_EMR0 (0x40014030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */
- #define REG_TC2_CCR1 (0x40014040U) /**< \brief (TC2) Channel Control Register (channel = 1) */
- #define REG_TC2_CMR1 (0x40014044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */
- #define REG_TC2_SMMR1 (0x40014048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC2_RAB1 (0x4001404CU) /**< \brief (TC2) Register AB (channel = 1) */
- #define REG_TC2_CV1 (0x40014050U) /**< \brief (TC2) Counter Value (channel = 1) */
- #define REG_TC2_RA1 (0x40014054U) /**< \brief (TC2) Register A (channel = 1) */
- #define REG_TC2_RB1 (0x40014058U) /**< \brief (TC2) Register B (channel = 1) */
- #define REG_TC2_RC1 (0x4001405CU) /**< \brief (TC2) Register C (channel = 1) */
- #define REG_TC2_SR1 (0x40014060U) /**< \brief (TC2) Status Register (channel = 1) */
- #define REG_TC2_IER1 (0x40014064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */
- #define REG_TC2_IDR1 (0x40014068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */
- #define REG_TC2_IMR1 (0x4001406CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */
- #define REG_TC2_EMR1 (0x40014070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */
- #define REG_TC2_CCR2 (0x40014080U) /**< \brief (TC2) Channel Control Register (channel = 2) */
- #define REG_TC2_CMR2 (0x40014084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */
- #define REG_TC2_SMMR2 (0x40014088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC2_RAB2 (0x4001408CU) /**< \brief (TC2) Register AB (channel = 2) */
- #define REG_TC2_CV2 (0x40014090U) /**< \brief (TC2) Counter Value (channel = 2) */
- #define REG_TC2_RA2 (0x40014094U) /**< \brief (TC2) Register A (channel = 2) */
- #define REG_TC2_RB2 (0x40014098U) /**< \brief (TC2) Register B (channel = 2) */
- #define REG_TC2_RC2 (0x4001409CU) /**< \brief (TC2) Register C (channel = 2) */
- #define REG_TC2_SR2 (0x400140A0U) /**< \brief (TC2) Status Register (channel = 2) */
- #define REG_TC2_IER2 (0x400140A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */
- #define REG_TC2_IDR2 (0x400140A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */
- #define REG_TC2_IMR2 (0x400140ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */
- #define REG_TC2_EMR2 (0x400140B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */
- #define REG_TC2_BCR (0x400140C0U) /**< \brief (TC2) Block Control Register */
- #define REG_TC2_BMR (0x400140C4U) /**< \brief (TC2) Block Mode Register */
- #define REG_TC2_QIER (0x400140C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */
- #define REG_TC2_QIDR (0x400140CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */
- #define REG_TC2_QIMR (0x400140D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */
- #define REG_TC2_QISR (0x400140D4U) /**< \brief (TC2) QDEC Interrupt Status Register */
- #define REG_TC2_FMR (0x400140D8U) /**< \brief (TC2) Fault Mode Register */
- #define REG_TC2_WPMR (0x400140E4U) /**< \brief (TC2) Write Protection Mode Register */
-#else
- #define REG_TC2_CCR0 (*(__O uint32_t*)0x40014000U) /**< \brief (TC2) Channel Control Register (channel = 0) */
- #define REG_TC2_CMR0 (*(__IO uint32_t*)0x40014004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */
- #define REG_TC2_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC2_RAB0 (*(__I uint32_t*)0x4001400CU) /**< \brief (TC2) Register AB (channel = 0) */
- #define REG_TC2_CV0 (*(__I uint32_t*)0x40014010U) /**< \brief (TC2) Counter Value (channel = 0) */
- #define REG_TC2_RA0 (*(__IO uint32_t*)0x40014014U) /**< \brief (TC2) Register A (channel = 0) */
- #define REG_TC2_RB0 (*(__IO uint32_t*)0x40014018U) /**< \brief (TC2) Register B (channel = 0) */
- #define REG_TC2_RC0 (*(__IO uint32_t*)0x4001401CU) /**< \brief (TC2) Register C (channel = 0) */
- #define REG_TC2_SR0 (*(__I uint32_t*)0x40014020U) /**< \brief (TC2) Status Register (channel = 0) */
- #define REG_TC2_IER0 (*(__O uint32_t*)0x40014024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */
- #define REG_TC2_IDR0 (*(__O uint32_t*)0x40014028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */
- #define REG_TC2_IMR0 (*(__I uint32_t*)0x4001402CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */
- #define REG_TC2_EMR0 (*(__IO uint32_t*)0x40014030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */
- #define REG_TC2_CCR1 (*(__O uint32_t*)0x40014040U) /**< \brief (TC2) Channel Control Register (channel = 1) */
- #define REG_TC2_CMR1 (*(__IO uint32_t*)0x40014044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */
- #define REG_TC2_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC2_RAB1 (*(__I uint32_t*)0x4001404CU) /**< \brief (TC2) Register AB (channel = 1) */
- #define REG_TC2_CV1 (*(__I uint32_t*)0x40014050U) /**< \brief (TC2) Counter Value (channel = 1) */
- #define REG_TC2_RA1 (*(__IO uint32_t*)0x40014054U) /**< \brief (TC2) Register A (channel = 1) */
- #define REG_TC2_RB1 (*(__IO uint32_t*)0x40014058U) /**< \brief (TC2) Register B (channel = 1) */
- #define REG_TC2_RC1 (*(__IO uint32_t*)0x4001405CU) /**< \brief (TC2) Register C (channel = 1) */
- #define REG_TC2_SR1 (*(__I uint32_t*)0x40014060U) /**< \brief (TC2) Status Register (channel = 1) */
- #define REG_TC2_IER1 (*(__O uint32_t*)0x40014064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */
- #define REG_TC2_IDR1 (*(__O uint32_t*)0x40014068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */
- #define REG_TC2_IMR1 (*(__I uint32_t*)0x4001406CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */
- #define REG_TC2_EMR1 (*(__IO uint32_t*)0x40014070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */
- #define REG_TC2_CCR2 (*(__O uint32_t*)0x40014080U) /**< \brief (TC2) Channel Control Register (channel = 2) */
- #define REG_TC2_CMR2 (*(__IO uint32_t*)0x40014084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */
- #define REG_TC2_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC2_RAB2 (*(__I uint32_t*)0x4001408CU) /**< \brief (TC2) Register AB (channel = 2) */
- #define REG_TC2_CV2 (*(__I uint32_t*)0x40014090U) /**< \brief (TC2) Counter Value (channel = 2) */
- #define REG_TC2_RA2 (*(__IO uint32_t*)0x40014094U) /**< \brief (TC2) Register A (channel = 2) */
- #define REG_TC2_RB2 (*(__IO uint32_t*)0x40014098U) /**< \brief (TC2) Register B (channel = 2) */
- #define REG_TC2_RC2 (*(__IO uint32_t*)0x4001409CU) /**< \brief (TC2) Register C (channel = 2) */
- #define REG_TC2_SR2 (*(__I uint32_t*)0x400140A0U) /**< \brief (TC2) Status Register (channel = 2) */
- #define REG_TC2_IER2 (*(__O uint32_t*)0x400140A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */
- #define REG_TC2_IDR2 (*(__O uint32_t*)0x400140A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */
- #define REG_TC2_IMR2 (*(__I uint32_t*)0x400140ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */
- #define REG_TC2_EMR2 (*(__IO uint32_t*)0x400140B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */
- #define REG_TC2_BCR (*(__O uint32_t*)0x400140C0U) /**< \brief (TC2) Block Control Register */
- #define REG_TC2_BMR (*(__IO uint32_t*)0x400140C4U) /**< \brief (TC2) Block Mode Register */
- #define REG_TC2_QIER (*(__O uint32_t*)0x400140C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */
- #define REG_TC2_QIDR (*(__O uint32_t*)0x400140CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */
- #define REG_TC2_QIMR (*(__I uint32_t*)0x400140D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */
- #define REG_TC2_QISR (*(__I uint32_t*)0x400140D4U) /**< \brief (TC2) QDEC Interrupt Status Register */
- #define REG_TC2_FMR (*(__IO uint32_t*)0x400140D8U) /**< \brief (TC2) Fault Mode Register */
- #define REG_TC2_WPMR (*(__IO uint32_t*)0x400140E4U) /**< \brief (TC2) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TC2_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/tc3.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/tc3.h
deleted file mode 100644
index 2921bd4..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/tc3.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TC3_INSTANCE_
-#define _SAMS70_TC3_INSTANCE_
-
-/* ========== Register definition for TC3 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TC3_CCR0 (0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */
- #define REG_TC3_CMR0 (0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */
- #define REG_TC3_SMMR0 (0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC3_RAB0 (0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */
- #define REG_TC3_CV0 (0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */
- #define REG_TC3_RA0 (0x40054014U) /**< \brief (TC3) Register A (channel = 0) */
- #define REG_TC3_RB0 (0x40054018U) /**< \brief (TC3) Register B (channel = 0) */
- #define REG_TC3_RC0 (0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */
- #define REG_TC3_SR0 (0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */
- #define REG_TC3_IER0 (0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */
- #define REG_TC3_IDR0 (0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */
- #define REG_TC3_IMR0 (0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */
- #define REG_TC3_EMR0 (0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */
- #define REG_TC3_CCR1 (0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */
- #define REG_TC3_CMR1 (0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */
- #define REG_TC3_SMMR1 (0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC3_RAB1 (0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */
- #define REG_TC3_CV1 (0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */
- #define REG_TC3_RA1 (0x40054054U) /**< \brief (TC3) Register A (channel = 1) */
- #define REG_TC3_RB1 (0x40054058U) /**< \brief (TC3) Register B (channel = 1) */
- #define REG_TC3_RC1 (0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */
- #define REG_TC3_SR1 (0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */
- #define REG_TC3_IER1 (0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */
- #define REG_TC3_IDR1 (0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */
- #define REG_TC3_IMR1 (0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */
- #define REG_TC3_EMR1 (0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */
- #define REG_TC3_CCR2 (0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */
- #define REG_TC3_CMR2 (0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */
- #define REG_TC3_SMMR2 (0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC3_RAB2 (0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */
- #define REG_TC3_CV2 (0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */
- #define REG_TC3_RA2 (0x40054094U) /**< \brief (TC3) Register A (channel = 2) */
- #define REG_TC3_RB2 (0x40054098U) /**< \brief (TC3) Register B (channel = 2) */
- #define REG_TC3_RC2 (0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */
- #define REG_TC3_SR2 (0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */
- #define REG_TC3_IER2 (0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */
- #define REG_TC3_IDR2 (0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */
- #define REG_TC3_IMR2 (0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */
- #define REG_TC3_EMR2 (0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */
- #define REG_TC3_BCR (0x400540C0U) /**< \brief (TC3) Block Control Register */
- #define REG_TC3_BMR (0x400540C4U) /**< \brief (TC3) Block Mode Register */
- #define REG_TC3_QIER (0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */
- #define REG_TC3_QIDR (0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */
- #define REG_TC3_QIMR (0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */
- #define REG_TC3_QISR (0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */
- #define REG_TC3_FMR (0x400540D8U) /**< \brief (TC3) Fault Mode Register */
- #define REG_TC3_WPMR (0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */
-#else
- #define REG_TC3_CCR0 (*(__O uint32_t*)0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */
- #define REG_TC3_CMR0 (*(__IO uint32_t*)0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */
- #define REG_TC3_SMMR0 (*(__IO uint32_t*)0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */
- #define REG_TC3_RAB0 (*(__I uint32_t*)0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */
- #define REG_TC3_CV0 (*(__I uint32_t*)0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */
- #define REG_TC3_RA0 (*(__IO uint32_t*)0x40054014U) /**< \brief (TC3) Register A (channel = 0) */
- #define REG_TC3_RB0 (*(__IO uint32_t*)0x40054018U) /**< \brief (TC3) Register B (channel = 0) */
- #define REG_TC3_RC0 (*(__IO uint32_t*)0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */
- #define REG_TC3_SR0 (*(__I uint32_t*)0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */
- #define REG_TC3_IER0 (*(__O uint32_t*)0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */
- #define REG_TC3_IDR0 (*(__O uint32_t*)0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */
- #define REG_TC3_IMR0 (*(__I uint32_t*)0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */
- #define REG_TC3_EMR0 (*(__IO uint32_t*)0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */
- #define REG_TC3_CCR1 (*(__O uint32_t*)0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */
- #define REG_TC3_CMR1 (*(__IO uint32_t*)0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */
- #define REG_TC3_SMMR1 (*(__IO uint32_t*)0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */
- #define REG_TC3_RAB1 (*(__I uint32_t*)0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */
- #define REG_TC3_CV1 (*(__I uint32_t*)0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */
- #define REG_TC3_RA1 (*(__IO uint32_t*)0x40054054U) /**< \brief (TC3) Register A (channel = 1) */
- #define REG_TC3_RB1 (*(__IO uint32_t*)0x40054058U) /**< \brief (TC3) Register B (channel = 1) */
- #define REG_TC3_RC1 (*(__IO uint32_t*)0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */
- #define REG_TC3_SR1 (*(__I uint32_t*)0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */
- #define REG_TC3_IER1 (*(__O uint32_t*)0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */
- #define REG_TC3_IDR1 (*(__O uint32_t*)0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */
- #define REG_TC3_IMR1 (*(__I uint32_t*)0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */
- #define REG_TC3_EMR1 (*(__IO uint32_t*)0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */
- #define REG_TC3_CCR2 (*(__O uint32_t*)0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */
- #define REG_TC3_CMR2 (*(__IO uint32_t*)0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */
- #define REG_TC3_SMMR2 (*(__IO uint32_t*)0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */
- #define REG_TC3_RAB2 (*(__I uint32_t*)0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */
- #define REG_TC3_CV2 (*(__I uint32_t*)0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */
- #define REG_TC3_RA2 (*(__IO uint32_t*)0x40054094U) /**< \brief (TC3) Register A (channel = 2) */
- #define REG_TC3_RB2 (*(__IO uint32_t*)0x40054098U) /**< \brief (TC3) Register B (channel = 2) */
- #define REG_TC3_RC2 (*(__IO uint32_t*)0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */
- #define REG_TC3_SR2 (*(__I uint32_t*)0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */
- #define REG_TC3_IER2 (*(__O uint32_t*)0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */
- #define REG_TC3_IDR2 (*(__O uint32_t*)0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */
- #define REG_TC3_IMR2 (*(__I uint32_t*)0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */
- #define REG_TC3_EMR2 (*(__IO uint32_t*)0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */
- #define REG_TC3_BCR (*(__O uint32_t*)0x400540C0U) /**< \brief (TC3) Block Control Register */
- #define REG_TC3_BMR (*(__IO uint32_t*)0x400540C4U) /**< \brief (TC3) Block Mode Register */
- #define REG_TC3_QIER (*(__O uint32_t*)0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */
- #define REG_TC3_QIDR (*(__O uint32_t*)0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */
- #define REG_TC3_QIMR (*(__I uint32_t*)0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */
- #define REG_TC3_QISR (*(__I uint32_t*)0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */
- #define REG_TC3_FMR (*(__IO uint32_t*)0x400540D8U) /**< \brief (TC3) Fault Mode Register */
- #define REG_TC3_WPMR (*(__IO uint32_t*)0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TC3_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/trng.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/trng.h
deleted file mode 100644
index aa70ee0..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/trng.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TRNG_INSTANCE_
-#define _SAMS70_TRNG_INSTANCE_
-
-/* ========== Register definition for TRNG peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TRNG_CR (0x40070000U) /**< \brief (TRNG) Control Register */
- #define REG_TRNG_IER (0x40070010U) /**< \brief (TRNG) Interrupt Enable Register */
- #define REG_TRNG_IDR (0x40070014U) /**< \brief (TRNG) Interrupt Disable Register */
- #define REG_TRNG_IMR (0x40070018U) /**< \brief (TRNG) Interrupt Mask Register */
- #define REG_TRNG_ISR (0x4007001CU) /**< \brief (TRNG) Interrupt Status Register */
- #define REG_TRNG_ODATA (0x40070050U) /**< \brief (TRNG) Output Data Register */
-#else
- #define REG_TRNG_CR (*(__O uint32_t*)0x40070000U) /**< \brief (TRNG) Control Register */
- #define REG_TRNG_IER (*(__O uint32_t*)0x40070010U) /**< \brief (TRNG) Interrupt Enable Register */
- #define REG_TRNG_IDR (*(__O uint32_t*)0x40070014U) /**< \brief (TRNG) Interrupt Disable Register */
- #define REG_TRNG_IMR (*(__I uint32_t*)0x40070018U) /**< \brief (TRNG) Interrupt Mask Register */
- #define REG_TRNG_ISR (*(__I uint32_t*)0x4007001CU) /**< \brief (TRNG) Interrupt Status Register */
- #define REG_TRNG_ODATA (*(__I uint32_t*)0x40070050U) /**< \brief (TRNG) Output Data Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TRNG_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs0.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs0.h
deleted file mode 100644
index 8fc2286..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs0.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TWIHS0_INSTANCE_
-#define _SAMS70_TWIHS0_INSTANCE_
-
-/* ========== Register definition for TWIHS0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TWIHS0_CR (0x40018000U) /**< \brief (TWIHS0) Control Register */
- #define REG_TWIHS0_MMR (0x40018004U) /**< \brief (TWIHS0) Master Mode Register */
- #define REG_TWIHS0_SMR (0x40018008U) /**< \brief (TWIHS0) Slave Mode Register */
- #define REG_TWIHS0_IADR (0x4001800CU) /**< \brief (TWIHS0) Internal Address Register */
- #define REG_TWIHS0_CWGR (0x40018010U) /**< \brief (TWIHS0) Clock Waveform Generator Register */
- #define REG_TWIHS0_SR (0x40018020U) /**< \brief (TWIHS0) Status Register */
- #define REG_TWIHS0_IER (0x40018024U) /**< \brief (TWIHS0) Interrupt Enable Register */
- #define REG_TWIHS0_IDR (0x40018028U) /**< \brief (TWIHS0) Interrupt Disable Register */
- #define REG_TWIHS0_IMR (0x4001802CU) /**< \brief (TWIHS0) Interrupt Mask Register */
- #define REG_TWIHS0_RHR (0x40018030U) /**< \brief (TWIHS0) Receive Holding Register */
- #define REG_TWIHS0_THR (0x40018034U) /**< \brief (TWIHS0) Transmit Holding Register */
- #define REG_TWIHS0_SMBTR (0x40018038U) /**< \brief (TWIHS0) SMBus Timing Register */
- #define REG_TWIHS0_FILTR (0x40018044U) /**< \brief (TWIHS0) Filter Register */
- #define REG_TWIHS0_SWMR (0x4001804CU) /**< \brief (TWIHS0) SleepWalking Matching Register */
- #define REG_TWIHS0_WPMR (0x400180E4U) /**< \brief (TWIHS0) Write Protection Mode Register */
- #define REG_TWIHS0_WPSR (0x400180E8U) /**< \brief (TWIHS0) Write Protection Status Register */
-#else
- #define REG_TWIHS0_CR (*(__O uint32_t*)0x40018000U) /**< \brief (TWIHS0) Control Register */
- #define REG_TWIHS0_MMR (*(__IO uint32_t*)0x40018004U) /**< \brief (TWIHS0) Master Mode Register */
- #define REG_TWIHS0_SMR (*(__IO uint32_t*)0x40018008U) /**< \brief (TWIHS0) Slave Mode Register */
- #define REG_TWIHS0_IADR (*(__IO uint32_t*)0x4001800CU) /**< \brief (TWIHS0) Internal Address Register */
- #define REG_TWIHS0_CWGR (*(__IO uint32_t*)0x40018010U) /**< \brief (TWIHS0) Clock Waveform Generator Register */
- #define REG_TWIHS0_SR (*(__I uint32_t*)0x40018020U) /**< \brief (TWIHS0) Status Register */
- #define REG_TWIHS0_IER (*(__O uint32_t*)0x40018024U) /**< \brief (TWIHS0) Interrupt Enable Register */
- #define REG_TWIHS0_IDR (*(__O uint32_t*)0x40018028U) /**< \brief (TWIHS0) Interrupt Disable Register */
- #define REG_TWIHS0_IMR (*(__I uint32_t*)0x4001802CU) /**< \brief (TWIHS0) Interrupt Mask Register */
- #define REG_TWIHS0_RHR (*(__I uint32_t*)0x40018030U) /**< \brief (TWIHS0) Receive Holding Register */
- #define REG_TWIHS0_THR (*(__O uint32_t*)0x40018034U) /**< \brief (TWIHS0) Transmit Holding Register */
- #define REG_TWIHS0_SMBTR (*(__IO uint32_t*)0x40018038U) /**< \brief (TWIHS0) SMBus Timing Register */
- #define REG_TWIHS0_FILTR (*(__IO uint32_t*)0x40018044U) /**< \brief (TWIHS0) Filter Register */
- #define REG_TWIHS0_SWMR (*(__IO uint32_t*)0x4001804CU) /**< \brief (TWIHS0) SleepWalking Matching Register */
- #define REG_TWIHS0_WPMR (*(__IO uint32_t*)0x400180E4U) /**< \brief (TWIHS0) Write Protection Mode Register */
- #define REG_TWIHS0_WPSR (*(__I uint32_t*)0x400180E8U) /**< \brief (TWIHS0) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TWIHS0_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs1.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs1.h
deleted file mode 100644
index ca179cc..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs1.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TWIHS1_INSTANCE_
-#define _SAMS70_TWIHS1_INSTANCE_
-
-/* ========== Register definition for TWIHS1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TWIHS1_CR (0x4001C000U) /**< \brief (TWIHS1) Control Register */
- #define REG_TWIHS1_MMR (0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */
- #define REG_TWIHS1_SMR (0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */
- #define REG_TWIHS1_IADR (0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */
- #define REG_TWIHS1_CWGR (0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */
- #define REG_TWIHS1_SR (0x4001C020U) /**< \brief (TWIHS1) Status Register */
- #define REG_TWIHS1_IER (0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */
- #define REG_TWIHS1_IDR (0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */
- #define REG_TWIHS1_IMR (0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */
- #define REG_TWIHS1_RHR (0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */
- #define REG_TWIHS1_THR (0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */
- #define REG_TWIHS1_SMBTR (0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */
- #define REG_TWIHS1_FILTR (0x4001C044U) /**< \brief (TWIHS1) Filter Register */
- #define REG_TWIHS1_SWMR (0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */
- #define REG_TWIHS1_WPMR (0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */
- #define REG_TWIHS1_WPSR (0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */
-#else
- #define REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) /**< \brief (TWIHS1) Control Register */
- #define REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */
- #define REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */
- #define REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */
- #define REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */
- #define REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) /**< \brief (TWIHS1) Status Register */
- #define REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */
- #define REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */
- #define REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */
- #define REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */
- #define REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */
- #define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */
- #define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) /**< \brief (TWIHS1) Filter Register */
- #define REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */
- #define REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */
- #define REG_TWIHS1_WPSR (*(__I uint32_t*)0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TWIHS1_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs2.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs2.h
deleted file mode 100644
index d67cbf3..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/twihs2.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_TWIHS2_INSTANCE_
-#define _SAMS70_TWIHS2_INSTANCE_
-
-/* ========== Register definition for TWIHS2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_TWIHS2_CR (0x40060000U) /**< \brief (TWIHS2) Control Register */
- #define REG_TWIHS2_MMR (0x40060004U) /**< \brief (TWIHS2) Master Mode Register */
- #define REG_TWIHS2_SMR (0x40060008U) /**< \brief (TWIHS2) Slave Mode Register */
- #define REG_TWIHS2_IADR (0x4006000CU) /**< \brief (TWIHS2) Internal Address Register */
- #define REG_TWIHS2_CWGR (0x40060010U) /**< \brief (TWIHS2) Clock Waveform Generator Register */
- #define REG_TWIHS2_SR (0x40060020U) /**< \brief (TWIHS2) Status Register */
- #define REG_TWIHS2_IER (0x40060024U) /**< \brief (TWIHS2) Interrupt Enable Register */
- #define REG_TWIHS2_IDR (0x40060028U) /**< \brief (TWIHS2) Interrupt Disable Register */
- #define REG_TWIHS2_IMR (0x4006002CU) /**< \brief (TWIHS2) Interrupt Mask Register */
- #define REG_TWIHS2_RHR (0x40060030U) /**< \brief (TWIHS2) Receive Holding Register */
- #define REG_TWIHS2_THR (0x40060034U) /**< \brief (TWIHS2) Transmit Holding Register */
- #define REG_TWIHS2_SMBTR (0x40060038U) /**< \brief (TWIHS2) SMBus Timing Register */
- #define REG_TWIHS2_FILTR (0x40060044U) /**< \brief (TWIHS2) Filter Register */
- #define REG_TWIHS2_SWMR (0x4006004CU) /**< \brief (TWIHS2) SleepWalking Matching Register */
- #define REG_TWIHS2_WPMR (0x400600E4U) /**< \brief (TWIHS2) Write Protection Mode Register */
- #define REG_TWIHS2_WPSR (0x400600E8U) /**< \brief (TWIHS2) Write Protection Status Register */
-#else
- #define REG_TWIHS2_CR (*(__O uint32_t*)0x40060000U) /**< \brief (TWIHS2) Control Register */
- #define REG_TWIHS2_MMR (*(__IO uint32_t*)0x40060004U) /**< \brief (TWIHS2) Master Mode Register */
- #define REG_TWIHS2_SMR (*(__IO uint32_t*)0x40060008U) /**< \brief (TWIHS2) Slave Mode Register */
- #define REG_TWIHS2_IADR (*(__IO uint32_t*)0x4006000CU) /**< \brief (TWIHS2) Internal Address Register */
- #define REG_TWIHS2_CWGR (*(__IO uint32_t*)0x40060010U) /**< \brief (TWIHS2) Clock Waveform Generator Register */
- #define REG_TWIHS2_SR (*(__I uint32_t*)0x40060020U) /**< \brief (TWIHS2) Status Register */
- #define REG_TWIHS2_IER (*(__O uint32_t*)0x40060024U) /**< \brief (TWIHS2) Interrupt Enable Register */
- #define REG_TWIHS2_IDR (*(__O uint32_t*)0x40060028U) /**< \brief (TWIHS2) Interrupt Disable Register */
- #define REG_TWIHS2_IMR (*(__I uint32_t*)0x4006002CU) /**< \brief (TWIHS2) Interrupt Mask Register */
- #define REG_TWIHS2_RHR (*(__I uint32_t*)0x40060030U) /**< \brief (TWIHS2) Receive Holding Register */
- #define REG_TWIHS2_THR (*(__O uint32_t*)0x40060034U) /**< \brief (TWIHS2) Transmit Holding Register */
- #define REG_TWIHS2_SMBTR (*(__IO uint32_t*)0x40060038U) /**< \brief (TWIHS2) SMBus Timing Register */
- #define REG_TWIHS2_FILTR (*(__IO uint32_t*)0x40060044U) /**< \brief (TWIHS2) Filter Register */
- #define REG_TWIHS2_SWMR (*(__IO uint32_t*)0x4006004CU) /**< \brief (TWIHS2) SleepWalking Matching Register */
- #define REG_TWIHS2_WPMR (*(__IO uint32_t*)0x400600E4U) /**< \brief (TWIHS2) Write Protection Mode Register */
- #define REG_TWIHS2_WPSR (*(__I uint32_t*)0x400600E8U) /**< \brief (TWIHS2) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_TWIHS2_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart0.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart0.h
deleted file mode 100644
index f03845e..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart0.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UART0_INSTANCE_
-#define _SAMS70_UART0_INSTANCE_
-
-/* ========== Register definition for UART0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_UART0_CR (0x400E0800U) /**< \brief (UART0) Control Register */
- #define REG_UART0_MR (0x400E0804U) /**< \brief (UART0) Mode Register */
- #define REG_UART0_IER (0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */
- #define REG_UART0_IDR (0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */
- #define REG_UART0_IMR (0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */
- #define REG_UART0_SR (0x400E0814U) /**< \brief (UART0) Status Register */
- #define REG_UART0_RHR (0x400E0818U) /**< \brief (UART0) Receive Holding Register */
- #define REG_UART0_THR (0x400E081CU) /**< \brief (UART0) Transmit Holding Register */
- #define REG_UART0_BRGR (0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */
- #define REG_UART0_CMPR (0x400E0824U) /**< \brief (UART0) Comparison Register */
- #define REG_UART0_WPMR (0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */
-#else
- #define REG_UART0_CR (*(__O uint32_t*)0x400E0800U) /**< \brief (UART0) Control Register */
- #define REG_UART0_MR (*(__IO uint32_t*)0x400E0804U) /**< \brief (UART0) Mode Register */
- #define REG_UART0_IER (*(__O uint32_t*)0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */
- #define REG_UART0_IDR (*(__O uint32_t*)0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */
- #define REG_UART0_IMR (*(__I uint32_t*)0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */
- #define REG_UART0_SR (*(__I uint32_t*)0x400E0814U) /**< \brief (UART0) Status Register */
- #define REG_UART0_RHR (*(__I uint32_t*)0x400E0818U) /**< \brief (UART0) Receive Holding Register */
- #define REG_UART0_THR (*(__O uint32_t*)0x400E081CU) /**< \brief (UART0) Transmit Holding Register */
- #define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */
- #define REG_UART0_CMPR (*(__IO uint32_t*)0x400E0824U) /**< \brief (UART0) Comparison Register */
- #define REG_UART0_WPMR (*(__IO uint32_t*)0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_UART0_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart1.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart1.h
deleted file mode 100644
index f88ca7f..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart1.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UART1_INSTANCE_
-#define _SAMS70_UART1_INSTANCE_
-
-/* ========== Register definition for UART1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_UART1_CR (0x400E0A00U) /**< \brief (UART1) Control Register */
- #define REG_UART1_MR (0x400E0A04U) /**< \brief (UART1) Mode Register */
- #define REG_UART1_IER (0x400E0A08U) /**< \brief (UART1) Interrupt Enable Register */
- #define REG_UART1_IDR (0x400E0A0CU) /**< \brief (UART1) Interrupt Disable Register */
- #define REG_UART1_IMR (0x400E0A10U) /**< \brief (UART1) Interrupt Mask Register */
- #define REG_UART1_SR (0x400E0A14U) /**< \brief (UART1) Status Register */
- #define REG_UART1_RHR (0x400E0A18U) /**< \brief (UART1) Receive Holding Register */
- #define REG_UART1_THR (0x400E0A1CU) /**< \brief (UART1) Transmit Holding Register */
- #define REG_UART1_BRGR (0x400E0A20U) /**< \brief (UART1) Baud Rate Generator Register */
- #define REG_UART1_CMPR (0x400E0A24U) /**< \brief (UART1) Comparison Register */
- #define REG_UART1_WPMR (0x400E0AE4U) /**< \brief (UART1) Write Protection Mode Register */
-#else
- #define REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) /**< \brief (UART1) Control Register */
- #define REG_UART1_MR (*(__IO uint32_t*)0x400E0A04U) /**< \brief (UART1) Mode Register */
- #define REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) /**< \brief (UART1) Interrupt Enable Register */
- #define REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) /**< \brief (UART1) Interrupt Disable Register */
- #define REG_UART1_IMR (*(__I uint32_t*)0x400E0A10U) /**< \brief (UART1) Interrupt Mask Register */
- #define REG_UART1_SR (*(__I uint32_t*)0x400E0A14U) /**< \brief (UART1) Status Register */
- #define REG_UART1_RHR (*(__I uint32_t*)0x400E0A18U) /**< \brief (UART1) Receive Holding Register */
- #define REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) /**< \brief (UART1) Transmit Holding Register */
- #define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0A20U) /**< \brief (UART1) Baud Rate Generator Register */
- #define REG_UART1_CMPR (*(__IO uint32_t*)0x400E0A24U) /**< \brief (UART1) Comparison Register */
- #define REG_UART1_WPMR (*(__IO uint32_t*)0x400E0AE4U) /**< \brief (UART1) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_UART1_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart2.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart2.h
deleted file mode 100644
index 68d5c0e..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart2.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UART2_INSTANCE_
-#define _SAMS70_UART2_INSTANCE_
-
-/* ========== Register definition for UART2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_UART2_CR (0x400E1A00U) /**< \brief (UART2) Control Register */
- #define REG_UART2_MR (0x400E1A04U) /**< \brief (UART2) Mode Register */
- #define REG_UART2_IER (0x400E1A08U) /**< \brief (UART2) Interrupt Enable Register */
- #define REG_UART2_IDR (0x400E1A0CU) /**< \brief (UART2) Interrupt Disable Register */
- #define REG_UART2_IMR (0x400E1A10U) /**< \brief (UART2) Interrupt Mask Register */
- #define REG_UART2_SR (0x400E1A14U) /**< \brief (UART2) Status Register */
- #define REG_UART2_RHR (0x400E1A18U) /**< \brief (UART2) Receive Holding Register */
- #define REG_UART2_THR (0x400E1A1CU) /**< \brief (UART2) Transmit Holding Register */
- #define REG_UART2_BRGR (0x400E1A20U) /**< \brief (UART2) Baud Rate Generator Register */
- #define REG_UART2_CMPR (0x400E1A24U) /**< \brief (UART2) Comparison Register */
- #define REG_UART2_WPMR (0x400E1AE4U) /**< \brief (UART2) Write Protection Mode Register */
-#else
- #define REG_UART2_CR (*(__O uint32_t*)0x400E1A00U) /**< \brief (UART2) Control Register */
- #define REG_UART2_MR (*(__IO uint32_t*)0x400E1A04U) /**< \brief (UART2) Mode Register */
- #define REG_UART2_IER (*(__O uint32_t*)0x400E1A08U) /**< \brief (UART2) Interrupt Enable Register */
- #define REG_UART2_IDR (*(__O uint32_t*)0x400E1A0CU) /**< \brief (UART2) Interrupt Disable Register */
- #define REG_UART2_IMR (*(__I uint32_t*)0x400E1A10U) /**< \brief (UART2) Interrupt Mask Register */
- #define REG_UART2_SR (*(__I uint32_t*)0x400E1A14U) /**< \brief (UART2) Status Register */
- #define REG_UART2_RHR (*(__I uint32_t*)0x400E1A18U) /**< \brief (UART2) Receive Holding Register */
- #define REG_UART2_THR (*(__O uint32_t*)0x400E1A1CU) /**< \brief (UART2) Transmit Holding Register */
- #define REG_UART2_BRGR (*(__IO uint32_t*)0x400E1A20U) /**< \brief (UART2) Baud Rate Generator Register */
- #define REG_UART2_CMPR (*(__IO uint32_t*)0x400E1A24U) /**< \brief (UART2) Comparison Register */
- #define REG_UART2_WPMR (*(__IO uint32_t*)0x400E1AE4U) /**< \brief (UART2) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_UART2_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart3.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart3.h
deleted file mode 100644
index b519395..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart3.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UART3_INSTANCE_
-#define _SAMS70_UART3_INSTANCE_
-
-/* ========== Register definition for UART3 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_UART3_CR (0x400E1C00U) /**< \brief (UART3) Control Register */
- #define REG_UART3_MR (0x400E1C04U) /**< \brief (UART3) Mode Register */
- #define REG_UART3_IER (0x400E1C08U) /**< \brief (UART3) Interrupt Enable Register */
- #define REG_UART3_IDR (0x400E1C0CU) /**< \brief (UART3) Interrupt Disable Register */
- #define REG_UART3_IMR (0x400E1C10U) /**< \brief (UART3) Interrupt Mask Register */
- #define REG_UART3_SR (0x400E1C14U) /**< \brief (UART3) Status Register */
- #define REG_UART3_RHR (0x400E1C18U) /**< \brief (UART3) Receive Holding Register */
- #define REG_UART3_THR (0x400E1C1CU) /**< \brief (UART3) Transmit Holding Register */
- #define REG_UART3_BRGR (0x400E1C20U) /**< \brief (UART3) Baud Rate Generator Register */
- #define REG_UART3_CMPR (0x400E1C24U) /**< \brief (UART3) Comparison Register */
- #define REG_UART3_WPMR (0x400E1CE4U) /**< \brief (UART3) Write Protection Mode Register */
-#else
- #define REG_UART3_CR (*(__O uint32_t*)0x400E1C00U) /**< \brief (UART3) Control Register */
- #define REG_UART3_MR (*(__IO uint32_t*)0x400E1C04U) /**< \brief (UART3) Mode Register */
- #define REG_UART3_IER (*(__O uint32_t*)0x400E1C08U) /**< \brief (UART3) Interrupt Enable Register */
- #define REG_UART3_IDR (*(__O uint32_t*)0x400E1C0CU) /**< \brief (UART3) Interrupt Disable Register */
- #define REG_UART3_IMR (*(__I uint32_t*)0x400E1C10U) /**< \brief (UART3) Interrupt Mask Register */
- #define REG_UART3_SR (*(__I uint32_t*)0x400E1C14U) /**< \brief (UART3) Status Register */
- #define REG_UART3_RHR (*(__I uint32_t*)0x400E1C18U) /**< \brief (UART3) Receive Holding Register */
- #define REG_UART3_THR (*(__O uint32_t*)0x400E1C1CU) /**< \brief (UART3) Transmit Holding Register */
- #define REG_UART3_BRGR (*(__IO uint32_t*)0x400E1C20U) /**< \brief (UART3) Baud Rate Generator Register */
- #define REG_UART3_CMPR (*(__IO uint32_t*)0x400E1C24U) /**< \brief (UART3) Comparison Register */
- #define REG_UART3_WPMR (*(__IO uint32_t*)0x400E1CE4U) /**< \brief (UART3) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_UART3_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart4.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart4.h
deleted file mode 100644
index c96331c..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/uart4.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UART4_INSTANCE_
-#define _SAMS70_UART4_INSTANCE_
-
-/* ========== Register definition for UART4 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_UART4_CR (0x400E1E00U) /**< \brief (UART4) Control Register */
- #define REG_UART4_MR (0x400E1E04U) /**< \brief (UART4) Mode Register */
- #define REG_UART4_IER (0x400E1E08U) /**< \brief (UART4) Interrupt Enable Register */
- #define REG_UART4_IDR (0x400E1E0CU) /**< \brief (UART4) Interrupt Disable Register */
- #define REG_UART4_IMR (0x400E1E10U) /**< \brief (UART4) Interrupt Mask Register */
- #define REG_UART4_SR (0x400E1E14U) /**< \brief (UART4) Status Register */
- #define REG_UART4_RHR (0x400E1E18U) /**< \brief (UART4) Receive Holding Register */
- #define REG_UART4_THR (0x400E1E1CU) /**< \brief (UART4) Transmit Holding Register */
- #define REG_UART4_BRGR (0x400E1E20U) /**< \brief (UART4) Baud Rate Generator Register */
- #define REG_UART4_CMPR (0x400E1E24U) /**< \brief (UART4) Comparison Register */
- #define REG_UART4_WPMR (0x400E1EE4U) /**< \brief (UART4) Write Protection Mode Register */
-#else
- #define REG_UART4_CR (*(__O uint32_t*)0x400E1E00U) /**< \brief (UART4) Control Register */
- #define REG_UART4_MR (*(__IO uint32_t*)0x400E1E04U) /**< \brief (UART4) Mode Register */
- #define REG_UART4_IER (*(__O uint32_t*)0x400E1E08U) /**< \brief (UART4) Interrupt Enable Register */
- #define REG_UART4_IDR (*(__O uint32_t*)0x400E1E0CU) /**< \brief (UART4) Interrupt Disable Register */
- #define REG_UART4_IMR (*(__I uint32_t*)0x400E1E10U) /**< \brief (UART4) Interrupt Mask Register */
- #define REG_UART4_SR (*(__I uint32_t*)0x400E1E14U) /**< \brief (UART4) Status Register */
- #define REG_UART4_RHR (*(__I uint32_t*)0x400E1E18U) /**< \brief (UART4) Receive Holding Register */
- #define REG_UART4_THR (*(__O uint32_t*)0x400E1E1CU) /**< \brief (UART4) Transmit Holding Register */
- #define REG_UART4_BRGR (*(__IO uint32_t*)0x400E1E20U) /**< \brief (UART4) Baud Rate Generator Register */
- #define REG_UART4_CMPR (*(__IO uint32_t*)0x400E1E24U) /**< \brief (UART4) Comparison Register */
- #define REG_UART4_WPMR (*(__IO uint32_t*)0x400E1EE4U) /**< \brief (UART4) Write Protection Mode Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_UART4_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/usart0.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/usart0.h
deleted file mode 100644
index 2715694..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/usart0.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_USART0_INSTANCE_
-#define _SAMS70_USART0_INSTANCE_
-
-/* ========== Register definition for USART0 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */
- #define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */
- #define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
- #define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
- #define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
- #define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */
- #define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receive Holding Register */
- #define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmit Holding Register */
- #define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
- #define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
- #define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
- #define REG_USART0_MAN (0x40024050U) /**< \brief (USART0) Manchester Configuration Register */
- #define REG_USART0_LINMR (0x40024054U) /**< \brief (USART0) LIN Mode Register */
- #define REG_USART0_LINIR (0x40024058U) /**< \brief (USART0) LIN Identifier Register */
- #define REG_USART0_LINBRR (0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */
- #define REG_USART0_LONMR (0x40024060U) /**< \brief (USART0) LON Mode Register */
- #define REG_USART0_LONPR (0x40024064U) /**< \brief (USART0) LON Preamble Register */
- #define REG_USART0_LONDL (0x40024068U) /**< \brief (USART0) LON Data Length Register */
- #define REG_USART0_LONL2HDR (0x4002406CU) /**< \brief (USART0) LON L2HDR Register */
- #define REG_USART0_LONBL (0x40024070U) /**< \brief (USART0) LON Backlog Register */
- #define REG_USART0_LONB1TX (0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */
- #define REG_USART0_LONB1RX (0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */
- #define REG_USART0_LONPRIO (0x4002407CU) /**< \brief (USART0) LON Priority Register */
- #define REG_USART0_IDTTX (0x40024080U) /**< \brief (USART0) LON IDT Tx Register */
- #define REG_USART0_IDTRX (0x40024084U) /**< \brief (USART0) LON IDT Rx Register */
- #define REG_USART0_ICDIFF (0x40024088U) /**< \brief (USART0) IC DIFF Register */
- #define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */
- #define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protection Status Register */
-#else
- #define REG_USART0_CR (*(__O uint32_t*)0x40024000U) /**< \brief (USART0) Control Register */
- #define REG_USART0_MR (*(__IO uint32_t*)0x40024004U) /**< \brief (USART0) Mode Register */
- #define REG_USART0_IER (*(__O uint32_t*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
- #define REG_USART0_IDR (*(__O uint32_t*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
- #define REG_USART0_IMR (*(__I uint32_t*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
- #define REG_USART0_CSR (*(__I uint32_t*)0x40024014U) /**< \brief (USART0) Channel Status Register */
- #define REG_USART0_RHR (*(__I uint32_t*)0x40024018U) /**< \brief (USART0) Receive Holding Register */
- #define REG_USART0_THR (*(__O uint32_t*)0x4002401CU) /**< \brief (USART0) Transmit Holding Register */
- #define REG_USART0_BRGR (*(__IO uint32_t*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
- #define REG_USART0_RTOR (*(__IO uint32_t*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
- #define REG_USART0_TTGR (*(__IO uint32_t*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
- #define REG_USART0_MAN (*(__IO uint32_t*)0x40024050U) /**< \brief (USART0) Manchester Configuration Register */
- #define REG_USART0_LINMR (*(__IO uint32_t*)0x40024054U) /**< \brief (USART0) LIN Mode Register */
- #define REG_USART0_LINIR (*(__IO uint32_t*)0x40024058U) /**< \brief (USART0) LIN Identifier Register */
- #define REG_USART0_LINBRR (*(__I uint32_t*)0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */
- #define REG_USART0_LONMR (*(__IO uint32_t*)0x40024060U) /**< \brief (USART0) LON Mode Register */
- #define REG_USART0_LONPR (*(__IO uint32_t*)0x40024064U) /**< \brief (USART0) LON Preamble Register */
- #define REG_USART0_LONDL (*(__IO uint32_t*)0x40024068U) /**< \brief (USART0) LON Data Length Register */
- #define REG_USART0_LONL2HDR (*(__IO uint32_t*)0x4002406CU) /**< \brief (USART0) LON L2HDR Register */
- #define REG_USART0_LONBL (*(__I uint32_t*)0x40024070U) /**< \brief (USART0) LON Backlog Register */
- #define REG_USART0_LONB1TX (*(__IO uint32_t*)0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */
- #define REG_USART0_LONB1RX (*(__IO uint32_t*)0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */
- #define REG_USART0_LONPRIO (*(__IO uint32_t*)0x4002407CU) /**< \brief (USART0) LON Priority Register */
- #define REG_USART0_IDTTX (*(__IO uint32_t*)0x40024080U) /**< \brief (USART0) LON IDT Tx Register */
- #define REG_USART0_IDTRX (*(__IO uint32_t*)0x40024084U) /**< \brief (USART0) LON IDT Rx Register */
- #define REG_USART0_ICDIFF (*(__IO uint32_t*)0x40024088U) /**< \brief (USART0) IC DIFF Register */
- #define REG_USART0_WPMR (*(__IO uint32_t*)0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */
- #define REG_USART0_WPSR (*(__I uint32_t*)0x400240E8U) /**< \brief (USART0) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_USART0_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/usart1.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/usart1.h
deleted file mode 100644
index 067f32e..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/usart1.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_USART1_INSTANCE_
-#define _SAMS70_USART1_INSTANCE_
-
-/* ========== Register definition for USART1 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_USART1_CR (0x40028000U) /**< \brief (USART1) Control Register */
- #define REG_USART1_MR (0x40028004U) /**< \brief (USART1) Mode Register */
- #define REG_USART1_IER (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
- #define REG_USART1_IDR (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
- #define REG_USART1_IMR (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
- #define REG_USART1_CSR (0x40028014U) /**< \brief (USART1) Channel Status Register */
- #define REG_USART1_RHR (0x40028018U) /**< \brief (USART1) Receive Holding Register */
- #define REG_USART1_THR (0x4002801CU) /**< \brief (USART1) Transmit Holding Register */
- #define REG_USART1_BRGR (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
- #define REG_USART1_RTOR (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
- #define REG_USART1_TTGR (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
- #define REG_USART1_MAN (0x40028050U) /**< \brief (USART1) Manchester Configuration Register */
- #define REG_USART1_LINMR (0x40028054U) /**< \brief (USART1) LIN Mode Register */
- #define REG_USART1_LINIR (0x40028058U) /**< \brief (USART1) LIN Identifier Register */
- #define REG_USART1_LINBRR (0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */
- #define REG_USART1_LONMR (0x40028060U) /**< \brief (USART1) LON Mode Register */
- #define REG_USART1_LONPR (0x40028064U) /**< \brief (USART1) LON Preamble Register */
- #define REG_USART1_LONDL (0x40028068U) /**< \brief (USART1) LON Data Length Register */
- #define REG_USART1_LONL2HDR (0x4002806CU) /**< \brief (USART1) LON L2HDR Register */
- #define REG_USART1_LONBL (0x40028070U) /**< \brief (USART1) LON Backlog Register */
- #define REG_USART1_LONB1TX (0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */
- #define REG_USART1_LONB1RX (0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */
- #define REG_USART1_LONPRIO (0x4002807CU) /**< \brief (USART1) LON Priority Register */
- #define REG_USART1_IDTTX (0x40028080U) /**< \brief (USART1) LON IDT Tx Register */
- #define REG_USART1_IDTRX (0x40028084U) /**< \brief (USART1) LON IDT Rx Register */
- #define REG_USART1_ICDIFF (0x40028088U) /**< \brief (USART1) IC DIFF Register */
- #define REG_USART1_WPMR (0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */
- #define REG_USART1_WPSR (0x400280E8U) /**< \brief (USART1) Write Protection Status Register */
-#else
- #define REG_USART1_CR (*(__O uint32_t*)0x40028000U) /**< \brief (USART1) Control Register */
- #define REG_USART1_MR (*(__IO uint32_t*)0x40028004U) /**< \brief (USART1) Mode Register */
- #define REG_USART1_IER (*(__O uint32_t*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
- #define REG_USART1_IDR (*(__O uint32_t*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
- #define REG_USART1_IMR (*(__I uint32_t*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
- #define REG_USART1_CSR (*(__I uint32_t*)0x40028014U) /**< \brief (USART1) Channel Status Register */
- #define REG_USART1_RHR (*(__I uint32_t*)0x40028018U) /**< \brief (USART1) Receive Holding Register */
- #define REG_USART1_THR (*(__O uint32_t*)0x4002801CU) /**< \brief (USART1) Transmit Holding Register */
- #define REG_USART1_BRGR (*(__IO uint32_t*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
- #define REG_USART1_RTOR (*(__IO uint32_t*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
- #define REG_USART1_TTGR (*(__IO uint32_t*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
- #define REG_USART1_MAN (*(__IO uint32_t*)0x40028050U) /**< \brief (USART1) Manchester Configuration Register */
- #define REG_USART1_LINMR (*(__IO uint32_t*)0x40028054U) /**< \brief (USART1) LIN Mode Register */
- #define REG_USART1_LINIR (*(__IO uint32_t*)0x40028058U) /**< \brief (USART1) LIN Identifier Register */
- #define REG_USART1_LINBRR (*(__I uint32_t*)0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */
- #define REG_USART1_LONMR (*(__IO uint32_t*)0x40028060U) /**< \brief (USART1) LON Mode Register */
- #define REG_USART1_LONPR (*(__IO uint32_t*)0x40028064U) /**< \brief (USART1) LON Preamble Register */
- #define REG_USART1_LONDL (*(__IO uint32_t*)0x40028068U) /**< \brief (USART1) LON Data Length Register */
- #define REG_USART1_LONL2HDR (*(__IO uint32_t*)0x4002806CU) /**< \brief (USART1) LON L2HDR Register */
- #define REG_USART1_LONBL (*(__I uint32_t*)0x40028070U) /**< \brief (USART1) LON Backlog Register */
- #define REG_USART1_LONB1TX (*(__IO uint32_t*)0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */
- #define REG_USART1_LONB1RX (*(__IO uint32_t*)0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */
- #define REG_USART1_LONPRIO (*(__IO uint32_t*)0x4002807CU) /**< \brief (USART1) LON Priority Register */
- #define REG_USART1_IDTTX (*(__IO uint32_t*)0x40028080U) /**< \brief (USART1) LON IDT Tx Register */
- #define REG_USART1_IDTRX (*(__IO uint32_t*)0x40028084U) /**< \brief (USART1) LON IDT Rx Register */
- #define REG_USART1_ICDIFF (*(__IO uint32_t*)0x40028088U) /**< \brief (USART1) IC DIFF Register */
- #define REG_USART1_WPMR (*(__IO uint32_t*)0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */
- #define REG_USART1_WPSR (*(__I uint32_t*)0x400280E8U) /**< \brief (USART1) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_USART1_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/usart2.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/usart2.h
deleted file mode 100644
index 88c8ce8..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/usart2.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_USART2_INSTANCE_
-#define _SAMS70_USART2_INSTANCE_
-
-/* ========== Register definition for USART2 peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_USART2_CR (0x4002C000U) /**< \brief (USART2) Control Register */
- #define REG_USART2_MR (0x4002C004U) /**< \brief (USART2) Mode Register */
- #define REG_USART2_IER (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
- #define REG_USART2_IDR (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
- #define REG_USART2_IMR (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
- #define REG_USART2_CSR (0x4002C014U) /**< \brief (USART2) Channel Status Register */
- #define REG_USART2_RHR (0x4002C018U) /**< \brief (USART2) Receive Holding Register */
- #define REG_USART2_THR (0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */
- #define REG_USART2_BRGR (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
- #define REG_USART2_RTOR (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
- #define REG_USART2_TTGR (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
- #define REG_USART2_MAN (0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */
- #define REG_USART2_LINMR (0x4002C054U) /**< \brief (USART2) LIN Mode Register */
- #define REG_USART2_LINIR (0x4002C058U) /**< \brief (USART2) LIN Identifier Register */
- #define REG_USART2_LINBRR (0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */
- #define REG_USART2_LONMR (0x4002C060U) /**< \brief (USART2) LON Mode Register */
- #define REG_USART2_LONPR (0x4002C064U) /**< \brief (USART2) LON Preamble Register */
- #define REG_USART2_LONDL (0x4002C068U) /**< \brief (USART2) LON Data Length Register */
- #define REG_USART2_LONL2HDR (0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */
- #define REG_USART2_LONBL (0x4002C070U) /**< \brief (USART2) LON Backlog Register */
- #define REG_USART2_LONB1TX (0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */
- #define REG_USART2_LONB1RX (0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */
- #define REG_USART2_LONPRIO (0x4002C07CU) /**< \brief (USART2) LON Priority Register */
- #define REG_USART2_IDTTX (0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */
- #define REG_USART2_IDTRX (0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */
- #define REG_USART2_ICDIFF (0x4002C088U) /**< \brief (USART2) IC DIFF Register */
- #define REG_USART2_WPMR (0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */
- #define REG_USART2_WPSR (0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */
-#else
- #define REG_USART2_CR (*(__O uint32_t*)0x4002C000U) /**< \brief (USART2) Control Register */
- #define REG_USART2_MR (*(__IO uint32_t*)0x4002C004U) /**< \brief (USART2) Mode Register */
- #define REG_USART2_IER (*(__O uint32_t*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
- #define REG_USART2_IDR (*(__O uint32_t*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
- #define REG_USART2_IMR (*(__I uint32_t*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
- #define REG_USART2_CSR (*(__I uint32_t*)0x4002C014U) /**< \brief (USART2) Channel Status Register */
- #define REG_USART2_RHR (*(__I uint32_t*)0x4002C018U) /**< \brief (USART2) Receive Holding Register */
- #define REG_USART2_THR (*(__O uint32_t*)0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */
- #define REG_USART2_BRGR (*(__IO uint32_t*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
- #define REG_USART2_RTOR (*(__IO uint32_t*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
- #define REG_USART2_TTGR (*(__IO uint32_t*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
- #define REG_USART2_MAN (*(__IO uint32_t*)0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */
- #define REG_USART2_LINMR (*(__IO uint32_t*)0x4002C054U) /**< \brief (USART2) LIN Mode Register */
- #define REG_USART2_LINIR (*(__IO uint32_t*)0x4002C058U) /**< \brief (USART2) LIN Identifier Register */
- #define REG_USART2_LINBRR (*(__I uint32_t*)0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */
- #define REG_USART2_LONMR (*(__IO uint32_t*)0x4002C060U) /**< \brief (USART2) LON Mode Register */
- #define REG_USART2_LONPR (*(__IO uint32_t*)0x4002C064U) /**< \brief (USART2) LON Preamble Register */
- #define REG_USART2_LONDL (*(__IO uint32_t*)0x4002C068U) /**< \brief (USART2) LON Data Length Register */
- #define REG_USART2_LONL2HDR (*(__IO uint32_t*)0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */
- #define REG_USART2_LONBL (*(__I uint32_t*)0x4002C070U) /**< \brief (USART2) LON Backlog Register */
- #define REG_USART2_LONB1TX (*(__IO uint32_t*)0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */
- #define REG_USART2_LONB1RX (*(__IO uint32_t*)0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */
- #define REG_USART2_LONPRIO (*(__IO uint32_t*)0x4002C07CU) /**< \brief (USART2) LON Priority Register */
- #define REG_USART2_IDTTX (*(__IO uint32_t*)0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */
- #define REG_USART2_IDTRX (*(__IO uint32_t*)0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */
- #define REG_USART2_ICDIFF (*(__IO uint32_t*)0x4002C088U) /**< \brief (USART2) IC DIFF Register */
- #define REG_USART2_WPMR (*(__IO uint32_t*)0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */
- #define REG_USART2_WPSR (*(__I uint32_t*)0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_USART2_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/usbhs.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/usbhs.h
deleted file mode 100644
index 39b7629..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/usbhs.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_USBHS_INSTANCE_
-#define _SAMS70_USBHS_INSTANCE_
-
-/* ========== Register definition for USBHS peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_USBHS_DEVCTRL (0x40038000U) /**< \brief (USBHS) Device General Control Register */
- #define REG_USBHS_DEVISR (0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */
- #define REG_USBHS_DEVICR (0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */
- #define REG_USBHS_DEVIFR (0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */
- #define REG_USBHS_DEVIMR (0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */
- #define REG_USBHS_DEVIDR (0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */
- #define REG_USBHS_DEVIER (0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */
- #define REG_USBHS_DEVEPT (0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */
- #define REG_USBHS_DEVFNUM (0x40038020U) /**< \brief (USBHS) Device Frame Number Register */
- #define REG_USBHS_DEVEPTCFG (0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */
- #define REG_USBHS_DEVEPTISR (0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */
- #define REG_USBHS_DEVEPTICR (0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */
- #define REG_USBHS_DEVEPTIFR (0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */
- #define REG_USBHS_DEVEPTIMR (0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */
- #define REG_USBHS_DEVEPTIER (0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */
- #define REG_USBHS_DEVEPTIDR (0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */
- #define REG_USBHS_DEVDMANXTDSC1 (0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */
- #define REG_USBHS_DEVDMAADDRESS1 (0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */
- #define REG_USBHS_DEVDMACONTROL1 (0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */
- #define REG_USBHS_DEVDMASTATUS1 (0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */
- #define REG_USBHS_DEVDMANXTDSC2 (0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */
- #define REG_USBHS_DEVDMAADDRESS2 (0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */
- #define REG_USBHS_DEVDMACONTROL2 (0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */
- #define REG_USBHS_DEVDMASTATUS2 (0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */
- #define REG_USBHS_DEVDMANXTDSC3 (0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */
- #define REG_USBHS_DEVDMAADDRESS3 (0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */
- #define REG_USBHS_DEVDMACONTROL3 (0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */
- #define REG_USBHS_DEVDMASTATUS3 (0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */
- #define REG_USBHS_DEVDMANXTDSC4 (0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */
- #define REG_USBHS_DEVDMAADDRESS4 (0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */
- #define REG_USBHS_DEVDMACONTROL4 (0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */
- #define REG_USBHS_DEVDMASTATUS4 (0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */
- #define REG_USBHS_DEVDMANXTDSC5 (0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */
- #define REG_USBHS_DEVDMAADDRESS5 (0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */
- #define REG_USBHS_DEVDMACONTROL5 (0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */
- #define REG_USBHS_DEVDMASTATUS5 (0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */
- #define REG_USBHS_DEVDMANXTDSC6 (0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */
- #define REG_USBHS_DEVDMAADDRESS6 (0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */
- #define REG_USBHS_DEVDMACONTROL6 (0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */
- #define REG_USBHS_DEVDMASTATUS6 (0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */
- #define REG_USBHS_DEVDMANXTDSC7 (0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */
- #define REG_USBHS_DEVDMAADDRESS7 (0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */
- #define REG_USBHS_DEVDMACONTROL7 (0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */
- #define REG_USBHS_DEVDMASTATUS7 (0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */
- #define REG_USBHS_HSTCTRL (0x40038400U) /**< \brief (USBHS) Host General Control Register */
- #define REG_USBHS_HSTISR (0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */
- #define REG_USBHS_HSTICR (0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */
- #define REG_USBHS_HSTIFR (0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */
- #define REG_USBHS_HSTIMR (0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */
- #define REG_USBHS_HSTIDR (0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */
- #define REG_USBHS_HSTIER (0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */
- #define REG_USBHS_HSTPIP (0x4003841CU) /**< \brief (USBHS) Host Pipe Register */
- #define REG_USBHS_HSTFNUM (0x40038420U) /**< \brief (USBHS) Host Frame Number Register */
- #define REG_USBHS_HSTADDR1 (0x40038424U) /**< \brief (USBHS) Host Address 1 Register */
- #define REG_USBHS_HSTADDR2 (0x40038428U) /**< \brief (USBHS) Host Address 2 Register */
- #define REG_USBHS_HSTADDR3 (0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */
- #define REG_USBHS_HSTPIPCFG (0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */
- #define REG_USBHS_HSTPIPISR (0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */
- #define REG_USBHS_HSTPIPICR (0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */
- #define REG_USBHS_HSTPIPIFR (0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */
- #define REG_USBHS_HSTPIPIMR (0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */
- #define REG_USBHS_HSTPIPIER (0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */
- #define REG_USBHS_HSTPIPIDR (0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */
- #define REG_USBHS_HSTPIPINRQ (0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */
- #define REG_USBHS_HSTPIPERR (0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */
- #define REG_USBHS_HSTDMANXTDSC1 (0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */
- #define REG_USBHS_HSTDMAADDRESS1 (0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */
- #define REG_USBHS_HSTDMACONTROL1 (0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */
- #define REG_USBHS_HSTDMASTATUS1 (0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */
- #define REG_USBHS_HSTDMANXTDSC2 (0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */
- #define REG_USBHS_HSTDMAADDRESS2 (0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */
- #define REG_USBHS_HSTDMACONTROL2 (0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */
- #define REG_USBHS_HSTDMASTATUS2 (0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */
- #define REG_USBHS_HSTDMANXTDSC3 (0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */
- #define REG_USBHS_HSTDMAADDRESS3 (0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */
- #define REG_USBHS_HSTDMACONTROL3 (0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */
- #define REG_USBHS_HSTDMASTATUS3 (0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */
- #define REG_USBHS_HSTDMANXTDSC4 (0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */
- #define REG_USBHS_HSTDMAADDRESS4 (0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */
- #define REG_USBHS_HSTDMACONTROL4 (0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */
- #define REG_USBHS_HSTDMASTATUS4 (0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */
- #define REG_USBHS_HSTDMANXTDSC5 (0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */
- #define REG_USBHS_HSTDMAADDRESS5 (0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */
- #define REG_USBHS_HSTDMACONTROL5 (0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */
- #define REG_USBHS_HSTDMASTATUS5 (0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */
- #define REG_USBHS_HSTDMANXTDSC6 (0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */
- #define REG_USBHS_HSTDMAADDRESS6 (0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */
- #define REG_USBHS_HSTDMACONTROL6 (0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */
- #define REG_USBHS_HSTDMASTATUS6 (0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */
- #define REG_USBHS_HSTDMANXTDSC7 (0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */
- #define REG_USBHS_HSTDMAADDRESS7 (0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */
- #define REG_USBHS_HSTDMACONTROL7 (0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */
- #define REG_USBHS_HSTDMASTATUS7 (0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */
- #define REG_USBHS_CTRL (0x40038800U) /**< \brief (USBHS) General Control Register */
- #define REG_USBHS_SR (0x40038804U) /**< \brief (USBHS) General Status Register */
- #define REG_USBHS_SCR (0x40038808U) /**< \brief (USBHS) General Status Clear Register */
- #define REG_USBHS_SFR (0x4003880CU) /**< \brief (USBHS) General Status Set Register */
- #define REG_USBHS_TSTA1 (0x40038810U) /**< \brief (USBHS) General Test A1 Register */
- #define REG_USBHS_TSTA2 (0x40038814U) /**< \brief (USBHS) General Test A2 Register */
- #define REG_USBHS_VERSION (0x40038818U) /**< \brief (USBHS) General Version Register */
- #define REG_USBHS_FSM (0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */
-#else
- #define REG_USBHS_DEVCTRL (*(__IO uint32_t*)0x40038000U) /**< \brief (USBHS) Device General Control Register */
- #define REG_USBHS_DEVISR (*(__I uint32_t*)0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */
- #define REG_USBHS_DEVICR (*(__O uint32_t*)0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */
- #define REG_USBHS_DEVIFR (*(__O uint32_t*)0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */
- #define REG_USBHS_DEVIMR (*(__I uint32_t*)0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */
- #define REG_USBHS_DEVIDR (*(__O uint32_t*)0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */
- #define REG_USBHS_DEVIER (*(__O uint32_t*)0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */
- #define REG_USBHS_DEVEPT (*(__IO uint32_t*)0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */
- #define REG_USBHS_DEVFNUM (*(__I uint32_t*)0x40038020U) /**< \brief (USBHS) Device Frame Number Register */
- #define REG_USBHS_DEVEPTCFG (*(__IO uint32_t*)0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */
- #define REG_USBHS_DEVEPTISR (*(__I uint32_t*)0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */
- #define REG_USBHS_DEVEPTICR (*(__O uint32_t*)0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */
- #define REG_USBHS_DEVEPTIFR (*(__O uint32_t*)0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */
- #define REG_USBHS_DEVEPTIMR (*(__I uint32_t*)0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */
- #define REG_USBHS_DEVEPTIER (*(__O uint32_t*)0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */
- #define REG_USBHS_DEVEPTIDR (*(__O uint32_t*)0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */
- #define REG_USBHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */
- #define REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */
- #define REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */
- #define REG_USBHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */
- #define REG_USBHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */
- #define REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */
- #define REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */
- #define REG_USBHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */
- #define REG_USBHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */
- #define REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */
- #define REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */
- #define REG_USBHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */
- #define REG_USBHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */
- #define REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */
- #define REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */
- #define REG_USBHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */
- #define REG_USBHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */
- #define REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */
- #define REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */
- #define REG_USBHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */
- #define REG_USBHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */
- #define REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */
- #define REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */
- #define REG_USBHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */
- #define REG_USBHS_DEVDMANXTDSC7 (*(__IO uint32_t*)0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */
- #define REG_USBHS_DEVDMAADDRESS7 (*(__IO uint32_t*)0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */
- #define REG_USBHS_DEVDMACONTROL7 (*(__IO uint32_t*)0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */
- #define REG_USBHS_DEVDMASTATUS7 (*(__IO uint32_t*)0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */
- #define REG_USBHS_HSTCTRL (*(__IO uint32_t*)0x40038400U) /**< \brief (USBHS) Host General Control Register */
- #define REG_USBHS_HSTISR (*(__I uint32_t*)0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */
- #define REG_USBHS_HSTICR (*(__O uint32_t*)0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */
- #define REG_USBHS_HSTIFR (*(__O uint32_t*)0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */
- #define REG_USBHS_HSTIMR (*(__I uint32_t*)0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */
- #define REG_USBHS_HSTIDR (*(__O uint32_t*)0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */
- #define REG_USBHS_HSTIER (*(__O uint32_t*)0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */
- #define REG_USBHS_HSTPIP (*(__IO uint32_t*)0x4003841CU) /**< \brief (USBHS) Host Pipe Register */
- #define REG_USBHS_HSTFNUM (*(__IO uint32_t*)0x40038420U) /**< \brief (USBHS) Host Frame Number Register */
- #define REG_USBHS_HSTADDR1 (*(__IO uint32_t*)0x40038424U) /**< \brief (USBHS) Host Address 1 Register */
- #define REG_USBHS_HSTADDR2 (*(__IO uint32_t*)0x40038428U) /**< \brief (USBHS) Host Address 2 Register */
- #define REG_USBHS_HSTADDR3 (*(__IO uint32_t*)0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */
- #define REG_USBHS_HSTPIPCFG (*(__IO uint32_t*)0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */
- #define REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */
- #define REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */
- #define REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */
- #define REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */
- #define REG_USBHS_HSTPIPIER (*(__O uint32_t*)0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */
- #define REG_USBHS_HSTPIPIDR (*(__O uint32_t*)0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */
- #define REG_USBHS_HSTPIPINRQ (*(__IO uint32_t*)0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */
- #define REG_USBHS_HSTPIPERR (*(__IO uint32_t*)0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */
- #define REG_USBHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */
- #define REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */
- #define REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */
- #define REG_USBHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */
- #define REG_USBHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */
- #define REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */
- #define REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */
- #define REG_USBHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */
- #define REG_USBHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */
- #define REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */
- #define REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */
- #define REG_USBHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */
- #define REG_USBHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */
- #define REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */
- #define REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */
- #define REG_USBHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */
- #define REG_USBHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */
- #define REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */
- #define REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */
- #define REG_USBHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */
- #define REG_USBHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */
- #define REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */
- #define REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */
- #define REG_USBHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */
- #define REG_USBHS_HSTDMANXTDSC7 (*(__IO uint32_t*)0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */
- #define REG_USBHS_HSTDMAADDRESS7 (*(__IO uint32_t*)0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */
- #define REG_USBHS_HSTDMACONTROL7 (*(__IO uint32_t*)0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */
- #define REG_USBHS_HSTDMASTATUS7 (*(__IO uint32_t*)0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */
- #define REG_USBHS_CTRL (*(__IO uint32_t*)0x40038800U) /**< \brief (USBHS) General Control Register */
- #define REG_USBHS_SR (*(__I uint32_t*)0x40038804U) /**< \brief (USBHS) General Status Register */
- #define REG_USBHS_SCR (*(__O uint32_t*)0x40038808U) /**< \brief (USBHS) General Status Clear Register */
- #define REG_USBHS_SFR (*(__O uint32_t*)0x4003880CU) /**< \brief (USBHS) General Status Set Register */
- #define REG_USBHS_TSTA1 (*(__IO uint32_t*)0x40038810U) /**< \brief (USBHS) General Test A1 Register */
- #define REG_USBHS_TSTA2 (*(__IO uint32_t*)0x40038814U) /**< \brief (USBHS) General Test A2 Register */
- #define REG_USBHS_VERSION (*(__I uint32_t*)0x40038818U) /**< \brief (USBHS) General Version Register */
- #define REG_USBHS_FSM (*(__I uint32_t*)0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_USBHS_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/utmi.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/utmi.h
deleted file mode 100644
index daf3766..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/utmi.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_UTMI_INSTANCE_
-#define _SAMS70_UTMI_INSTANCE_
-
-/* ========== Register definition for UTMI peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_UTMI_OHCIICR (0x400E0410U) /**< \brief (UTMI) OHCI Interrupt Configuration Register */
- #define REG_UTMI_CKTRIM (0x400E0430U) /**< \brief (UTMI) UTMI Clock Trimming Register */
-#else
- #define REG_UTMI_OHCIICR (*(__IO uint32_t*)0x400E0410U) /**< \brief (UTMI) OHCI Interrupt Configuration Register */
- #define REG_UTMI_CKTRIM (*(__IO uint32_t*)0x400E0430U) /**< \brief (UTMI) UTMI Clock Trimming Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_UTMI_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/wdt.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/wdt.h
deleted file mode 100644
index 963c644..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/wdt.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_WDT_INSTANCE_
-#define _SAMS70_WDT_INSTANCE_
-
-/* ========== Register definition for WDT peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_WDT_CR (0x400E1850U) /**< \brief (WDT) Control Register */
- #define REG_WDT_MR (0x400E1854U) /**< \brief (WDT) Mode Register */
- #define REG_WDT_SR (0x400E1858U) /**< \brief (WDT) Status Register */
-#else
- #define REG_WDT_CR (*(__O uint32_t*)0x400E1850U) /**< \brief (WDT) Control Register */
- #define REG_WDT_MR (*(__IO uint32_t*)0x400E1854U) /**< \brief (WDT) Mode Register */
- #define REG_WDT_SR (*(__I uint32_t*)0x400E1858U) /**< \brief (WDT) Status Register */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_WDT_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/xdmac.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/xdmac.h
deleted file mode 100644
index b6a043b..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/instance/xdmac.h
+++ /dev/null
@@ -1,759 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70_XDMAC_INSTANCE_
-#define _SAMS70_XDMAC_INSTANCE_
-
-/* ========== Register definition for XDMAC peripheral ========== */
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_XDMAC_GTYPE (0x40078000U) /**< \brief (XDMAC) Global Type Register */
- #define REG_XDMAC_GCFG (0x40078004U) /**< \brief (XDMAC) Global Configuration Register */
- #define REG_XDMAC_GWAC (0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */
- #define REG_XDMAC_GIE (0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */
- #define REG_XDMAC_GID (0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */
- #define REG_XDMAC_GIM (0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */
- #define REG_XDMAC_GIS (0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */
- #define REG_XDMAC_GE (0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */
- #define REG_XDMAC_GD (0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */
- #define REG_XDMAC_GS (0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */
- #define REG_XDMAC_GRS (0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */
- #define REG_XDMAC_GWS (0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */
- #define REG_XDMAC_GRWS (0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */
- #define REG_XDMAC_GRWR (0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */
- #define REG_XDMAC_GSWR (0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */
- #define REG_XDMAC_GSWS (0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */
- #define REG_XDMAC_GSWF (0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */
- #define REG_XDMAC_CIE0 (0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */
- #define REG_XDMAC_CID0 (0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */
- #define REG_XDMAC_CIM0 (0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */
- #define REG_XDMAC_CIS0 (0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */
- #define REG_XDMAC_CSA0 (0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */
- #define REG_XDMAC_CDA0 (0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */
- #define REG_XDMAC_CNDA0 (0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */
- #define REG_XDMAC_CNDC0 (0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */
- #define REG_XDMAC_CUBC0 (0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */
- #define REG_XDMAC_CBC0 (0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */
- #define REG_XDMAC_CC0 (0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */
- #define REG_XDMAC_CDS_MSP0 (0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */
- #define REG_XDMAC_CSUS0 (0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */
- #define REG_XDMAC_CDUS0 (0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */
- #define REG_XDMAC_CIE1 (0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */
- #define REG_XDMAC_CID1 (0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */
- #define REG_XDMAC_CIM1 (0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */
- #define REG_XDMAC_CIS1 (0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */
- #define REG_XDMAC_CSA1 (0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */
- #define REG_XDMAC_CDA1 (0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */
- #define REG_XDMAC_CNDA1 (0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */
- #define REG_XDMAC_CNDC1 (0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */
- #define REG_XDMAC_CUBC1 (0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */
- #define REG_XDMAC_CBC1 (0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */
- #define REG_XDMAC_CC1 (0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */
- #define REG_XDMAC_CDS_MSP1 (0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */
- #define REG_XDMAC_CSUS1 (0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */
- #define REG_XDMAC_CDUS1 (0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */
- #define REG_XDMAC_CIE2 (0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */
- #define REG_XDMAC_CID2 (0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */
- #define REG_XDMAC_CIM2 (0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */
- #define REG_XDMAC_CIS2 (0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */
- #define REG_XDMAC_CSA2 (0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */
- #define REG_XDMAC_CDA2 (0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */
- #define REG_XDMAC_CNDA2 (0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */
- #define REG_XDMAC_CNDC2 (0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */
- #define REG_XDMAC_CUBC2 (0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */
- #define REG_XDMAC_CBC2 (0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */
- #define REG_XDMAC_CC2 (0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */
- #define REG_XDMAC_CDS_MSP2 (0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */
- #define REG_XDMAC_CSUS2 (0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */
- #define REG_XDMAC_CDUS2 (0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */
- #define REG_XDMAC_CIE3 (0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */
- #define REG_XDMAC_CID3 (0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */
- #define REG_XDMAC_CIM3 (0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */
- #define REG_XDMAC_CIS3 (0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */
- #define REG_XDMAC_CSA3 (0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */
- #define REG_XDMAC_CDA3 (0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */
- #define REG_XDMAC_CNDA3 (0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */
- #define REG_XDMAC_CNDC3 (0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */
- #define REG_XDMAC_CUBC3 (0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */
- #define REG_XDMAC_CBC3 (0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */
- #define REG_XDMAC_CC3 (0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */
- #define REG_XDMAC_CDS_MSP3 (0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */
- #define REG_XDMAC_CSUS3 (0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */
- #define REG_XDMAC_CDUS3 (0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */
- #define REG_XDMAC_CIE4 (0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */
- #define REG_XDMAC_CID4 (0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */
- #define REG_XDMAC_CIM4 (0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */
- #define REG_XDMAC_CIS4 (0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */
- #define REG_XDMAC_CSA4 (0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */
- #define REG_XDMAC_CDA4 (0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */
- #define REG_XDMAC_CNDA4 (0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */
- #define REG_XDMAC_CNDC4 (0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */
- #define REG_XDMAC_CUBC4 (0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */
- #define REG_XDMAC_CBC4 (0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */
- #define REG_XDMAC_CC4 (0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */
- #define REG_XDMAC_CDS_MSP4 (0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */
- #define REG_XDMAC_CSUS4 (0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */
- #define REG_XDMAC_CDUS4 (0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */
- #define REG_XDMAC_CIE5 (0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */
- #define REG_XDMAC_CID5 (0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */
- #define REG_XDMAC_CIM5 (0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */
- #define REG_XDMAC_CIS5 (0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */
- #define REG_XDMAC_CSA5 (0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */
- #define REG_XDMAC_CDA5 (0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */
- #define REG_XDMAC_CNDA5 (0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */
- #define REG_XDMAC_CNDC5 (0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */
- #define REG_XDMAC_CUBC5 (0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */
- #define REG_XDMAC_CBC5 (0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */
- #define REG_XDMAC_CC5 (0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */
- #define REG_XDMAC_CDS_MSP5 (0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */
- #define REG_XDMAC_CSUS5 (0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */
- #define REG_XDMAC_CDUS5 (0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */
- #define REG_XDMAC_CIE6 (0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */
- #define REG_XDMAC_CID6 (0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */
- #define REG_XDMAC_CIM6 (0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */
- #define REG_XDMAC_CIS6 (0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */
- #define REG_XDMAC_CSA6 (0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */
- #define REG_XDMAC_CDA6 (0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */
- #define REG_XDMAC_CNDA6 (0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */
- #define REG_XDMAC_CNDC6 (0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */
- #define REG_XDMAC_CUBC6 (0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */
- #define REG_XDMAC_CBC6 (0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */
- #define REG_XDMAC_CC6 (0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */
- #define REG_XDMAC_CDS_MSP6 (0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */
- #define REG_XDMAC_CSUS6 (0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */
- #define REG_XDMAC_CDUS6 (0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */
- #define REG_XDMAC_CIE7 (0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */
- #define REG_XDMAC_CID7 (0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */
- #define REG_XDMAC_CIM7 (0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */
- #define REG_XDMAC_CIS7 (0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */
- #define REG_XDMAC_CSA7 (0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */
- #define REG_XDMAC_CDA7 (0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */
- #define REG_XDMAC_CNDA7 (0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */
- #define REG_XDMAC_CNDC7 (0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */
- #define REG_XDMAC_CUBC7 (0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */
- #define REG_XDMAC_CBC7 (0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */
- #define REG_XDMAC_CC7 (0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */
- #define REG_XDMAC_CDS_MSP7 (0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */
- #define REG_XDMAC_CSUS7 (0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */
- #define REG_XDMAC_CDUS7 (0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */
- #define REG_XDMAC_CIE8 (0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */
- #define REG_XDMAC_CID8 (0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */
- #define REG_XDMAC_CIM8 (0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */
- #define REG_XDMAC_CIS8 (0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */
- #define REG_XDMAC_CSA8 (0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */
- #define REG_XDMAC_CDA8 (0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */
- #define REG_XDMAC_CNDA8 (0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */
- #define REG_XDMAC_CNDC8 (0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */
- #define REG_XDMAC_CUBC8 (0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */
- #define REG_XDMAC_CBC8 (0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */
- #define REG_XDMAC_CC8 (0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */
- #define REG_XDMAC_CDS_MSP8 (0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */
- #define REG_XDMAC_CSUS8 (0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */
- #define REG_XDMAC_CDUS8 (0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */
- #define REG_XDMAC_CIE9 (0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */
- #define REG_XDMAC_CID9 (0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */
- #define REG_XDMAC_CIM9 (0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */
- #define REG_XDMAC_CIS9 (0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */
- #define REG_XDMAC_CSA9 (0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */
- #define REG_XDMAC_CDA9 (0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */
- #define REG_XDMAC_CNDA9 (0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */
- #define REG_XDMAC_CNDC9 (0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */
- #define REG_XDMAC_CUBC9 (0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */
- #define REG_XDMAC_CBC9 (0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */
- #define REG_XDMAC_CC9 (0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */
- #define REG_XDMAC_CDS_MSP9 (0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */
- #define REG_XDMAC_CSUS9 (0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */
- #define REG_XDMAC_CDUS9 (0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */
- #define REG_XDMAC_CIE10 (0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */
- #define REG_XDMAC_CID10 (0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */
- #define REG_XDMAC_CIM10 (0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */
- #define REG_XDMAC_CIS10 (0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */
- #define REG_XDMAC_CSA10 (0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */
- #define REG_XDMAC_CDA10 (0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */
- #define REG_XDMAC_CNDA10 (0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */
- #define REG_XDMAC_CNDC10 (0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */
- #define REG_XDMAC_CUBC10 (0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */
- #define REG_XDMAC_CBC10 (0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */
- #define REG_XDMAC_CC10 (0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */
- #define REG_XDMAC_CDS_MSP10 (0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */
- #define REG_XDMAC_CSUS10 (0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */
- #define REG_XDMAC_CDUS10 (0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */
- #define REG_XDMAC_CIE11 (0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */
- #define REG_XDMAC_CID11 (0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */
- #define REG_XDMAC_CIM11 (0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */
- #define REG_XDMAC_CIS11 (0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */
- #define REG_XDMAC_CSA11 (0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */
- #define REG_XDMAC_CDA11 (0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */
- #define REG_XDMAC_CNDA11 (0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */
- #define REG_XDMAC_CNDC11 (0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */
- #define REG_XDMAC_CUBC11 (0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */
- #define REG_XDMAC_CBC11 (0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */
- #define REG_XDMAC_CC11 (0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */
- #define REG_XDMAC_CDS_MSP11 (0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */
- #define REG_XDMAC_CSUS11 (0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */
- #define REG_XDMAC_CDUS11 (0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */
- #define REG_XDMAC_CIE12 (0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */
- #define REG_XDMAC_CID12 (0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */
- #define REG_XDMAC_CIM12 (0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */
- #define REG_XDMAC_CIS12 (0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */
- #define REG_XDMAC_CSA12 (0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */
- #define REG_XDMAC_CDA12 (0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */
- #define REG_XDMAC_CNDA12 (0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */
- #define REG_XDMAC_CNDC12 (0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */
- #define REG_XDMAC_CUBC12 (0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */
- #define REG_XDMAC_CBC12 (0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */
- #define REG_XDMAC_CC12 (0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */
- #define REG_XDMAC_CDS_MSP12 (0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */
- #define REG_XDMAC_CSUS12 (0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */
- #define REG_XDMAC_CDUS12 (0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */
- #define REG_XDMAC_CIE13 (0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */
- #define REG_XDMAC_CID13 (0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */
- #define REG_XDMAC_CIM13 (0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */
- #define REG_XDMAC_CIS13 (0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */
- #define REG_XDMAC_CSA13 (0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */
- #define REG_XDMAC_CDA13 (0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */
- #define REG_XDMAC_CNDA13 (0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */
- #define REG_XDMAC_CNDC13 (0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */
- #define REG_XDMAC_CUBC13 (0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */
- #define REG_XDMAC_CBC13 (0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */
- #define REG_XDMAC_CC13 (0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */
- #define REG_XDMAC_CDS_MSP13 (0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */
- #define REG_XDMAC_CSUS13 (0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */
- #define REG_XDMAC_CDUS13 (0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */
- #define REG_XDMAC_CIE14 (0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */
- #define REG_XDMAC_CID14 (0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */
- #define REG_XDMAC_CIM14 (0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */
- #define REG_XDMAC_CIS14 (0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */
- #define REG_XDMAC_CSA14 (0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */
- #define REG_XDMAC_CDA14 (0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */
- #define REG_XDMAC_CNDA14 (0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */
- #define REG_XDMAC_CNDC14 (0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */
- #define REG_XDMAC_CUBC14 (0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */
- #define REG_XDMAC_CBC14 (0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */
- #define REG_XDMAC_CC14 (0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */
- #define REG_XDMAC_CDS_MSP14 (0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */
- #define REG_XDMAC_CSUS14 (0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */
- #define REG_XDMAC_CDUS14 (0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */
- #define REG_XDMAC_CIE15 (0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */
- #define REG_XDMAC_CID15 (0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */
- #define REG_XDMAC_CIM15 (0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */
- #define REG_XDMAC_CIS15 (0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */
- #define REG_XDMAC_CSA15 (0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */
- #define REG_XDMAC_CDA15 (0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */
- #define REG_XDMAC_CNDA15 (0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */
- #define REG_XDMAC_CNDC15 (0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */
- #define REG_XDMAC_CUBC15 (0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */
- #define REG_XDMAC_CBC15 (0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */
- #define REG_XDMAC_CC15 (0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */
- #define REG_XDMAC_CDS_MSP15 (0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */
- #define REG_XDMAC_CSUS15 (0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */
- #define REG_XDMAC_CDUS15 (0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */
- #define REG_XDMAC_CIE16 (0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */
- #define REG_XDMAC_CID16 (0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */
- #define REG_XDMAC_CIM16 (0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */
- #define REG_XDMAC_CIS16 (0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */
- #define REG_XDMAC_CSA16 (0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */
- #define REG_XDMAC_CDA16 (0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */
- #define REG_XDMAC_CNDA16 (0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */
- #define REG_XDMAC_CNDC16 (0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */
- #define REG_XDMAC_CUBC16 (0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */
- #define REG_XDMAC_CBC16 (0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */
- #define REG_XDMAC_CC16 (0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */
- #define REG_XDMAC_CDS_MSP16 (0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */
- #define REG_XDMAC_CSUS16 (0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */
- #define REG_XDMAC_CDUS16 (0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */
- #define REG_XDMAC_CIE17 (0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */
- #define REG_XDMAC_CID17 (0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */
- #define REG_XDMAC_CIM17 (0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */
- #define REG_XDMAC_CIS17 (0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */
- #define REG_XDMAC_CSA17 (0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */
- #define REG_XDMAC_CDA17 (0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */
- #define REG_XDMAC_CNDA17 (0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */
- #define REG_XDMAC_CNDC17 (0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */
- #define REG_XDMAC_CUBC17 (0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */
- #define REG_XDMAC_CBC17 (0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */
- #define REG_XDMAC_CC17 (0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */
- #define REG_XDMAC_CDS_MSP17 (0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */
- #define REG_XDMAC_CSUS17 (0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */
- #define REG_XDMAC_CDUS17 (0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */
- #define REG_XDMAC_CIE18 (0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */
- #define REG_XDMAC_CID18 (0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */
- #define REG_XDMAC_CIM18 (0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */
- #define REG_XDMAC_CIS18 (0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */
- #define REG_XDMAC_CSA18 (0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */
- #define REG_XDMAC_CDA18 (0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */
- #define REG_XDMAC_CNDA18 (0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */
- #define REG_XDMAC_CNDC18 (0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */
- #define REG_XDMAC_CUBC18 (0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */
- #define REG_XDMAC_CBC18 (0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */
- #define REG_XDMAC_CC18 (0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */
- #define REG_XDMAC_CDS_MSP18 (0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */
- #define REG_XDMAC_CSUS18 (0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */
- #define REG_XDMAC_CDUS18 (0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */
- #define REG_XDMAC_CIE19 (0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */
- #define REG_XDMAC_CID19 (0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */
- #define REG_XDMAC_CIM19 (0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */
- #define REG_XDMAC_CIS19 (0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */
- #define REG_XDMAC_CSA19 (0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */
- #define REG_XDMAC_CDA19 (0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */
- #define REG_XDMAC_CNDA19 (0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */
- #define REG_XDMAC_CNDC19 (0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */
- #define REG_XDMAC_CUBC19 (0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */
- #define REG_XDMAC_CBC19 (0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */
- #define REG_XDMAC_CC19 (0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */
- #define REG_XDMAC_CDS_MSP19 (0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */
- #define REG_XDMAC_CSUS19 (0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */
- #define REG_XDMAC_CDUS19 (0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */
- #define REG_XDMAC_CIE20 (0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */
- #define REG_XDMAC_CID20 (0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */
- #define REG_XDMAC_CIM20 (0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */
- #define REG_XDMAC_CIS20 (0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */
- #define REG_XDMAC_CSA20 (0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */
- #define REG_XDMAC_CDA20 (0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */
- #define REG_XDMAC_CNDA20 (0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */
- #define REG_XDMAC_CNDC20 (0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */
- #define REG_XDMAC_CUBC20 (0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */
- #define REG_XDMAC_CBC20 (0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */
- #define REG_XDMAC_CC20 (0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */
- #define REG_XDMAC_CDS_MSP20 (0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */
- #define REG_XDMAC_CSUS20 (0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */
- #define REG_XDMAC_CDUS20 (0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */
- #define REG_XDMAC_CIE21 (0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */
- #define REG_XDMAC_CID21 (0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */
- #define REG_XDMAC_CIM21 (0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */
- #define REG_XDMAC_CIS21 (0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */
- #define REG_XDMAC_CSA21 (0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */
- #define REG_XDMAC_CDA21 (0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */
- #define REG_XDMAC_CNDA21 (0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */
- #define REG_XDMAC_CNDC21 (0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */
- #define REG_XDMAC_CUBC21 (0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */
- #define REG_XDMAC_CBC21 (0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */
- #define REG_XDMAC_CC21 (0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */
- #define REG_XDMAC_CDS_MSP21 (0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */
- #define REG_XDMAC_CSUS21 (0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */
- #define REG_XDMAC_CDUS21 (0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */
- #define REG_XDMAC_CIE22 (0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */
- #define REG_XDMAC_CID22 (0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */
- #define REG_XDMAC_CIM22 (0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */
- #define REG_XDMAC_CIS22 (0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */
- #define REG_XDMAC_CSA22 (0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */
- #define REG_XDMAC_CDA22 (0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */
- #define REG_XDMAC_CNDA22 (0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */
- #define REG_XDMAC_CNDC22 (0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */
- #define REG_XDMAC_CUBC22 (0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */
- #define REG_XDMAC_CBC22 (0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */
- #define REG_XDMAC_CC22 (0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */
- #define REG_XDMAC_CDS_MSP22 (0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */
- #define REG_XDMAC_CSUS22 (0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */
- #define REG_XDMAC_CDUS22 (0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */
- #define REG_XDMAC_CIE23 (0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */
- #define REG_XDMAC_CID23 (0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */
- #define REG_XDMAC_CIM23 (0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */
- #define REG_XDMAC_CIS23 (0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */
- #define REG_XDMAC_CSA23 (0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */
- #define REG_XDMAC_CDA23 (0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */
- #define REG_XDMAC_CNDA23 (0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */
- #define REG_XDMAC_CNDC23 (0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */
- #define REG_XDMAC_CUBC23 (0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */
- #define REG_XDMAC_CBC23 (0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */
- #define REG_XDMAC_CC23 (0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */
- #define REG_XDMAC_CDS_MSP23 (0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */
- #define REG_XDMAC_CSUS23 (0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */
- #define REG_XDMAC_CDUS23 (0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */
-#else
- #define REG_XDMAC_GTYPE (*(__IO uint32_t*)0x40078000U) /**< \brief (XDMAC) Global Type Register */
- #define REG_XDMAC_GCFG (*(__I uint32_t*)0x40078004U) /**< \brief (XDMAC) Global Configuration Register */
- #define REG_XDMAC_GWAC (*(__IO uint32_t*)0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */
- #define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */
- #define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */
- #define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */
- #define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */
- #define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */
- #define REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */
- #define REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */
- #define REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */
- #define REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */
- #define REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */
- #define REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */
- #define REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */
- #define REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */
- #define REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */
- #define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */
- #define REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */
- #define REG_XDMAC_CIM0 (*(__O uint32_t*)0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */
- #define REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */
- #define REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */
- #define REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */
- #define REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */
- #define REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */
- #define REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */
- #define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */
- #define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */
- #define REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */
- #define REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */
- #define REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */
- #define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */
- #define REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */
- #define REG_XDMAC_CIM1 (*(__O uint32_t*)0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */
- #define REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */
- #define REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */
- #define REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */
- #define REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */
- #define REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */
- #define REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */
- #define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */
- #define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */
- #define REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */
- #define REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */
- #define REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */
- #define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */
- #define REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */
- #define REG_XDMAC_CIM2 (*(__O uint32_t*)0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */
- #define REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */
- #define REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */
- #define REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */
- #define REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */
- #define REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */
- #define REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */
- #define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */
- #define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */
- #define REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */
- #define REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */
- #define REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */
- #define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */
- #define REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */
- #define REG_XDMAC_CIM3 (*(__O uint32_t*)0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */
- #define REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */
- #define REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */
- #define REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */
- #define REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */
- #define REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */
- #define REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */
- #define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */
- #define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */
- #define REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */
- #define REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */
- #define REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */
- #define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */
- #define REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */
- #define REG_XDMAC_CIM4 (*(__O uint32_t*)0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */
- #define REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */
- #define REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */
- #define REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */
- #define REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */
- #define REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */
- #define REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */
- #define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */
- #define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */
- #define REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */
- #define REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */
- #define REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */
- #define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */
- #define REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */
- #define REG_XDMAC_CIM5 (*(__O uint32_t*)0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */
- #define REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */
- #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */
- #define REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */
- #define REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */
- #define REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */
- #define REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */
- #define REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */
- #define REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */
- #define REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */
- #define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */
- #define REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */
- #define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */
- #define REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */
- #define REG_XDMAC_CIM6 (*(__O uint32_t*)0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */
- #define REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */
- #define REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */
- #define REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */
- #define REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */
- #define REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */
- #define REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */
- #define REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */
- #define REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */
- #define REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */
- #define REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */
- #define REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */
- #define REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */
- #define REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */
- #define REG_XDMAC_CIM7 (*(__O uint32_t*)0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */
- #define REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */
- #define REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */
- #define REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */
- #define REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */
- #define REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */
- #define REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */
- #define REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */
- #define REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */
- #define REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */
- #define REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */
- #define REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */
- #define REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */
- #define REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */
- #define REG_XDMAC_CIM8 (*(__O uint32_t*)0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */
- #define REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */
- #define REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */
- #define REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */
- #define REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */
- #define REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */
- #define REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */
- #define REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */
- #define REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */
- #define REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */
- #define REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */
- #define REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */
- #define REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */
- #define REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */
- #define REG_XDMAC_CIM9 (*(__O uint32_t*)0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */
- #define REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */
- #define REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */
- #define REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */
- #define REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */
- #define REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */
- #define REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */
- #define REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */
- #define REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */
- #define REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */
- #define REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */
- #define REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */
- #define REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */
- #define REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */
- #define REG_XDMAC_CIM10 (*(__O uint32_t*)0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */
- #define REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */
- #define REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */
- #define REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */
- #define REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */
- #define REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */
- #define REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */
- #define REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */
- #define REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */
- #define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */
- #define REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */
- #define REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */
- #define REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */
- #define REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */
- #define REG_XDMAC_CIM11 (*(__O uint32_t*)0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */
- #define REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */
- #define REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */
- #define REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */
- #define REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */
- #define REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */
- #define REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */
- #define REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */
- #define REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */
- #define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */
- #define REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */
- #define REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */
- #define REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */
- #define REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */
- #define REG_XDMAC_CIM12 (*(__O uint32_t*)0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */
- #define REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */
- #define REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */
- #define REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */
- #define REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */
- #define REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */
- #define REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */
- #define REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */
- #define REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */
- #define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */
- #define REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */
- #define REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */
- #define REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */
- #define REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */
- #define REG_XDMAC_CIM13 (*(__O uint32_t*)0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */
- #define REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */
- #define REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */
- #define REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */
- #define REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */
- #define REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */
- #define REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */
- #define REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */
- #define REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */
- #define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */
- #define REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */
- #define REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */
- #define REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */
- #define REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */
- #define REG_XDMAC_CIM14 (*(__O uint32_t*)0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */
- #define REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */
- #define REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */
- #define REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */
- #define REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */
- #define REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */
- #define REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */
- #define REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */
- #define REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */
- #define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */
- #define REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */
- #define REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */
- #define REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */
- #define REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */
- #define REG_XDMAC_CIM15 (*(__O uint32_t*)0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */
- #define REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */
- #define REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */
- #define REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */
- #define REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */
- #define REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */
- #define REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */
- #define REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */
- #define REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */
- #define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */
- #define REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */
- #define REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */
- #define REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */
- #define REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */
- #define REG_XDMAC_CIM16 (*(__O uint32_t*)0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */
- #define REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */
- #define REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */
- #define REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */
- #define REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */
- #define REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */
- #define REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */
- #define REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */
- #define REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */
- #define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */
- #define REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */
- #define REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */
- #define REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */
- #define REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */
- #define REG_XDMAC_CIM17 (*(__O uint32_t*)0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */
- #define REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */
- #define REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */
- #define REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */
- #define REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */
- #define REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */
- #define REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */
- #define REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */
- #define REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */
- #define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */
- #define REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */
- #define REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */
- #define REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */
- #define REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */
- #define REG_XDMAC_CIM18 (*(__O uint32_t*)0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */
- #define REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */
- #define REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */
- #define REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */
- #define REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */
- #define REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */
- #define REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */
- #define REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */
- #define REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */
- #define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */
- #define REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */
- #define REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */
- #define REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */
- #define REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */
- #define REG_XDMAC_CIM19 (*(__O uint32_t*)0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */
- #define REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */
- #define REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */
- #define REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */
- #define REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */
- #define REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */
- #define REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */
- #define REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */
- #define REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */
- #define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */
- #define REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */
- #define REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */
- #define REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */
- #define REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */
- #define REG_XDMAC_CIM20 (*(__O uint32_t*)0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */
- #define REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */
- #define REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */
- #define REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */
- #define REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */
- #define REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */
- #define REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */
- #define REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */
- #define REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */
- #define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */
- #define REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */
- #define REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */
- #define REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */
- #define REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */
- #define REG_XDMAC_CIM21 (*(__O uint32_t*)0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */
- #define REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */
- #define REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */
- #define REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */
- #define REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */
- #define REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */
- #define REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */
- #define REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */
- #define REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */
- #define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */
- #define REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */
- #define REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */
- #define REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */
- #define REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */
- #define REG_XDMAC_CIM22 (*(__O uint32_t*)0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */
- #define REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */
- #define REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */
- #define REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */
- #define REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */
- #define REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */
- #define REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */
- #define REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */
- #define REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */
- #define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */
- #define REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */
- #define REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */
- #define REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */
- #define REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */
- #define REG_XDMAC_CIM23 (*(__O uint32_t*)0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */
- #define REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */
- #define REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */
- #define REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */
- #define REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */
- #define REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */
- #define REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */
- #define REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */
- #define REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */
- #define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */
- #define REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */
- #define REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
-#endif /* _SAMS70_XDMAC_INSTANCE_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j19.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j19.h
deleted file mode 100644
index 786bdc6..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j19.h
+++ /dev/null
@@ -1,418 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70J19_PIO_
-#define _SAMS70J19_PIO_
-
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA24_IDX 24
-#define PIO_PA27_IDX 27
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD31_IDX 127
-
-#endif /* _SAMS70J19_PIO_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j20.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j20.h
deleted file mode 100644
index 77b1fb3..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j20.h
+++ /dev/null
@@ -1,422 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70J20_PIO_
-#define _SAMS70J20_PIO_
-
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for DACC peripheral ========== */
-#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
-#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */
-#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA24_IDX 24
-#define PIO_PA27_IDX 27
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD31_IDX 127
-
-#endif /* _SAMS70J20_PIO_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j21.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j21.h
deleted file mode 100644
index eac07be..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70j21.h
+++ /dev/null
@@ -1,422 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70J21_PIO_
-#define _SAMS70J21_PIO_
-
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for DACC peripheral ========== */
-#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
-#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */
-#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA24_IDX 24
-#define PIO_PA27_IDX 27
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD31_IDX 127
-
-#endif /* _SAMS70J21_PIO_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n19.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n19.h
deleted file mode 100644
index fc6b03a..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n19.h
+++ /dev/null
@@ -1,479 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70N19_PIO_
-#define _SAMS70N19_PIO_
-
-#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
-#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
-#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
-#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
-#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
-#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
-#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
-#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
-#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
-#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
-#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */
-#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */
-#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */
-#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */
-#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */
-#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */
-#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */
-#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */
-#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */
-#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for DACC peripheral ========== */
-#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
-#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */
-#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for TWIHS2 peripheral ========== */
-#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */
-#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA0_IDX 0
-#define PIO_PA1_IDX 1
-#define PIO_PA2_IDX 2
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA15_IDX 15
-#define PIO_PA16_IDX 16
-#define PIO_PA17_IDX 17
-#define PIO_PA18_IDX 18
-#define PIO_PA19_IDX 19
-#define PIO_PA20_IDX 20
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA23_IDX 23
-#define PIO_PA24_IDX 24
-#define PIO_PA25_IDX 25
-#define PIO_PA26_IDX 26
-#define PIO_PA27_IDX 27
-#define PIO_PA28_IDX 28
-#define PIO_PA30_IDX 30
-#define PIO_PA31_IDX 31
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PB13_IDX 45
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD13_IDX 109
-#define PIO_PD14_IDX 110
-#define PIO_PD15_IDX 111
-#define PIO_PD16_IDX 112
-#define PIO_PD17_IDX 113
-#define PIO_PD18_IDX 114
-#define PIO_PD19_IDX 115
-#define PIO_PD20_IDX 116
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD27_IDX 123
-#define PIO_PD28_IDX 124
-#define PIO_PD30_IDX 126
-#define PIO_PD31_IDX 127
-
-#endif /* _SAMS70N19_PIO_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n20.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n20.h
deleted file mode 100644
index 844f1f7..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n20.h
+++ /dev/null
@@ -1,475 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70N20_PIO_
-#define _SAMS70N20_PIO_
-
-#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
-#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
-#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
-#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
-#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
-#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
-#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
-#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
-#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
-#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
-#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */
-#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */
-#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */
-#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */
-#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */
-#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */
-#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */
-#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */
-#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */
-#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for TWIHS2 peripheral ========== */
-#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */
-#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA0_IDX 0
-#define PIO_PA1_IDX 1
-#define PIO_PA2_IDX 2
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA15_IDX 15
-#define PIO_PA16_IDX 16
-#define PIO_PA17_IDX 17
-#define PIO_PA18_IDX 18
-#define PIO_PA19_IDX 19
-#define PIO_PA20_IDX 20
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA23_IDX 23
-#define PIO_PA24_IDX 24
-#define PIO_PA25_IDX 25
-#define PIO_PA26_IDX 26
-#define PIO_PA27_IDX 27
-#define PIO_PA28_IDX 28
-#define PIO_PA30_IDX 30
-#define PIO_PA31_IDX 31
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PB13_IDX 45
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD13_IDX 109
-#define PIO_PD14_IDX 110
-#define PIO_PD15_IDX 111
-#define PIO_PD16_IDX 112
-#define PIO_PD17_IDX 113
-#define PIO_PD18_IDX 114
-#define PIO_PD19_IDX 115
-#define PIO_PD20_IDX 116
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD27_IDX 123
-#define PIO_PD28_IDX 124
-#define PIO_PD30_IDX 126
-#define PIO_PD31_IDX 127
-
-#endif /* _SAMS70N20_PIO_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n21.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n21.h
deleted file mode 100644
index 1e1d83c..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70n21.h
+++ /dev/null
@@ -1,475 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70N21_PIO_
-#define _SAMS70N21_PIO_
-
-#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
-#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
-#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
-#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
-#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
-#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
-#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
-#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
-#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
-#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
-#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */
-#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */
-#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */
-#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */
-#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */
-#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */
-#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */
-#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */
-#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */
-#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for TWIHS2 peripheral ========== */
-#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */
-#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA0_IDX 0
-#define PIO_PA1_IDX 1
-#define PIO_PA2_IDX 2
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA15_IDX 15
-#define PIO_PA16_IDX 16
-#define PIO_PA17_IDX 17
-#define PIO_PA18_IDX 18
-#define PIO_PA19_IDX 19
-#define PIO_PA20_IDX 20
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA23_IDX 23
-#define PIO_PA24_IDX 24
-#define PIO_PA25_IDX 25
-#define PIO_PA26_IDX 26
-#define PIO_PA27_IDX 27
-#define PIO_PA28_IDX 28
-#define PIO_PA30_IDX 30
-#define PIO_PA31_IDX 31
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PB13_IDX 45
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD13_IDX 109
-#define PIO_PD14_IDX 110
-#define PIO_PD15_IDX 111
-#define PIO_PD16_IDX 112
-#define PIO_PD17_IDX 113
-#define PIO_PD18_IDX 114
-#define PIO_PD19_IDX 115
-#define PIO_PD20_IDX 116
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD27_IDX 123
-#define PIO_PD28_IDX 124
-#define PIO_PD30_IDX 126
-#define PIO_PD31_IDX 127
-
-#endif /* _SAMS70N21_PIO_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q19.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q19.h
deleted file mode 100644
index d59cbc3..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q19.h
+++ /dev/null
@@ -1,652 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70Q19_PIO_
-#define _SAMS70Q19_PIO_
-
-#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
-#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
-#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
-#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
-#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
-#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
-#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
-#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
-#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
-#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
-#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
-#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
-#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */
-#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */
-#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */
-#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */
-#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */
-#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */
-#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */
-#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */
-#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */
-#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */
-#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */
-#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */
-#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */
-#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */
-#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */
-#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */
-#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */
-#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */
-#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */
-#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */
-#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */
-#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */
-#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */
-#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */
-#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */
-#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */
-#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */
-#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */
-#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */
-#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */
-#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */
-#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */
-#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */
-#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */
-#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */
-#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */
-#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */
-#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */
-#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */
-#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */
-#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */
-#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */
-#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */
-#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */
-#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */
-#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */
-#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for DACC peripheral ========== */
-#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
-#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */
-#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
-/* ========== Pio definition for EBI peripheral ========== */
-#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */
-#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */
-#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */
-#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */
-#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */
-#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */
-#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */
-#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */
-#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */
-#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */
-#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */
-#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */
-#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */
-#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */
-#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */
-#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */
-#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */
-#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
-#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
-#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
-#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
-#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */
-#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */
-#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */
-#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */
-#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */
-#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */
-#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */
-#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */
-#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */
-#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */
-#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */
-#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */
-#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */
-#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */
-#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */
-#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */
-#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */
-#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */
-#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */
-#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */
-#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */
-#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */
-#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */
-#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */
-#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */
-#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */
-#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */
-#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */
-#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */
-#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */
-#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */
-#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */
-#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */
-#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */
-#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */
-#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
-#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
-#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */
-#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */
-#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */
-#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */
-#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */
-#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC1 peripheral ========== */
-#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */
-#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */
-#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */
-#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */
-#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */
-#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */
-#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */
-#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */
-#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */
-/* ========== Pio definition for TC2 peripheral ========== */
-#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */
-#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */
-#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */
-#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */
-#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */
-#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */
-#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */
-#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */
-#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for TWIHS2 peripheral ========== */
-#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */
-#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA0_IDX 0
-#define PIO_PA1_IDX 1
-#define PIO_PA2_IDX 2
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA6_IDX 6
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA15_IDX 15
-#define PIO_PA16_IDX 16
-#define PIO_PA17_IDX 17
-#define PIO_PA18_IDX 18
-#define PIO_PA19_IDX 19
-#define PIO_PA20_IDX 20
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA23_IDX 23
-#define PIO_PA24_IDX 24
-#define PIO_PA25_IDX 25
-#define PIO_PA26_IDX 26
-#define PIO_PA27_IDX 27
-#define PIO_PA28_IDX 28
-#define PIO_PA29_IDX 29
-#define PIO_PA30_IDX 30
-#define PIO_PA31_IDX 31
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PB13_IDX 45
-#define PIO_PC0_IDX 64
-#define PIO_PC1_IDX 65
-#define PIO_PC2_IDX 66
-#define PIO_PC3_IDX 67
-#define PIO_PC4_IDX 68
-#define PIO_PC5_IDX 69
-#define PIO_PC6_IDX 70
-#define PIO_PC7_IDX 71
-#define PIO_PC8_IDX 72
-#define PIO_PC9_IDX 73
-#define PIO_PC10_IDX 74
-#define PIO_PC11_IDX 75
-#define PIO_PC12_IDX 76
-#define PIO_PC13_IDX 77
-#define PIO_PC14_IDX 78
-#define PIO_PC15_IDX 79
-#define PIO_PC16_IDX 80
-#define PIO_PC17_IDX 81
-#define PIO_PC18_IDX 82
-#define PIO_PC19_IDX 83
-#define PIO_PC20_IDX 84
-#define PIO_PC21_IDX 85
-#define PIO_PC22_IDX 86
-#define PIO_PC23_IDX 87
-#define PIO_PC24_IDX 88
-#define PIO_PC25_IDX 89
-#define PIO_PC26_IDX 90
-#define PIO_PC27_IDX 91
-#define PIO_PC28_IDX 92
-#define PIO_PC29_IDX 93
-#define PIO_PC30_IDX 94
-#define PIO_PC31_IDX 95
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD13_IDX 109
-#define PIO_PD14_IDX 110
-#define PIO_PD15_IDX 111
-#define PIO_PD16_IDX 112
-#define PIO_PD17_IDX 113
-#define PIO_PD18_IDX 114
-#define PIO_PD19_IDX 115
-#define PIO_PD20_IDX 116
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD23_IDX 119
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD27_IDX 123
-#define PIO_PD28_IDX 124
-#define PIO_PD29_IDX 125
-#define PIO_PD30_IDX 126
-#define PIO_PD31_IDX 127
-#define PIO_PE0_IDX 128
-#define PIO_PE1_IDX 129
-#define PIO_PE2_IDX 130
-#define PIO_PE3_IDX 131
-#define PIO_PE4_IDX 132
-#define PIO_PE5_IDX 133
-
-#endif /* _SAMS70Q19_PIO_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q20.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q20.h
deleted file mode 100644
index 38e6038..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q20.h
+++ /dev/null
@@ -1,652 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70Q20_PIO_
-#define _SAMS70Q20_PIO_
-
-#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
-#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
-#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
-#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
-#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
-#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
-#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
-#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
-#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
-#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
-#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
-#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
-#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */
-#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */
-#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */
-#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */
-#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */
-#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */
-#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */
-#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */
-#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */
-#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */
-#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */
-#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */
-#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */
-#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */
-#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */
-#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */
-#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */
-#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */
-#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */
-#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */
-#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */
-#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */
-#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */
-#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */
-#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */
-#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */
-#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */
-#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */
-#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */
-#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */
-#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */
-#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */
-#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */
-#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */
-#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */
-#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */
-#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */
-#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */
-#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */
-#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */
-#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */
-#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */
-#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */
-#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */
-#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */
-#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */
-#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for DACC peripheral ========== */
-#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
-#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */
-#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
-/* ========== Pio definition for EBI peripheral ========== */
-#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */
-#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */
-#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */
-#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */
-#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */
-#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */
-#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */
-#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */
-#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */
-#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */
-#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */
-#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */
-#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */
-#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */
-#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */
-#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */
-#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */
-#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
-#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
-#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
-#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
-#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */
-#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */
-#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */
-#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */
-#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */
-#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */
-#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */
-#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */
-#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */
-#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */
-#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */
-#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */
-#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */
-#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */
-#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */
-#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */
-#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */
-#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */
-#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */
-#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */
-#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */
-#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */
-#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */
-#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */
-#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */
-#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */
-#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */
-#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */
-#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */
-#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */
-#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */
-#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */
-#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */
-#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */
-#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */
-#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
-#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
-#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */
-#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */
-#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */
-#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */
-#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */
-#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC1 peripheral ========== */
-#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */
-#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */
-#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */
-#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */
-#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */
-#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */
-#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */
-#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */
-#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */
-/* ========== Pio definition for TC2 peripheral ========== */
-#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */
-#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */
-#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */
-#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */
-#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */
-#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */
-#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */
-#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */
-#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for TWIHS2 peripheral ========== */
-#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */
-#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA0_IDX 0
-#define PIO_PA1_IDX 1
-#define PIO_PA2_IDX 2
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA6_IDX 6
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA15_IDX 15
-#define PIO_PA16_IDX 16
-#define PIO_PA17_IDX 17
-#define PIO_PA18_IDX 18
-#define PIO_PA19_IDX 19
-#define PIO_PA20_IDX 20
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA23_IDX 23
-#define PIO_PA24_IDX 24
-#define PIO_PA25_IDX 25
-#define PIO_PA26_IDX 26
-#define PIO_PA27_IDX 27
-#define PIO_PA28_IDX 28
-#define PIO_PA29_IDX 29
-#define PIO_PA30_IDX 30
-#define PIO_PA31_IDX 31
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PB13_IDX 45
-#define PIO_PC0_IDX 64
-#define PIO_PC1_IDX 65
-#define PIO_PC2_IDX 66
-#define PIO_PC3_IDX 67
-#define PIO_PC4_IDX 68
-#define PIO_PC5_IDX 69
-#define PIO_PC6_IDX 70
-#define PIO_PC7_IDX 71
-#define PIO_PC8_IDX 72
-#define PIO_PC9_IDX 73
-#define PIO_PC10_IDX 74
-#define PIO_PC11_IDX 75
-#define PIO_PC12_IDX 76
-#define PIO_PC13_IDX 77
-#define PIO_PC14_IDX 78
-#define PIO_PC15_IDX 79
-#define PIO_PC16_IDX 80
-#define PIO_PC17_IDX 81
-#define PIO_PC18_IDX 82
-#define PIO_PC19_IDX 83
-#define PIO_PC20_IDX 84
-#define PIO_PC21_IDX 85
-#define PIO_PC22_IDX 86
-#define PIO_PC23_IDX 87
-#define PIO_PC24_IDX 88
-#define PIO_PC25_IDX 89
-#define PIO_PC26_IDX 90
-#define PIO_PC27_IDX 91
-#define PIO_PC28_IDX 92
-#define PIO_PC29_IDX 93
-#define PIO_PC30_IDX 94
-#define PIO_PC31_IDX 95
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD13_IDX 109
-#define PIO_PD14_IDX 110
-#define PIO_PD15_IDX 111
-#define PIO_PD16_IDX 112
-#define PIO_PD17_IDX 113
-#define PIO_PD18_IDX 114
-#define PIO_PD19_IDX 115
-#define PIO_PD20_IDX 116
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD23_IDX 119
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD27_IDX 123
-#define PIO_PD28_IDX 124
-#define PIO_PD29_IDX 125
-#define PIO_PD30_IDX 126
-#define PIO_PD31_IDX 127
-#define PIO_PE0_IDX 128
-#define PIO_PE1_IDX 129
-#define PIO_PE2_IDX 130
-#define PIO_PE3_IDX 131
-#define PIO_PE4_IDX 132
-#define PIO_PE5_IDX 133
-
-#endif /* _SAMS70Q20_PIO_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q21.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q21.h
deleted file mode 100644
index 25cb978..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/pio/sams70q21.h
+++ /dev/null
@@ -1,652 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70Q21_PIO_
-#define _SAMS70Q21_PIO_
-
-#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
-#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
-#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
-#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
-#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
-#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
-#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
-#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
-#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
-#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
-#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
-#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
-#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
-#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
-#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
-#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
-#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
-#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
-#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
-#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
-#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
-#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
-#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
-#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
-#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
-#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
-#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
-#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
-#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
-#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
-#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
-#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
-#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
-#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
-#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
-#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
-#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
-#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
-#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
-#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
-#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
-#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
-#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
-#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
-#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */
-#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */
-#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */
-#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */
-#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */
-#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */
-#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */
-#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */
-#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */
-#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */
-#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */
-#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */
-#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */
-#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */
-#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */
-#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */
-#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */
-#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */
-#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */
-#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */
-#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */
-#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */
-#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */
-#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */
-#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */
-#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */
-#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */
-#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */
-#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */
-#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */
-#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */
-#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */
-#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */
-#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */
-#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */
-#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */
-#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */
-#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */
-#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */
-#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */
-#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */
-#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */
-#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */
-#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */
-#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */
-#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */
-#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */
-#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */
-#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */
-#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */
-#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */
-#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */
-#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */
-#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */
-#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */
-#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */
-#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */
-#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */
-#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */
-#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */
-#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */
-#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */
-#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */
-#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */
-#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */
-#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */
-#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */
-#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */
-#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */
-#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */
-/* ========== Pio definition for AFEC0 peripheral ========== */
-#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */
-#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */
-#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */
-#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */
-#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */
-#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */
-#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */
-#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */
-#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */
-#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */
-/* ========== Pio definition for AFEC1 peripheral ========== */
-#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */
-#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */
-#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */
-#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */
-#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */
-#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */
-#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */
-#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */
-#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */
-#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */
-#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */
-#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */
-#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */
-/* ========== Pio definition for ARM peripheral ========== */
-#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */
-#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */
-#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */
-#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */
-/* ========== Pio definition for DACC peripheral ========== */
-#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
-#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */
-#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
-/* ========== Pio definition for EBI peripheral ========== */
-#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */
-#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */
-#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */
-#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */
-#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */
-#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */
-#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */
-#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */
-#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */
-#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */
-#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */
-#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */
-#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */
-#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */
-#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */
-#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */
-#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */
-#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
-#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */
-#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
-#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */
-#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */
-#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */
-#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */
-#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */
-#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */
-#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */
-#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */
-#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */
-#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */
-#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */
-#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */
-#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */
-#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */
-#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */
-#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */
-#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */
-#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */
-#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */
-#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */
-#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */
-#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */
-#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */
-#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */
-#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */
-#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */
-#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */
-#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */
-#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */
-#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */
-#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */
-#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */
-#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */
-#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */
-#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */
-#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */
-#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */
-#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
-#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
-#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */
-#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */
-#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */
-#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */
-#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */
-#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */
-/* ========== Pio definition for HSMCI peripheral ========== */
-#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */
-#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */
-#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */
-#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */
-#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */
-#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */
-/* ========== Pio definition for ISI peripheral ========== */
-#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */
-#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */
-#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */
-#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */
-#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */
-#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */
-#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */
-#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */
-#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */
-#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */
-#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */
-#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */
-#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */
-#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */
-#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */
-/* ========== Pio definition for PIOA peripheral ========== */
-#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */
-#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */
-#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */
-#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */
-#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */
-#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */
-#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */
-#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */
-#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */
-#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */
-#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */
-/* ========== Pio definition for PMC peripheral ========== */
-#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */
-#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
-#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
-#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
-#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
-#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
-/* ========== Pio definition for PWM0 peripheral ========== */
-#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */
-#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */
-#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */
-#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */
-#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */
-#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */
-#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */
-#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */
-#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */
-#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */
-#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */
-#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */
-#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */
-/* ========== Pio definition for PWM1 peripheral ========== */
-#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */
-#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */
-#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */
-#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */
-#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */
-#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */
-#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */
-#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */
-#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */
-#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */
-#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */
-#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */
-#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */
-/* ========== Pio definition for QSPI peripheral ========== */
-#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */
-#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */
-#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */
-#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */
-#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */
-#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */
-/* ========== Pio definition for SPI0 peripheral ========== */
-#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */
-#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */
-#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */
-#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */
-#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */
-#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */
-#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */
-/* ========== Pio definition for SPI1 peripheral ========== */
-#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */
-#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */
-#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */
-#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */
-#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */
-#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */
-#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */
-/* ========== Pio definition for SSC peripheral ========== */
-#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */
-#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */
-#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */
-#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */
-#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */
-#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */
-#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */
-#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */
-/* ========== Pio definition for TC0 peripheral ========== */
-#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
-#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
-#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
-#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
-#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
-#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
-#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
-#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
-#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
-/* ========== Pio definition for TC1 peripheral ========== */
-#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */
-#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */
-#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */
-#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */
-#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */
-#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */
-#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */
-#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */
-#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */
-/* ========== Pio definition for TC2 peripheral ========== */
-#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */
-#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */
-#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */
-#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */
-#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */
-#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */
-#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */
-#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */
-#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */
-/* ========== Pio definition for TC3 peripheral ========== */
-#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */
-#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */
-#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */
-#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */
-#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */
-#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */
-#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */
-#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */
-#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */
-/* ========== Pio definition for TWIHS0 peripheral ========== */
-#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */
-#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */
-/* ========== Pio definition for TWIHS1 peripheral ========== */
-#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */
-#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */
-/* ========== Pio definition for TWIHS2 peripheral ========== */
-#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */
-#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */
-/* ========== Pio definition for UART0 peripheral ========== */
-#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
-#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
-/* ========== Pio definition for UART1 peripheral ========== */
-#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */
-#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */
-#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */
-/* ========== Pio definition for UART2 peripheral ========== */
-#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */
-#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */
-/* ========== Pio definition for UART3 peripheral ========== */
-#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */
-#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */
-#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */
-/* ========== Pio definition for UART4 peripheral ========== */
-#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */
-#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */
-#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */
-/* ========== Pio definition for USART0 peripheral ========== */
-#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */
-#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */
-#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */
-#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */
-#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */
-#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */
-#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */
-#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */
-#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */
-/* ========== Pio definition for USART1 peripheral ========== */
-#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
-#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */
-#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */
-#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */
-#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */
-#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */
-#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
-#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
-#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
-#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */
-/* ========== Pio definition for USART2 peripheral ========== */
-#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */
-#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */
-#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */
-#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */
-#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */
-#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */
-#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */
-#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */
-#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */
-/* ========== Pio indexes ========== */
-#define PIO_PA0_IDX 0
-#define PIO_PA1_IDX 1
-#define PIO_PA2_IDX 2
-#define PIO_PA3_IDX 3
-#define PIO_PA4_IDX 4
-#define PIO_PA5_IDX 5
-#define PIO_PA6_IDX 6
-#define PIO_PA7_IDX 7
-#define PIO_PA8_IDX 8
-#define PIO_PA9_IDX 9
-#define PIO_PA10_IDX 10
-#define PIO_PA11_IDX 11
-#define PIO_PA12_IDX 12
-#define PIO_PA13_IDX 13
-#define PIO_PA14_IDX 14
-#define PIO_PA15_IDX 15
-#define PIO_PA16_IDX 16
-#define PIO_PA17_IDX 17
-#define PIO_PA18_IDX 18
-#define PIO_PA19_IDX 19
-#define PIO_PA20_IDX 20
-#define PIO_PA21_IDX 21
-#define PIO_PA22_IDX 22
-#define PIO_PA23_IDX 23
-#define PIO_PA24_IDX 24
-#define PIO_PA25_IDX 25
-#define PIO_PA26_IDX 26
-#define PIO_PA27_IDX 27
-#define PIO_PA28_IDX 28
-#define PIO_PA29_IDX 29
-#define PIO_PA30_IDX 30
-#define PIO_PA31_IDX 31
-#define PIO_PB0_IDX 32
-#define PIO_PB1_IDX 33
-#define PIO_PB2_IDX 34
-#define PIO_PB3_IDX 35
-#define PIO_PB4_IDX 36
-#define PIO_PB5_IDX 37
-#define PIO_PB6_IDX 38
-#define PIO_PB7_IDX 39
-#define PIO_PB8_IDX 40
-#define PIO_PB9_IDX 41
-#define PIO_PB12_IDX 44
-#define PIO_PB13_IDX 45
-#define PIO_PC0_IDX 64
-#define PIO_PC1_IDX 65
-#define PIO_PC2_IDX 66
-#define PIO_PC3_IDX 67
-#define PIO_PC4_IDX 68
-#define PIO_PC5_IDX 69
-#define PIO_PC6_IDX 70
-#define PIO_PC7_IDX 71
-#define PIO_PC8_IDX 72
-#define PIO_PC9_IDX 73
-#define PIO_PC10_IDX 74
-#define PIO_PC11_IDX 75
-#define PIO_PC12_IDX 76
-#define PIO_PC13_IDX 77
-#define PIO_PC14_IDX 78
-#define PIO_PC15_IDX 79
-#define PIO_PC16_IDX 80
-#define PIO_PC17_IDX 81
-#define PIO_PC18_IDX 82
-#define PIO_PC19_IDX 83
-#define PIO_PC20_IDX 84
-#define PIO_PC21_IDX 85
-#define PIO_PC22_IDX 86
-#define PIO_PC23_IDX 87
-#define PIO_PC24_IDX 88
-#define PIO_PC25_IDX 89
-#define PIO_PC26_IDX 90
-#define PIO_PC27_IDX 91
-#define PIO_PC28_IDX 92
-#define PIO_PC29_IDX 93
-#define PIO_PC30_IDX 94
-#define PIO_PC31_IDX 95
-#define PIO_PD0_IDX 96
-#define PIO_PD1_IDX 97
-#define PIO_PD2_IDX 98
-#define PIO_PD3_IDX 99
-#define PIO_PD4_IDX 100
-#define PIO_PD5_IDX 101
-#define PIO_PD6_IDX 102
-#define PIO_PD7_IDX 103
-#define PIO_PD8_IDX 104
-#define PIO_PD9_IDX 105
-#define PIO_PD10_IDX 106
-#define PIO_PD11_IDX 107
-#define PIO_PD12_IDX 108
-#define PIO_PD13_IDX 109
-#define PIO_PD14_IDX 110
-#define PIO_PD15_IDX 111
-#define PIO_PD16_IDX 112
-#define PIO_PD17_IDX 113
-#define PIO_PD18_IDX 114
-#define PIO_PD19_IDX 115
-#define PIO_PD20_IDX 116
-#define PIO_PD21_IDX 117
-#define PIO_PD22_IDX 118
-#define PIO_PD23_IDX 119
-#define PIO_PD24_IDX 120
-#define PIO_PD25_IDX 121
-#define PIO_PD26_IDX 122
-#define PIO_PD27_IDX 123
-#define PIO_PD28_IDX 124
-#define PIO_PD29_IDX 125
-#define PIO_PD30_IDX 126
-#define PIO_PD31_IDX 127
-#define PIO_PE0_IDX 128
-#define PIO_PE1_IDX 129
-#define PIO_PE2_IDX 130
-#define PIO_PE3_IDX 131
-#define PIO_PE4_IDX 132
-#define PIO_PE5_IDX 133
-
-#endif /* _SAMS70Q21_PIO_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70.h
deleted file mode 100644
index aca1034..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-#ifndef _SAMS70_
-#define _SAMS70_
-
-#if defined (__SAMS70J19__)
-#include "sams70j19.h"
-#elif defined (__SAMS70J20__)
-#include "sams70j20.h"
-#elif defined (__SAMS70J21__)
-#include "sams70j21.h"
-#elif defined (__SAMS70N19__)
-#include "sams70n19.h"
-#elif defined (__SAMS70N20__)
-#include "sams70n20.h"
-#elif defined (__SAMS70N21__)
-#include "sams70n21.h"
-#elif defined (__SAMS70Q19__)
-#include "sams70q19.h"
-#elif defined (__SAMS70Q20__)
-#include "sams70q20.h"
-#elif defined (__SAMS70Q21__)
-#include "sams70q21.h"
-#else
- #error Library does not support the specified device.
-#endif
-
-#endif /* _SAMS70_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70j19.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70j19.h
deleted file mode 100644
index f4edaa2..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70j19.h
+++ /dev/null
@@ -1,618 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70J19_
-#define _SAMS70J19_
-
-/** \addtogroup SAMS70J19_definitions SAMS70J19 definitions
- This file defines all structures and symbols for SAMS70J19:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J19_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70J19 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70J19 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70J19 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70J19 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70J19 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70J19 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70J19 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70J19 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70J19 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70J19 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70J19 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70J19 Parallel I/O Controller B (PIOB) */
- USART0_IRQn = 13, /**< 13 SAMS70J19 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70J19 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70J19 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70J19 Parallel I/O Controller D (PIOD) */
- HSMCI_IRQn = 18, /**< 18 SAMS70J19 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70J19 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70J19 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70J19 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70J19 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70J19 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70J19 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70J19 Timer/Counter 2 (TC2) */
- AFEC0_IRQn = 29, /**< 29 SAMS70J19 Analog Front End 0 (AFEC0) */
- PWM0_IRQn = 31, /**< 31 SAMS70J19 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70J19 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70J19 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70J19 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70J19 Analog Front End 1 (AFEC1) */
- SPI1_IRQn = 42, /**< 42 SAMS70J19 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70J19 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70J19 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70J19 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70J19 UART 4 (UART4) */
- TC9_IRQn = 50, /**< 50 SAMS70J19 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70J19 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70J19 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70J19 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70J19 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70J19 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70J19 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70J19 Pulse Width Modulation 1 (PWM1) */
- RSWDT_IRQn = 63, /**< 63 SAMS70J19 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pvReserved12;
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pvReserved17;
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pvReserved26;
- void* pvReserved27;
- void* pvReserved28;
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pvReserved30;
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pvReserved41;
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pvReserved47;
- void* pvReserved48;
- void* pvReserved49;
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pvReserved62;
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOD_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70J19 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70J19 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70J19 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70J19 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70J19 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70J19 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70J19 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70J19 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70J19 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70J19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J19_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J19_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/piod.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J19_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J19_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J19_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70j19.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x80000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (1024u)
-#define IFLASH_NB_OF_LOCK_BITS (32u)
-#define IRAM_SIZE (0x40000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA11D0A00UL)
-#define CHIP_EXID (0x00000000UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70J19 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70J19_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70j20.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70j20.h
deleted file mode 100644
index e2fd998..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70j20.h
+++ /dev/null
@@ -1,625 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70J20_
-#define _SAMS70J20_
-
-/** \addtogroup SAMS70J20_definitions SAMS70J20 definitions
- This file defines all structures and symbols for SAMS70J20:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J20_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70J20 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70J20 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70J20 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70J20 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70J20 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70J20 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70J20 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70J20 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70J20 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70J20 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70J20 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70J20 Parallel I/O Controller B (PIOB) */
- USART0_IRQn = 13, /**< 13 SAMS70J20 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70J20 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70J20 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70J20 Parallel I/O Controller D (PIOD) */
- HSMCI_IRQn = 18, /**< 18 SAMS70J20 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70J20 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70J20 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70J20 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70J20 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70J20 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70J20 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70J20 Timer/Counter 2 (TC2) */
- AFEC0_IRQn = 29, /**< 29 SAMS70J20 Analog Front End 0 (AFEC0) */
- DACC_IRQn = 30, /**< 30 SAMS70J20 Digital To Analog Converter (DACC) */
- PWM0_IRQn = 31, /**< 31 SAMS70J20 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70J20 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70J20 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70J20 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70J20 Analog Front End 1 (AFEC1) */
- SPI1_IRQn = 42, /**< 42 SAMS70J20 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70J20 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70J20 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70J20 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70J20 UART 4 (UART4) */
- TC9_IRQn = 50, /**< 50 SAMS70J20 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70J20 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70J20 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70J20 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70J20 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70J20 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70J20 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70J20 Pulse Width Modulation 1 (PWM1) */
- RSWDT_IRQn = 63, /**< 63 SAMS70J20 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pvReserved12;
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pvReserved17;
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pvReserved26;
- void* pvReserved27;
- void* pvReserved28;
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pvReserved41;
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pvReserved47;
- void* pvReserved48;
- void* pvReserved49;
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pvReserved62;
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void DACC_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOD_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70J20 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70J20 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70J20 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70J20 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70J20 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70J20 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70J20 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70J20 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70J20 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70J20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J20_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/dacc.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J20_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/dacc.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/piod.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J20_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J20_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J20_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70j20.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x100000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (2048u)
-#define IFLASH_NB_OF_LOCK_BITS (64u)
-#define IRAM_SIZE (0x60000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA1120C00UL)
-#define CHIP_EXID (0x00000000UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70J20 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70J20_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70j21.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70j21.h
deleted file mode 100644
index b554f03..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70j21.h
+++ /dev/null
@@ -1,625 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70J21_
-#define _SAMS70J21_
-
-/** \addtogroup SAMS70J21_definitions SAMS70J21 definitions
- This file defines all structures and symbols for SAMS70J21:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J21_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70J21 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70J21 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70J21 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70J21 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70J21 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70J21 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70J21 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70J21 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70J21 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70J21 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70J21 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70J21 Parallel I/O Controller B (PIOB) */
- USART0_IRQn = 13, /**< 13 SAMS70J21 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70J21 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70J21 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70J21 Parallel I/O Controller D (PIOD) */
- HSMCI_IRQn = 18, /**< 18 SAMS70J21 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70J21 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70J21 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70J21 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70J21 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70J21 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70J21 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70J21 Timer/Counter 2 (TC2) */
- AFEC0_IRQn = 29, /**< 29 SAMS70J21 Analog Front End 0 (AFEC0) */
- DACC_IRQn = 30, /**< 30 SAMS70J21 Digital To Analog Converter (DACC) */
- PWM0_IRQn = 31, /**< 31 SAMS70J21 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70J21 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70J21 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70J21 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70J21 Analog Front End 1 (AFEC1) */
- SPI1_IRQn = 42, /**< 42 SAMS70J21 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70J21 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70J21 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70J21 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70J21 UART 4 (UART4) */
- TC9_IRQn = 50, /**< 50 SAMS70J21 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70J21 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70J21 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70J21 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70J21 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70J21 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70J21 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70J21 Pulse Width Modulation 1 (PWM1) */
- RSWDT_IRQn = 63, /**< 63 SAMS70J21 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pvReserved12;
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pvReserved17;
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pvReserved26;
- void* pvReserved27;
- void* pvReserved28;
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pvReserved41;
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pvReserved47;
- void* pvReserved48;
- void* pvReserved49;
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pvReserved62;
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void DACC_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOD_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70J21 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70J21 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70J21 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70J21 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70J21 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70J21 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70J21 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70J21 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70J21 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70J21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J21_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/dacc.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J21_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/dacc.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/piod.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J21_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J21_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70J21_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70j21.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x200000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (4096u)
-#define IFLASH_NB_OF_LOCK_BITS (128u)
-#define IRAM_SIZE (0x60000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA1120E00UL)
-#define CHIP_EXID (0x00000000UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70J21 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70J21_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70n19.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70n19.h
deleted file mode 100644
index 1957933..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70n19.h
+++ /dev/null
@@ -1,631 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70N19_
-#define _SAMS70N19_
-
-/** \addtogroup SAMS70N19_definitions SAMS70N19 definitions
- This file defines all structures and symbols for SAMS70N19:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N19_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70N19 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70N19 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70N19 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70N19 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70N19 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70N19 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70N19 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70N19 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70N19 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70N19 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70N19 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70N19 Parallel I/O Controller B (PIOB) */
- USART0_IRQn = 13, /**< 13 SAMS70N19 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70N19 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70N19 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70N19 Parallel I/O Controller D (PIOD) */
- HSMCI_IRQn = 18, /**< 18 SAMS70N19 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70N19 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70N19 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70N19 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70N19 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70N19 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70N19 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70N19 Timer/Counter 2 (TC2) */
- AFEC0_IRQn = 29, /**< 29 SAMS70N19 Analog Front End 0 (AFEC0) */
- DACC_IRQn = 30, /**< 30 SAMS70N19 Digital To Analog Converter (DACC) */
- PWM0_IRQn = 31, /**< 31 SAMS70N19 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70N19 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70N19 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70N19 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70N19 Analog Front End 1 (AFEC1) */
- TWIHS2_IRQn = 41, /**< 41 SAMS70N19 Two Wire Interface 2 HS (TWIHS2) */
- SPI1_IRQn = 42, /**< 42 SAMS70N19 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70N19 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70N19 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70N19 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70N19 UART 4 (UART4) */
- TC9_IRQn = 50, /**< 50 SAMS70N19 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70N19 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70N19 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70N19 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70N19 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70N19 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70N19 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70N19 Pulse Width Modulation 1 (PWM1) */
- RSWDT_IRQn = 63, /**< 63 SAMS70N19 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pvReserved12;
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pvReserved17;
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pvReserved26;
- void* pvReserved27;
- void* pvReserved28;
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pvReserved47;
- void* pvReserved48;
- void* pvReserved49;
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pvReserved62;
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void DACC_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOD_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void TWIHS2_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70N19 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70N19 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70N19 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70N19 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70N19 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70N19 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70N19 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70N19 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70N19 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70N19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N19_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/dacc.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N19_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/dacc.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/twihs2.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/piod.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N19_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N19_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N19_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70n19.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x80000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (1024u)
-#define IFLASH_NB_OF_LOCK_BITS (32u)
-#define IRAM_SIZE (0x40000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA11D0A00UL)
-#define CHIP_EXID (0x00000001UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70N19 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70N19_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70n20.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70n20.h
deleted file mode 100644
index fabfc0c..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70n20.h
+++ /dev/null
@@ -1,624 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70N20_
-#define _SAMS70N20_
-
-/** \addtogroup SAMS70N20_definitions SAMS70N20 definitions
- This file defines all structures and symbols for SAMS70N20:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N20_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70N20 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70N20 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70N20 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70N20 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70N20 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70N20 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70N20 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70N20 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70N20 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70N20 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70N20 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70N20 Parallel I/O Controller B (PIOB) */
- USART0_IRQn = 13, /**< 13 SAMS70N20 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70N20 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70N20 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70N20 Parallel I/O Controller D (PIOD) */
- HSMCI_IRQn = 18, /**< 18 SAMS70N20 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70N20 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70N20 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70N20 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70N20 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70N20 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70N20 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70N20 Timer/Counter 2 (TC2) */
- AFEC0_IRQn = 29, /**< 29 SAMS70N20 Analog Front End 0 (AFEC0) */
- PWM0_IRQn = 31, /**< 31 SAMS70N20 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70N20 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70N20 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70N20 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70N20 Analog Front End 1 (AFEC1) */
- TWIHS2_IRQn = 41, /**< 41 SAMS70N20 Two Wire Interface 2 HS (TWIHS2) */
- SPI1_IRQn = 42, /**< 42 SAMS70N20 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70N20 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70N20 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70N20 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70N20 UART 4 (UART4) */
- TC9_IRQn = 50, /**< 50 SAMS70N20 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70N20 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70N20 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70N20 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70N20 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70N20 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70N20 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70N20 Pulse Width Modulation 1 (PWM1) */
- RSWDT_IRQn = 63, /**< 63 SAMS70N20 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pvReserved12;
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pvReserved17;
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pvReserved26;
- void* pvReserved27;
- void* pvReserved28;
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pvReserved30;
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pvReserved47;
- void* pvReserved48;
- void* pvReserved49;
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pvReserved62;
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOD_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void TWIHS2_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70N20 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70N20 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70N20 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70N20 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70N20 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70N20 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70N20 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70N20 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70N20 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70N20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N20_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N20_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/twihs2.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/piod.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N20_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N20_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N20_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70n20.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x100000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (2048u)
-#define IFLASH_NB_OF_LOCK_BITS (64u)
-#define IRAM_SIZE (0x60000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA1120C00UL)
-#define CHIP_EXID (0x00000001UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70N20 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70N20_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70n21.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70n21.h
deleted file mode 100644
index 2e98fd9..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70n21.h
+++ /dev/null
@@ -1,624 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70N21_
-#define _SAMS70N21_
-
-/** \addtogroup SAMS70N21_definitions SAMS70N21 definitions
- This file defines all structures and symbols for SAMS70N21:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N21_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70N21 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70N21 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70N21 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70N21 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70N21 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70N21 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70N21 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70N21 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70N21 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70N21 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70N21 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70N21 Parallel I/O Controller B (PIOB) */
- USART0_IRQn = 13, /**< 13 SAMS70N21 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70N21 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70N21 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70N21 Parallel I/O Controller D (PIOD) */
- HSMCI_IRQn = 18, /**< 18 SAMS70N21 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70N21 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70N21 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70N21 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70N21 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70N21 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70N21 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70N21 Timer/Counter 2 (TC2) */
- AFEC0_IRQn = 29, /**< 29 SAMS70N21 Analog Front End 0 (AFEC0) */
- PWM0_IRQn = 31, /**< 31 SAMS70N21 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70N21 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70N21 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70N21 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70N21 Analog Front End 1 (AFEC1) */
- TWIHS2_IRQn = 41, /**< 41 SAMS70N21 Two Wire Interface 2 HS (TWIHS2) */
- SPI1_IRQn = 42, /**< 42 SAMS70N21 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70N21 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70N21 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70N21 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70N21 UART 4 (UART4) */
- TC9_IRQn = 50, /**< 50 SAMS70N21 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70N21 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70N21 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70N21 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70N21 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70N21 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70N21 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70N21 Pulse Width Modulation 1 (PWM1) */
- RSWDT_IRQn = 63, /**< 63 SAMS70N21 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pvReserved12;
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pvReserved17;
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pvReserved26;
- void* pvReserved27;
- void* pvReserved28;
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pvReserved30;
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pvReserved47;
- void* pvReserved48;
- void* pvReserved49;
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pvReserved62;
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOD_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void TWIHS2_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70N21 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70N21 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70N21 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70N21 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70N21 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70N21 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70N21 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70N21 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70N21 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70N21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N21_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N21_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/twihs2.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/piod.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N21_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N21_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70N21_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70n21.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x200000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (4096u)
-#define IFLASH_NB_OF_LOCK_BITS (128u)
-#define IRAM_SIZE (0x60000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA1120E00UL)
-#define CHIP_EXID (0x00000001UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70N21 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70N21_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70q19.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70q19.h
deleted file mode 100644
index ef33389..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70q19.h
+++ /dev/null
@@ -1,679 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70Q19_
-#define _SAMS70Q19_
-
-/** \addtogroup SAMS70Q19_definitions SAMS70Q19 definitions
- This file defines all structures and symbols for SAMS70Q19:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q19_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70Q19 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70Q19 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70Q19 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70Q19 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70Q19 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70Q19 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70Q19 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70Q19 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70Q19 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70Q19 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70Q19 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70Q19 Parallel I/O Controller B (PIOB) */
- PIOC_IRQn = 12, /**< 12 SAMS70Q19 Parallel I/O Controller C (PIOC) */
- USART0_IRQn = 13, /**< 13 SAMS70Q19 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70Q19 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70Q19 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70Q19 Parallel I/O Controller D (PIOD) */
- PIOE_IRQn = 17, /**< 17 SAMS70Q19 Parallel I/O Controller E (PIOE) */
- HSMCI_IRQn = 18, /**< 18 SAMS70Q19 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70Q19 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70Q19 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70Q19 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70Q19 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70Q19 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70Q19 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70Q19 Timer/Counter 2 (TC2) */
- TC3_IRQn = 26, /**< 26 SAMS70Q19 Timer/Counter 3 (TC3) */
- TC4_IRQn = 27, /**< 27 SAMS70Q19 Timer/Counter 4 (TC4) */
- TC5_IRQn = 28, /**< 28 SAMS70Q19 Timer/Counter 5 (TC5) */
- AFEC0_IRQn = 29, /**< 29 SAMS70Q19 Analog Front End 0 (AFEC0) */
- DACC_IRQn = 30, /**< 30 SAMS70Q19 Digital To Analog Converter (DACC) */
- PWM0_IRQn = 31, /**< 31 SAMS70Q19 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70Q19 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70Q19 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70Q19 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70Q19 Analog Front End 1 (AFEC1) */
- TWIHS2_IRQn = 41, /**< 41 SAMS70Q19 Two Wire Interface 2 HS (TWIHS2) */
- SPI1_IRQn = 42, /**< 42 SAMS70Q19 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70Q19 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70Q19 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70Q19 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70Q19 UART 4 (UART4) */
- TC6_IRQn = 47, /**< 47 SAMS70Q19 Timer/Counter 6 (TC6) */
- TC7_IRQn = 48, /**< 48 SAMS70Q19 Timer/Counter 7 (TC7) */
- TC8_IRQn = 49, /**< 49 SAMS70Q19 Timer/Counter 8 (TC8) */
- TC9_IRQn = 50, /**< 50 SAMS70Q19 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70Q19 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70Q19 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70Q19 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70Q19 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70Q19 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70Q19 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70Q19 Pulse Width Modulation 1 (PWM1) */
- SDRAMC_IRQn = 62, /**< 62 SAMS70Q19 SDRAM Controller (SDRAMC) */
- RSWDT_IRQn = 63, /**< 63 SAMS70Q19 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
- void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
- void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pfnTC6_Handler; /* 47 Timer/Counter 6 */
- void* pfnTC7_Handler; /* 48 Timer/Counter 7 */
- void* pfnTC8_Handler; /* 49 Timer/Counter 8 */
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void DACC_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOC_Handler ( void );
-void PIOD_Handler ( void );
-void PIOE_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SDRAMC_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC3_Handler ( void );
-void TC4_Handler ( void );
-void TC5_Handler ( void );
-void TC6_Handler ( void );
-void TC7_Handler ( void );
-void TC8_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void TWIHS2_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70Q19 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70Q19 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70Q19 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70Q19 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70Q19 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70Q19 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70Q19 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70Q19 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70Q19 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70Q19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q19_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/dacc.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/sdramc.h"
-#include "component/smc.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q19_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/tc1.h"
-#include "instance/tc2.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/dacc.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/twihs2.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/smc.h"
-#include "instance/sdramc.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/pioc.h"
-#include "instance/piod.h"
-#include "instance/pioe.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q19_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
-#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
-#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */
-#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */
-#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q19_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */
-#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */
-#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */
-#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */
-#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q19_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70q19.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x80000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (1024u)
-#define IFLASH_NB_OF_LOCK_BITS (32u)
-#define IRAM_SIZE (0x40000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA11D0A00UL)
-#define CHIP_EXID (0x00000002UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70Q19 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70Q19_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70q20.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70q20.h
deleted file mode 100644
index bfadf15..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70q20.h
+++ /dev/null
@@ -1,679 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70Q20_
-#define _SAMS70Q20_
-
-/** \addtogroup SAMS70Q20_definitions SAMS70Q20 definitions
- This file defines all structures and symbols for SAMS70Q20:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q20_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70Q20 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70Q20 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70Q20 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70Q20 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70Q20 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70Q20 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70Q20 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70Q20 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70Q20 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70Q20 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70Q20 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70Q20 Parallel I/O Controller B (PIOB) */
- PIOC_IRQn = 12, /**< 12 SAMS70Q20 Parallel I/O Controller C (PIOC) */
- USART0_IRQn = 13, /**< 13 SAMS70Q20 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70Q20 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70Q20 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70Q20 Parallel I/O Controller D (PIOD) */
- PIOE_IRQn = 17, /**< 17 SAMS70Q20 Parallel I/O Controller E (PIOE) */
- HSMCI_IRQn = 18, /**< 18 SAMS70Q20 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70Q20 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70Q20 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70Q20 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70Q20 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70Q20 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70Q20 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70Q20 Timer/Counter 2 (TC2) */
- TC3_IRQn = 26, /**< 26 SAMS70Q20 Timer/Counter 3 (TC3) */
- TC4_IRQn = 27, /**< 27 SAMS70Q20 Timer/Counter 4 (TC4) */
- TC5_IRQn = 28, /**< 28 SAMS70Q20 Timer/Counter 5 (TC5) */
- AFEC0_IRQn = 29, /**< 29 SAMS70Q20 Analog Front End 0 (AFEC0) */
- DACC_IRQn = 30, /**< 30 SAMS70Q20 Digital To Analog Converter (DACC) */
- PWM0_IRQn = 31, /**< 31 SAMS70Q20 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70Q20 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70Q20 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70Q20 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70Q20 Analog Front End 1 (AFEC1) */
- TWIHS2_IRQn = 41, /**< 41 SAMS70Q20 Two Wire Interface 2 HS (TWIHS2) */
- SPI1_IRQn = 42, /**< 42 SAMS70Q20 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70Q20 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70Q20 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70Q20 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70Q20 UART 4 (UART4) */
- TC6_IRQn = 47, /**< 47 SAMS70Q20 Timer/Counter 6 (TC6) */
- TC7_IRQn = 48, /**< 48 SAMS70Q20 Timer/Counter 7 (TC7) */
- TC8_IRQn = 49, /**< 49 SAMS70Q20 Timer/Counter 8 (TC8) */
- TC9_IRQn = 50, /**< 50 SAMS70Q20 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70Q20 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70Q20 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70Q20 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70Q20 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70Q20 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70Q20 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70Q20 Pulse Width Modulation 1 (PWM1) */
- SDRAMC_IRQn = 62, /**< 62 SAMS70Q20 SDRAM Controller (SDRAMC) */
- RSWDT_IRQn = 63, /**< 63 SAMS70Q20 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
- void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
- void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pfnTC6_Handler; /* 47 Timer/Counter 6 */
- void* pfnTC7_Handler; /* 48 Timer/Counter 7 */
- void* pfnTC8_Handler; /* 49 Timer/Counter 8 */
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void DACC_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOC_Handler ( void );
-void PIOD_Handler ( void );
-void PIOE_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SDRAMC_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC3_Handler ( void );
-void TC4_Handler ( void );
-void TC5_Handler ( void );
-void TC6_Handler ( void );
-void TC7_Handler ( void );
-void TC8_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void TWIHS2_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70Q20 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70Q20 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70Q20 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70Q20 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70Q20 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70Q20 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70Q20 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70Q20 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70Q20 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70Q20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q20_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/dacc.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/sdramc.h"
-#include "component/smc.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q20_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/tc1.h"
-#include "instance/tc2.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/dacc.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/twihs2.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/smc.h"
-#include "instance/sdramc.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/pioc.h"
-#include "instance/piod.h"
-#include "instance/pioe.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q20_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
-#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
-#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */
-#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */
-#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q20_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */
-#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */
-#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */
-#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */
-#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q20_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70q20.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x100000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (2048u)
-#define IFLASH_NB_OF_LOCK_BITS (64u)
-#define IRAM_SIZE (0x60000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA1120C00UL)
-#define CHIP_EXID (0x00000002UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70Q20 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70Q20_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70q21.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70q21.h
deleted file mode 100644
index 10bb674..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/include/sams70q21.h
+++ /dev/null
@@ -1,679 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAMS70Q21_
-#define _SAMS70Q21_
-
-/** \addtogroup SAMS70Q21_definitions SAMS70Q21 definitions
- This file defines all structures and symbols for SAMS70Q21:
- - registers and bitfields
- - peripheral base address
- - peripheral ID
- - PIO definitions
-*/
-/*@{*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#include <stdint.h>
-#endif
-
-/* ************************************************************************** */
-/* CMSIS DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q21_cmsis CMSIS Definitions */
-/*@{*/
-
-/**< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M7 Processor Exceptions Numbers ******************************/
- NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< 3 HardFault Interrupt */
- MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */
-/****** SAMS70Q21 specific Interrupt Numbers *********************************/
-
- SUPC_IRQn = 0, /**< 0 SAMS70Q21 Supply Controller (SUPC) */
- RSTC_IRQn = 1, /**< 1 SAMS70Q21 Reset Controller (RSTC) */
- RTC_IRQn = 2, /**< 2 SAMS70Q21 Real Time Clock (RTC) */
- RTT_IRQn = 3, /**< 3 SAMS70Q21 Real Time Timer (RTT) */
- WDT_IRQn = 4, /**< 4 SAMS70Q21 Watchdog Timer (WDT) */
- PMC_IRQn = 5, /**< 5 SAMS70Q21 Power Management Controller (PMC) */
- EFC_IRQn = 6, /**< 6 SAMS70Q21 Enhanced Embedded Flash Controller (EFC) */
- UART0_IRQn = 7, /**< 7 SAMS70Q21 UART 0 (UART0) */
- UART1_IRQn = 8, /**< 8 SAMS70Q21 UART 1 (UART1) */
- PIOA_IRQn = 10, /**< 10 SAMS70Q21 Parallel I/O Controller A (PIOA) */
- PIOB_IRQn = 11, /**< 11 SAMS70Q21 Parallel I/O Controller B (PIOB) */
- PIOC_IRQn = 12, /**< 12 SAMS70Q21 Parallel I/O Controller C (PIOC) */
- USART0_IRQn = 13, /**< 13 SAMS70Q21 USART 0 (USART0) */
- USART1_IRQn = 14, /**< 14 SAMS70Q21 USART 1 (USART1) */
- USART2_IRQn = 15, /**< 15 SAMS70Q21 USART 2 (USART2) */
- PIOD_IRQn = 16, /**< 16 SAMS70Q21 Parallel I/O Controller D (PIOD) */
- PIOE_IRQn = 17, /**< 17 SAMS70Q21 Parallel I/O Controller E (PIOE) */
- HSMCI_IRQn = 18, /**< 18 SAMS70Q21 Multimedia Card Interface (HSMCI) */
- TWIHS0_IRQn = 19, /**< 19 SAMS70Q21 Two Wire Interface 0 HS (TWIHS0) */
- TWIHS1_IRQn = 20, /**< 20 SAMS70Q21 Two Wire Interface 1 HS (TWIHS1) */
- SPI0_IRQn = 21, /**< 21 SAMS70Q21 Serial Peripheral Interface 0 (SPI0) */
- SSC_IRQn = 22, /**< 22 SAMS70Q21 Synchronous Serial Controller (SSC) */
- TC0_IRQn = 23, /**< 23 SAMS70Q21 Timer/Counter 0 (TC0) */
- TC1_IRQn = 24, /**< 24 SAMS70Q21 Timer/Counter 1 (TC1) */
- TC2_IRQn = 25, /**< 25 SAMS70Q21 Timer/Counter 2 (TC2) */
- TC3_IRQn = 26, /**< 26 SAMS70Q21 Timer/Counter 3 (TC3) */
- TC4_IRQn = 27, /**< 27 SAMS70Q21 Timer/Counter 4 (TC4) */
- TC5_IRQn = 28, /**< 28 SAMS70Q21 Timer/Counter 5 (TC5) */
- AFEC0_IRQn = 29, /**< 29 SAMS70Q21 Analog Front End 0 (AFEC0) */
- DACC_IRQn = 30, /**< 30 SAMS70Q21 Digital To Analog Converter (DACC) */
- PWM0_IRQn = 31, /**< 31 SAMS70Q21 Pulse Width Modulation 0 (PWM0) */
- ICM_IRQn = 32, /**< 32 SAMS70Q21 Integrity Check Monitor (ICM) */
- ACC_IRQn = 33, /**< 33 SAMS70Q21 Analog Comparator (ACC) */
- USBHS_IRQn = 34, /**< 34 SAMS70Q21 USB Host / Device Controller (USBHS) */
- AFEC1_IRQn = 40, /**< 40 SAMS70Q21 Analog Front End 1 (AFEC1) */
- TWIHS2_IRQn = 41, /**< 41 SAMS70Q21 Two Wire Interface 2 HS (TWIHS2) */
- SPI1_IRQn = 42, /**< 42 SAMS70Q21 Serial Peripheral Interface 1 (SPI1) */
- QSPI_IRQn = 43, /**< 43 SAMS70Q21 Quad I/O Serial Peripheral Interface (QSPI) */
- UART2_IRQn = 44, /**< 44 SAMS70Q21 UART 2 (UART2) */
- UART3_IRQn = 45, /**< 45 SAMS70Q21 UART 3 (UART3) */
- UART4_IRQn = 46, /**< 46 SAMS70Q21 UART 4 (UART4) */
- TC6_IRQn = 47, /**< 47 SAMS70Q21 Timer/Counter 6 (TC6) */
- TC7_IRQn = 48, /**< 48 SAMS70Q21 Timer/Counter 7 (TC7) */
- TC8_IRQn = 49, /**< 49 SAMS70Q21 Timer/Counter 8 (TC8) */
- TC9_IRQn = 50, /**< 50 SAMS70Q21 Timer/Counter 9 (TC9) */
- TC10_IRQn = 51, /**< 51 SAMS70Q21 Timer/Counter 10 (TC10) */
- TC11_IRQn = 52, /**< 52 SAMS70Q21 Timer/Counter 11 (TC11) */
- AES_IRQn = 56, /**< 56 SAMS70Q21 AES (AES) */
- TRNG_IRQn = 57, /**< 57 SAMS70Q21 True Random Generator (TRNG) */
- XDMAC_IRQn = 58, /**< 58 SAMS70Q21 DMA (XDMAC) */
- ISI_IRQn = 59, /**< 59 SAMS70Q21 Camera Interface (ISI) */
- PWM1_IRQn = 60, /**< 60 SAMS70Q21 Pulse Width Modulation 1 (PWM1) */
- SDRAMC_IRQn = 62, /**< 62 SAMS70Q21 SDRAM Controller (SDRAMC) */
- RSWDT_IRQn = 63, /**< 63 SAMS70Q21 Reinforced Secure Watchdog Timer (RSWDT) */
-
- PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */
-} IRQn_Type;
-
-typedef struct _DeviceVectors
-{
- /* Stack pointer */
- void* pvStack;
-
- /* Cortex-M handlers */
- void* pfnReset_Handler;
- void* pfnNMI_Handler;
- void* pfnHardFault_Handler;
- void* pfnMemManage_Handler;
- void* pfnBusFault_Handler;
- void* pfnUsageFault_Handler;
- void* pfnReserved1_Handler;
- void* pfnReserved2_Handler;
- void* pfnReserved3_Handler;
- void* pfnReserved4_Handler;
- void* pfnSVC_Handler;
- void* pfnDebugMon_Handler;
- void* pfnReserved5_Handler;
- void* pfnPendSV_Handler;
- void* pfnSysTick_Handler;
-
- /* Peripheral handlers */
- void* pfnSUPC_Handler; /* 0 Supply Controller */
- void* pfnRSTC_Handler; /* 1 Reset Controller */
- void* pfnRTC_Handler; /* 2 Real Time Clock */
- void* pfnRTT_Handler; /* 3 Real Time Timer */
- void* pfnWDT_Handler; /* 4 Watchdog Timer */
- void* pfnPMC_Handler; /* 5 Power Management Controller */
- void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
- void* pfnUART0_Handler; /* 7 UART 0 */
- void* pfnUART1_Handler; /* 8 UART 1 */
- void* pvReserved9;
- void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
- void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
- void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */
- void* pfnUSART0_Handler; /* 13 USART 0 */
- void* pfnUSART1_Handler; /* 14 USART 1 */
- void* pfnUSART2_Handler; /* 15 USART 2 */
- void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
- void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */
- void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
- void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
- void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
- void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
- void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
- void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
- void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
- void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
- void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
- void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
- void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
- void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
- void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
- void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
- void* pfnICM_Handler; /* 32 Integrity Check Monitor */
- void* pfnACC_Handler; /* 33 Analog Comparator */
- void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
- void* pvReserved35;
- void* pvReserved36;
- void* pvReserved37;
- void* pvReserved38;
- void* pvReserved39;
- void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
- void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
- void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
- void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
- void* pfnUART2_Handler; /* 44 UART 2 */
- void* pfnUART3_Handler; /* 45 UART 3 */
- void* pfnUART4_Handler; /* 46 UART 4 */
- void* pfnTC6_Handler; /* 47 Timer/Counter 6 */
- void* pfnTC7_Handler; /* 48 Timer/Counter 7 */
- void* pfnTC8_Handler; /* 49 Timer/Counter 8 */
- void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
- void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
- void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
- void* pvReserved53;
- void* pvReserved54;
- void* pvReserved55;
- void* pfnAES_Handler; /* 56 AES */
- void* pfnTRNG_Handler; /* 57 True Random Generator */
- void* pfnXDMAC_Handler; /* 58 DMA */
- void* pfnISI_Handler; /* 59 Camera Interface */
- void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
- void* pvReserved61;
- void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */
- void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
-} DeviceVectors;
-
-/* Cortex-M7 core handlers */
-void Reset_Handler ( void );
-void NMI_Handler ( void );
-void HardFault_Handler ( void );
-void MemManage_Handler ( void );
-void BusFault_Handler ( void );
-void UsageFault_Handler ( void );
-void SVC_Handler ( void );
-void DebugMon_Handler ( void );
-void PendSV_Handler ( void );
-void SysTick_Handler ( void );
-
-/* Peripherals handlers */
-void ACC_Handler ( void );
-void AES_Handler ( void );
-void AFEC0_Handler ( void );
-void AFEC1_Handler ( void );
-void DACC_Handler ( void );
-void EFC_Handler ( void );
-void HSMCI_Handler ( void );
-void ICM_Handler ( void );
-void ISI_Handler ( void );
-void PIOA_Handler ( void );
-void PIOB_Handler ( void );
-void PIOC_Handler ( void );
-void PIOD_Handler ( void );
-void PIOE_Handler ( void );
-void PMC_Handler ( void );
-void PWM0_Handler ( void );
-void PWM1_Handler ( void );
-void QSPI_Handler ( void );
-void RSTC_Handler ( void );
-void RSWDT_Handler ( void );
-void RTC_Handler ( void );
-void RTT_Handler ( void );
-void SDRAMC_Handler ( void );
-void SPI0_Handler ( void );
-void SPI1_Handler ( void );
-void SSC_Handler ( void );
-void SUPC_Handler ( void );
-void TC0_Handler ( void );
-void TC1_Handler ( void );
-void TC2_Handler ( void );
-void TC3_Handler ( void );
-void TC4_Handler ( void );
-void TC5_Handler ( void );
-void TC6_Handler ( void );
-void TC7_Handler ( void );
-void TC8_Handler ( void );
-void TC9_Handler ( void );
-void TC10_Handler ( void );
-void TC11_Handler ( void );
-void TRNG_Handler ( void );
-void TWIHS0_Handler ( void );
-void TWIHS1_Handler ( void );
-void TWIHS2_Handler ( void );
-void UART0_Handler ( void );
-void UART1_Handler ( void );
-void UART2_Handler ( void );
-void UART3_Handler ( void );
-void UART4_Handler ( void );
-void USART0_Handler ( void );
-void USART1_Handler ( void );
-void USART2_Handler ( void );
-void USBHS_Handler ( void );
-void WDT_Handler ( void );
-void XDMAC_Handler ( void );
-
-/**
- * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
- */
-
-#define __CM7_REV 0x0000 /**< SAMS70Q21 core revision number ([15:8] revision number, [7:0] patch number) */
-#define __MPU_PRESENT 1 /**< SAMS70Q21 does provide a MPU */
-#define __NVIC_PRIO_BITS 3 /**< SAMS70Q21 uses 3 Bits for the Priority Levels */
-#define __FPU_PRESENT 1 /**< SAMS70Q21 does provide a FPU */
-#define __FPU_DP 1 /**< SAMS70Q21 Double precision FPU */
-#define __ICACHE_PRESENT 1 /**< SAMS70Q21 does provide an Instruction Cache */
-#define __DCACHE_PRESENT 1 /**< SAMS70Q21 does provide a Data Cache */
-#define __DTCM_PRESENT 1 /**< SAMS70Q21 does provide a Data TCM */
-#define __ITCM_PRESENT 1 /**< SAMS70Q21 does provide an Instruction TCM */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
-
-/*
- * \brief CMSIS includes
- */
-
-#include <core_cm7.h>
-#if !defined DONT_USE_CMSIS_INIT
-#include "system_sams70.h"
-#endif /* DONT_USE_CMSIS_INIT */
-
-/*@}*/
-
-/* ************************************************************************** */
-/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMS70Q21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q21_api Peripheral Software API */
-/*@{*/
-
-#include "component/acc.h"
-#include "component/aes.h"
-#include "component/afec.h"
-#include "component/chipid.h"
-#include "component/dacc.h"
-#include "component/efc.h"
-#include "component/gpbr.h"
-#include "component/hsmci.h"
-#include "component/icm.h"
-#include "component/isi.h"
-#include "component/matrix.h"
-#include "component/pio.h"
-#include "component/pmc.h"
-#include "component/pwm.h"
-#include "component/qspi.h"
-#include "component/rstc.h"
-#include "component/rswdt.h"
-#include "component/rtc.h"
-#include "component/rtt.h"
-#include "component/sdramc.h"
-#include "component/smc.h"
-#include "component/spi.h"
-#include "component/ssc.h"
-#include "component/supc.h"
-#include "component/tc.h"
-#include "component/trng.h"
-#include "component/twihs.h"
-#include "component/uart.h"
-#include "component/usart.h"
-#include "component/usbhs.h"
-#include "component/utmi.h"
-#include "component/wdt.h"
-#include "component/xdmac.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* REGISTER ACCESS DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q21_reg Registers Access Definitions */
-/*@{*/
-
-#include "instance/hsmci.h"
-#include "instance/ssc.h"
-#include "instance/spi0.h"
-#include "instance/tc0.h"
-#include "instance/tc1.h"
-#include "instance/tc2.h"
-#include "instance/twihs0.h"
-#include "instance/twihs1.h"
-#include "instance/pwm0.h"
-#include "instance/usart0.h"
-#include "instance/usart1.h"
-#include "instance/usart2.h"
-#include "instance/usbhs.h"
-#include "instance/afec0.h"
-#include "instance/dacc.h"
-#include "instance/acc.h"
-#include "instance/icm.h"
-#include "instance/isi.h"
-#include "instance/tc3.h"
-#include "instance/spi1.h"
-#include "instance/pwm1.h"
-#include "instance/twihs2.h"
-#include "instance/afec1.h"
-#include "instance/aes.h"
-#include "instance/trng.h"
-#include "instance/xdmac.h"
-#include "instance/qspi.h"
-#include "instance/smc.h"
-#include "instance/sdramc.h"
-#include "instance/matrix.h"
-#include "instance/utmi.h"
-#include "instance/pmc.h"
-#include "instance/uart0.h"
-#include "instance/chipid.h"
-#include "instance/uart1.h"
-#include "instance/efc.h"
-#include "instance/pioa.h"
-#include "instance/piob.h"
-#include "instance/pioc.h"
-#include "instance/piod.h"
-#include "instance/pioe.h"
-#include "instance/rstc.h"
-#include "instance/supc.h"
-#include "instance/rtt.h"
-#include "instance/wdt.h"
-#include "instance/rtc.h"
-#include "instance/gpbr.h"
-#include "instance/rswdt.h"
-#include "instance/uart2.h"
-#include "instance/uart3.h"
-#include "instance/uart4.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* PERIPHERAL ID DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q21_id Peripheral Ids Definitions */
-/*@{*/
-
-#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
-#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
-#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
-#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
-#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
-#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
-#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
-#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */
-#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */
-#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
-#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */
-#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
-#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
-#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
-#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
-#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
-#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */
-#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */
-#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */
-#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
-#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
-#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
-#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */
-#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
-#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
-#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
-#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
-#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
-#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
-#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */
-#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
-#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
-#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */
-#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */
-#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */
-#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */
-#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */
-#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
-#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
-#define ID_UART2 (44) /**< \brief UART 2 (UART2) */
-#define ID_UART3 (45) /**< \brief UART 3 (UART3) */
-#define ID_UART4 (46) /**< \brief UART 4 (UART4) */
-#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */
-#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */
-#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */
-#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */
-#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */
-#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */
-#define ID_AES (56) /**< \brief AES (AES) */
-#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */
-#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */
-#define ID_ISI (59) /**< \brief Camera Interface (ISI) */
-#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
-#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */
-#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
-
-#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
-/*@}*/
-
-/* ************************************************************************** */
-/* BASE ADDRESS DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q21_base Peripheral Base Address Definitions */
-/*@{*/
-
-#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */
-#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */
-#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES (0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */
-#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */
-#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */
-#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */
-#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#else
-#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */
-#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */
-#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */
-#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */
-#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */
-#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */
-#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */
-#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
-#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */
-#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */
-#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */
-#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */
-#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */
-#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
-#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */
-#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */
-#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */
-#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */
-#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */
-#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */
-#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */
-#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */
-#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
-#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */
-#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */
-#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */
-#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */
-#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */
-#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */
-#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
-#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */
-#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */
-#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */
-#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
-#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
-#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */
-#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */
-#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */
-#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */
-#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */
-#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */
-#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */
-#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */
-#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */
-#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */
-#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */
-#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */
-#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
-#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
-#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
-#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
-#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-/*@}*/
-
-/* ************************************************************************** */
-/* PIO DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-/** \addtogroup SAMS70Q21_pio Peripheral Pio Definitions */
-/*@{*/
-
-#include "pio/sams70q21.h"
-/*@}*/
-
-/* ************************************************************************** */
-/* MEMORY MAPPING DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-
-#define IFLASH_SIZE (0x200000u)
-#define IFLASH_PAGE_SIZE (512u)
-#define IFLASH_LOCK_REGION_SIZE (16384u)
-#define IFLASH_NB_OF_PAGES (4096u)
-#define IFLASH_NB_OF_LOCK_BITS (128u)
-#define IRAM_SIZE (0x60000u)
-
-#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */
-#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */
-#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
-#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
-#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
-#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */
-#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */
-#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
-#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
-#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */
-#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */
-#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
-#define USBHS_RAM_ADDR (0xA0100000u) /**< USBHS Chip Select base address */
-
-/* ************************************************************************** */
-/* MISCELLANEOUS DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-
-#define CHIP_JTAGID (0x05B3D03FUL)
-#define CHIP_CIDR (0xA1120E00UL)
-#define CHIP_EXID (0x00000002UL)
-
-/* ************************************************************************** */
-/* ELECTRICAL DEFINITIONS FOR SAMS70Q21 */
-/* ************************************************************************** */
-
-/* %ATMEL_ELECTRICAL% */
-
-/* Device characteristics */
-#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
-#define CHIP_FREQ_SLCK_RC (32000UL)
-#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
-#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
-#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
-#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
-#define CHIP_FREQ_CPU_MAX (300000000UL)
-#define CHIP_FREQ_XTAL_32K (32768UL)
-#define CHIP_FREQ_XTAL_12M (12000000UL)
-
-/* Embedded Flash Read Wait State (for Worst-Case Conditions) */
-#define CHIP_FREQ_FWS_0 (23000000UL) /**< \brief Maximum operating frequency when FWS is 0 */
-#define CHIP_FREQ_FWS_1 (46000000UL) /**< \brief Maximum operating frequency when FWS is 1 */
-#define CHIP_FREQ_FWS_2 (69000000UL) /**< \brief Maximum operating frequency when FWS is 2 */
-#define CHIP_FREQ_FWS_3 (92000000UL) /**< \brief Maximum operating frequency when FWS is 3 */
-#define CHIP_FREQ_FWS_4 (115000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
-#define CHIP_FREQ_FWS_5 (138000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
-#define CHIP_FREQ_FWS_6 (150000000UL) /**< \brief Maximum operating frequency when FWS is 6 */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/
-
-#endif /* _SAMS70Q21_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/source/templates/gcc/startup_sams70.c b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/source/templates/gcc/startup_sams70.c
deleted file mode 100644
index b7e19af..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/source/templates/gcc/startup_sams70.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include "sams70.h"
-
-/* Initialize segments */
-extern uint32_t _sfixed;
-extern uint32_t _efixed;
-extern uint32_t _etext;
-extern uint32_t _srelocate;
-extern uint32_t _erelocate;
-extern uint32_t _szero;
-extern uint32_t _ezero;
-extern uint32_t _sstack;
-extern uint32_t _estack;
-
-/** \cond DOXYGEN_SHOULD_SKIP_THIS */
-int main(void);
-/** \endcond */
-
-void __libc_init_array(void);
-
-/* Default empty handler */
-void Dummy_Handler(void);
-
-/* Cortex-M7 core handlers */
-void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void MemManage_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void DebugMon_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-
-/* Peripherals handlers */
-void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef _SAMS70_PIOC_INSTANCE_
-void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_PIOC_INSTANCE_ */
-void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void PIOD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef _SAMS70_PIOE_INSTANCE_
-void PIOE_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_PIOE_INSTANCE_ */
-void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TWIHS0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TWIHS1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SPI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef _SAMS70_TC1_INSTANCE_
-void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_TC1_INSTANCE_ */
-#ifdef _SAMS70_TC1_INSTANCE_
-void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_TC1_INSTANCE_ */
-#ifdef _SAMS70_TC1_INSTANCE_
-void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_TC1_INSTANCE_ */
-void AFEC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef _SAMS70_DACC_INSTANCE_
-void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_DACC_INSTANCE_ */
-void PWM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void USBHS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void AFEC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef _SAMS70_TWIHS2_INSTANCE_
-void TWIHS2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_TWIHS2_INSTANCE_ */
-void SPI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void UART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void UART3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void UART4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef _SAMS70_TC2_INSTANCE_
-void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_TC2_INSTANCE_ */
-#ifdef _SAMS70_TC2_INSTANCE_
-void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_TC2_INSTANCE_ */
-#ifdef _SAMS70_TC2_INSTANCE_
-void TC8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_TC2_INSTANCE_ */
-void TC9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TC10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TC11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void XDMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void ISI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-void PWM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#ifdef _SAMS70_SDRAMC_INSTANCE_
-void SDRAMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-#endif /* _SAMS70_SDRAMC_INSTANCE_ */
-void RSWDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
-
-/* Exception Table */
-__attribute__ ((section(".vectors")))
-const DeviceVectors exception_table = {
-
- /* Configure Initial Stack Pointer, using linker-generated symbols */
- .pvStack = (void*) (&_estack),
-
- .pfnReset_Handler = (void*) Reset_Handler,
- .pfnNMI_Handler = (void*) NMI_Handler,
- .pfnHardFault_Handler = (void*) HardFault_Handler,
- .pfnMemManage_Handler = (void*) MemManage_Handler,
- .pfnBusFault_Handler = (void*) BusFault_Handler,
- .pfnUsageFault_Handler = (void*) UsageFault_Handler,
- .pfnReserved1_Handler = (void*) (0UL), /* Reserved */
- .pfnReserved2_Handler = (void*) (0UL), /* Reserved */
- .pfnReserved3_Handler = (void*) (0UL), /* Reserved */
- .pfnReserved4_Handler = (void*) (0UL), /* Reserved */
- .pfnSVC_Handler = (void*) SVC_Handler,
- .pfnDebugMon_Handler = (void*) DebugMon_Handler,
- .pfnReserved5_Handler = (void*) (0UL), /* Reserved */
- .pfnPendSV_Handler = (void*) PendSV_Handler,
- .pfnSysTick_Handler = (void*) SysTick_Handler,
-
- /* Configurable interrupts */
- .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */
- .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */
- .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real Time Clock */
- .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real Time Timer */
- .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */
- .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */
- .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Enhanced Embedded Flash Controller */
- .pfnUART0_Handler = (void*) UART0_Handler, /* 7 UART 0 */
- .pfnUART1_Handler = (void*) UART1_Handler, /* 8 UART 1 */
- .pvReserved9 = (void*) (0UL), /* 9 Reserved */
- .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel I/O Controller A */
- .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel I/O Controller B */
-#ifdef _SAMS70_PIOC_INSTANCE_
- .pfnPIOC_Handler = (void*) PIOC_Handler, /* 12 Parallel I/O Controller C */
-#else
- .pvReserved12 = (void*) (0UL), /* 12 Reserved */
-#endif /* _SAMS70_PIOC_INSTANCE_ */
- .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 USART 0 */
- .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 USART 1 */
- .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 USART 2 */
- .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel I/O Controller D */
-#ifdef _SAMS70_PIOE_INSTANCE_
- .pfnPIOE_Handler = (void*) PIOE_Handler, /* 17 Parallel I/O Controller E */
-#else
- .pvReserved17 = (void*) (0UL), /* 17 Reserved */
-#endif /* _SAMS70_PIOE_INSTANCE_ */
- .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 Multimedia Card Interface */
- .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two Wire Interface 0 HS */
- .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two Wire Interface 1 HS */
- .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface 0 */
- .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */
- .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer/Counter 0 */
- .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer/Counter 1 */
- .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer/Counter 2 */
-#ifdef _SAMS70_TC1_INSTANCE_
- .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer/Counter 3 */
-#else
- .pvReserved26 = (void*) (0UL), /* 26 Reserved */
-#endif /* _SAMS70_TC1_INSTANCE_ */
-#ifdef _SAMS70_TC1_INSTANCE_
- .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer/Counter 4 */
-#else
- .pvReserved27 = (void*) (0UL), /* 27 Reserved */
-#endif /* _SAMS70_TC1_INSTANCE_ */
-#ifdef _SAMS70_TC1_INSTANCE_
- .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer/Counter 5 */
-#else
- .pvReserved28 = (void*) (0UL), /* 28 Reserved */
-#endif /* _SAMS70_TC1_INSTANCE_ */
- .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front End 0 */
-#ifdef _SAMS70_DACC_INSTANCE_
- .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital To Analog Converter */
-#else
- .pvReserved30 = (void*) (0UL), /* 30 Reserved */
-#endif /* _SAMS70_DACC_INSTANCE_ */
- .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation 0 */
- .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */
- .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator */
- .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB Host / Device Controller */
- .pvReserved35 = (void*) (0UL), /* 35 Reserved */
- .pvReserved36 = (void*) (0UL), /* 36 Reserved */
- .pvReserved37 = (void*) (0UL), /* 37 Reserved */
- .pvReserved38 = (void*) (0UL), /* 38 Reserved */
- .pvReserved39 = (void*) (0UL), /* 39 Reserved */
- .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front End 1 */
-#ifdef _SAMS70_TWIHS2_INSTANCE_
- .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two Wire Interface 2 HS */
-#else
- .pvReserved41 = (void*) (0UL), /* 41 Reserved */
-#endif /* _SAMS70_TWIHS2_INSTANCE_ */
- .pfnSPI1_Handler = (void*) SPI1_Handler, /* 42 Serial Peripheral Interface 1 */
- .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad I/O Serial Peripheral Interface */
- .pfnUART2_Handler = (void*) UART2_Handler, /* 44 UART 2 */
- .pfnUART3_Handler = (void*) UART3_Handler, /* 45 UART 3 */
- .pfnUART4_Handler = (void*) UART4_Handler, /* 46 UART 4 */
-#ifdef _SAMS70_TC2_INSTANCE_
- .pfnTC6_Handler = (void*) TC6_Handler, /* 47 Timer/Counter 6 */
-#else
- .pvReserved47 = (void*) (0UL), /* 47 Reserved */
-#endif /* _SAMS70_TC2_INSTANCE_ */
-#ifdef _SAMS70_TC2_INSTANCE_
- .pfnTC7_Handler = (void*) TC7_Handler, /* 48 Timer/Counter 7 */
-#else
- .pvReserved48 = (void*) (0UL), /* 48 Reserved */
-#endif /* _SAMS70_TC2_INSTANCE_ */
-#ifdef _SAMS70_TC2_INSTANCE_
- .pfnTC8_Handler = (void*) TC8_Handler, /* 49 Timer/Counter 8 */
-#else
- .pvReserved49 = (void*) (0UL), /* 49 Reserved */
-#endif /* _SAMS70_TC2_INSTANCE_ */
- .pfnTC9_Handler = (void*) TC9_Handler, /* 50 Timer/Counter 9 */
- .pfnTC10_Handler = (void*) TC10_Handler, /* 51 Timer/Counter 10 */
- .pfnTC11_Handler = (void*) TC11_Handler, /* 52 Timer/Counter 11 */
- .pvReserved53 = (void*) (0UL), /* 53 Reserved */
- .pvReserved54 = (void*) (0UL), /* 54 Reserved */
- .pvReserved55 = (void*) (0UL), /* 55 Reserved */
- .pfnAES_Handler = (void*) AES_Handler, /* 56 AES */
- .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Generator */
- .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 DMA */
- .pfnISI_Handler = (void*) ISI_Handler, /* 59 Camera Interface */
- .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation 1 */
- .pvReserved61 = (void*) (0UL), /* 61 Reserved */
-#ifdef _SAMS70_SDRAMC_INSTANCE_
- .pfnSDRAMC_Handler = (void*) SDRAMC_Handler, /* 62 SDRAM Controller */
-#else
- .pvReserved62 = (void*) (0UL), /* 62 Reserved */
-#endif /* _SAMS70_SDRAMC_INSTANCE_ */
- .pfnRSWDT_Handler = (void*) RSWDT_Handler /* 63 Reinforced Secure Watchdog Timer */
-};
-
-/**
- * \brief This is the code that gets called on processor reset.
- * To initialize the device, and call the main() routine.
- */
-void Reset_Handler(void)
-{
- uint32_t *pSrc, *pDest;
-
- /* Initialize the relocate segment */
- pSrc = &_etext;
- pDest = &_srelocate;
-
- if (pSrc != pDest) {
- for (; pDest < &_erelocate;) {
- *pDest++ = *pSrc++;
- }
- }
-
- /* Clear the zero segment */
- for (pDest = &_szero; pDest < &_ezero;) {
- *pDest++ = 0;
- }
-
- /* Set the vector table base address */
- pSrc = (uint32_t *) & _sfixed;
- SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
-
- /* Initialize the C library */
- __libc_init_array();
-
- /* Branch to main function */
- main();
-
- /* Infinite loop */
- while (1);
-}
-
-/**
- * \brief Default interrupt handler for unused IRQs.
- */
-void Dummy_Handler(void)
-{
- while (1) {
- }
-}
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/source/templates/system_sams70.c b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/source/templates/system_sams70.c
deleted file mode 100644
index 0f7215a..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/source/templates/system_sams70.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include "sams70.h"
-
-/* @cond 0 */
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/* @endcond */
-
-/* %ATMEL_SYSTEM% */
-/* Clock Settings (600MHz PLL VDDIO 3.3V and VDDCORE 1.2V) */
-/* Clock Settings (300MHz HCLK, 150MHz MCK)=> PRESC = 2, MDIV = 2 */
-#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U))
-#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x31U) | \
- CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U))
-#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK | (1<<8))
-
-uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
-
-/**
- * \brief Setup the microcontroller system.
- * Initialize the System and update the SystemFrequency variable.
- */
- void SystemInit( void )
-{
- /* Set FWS according to SYS_BOARD_MCKR configuration */
- EFC->EEFC_FMR = EEFC_FMR_FWS(5);
-
- /* Initialize main oscillator */
- if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
- {
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
-
- while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) )
- {
- }
- }
-
- /* Switch to 3-20MHz Xtal oscillator */
- PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
-
- while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) )
- {
- }
-
- PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
-
- while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
- {
- }
-
- /* Initialize PLLA */
- PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
- while ( !(PMC->PMC_SR & PMC_SR_LOCKA) )
- {
- }
-
- /* Switch to main clock */
- PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
- while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
- {
- }
-
- /* Switch to PLLA */
- PMC->PMC_MCKR = SYS_BOARD_MCKR;
- while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
- {
- }
-
- SystemCoreClock = CHIP_FREQ_CPU_MAX;
-}
-
-void SystemCoreClockUpdate( void )
-{
- /* Determine clock frequency according to clock register values */
- switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk)
- {
- case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
- if ( SUPC->SUPC_SR & SUPC_SR_OSCSEL )
- {
- SystemCoreClock = CHIP_FREQ_XTAL_32K;
- }
- else
- {
- SystemCoreClock = CHIP_FREQ_SLCK_RC;
- }
- break;
-
- case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
- if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL )
- {
- SystemCoreClock = CHIP_FREQ_XTAL_12M;
- }
- else
- {
- SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
-
- switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk )
- {
- case CKGR_MOR_MOSCRCF_4_MHz:
- break;
-
- case CKGR_MOR_MOSCRCF_8_MHz:
- SystemCoreClock *= 2U;
- break;
-
- case CKGR_MOR_MOSCRCF_12_MHz:
- SystemCoreClock *= 3U;
- break;
-
- default:
- break;
- }
- }
- break;
-
- case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
- if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL )
- {
- SystemCoreClock = CHIP_FREQ_XTAL_12M ;
- }
- else
- {
- SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
-
- switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk )
- {
- case CKGR_MOR_MOSCRCF_4_MHz:
- break;
-
- case CKGR_MOR_MOSCRCF_8_MHz:
- SystemCoreClock *= 2U;
- break;
-
- case CKGR_MOR_MOSCRCF_12_MHz:
- SystemCoreClock *= 3U;
- break;
-
- default:
- break;
- }
- }
-
- if ( (uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK )
- {
- SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos) + 1U);
- SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos));
- }
- break;
-
- default:
- break;
- }
-
- if ( (PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3 )
- {
- SystemCoreClock /= 3U;
- }
- else
- {
- SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
- }
-}
-/**
- * Initialize flash.
- */
-void system_init_flash( uint32_t ul_clk )
-{
- /* Set FWS for embedded Flash access according to operating frequency */
- if ( ul_clk < CHIP_FREQ_FWS_0 )
- {
- EFC->EEFC_FMR = EEFC_FMR_FWS(0)|EEFC_FMR_CLOE;
- }
- else
- {
- if (ul_clk < CHIP_FREQ_FWS_1)
- {
- EFC->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE;
- }
- else
- {
- if (ul_clk < CHIP_FREQ_FWS_2)
- {
- EFC->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE;
- }
- else
- {
- if ( ul_clk < CHIP_FREQ_FWS_3 )
- {
- EFC->EEFC_FMR = EEFC_FMR_FWS(3)|EEFC_FMR_CLOE;
- }
- else
- {
- if ( ul_clk < CHIP_FREQ_FWS_4 )
- {
- EFC->EEFC_FMR = EEFC_FMR_FWS(4)|EEFC_FMR_CLOE;
- }
- else
- {
- if ( ul_clk < CHIP_FREQ_FWS_5 )
- {
- EFC->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE;
- }
- else
- {
- EFC->EEFC_FMR = EEFC_FMR_FWS(6)|EEFC_FMR_CLOE;
- }
- }
- }
- }
- }
- }
-}
-/* @cond 0 */
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/* @endcond */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/source/templates/system_sams70.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/source/templates/system_sams70.h
deleted file mode 100644
index 3eaf055..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/cmsis/sams70/source/templates/system_sams70.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef SYSTEM_SAMS70_H_INCLUDED
-#define SYSTEM_SAMS70_H_INCLUDED
-
-/* @cond 0 */
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/* @endcond */
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
-
-/**
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-void SystemInit(void);
-
-/**
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-void SystemCoreClockUpdate(void);
-
-/**
- * Initialize flash.
- */
-void system_init_flash(uint32_t dw_clk);
-
-/* @cond 0 */
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/* @endcond */
-
-#endif /* SYSTEM_SAMS70_H_INCLUDED */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/compiler.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/compiler.h
deleted file mode 100644
index 201fa7e..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/compiler.h
+++ /dev/null
@@ -1,1199 +0,0 @@
-/**
- * \file
- *
- * \brief Commonly used includes, types and macros.
- *
- * Copyright (c) 2010-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef UTILS_COMPILER_H
-#define UTILS_COMPILER_H
-
-/**
- * \defgroup group_sam_utils Compiler abstraction layer and code utilities
- *
- * Compiler abstraction layer and code utilities for AT91SAM.
- * This module provides various abstraction layers and utilities to make code compatible between different compilers.
- *
- * \{
- */
-#include <stddef.h>
-
-#if (defined __ICCARM__)
-# include <intrinsics.h>
-#endif
-
-#include <parts.h>
-#include "preprocessor.h"
-
-#include <io.h>
-
-//_____ D E C L A R A T I O N S ____________________________________________
-
-#ifndef __ASSEMBLY__ // Not defined for assembling.
-
-#include <stdio.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdlib.h>
-
-#ifdef __ICCARM__
-/*! \name Compiler Keywords
- *
- * Port of some keywords from GCC to IAR Embedded Workbench.
- */
-//! @{
-#define __asm__ asm
-#define __inline__ inline
-#define __volatile__
-//! @}
-
-#endif
-
-#define FUNC_PTR void *
-/**
- * \def UNUSED
- * \brief Marking \a v as a unused parameter or value.
- */
-#define UNUSED(v) (void)(v)
-
-/**
- * \def unused
- * \brief Marking \a v as a unused parameter or value.
- */
-#define unused(v) do { (void)(v); } while(0)
-
-/**
- * \def barrier
- * \brief Memory barrier
- */
-#define barrier() __DMB()
-
-/**
- * \brief Emit the compiler pragma \a arg.
- *
- * \param arg The pragma directive as it would appear after \e \#pragma
- * (i.e. not stringified).
- */
-#define COMPILER_PRAGMA(arg) _Pragma(#arg)
-
-/**
- * \def COMPILER_PACK_SET(alignment)
- * \brief Set maximum alignment for subsequent struct and union
- * definitions to \a alignment.
- */
-#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))
-
-/**
- * \def COMPILER_PACK_RESET()
- * \brief Set default alignment for subsequent struct and union
- * definitions.
- */
-#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())
-
-
-/**
- * \brief Set aligned boundary.
- */
-#if (defined __GNUC__) || (defined __CC_ARM)
-# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
-#elif (defined __ICCARM__)
-# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)
-#endif
-
-/**
- * \brief Set word-aligned boundary.
- */
-#if (defined __GNUC__) || defined(__CC_ARM)
-#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))
-#elif (defined __ICCARM__)
-#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4)
-#endif
-
-/**
- * \def __always_inline
- * \brief The function should always be inlined.
- *
- * This annotation instructs the compiler to ignore its inlining
- * heuristics and inline the function no matter how big it thinks it
- * becomes.
- */
-#if defined(__CC_ARM)
-# define __always_inline __forceinline
-#elif (defined __GNUC__)
-#ifdef __always_inline
-# undef __always_inline
-#endif
-# define __always_inline inline __attribute__((__always_inline__))
-#elif (defined __ICCARM__)
-# define __always_inline _Pragma("inline=forced")
-#endif
-
-/**
- * \def __no_inline
- * \brief The function should not be inlined.
- *
- * This annotation instructs the compiler to ignore its inlining
- * heuristics and not inline the function.
- */
-#if defined(__CC_ARM)
-# define __no_inline __attribute__((noinline))
-#elif (defined __GNUC__)
-# define __no_inline __attribute__((__noinline__))
-#elif (defined __ICCARM__)
-# define __no_inline _Pragma("inline=never")
-#endif
-
-/*! \brief This macro is used to test fatal errors.
- *
- * The macro tests if the expression is false. If it is, a fatal error is
- * detected and the application hangs up. If TEST_SUITE_DEFINE_ASSERT_MACRO
- * is defined, a unit test version of the macro is used, to allow execution
- * of further tests after a false expression.
- *
- * \param expr Expression to evaluate and supposed to be nonzero.
- */
-#if defined(_ASSERT_ENABLE_)
-# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)
- // Assert() is defined in unit_test/suite.h
-# include "unit_test/suite.h"
-# else
-#undef TEST_SUITE_DEFINE_ASSERT_MACRO
-# define Assert(expr) \
- {\
- if (!(expr)) while (true);\
- }
-# endif
-#else
-# define Assert(expr) ((void) 0)
-#endif
-
-/* Define WEAK attribute */
-#if defined ( __CC_ARM ) /* Keil µVision 4 */
-# define WEAK __attribute__ ((weak))
-#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
-# define WEAK __weak
-#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
-# define WEAK __attribute__ ((weak))
-#endif
-
-/* Define NO_INIT attribute */
-#if defined ( __CC_ARM )
-# define NO_INIT __attribute__((zero_init))
-#elif defined ( __ICCARM__ )
-# define NO_INIT __no_init
-#elif defined ( __GNUC__ )
-# define NO_INIT __attribute__((section(".no_init")))
-#endif
-
-/* Define RAMFUNC attribute */
-#if defined ( __CC_ARM ) /* Keil µVision 4 */
-# define RAMFUNC __attribute__ ((section(".ramfunc")))
-#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
-# define RAMFUNC __ramfunc
-#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
-# define RAMFUNC __attribute__ ((section(".ramfunc")))
-#endif
-
-/* Define OPTIMIZE_HIGH attribute */
-#if defined ( __CC_ARM ) /* Keil µVision 4 */
-# define OPTIMIZE_HIGH _Pragma("O3")
-#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
-# define OPTIMIZE_HIGH _Pragma("optimize=high")
-#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */
-# define OPTIMIZE_HIGH __attribute__((optimize("s")))
-#endif
-
-#include "interrupt.h"
-
-/*! \name Usual Types
- */
-//! @{
-typedef unsigned char Bool; //!< Boolean.
-#ifndef __cplusplus
-#if !defined(__bool_true_false_are_defined)
-typedef unsigned char bool; //!< Boolean.
-#endif
-#endif
-typedef int8_t S8 ; //!< 8-bit signed integer.
-typedef uint8_t U8 ; //!< 8-bit unsigned integer.
-typedef int16_t S16; //!< 16-bit signed integer.
-typedef uint16_t U16; //!< 16-bit unsigned integer.
-typedef uint16_t le16_t;
-typedef uint16_t be16_t;
-typedef int32_t S32; //!< 32-bit signed integer.
-typedef uint32_t U32; //!< 32-bit unsigned integer.
-typedef uint32_t le32_t;
-typedef uint32_t be32_t;
-typedef int64_t S64; //!< 64-bit signed integer.
-typedef uint64_t U64; //!< 64-bit unsigned integer.
-typedef float F32; //!< 32-bit floating-point number.
-typedef double F64; //!< 64-bit floating-point number.
-typedef uint32_t iram_size_t;
-//! @}
-
-
-/*! \name Status Types
- */
-//! @{
-typedef bool Status_bool_t; //!< Boolean status.
-typedef U8 Status_t; //!< 8-bit-coded status.
-//! @}
-
-
-/*! \name Aliasing Aggregate Types
- */
-//! @{
-
-//! 16-bit union.
-typedef union
-{
- S16 s16 ;
- U16 u16 ;
- S8 s8 [2];
- U8 u8 [2];
-} Union16;
-
-//! 32-bit union.
-typedef union
-{
- S32 s32 ;
- U32 u32 ;
- S16 s16[2];
- U16 u16[2];
- S8 s8 [4];
- U8 u8 [4];
-} Union32;
-
-//! 64-bit union.
-typedef union
-{
- S64 s64 ;
- U64 u64 ;
- S32 s32[2];
- U32 u32[2];
- S16 s16[4];
- U16 u16[4];
- S8 s8 [8];
- U8 u8 [8];
-} Union64;
-
-//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
-typedef union
-{
- S64 *s64ptr;
- U64 *u64ptr;
- S32 *s32ptr;
- U32 *u32ptr;
- S16 *s16ptr;
- U16 *u16ptr;
- S8 *s8ptr ;
- U8 *u8ptr ;
-} UnionPtr;
-
-//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
-typedef union
-{
- volatile S64 *s64ptr;
- volatile U64 *u64ptr;
- volatile S32 *s32ptr;
- volatile U32 *u32ptr;
- volatile S16 *s16ptr;
- volatile U16 *u16ptr;
- volatile S8 *s8ptr ;
- volatile U8 *u8ptr ;
-} UnionVPtr;
-
-//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
-typedef union
-{
- const S64 *s64ptr;
- const U64 *u64ptr;
- const S32 *s32ptr;
- const U32 *u32ptr;
- const S16 *s16ptr;
- const U16 *u16ptr;
- const S8 *s8ptr ;
- const U8 *u8ptr ;
-} UnionCPtr;
-
-//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
-typedef union
-{
- const volatile S64 *s64ptr;
- const volatile U64 *u64ptr;
- const volatile S32 *s32ptr;
- const volatile U32 *u32ptr;
- const volatile S16 *s16ptr;
- const volatile U16 *u16ptr;
- const volatile S8 *s8ptr ;
- const volatile U8 *u8ptr ;
-} UnionCVPtr;
-
-//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
-typedef struct
-{
- S64 *s64ptr;
- U64 *u64ptr;
- S32 *s32ptr;
- U32 *u32ptr;
- S16 *s16ptr;
- U16 *u16ptr;
- S8 *s8ptr ;
- U8 *u8ptr ;
-} StructPtr;
-
-//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
-typedef struct
-{
- volatile S64 *s64ptr;
- volatile U64 *u64ptr;
- volatile S32 *s32ptr;
- volatile U32 *u32ptr;
- volatile S16 *s16ptr;
- volatile U16 *u16ptr;
- volatile S8 *s8ptr ;
- volatile U8 *u8ptr ;
-} StructVPtr;
-
-//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
-typedef struct
-{
- const S64 *s64ptr;
- const U64 *u64ptr;
- const S32 *s32ptr;
- const U32 *u32ptr;
- const S16 *s16ptr;
- const U16 *u16ptr;
- const S8 *s8ptr ;
- const U8 *u8ptr ;
-} StructCPtr;
-
-//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
-typedef struct
-{
- const volatile S64 *s64ptr;
- const volatile U64 *u64ptr;
- const volatile S32 *s32ptr;
- const volatile U32 *u32ptr;
- const volatile S16 *s16ptr;
- const volatile U16 *u16ptr;
- const volatile S8 *s8ptr ;
- const volatile U8 *u8ptr ;
-} StructCVPtr;
-
-//! @}
-
-#endif // #ifndef __ASSEMBLY__
-
-/*! \name Usual Constants
- */
-//! @{
-#define DISABLE 0
-#define ENABLE 1
-#ifndef __cplusplus
-#if !defined(__bool_true_false_are_defined)
-#define false 0
-#define true 1
-#endif
-#endif
-#define PASS 0
-#define FAIL 1
-#define LOW 0
-#define HIGH 1
-//! @}
-
-
-#ifndef __ASSEMBLY__ // not for assembling.
-
-//! \name Optimization Control
-//@{
-
-/**
- * \def likely(exp)
- * \brief The expression \a exp is likely to be true
- */
-#ifndef likely
-# define likely(exp) (exp)
-#endif
-
-/**
- * \def unlikely(exp)
- * \brief The expression \a exp is unlikely to be true
- */
-#ifndef unlikely
-# define unlikely(exp) (exp)
-#endif
-
-/**
- * \def is_constant(exp)
- * \brief Determine if an expression evaluates to a constant value.
- *
- * \param exp Any expression
- *
- * \return true if \a exp is constant, false otherwise.
- */
-#if (defined __GNUC__) || (defined __CC_ARM)
-# define is_constant(exp) __builtin_constant_p(exp)
-#else
-# define is_constant(exp) (0)
-#endif
-
-//! @}
-
-/*! \name Bit-Field Handling
- */
-//! @{
-
-/*! \brief Reads the bits of a value specified by a given bit-mask.
- *
- * \param value Value to read bits from.
- * \param mask Bit-mask indicating bits to read.
- *
- * \return Read bits.
- */
-#define Rd_bits( value, mask) ((value) & (mask))
-
-/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.
- *
- * \param lvalue C lvalue to write bits to.
- * \param mask Bit-mask indicating bits to write.
- * \param bits Bits to write.
- *
- * \return Resulting value with written bits.
- */
-#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\
- ((bits ) & (mask)))
-
-/*! \brief Tests the bits of a value specified by a given bit-mask.
- *
- * \param value Value of which to test bits.
- * \param mask Bit-mask indicating bits to test.
- *
- * \return \c 1 if at least one of the tested bits is set, else \c 0.
- */
-#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0)
-
-/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.
- *
- * \param lvalue C lvalue of which to clear bits.
- * \param mask Bit-mask indicating bits to clear.
- *
- * \return Resulting value with cleared bits.
- */
-#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask))
-
-/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.
- *
- * \param lvalue C lvalue of which to set bits.
- * \param mask Bit-mask indicating bits to set.
- *
- * \return Resulting value with set bits.
- */
-#define Set_bits(lvalue, mask) ((lvalue) |= (mask))
-
-/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.
- *
- * \param lvalue C lvalue of which to toggle bits.
- * \param mask Bit-mask indicating bits to toggle.
- *
- * \return Resulting value with toggled bits.
- */
-#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask))
-
-/*! \brief Reads the bit-field of a value specified by a given bit-mask.
- *
- * \param value Value to read a bit-field from.
- * \param mask Bit-mask indicating the bit-field to read.
- *
- * \return Read bit-field.
- */
-#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask))
-
-/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
- *
- * \param lvalue C lvalue to write a bit-field to.
- * \param mask Bit-mask indicating the bit-field to write.
- * \param bitfield Bit-field to write.
- *
- * \return Resulting value with written bit-field.
- */
-#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))
-
-//! @}
-
-
-/*! \name Zero-Bit Counting
- *
- * Under GCC, __builtin_clz and __builtin_ctz behave like macros when
- * applied to constant expressions (values known at compile time), so they are
- * more optimized than the use of the corresponding assembly instructions and
- * they can be used as constant expressions e.g. to initialize objects having
- * static storage duration, and like the corresponding assembly instructions
- * when applied to non-constant expressions (values unknown at compile time), so
- * they are more optimized than an assembly periphrasis. Hence, clz and ctz
- * ensure a possible and optimized behavior for both constant and non-constant
- * expressions.
- */
-//! @{
-
-/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
- *
- * \param u Value of which to count the leading zero bits.
- *
- * \return The count of leading zero bits in \a u.
- */
-#if (defined __GNUC__) || (defined __CC_ARM)
-# define clz(u) ((u) ? __builtin_clz(u) : 32)
-#elif (defined __ICCARM__)
-# define clz(u) ((u) ? __CLZ(u) : 32)
-#else
-# define clz(u) (((u) == 0) ? 32 : \
- ((u) & (1ul << 31)) ? 0 : \
- ((u) & (1ul << 30)) ? 1 : \
- ((u) & (1ul << 29)) ? 2 : \
- ((u) & (1ul << 28)) ? 3 : \
- ((u) & (1ul << 27)) ? 4 : \
- ((u) & (1ul << 26)) ? 5 : \
- ((u) & (1ul << 25)) ? 6 : \
- ((u) & (1ul << 24)) ? 7 : \
- ((u) & (1ul << 23)) ? 8 : \
- ((u) & (1ul << 22)) ? 9 : \
- ((u) & (1ul << 21)) ? 10 : \
- ((u) & (1ul << 20)) ? 11 : \
- ((u) & (1ul << 19)) ? 12 : \
- ((u) & (1ul << 18)) ? 13 : \
- ((u) & (1ul << 17)) ? 14 : \
- ((u) & (1ul << 16)) ? 15 : \
- ((u) & (1ul << 15)) ? 16 : \
- ((u) & (1ul << 14)) ? 17 : \
- ((u) & (1ul << 13)) ? 18 : \
- ((u) & (1ul << 12)) ? 19 : \
- ((u) & (1ul << 11)) ? 20 : \
- ((u) & (1ul << 10)) ? 21 : \
- ((u) & (1ul << 9)) ? 22 : \
- ((u) & (1ul << 8)) ? 23 : \
- ((u) & (1ul << 7)) ? 24 : \
- ((u) & (1ul << 6)) ? 25 : \
- ((u) & (1ul << 5)) ? 26 : \
- ((u) & (1ul << 4)) ? 27 : \
- ((u) & (1ul << 3)) ? 28 : \
- ((u) & (1ul << 2)) ? 29 : \
- ((u) & (1ul << 1)) ? 30 : \
- 31)
-#endif
-
-/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
- *
- * \param u Value of which to count the trailing zero bits.
- *
- * \return The count of trailing zero bits in \a u.
- */
-#if (defined __GNUC__) || (defined __CC_ARM)
-# define ctz(u) ((u) ? __builtin_ctz(u) : 32)
-#else
-# define ctz(u) ((u) & (1ul << 0) ? 0 : \
- (u) & (1ul << 1) ? 1 : \
- (u) & (1ul << 2) ? 2 : \
- (u) & (1ul << 3) ? 3 : \
- (u) & (1ul << 4) ? 4 : \
- (u) & (1ul << 5) ? 5 : \
- (u) & (1ul << 6) ? 6 : \
- (u) & (1ul << 7) ? 7 : \
- (u) & (1ul << 8) ? 8 : \
- (u) & (1ul << 9) ? 9 : \
- (u) & (1ul << 10) ? 10 : \
- (u) & (1ul << 11) ? 11 : \
- (u) & (1ul << 12) ? 12 : \
- (u) & (1ul << 13) ? 13 : \
- (u) & (1ul << 14) ? 14 : \
- (u) & (1ul << 15) ? 15 : \
- (u) & (1ul << 16) ? 16 : \
- (u) & (1ul << 17) ? 17 : \
- (u) & (1ul << 18) ? 18 : \
- (u) & (1ul << 19) ? 19 : \
- (u) & (1ul << 20) ? 20 : \
- (u) & (1ul << 21) ? 21 : \
- (u) & (1ul << 22) ? 22 : \
- (u) & (1ul << 23) ? 23 : \
- (u) & (1ul << 24) ? 24 : \
- (u) & (1ul << 25) ? 25 : \
- (u) & (1ul << 26) ? 26 : \
- (u) & (1ul << 27) ? 27 : \
- (u) & (1ul << 28) ? 28 : \
- (u) & (1ul << 29) ? 29 : \
- (u) & (1ul << 30) ? 30 : \
- (u) & (1ul << 31) ? 31 : \
- 32)
-#endif
-
-//! @}
-
-
-/*! \name Bit Reversing
- */
-//! @{
-
-/*! \brief Reverses the bits of \a u8.
- *
- * \param u8 U8 of which to reverse the bits.
- *
- * \return Value resulting from \a u8 with reversed bits.
- */
-#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24))
-
-/*! \brief Reverses the bits of \a u16.
- *
- * \param u16 U16 of which to reverse the bits.
- *
- * \return Value resulting from \a u16 with reversed bits.
- */
-#define bit_reverse16(u16) ((U16)(bit_reverse32((U16)(u16)) >> 16))
-
-/*! \brief Reverses the bits of \a u32.
- *
- * \param u32 U32 of which to reverse the bits.
- *
- * \return Value resulting from \a u32 with reversed bits.
- */
-#define bit_reverse32(u32) __RBIT(u32)
-
-/*! \brief Reverses the bits of \a u64.
- *
- * \param u64 U64 of which to reverse the bits.
- *
- * \return Value resulting from \a u64 with reversed bits.
- */
-#define bit_reverse64(u64) ((U64)(((U64)bit_reverse32((U64)(u64) >> 32)) |\
- ((U64)bit_reverse32((U64)(u64)) << 32)))
-
-//! @}
-
-
-/*! \name Alignment
- */
-//! @{
-
-/*! \brief Tests alignment of the number \a val with the \a n boundary.
- *
- * \param val Input value.
- * \param n Boundary.
- *
- * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.
- */
-#define Test_align(val, n ) (!Tst_bits( val, (n) - 1 ) )
-
-/*! \brief Gets alignment of the number \a val with respect to the \a n boundary.
- *
- * \param val Input value.
- * \param n Boundary.
- *
- * \return Alignment of the number \a val with respect to the \a n boundary.
- */
-#define Get_align( val, n ) ( Rd_bits( val, (n) - 1 ) )
-
-/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.
- *
- * \param lval Input/output lvalue.
- * \param n Boundary.
- * \param alg Alignment.
- *
- * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.
- */
-#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) )
-
-/*! \brief Aligns the number \a val with the upper \a n boundary.
- *
- * \param val Input value.
- * \param n Boundary.
- *
- * \return Value resulting from the number \a val aligned with the upper \a n boundary.
- */
-#define Align_up( val, n ) (((val) + ((n) - 1)) & ~((n) - 1))
-
-/*! \brief Aligns the number \a val with the lower \a n boundary.
- *
- * \param val Input value.
- * \param n Boundary.
- *
- * \return Value resulting from the number \a val aligned with the lower \a n boundary.
- */
-#define Align_down(val, n ) ( (val) & ~((n) - 1))
-
-//! @}
-
-
-/*! \name Mathematics
- *
- * The same considerations as for clz and ctz apply here but GCC does not
- * provide built-in functions to access the assembly instructions abs, min and
- * max and it does not produce them by itself in most cases, so two sets of
- * macros are defined here:
- * - Abs, Min and Max to apply to constant expressions (values known at
- * compile time);
- * - abs, min and max to apply to non-constant expressions (values unknown at
- * compile time), abs is found in stdlib.h.
- */
-//! @{
-
-/*! \brief Takes the absolute value of \a a.
- *
- * \param a Input value.
- *
- * \return Absolute value of \a a.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Abs(a) (((a) < 0 ) ? -(a) : (a))
-
-/*! \brief Takes the minimal value of \a a and \a b.
- *
- * \param a Input value.
- * \param b Input value.
- *
- * \return Minimal value of \a a and \a b.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Min(a, b) (((a) < (b)) ? (a) : (b))
-
-/*! \brief Takes the maximal value of \a a and \a b.
- *
- * \param a Input value.
- * \param b Input value.
- *
- * \return Maximal value of \a a and \a b.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Max(a, b) (((a) > (b)) ? (a) : (b))
-
-// abs() is already defined by stdlib.h
-
-/*! \brief Takes the minimal value of \a a and \a b.
- *
- * \param a Input value.
- * \param b Input value.
- *
- * \return Minimal value of \a a and \a b.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#define min(a, b) Min(a, b)
-
-/*! \brief Takes the maximal value of \a a and \a b.
- *
- * \param a Input value.
- * \param b Input value.
- *
- * \return Maximal value of \a a and \a b.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#define max(a, b) Max(a, b)
-
-//! @}
-
-
-/*! \brief Calls the routine at address \a addr.
- *
- * It generates a long call opcode.
- *
- * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if
- * it is invoked from the CPU supervisor mode.
- *
- * \param addr Address of the routine to call.
- *
- * \note It may be used as a long jump opcode in some special cases.
- */
-#define Long_call(addr) ((*(void (*)(void))(addr))())
-
-
-/*! \name MCU Endianism Handling
- * ARM is MCU little endianism.
- */
-//! @{
-#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.
-#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.
-
-#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.
-#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.
-#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.
-#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.
-#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.
-#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.
-#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.
-#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.
-#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.
-#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.
-
-#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.
-#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.
-#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.
-#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.
-#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.
-#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.
-#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.
-#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.
-#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.
-#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.
-#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.
-#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.
-#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.
-#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.
-#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.
-#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.
-#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.
-#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.
-#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.
-#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.
-#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.
-#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.
-#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.
-#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.
-#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.
-#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.
-
-#define BE16(x) swap16(x)
-#define LE16(x) (x)
-
-#define le16_to_cpu(x) (x)
-#define cpu_to_le16(x) (x)
-#define LE16_TO_CPU(x) (x)
-#define CPU_TO_LE16(x) (x)
-
-#define be16_to_cpu(x) swap16(x)
-#define cpu_to_be16(x) swap16(x)
-#define BE16_TO_CPU(x) swap16(x)
-#define CPU_TO_BE16(x) swap16(x)
-
-#define le32_to_cpu(x) (x)
-#define cpu_to_le32(x) (x)
-#define LE32_TO_CPU(x) (x)
-#define CPU_TO_LE32(x) (x)
-
-#define be32_to_cpu(x) swap32(x)
-#define cpu_to_be32(x) swap32(x)
-#define BE32_TO_CPU(x) swap32(x)
-#define CPU_TO_BE32(x) swap32(x)
-//! @}
-
-
-/*! \name Endianism Conversion
- *
- * The same considerations as for clz and ctz apply here but GCC's
- * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when
- * applied to constant expressions, so two sets of macros are defined here:
- * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known
- * at compile time);
- * - swap16, swap32 and swap64 to apply to non-constant expressions (values
- * unknown at compile time).
- */
-//! @{
-
-/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
- *
- * \param u16 U16 of which to toggle the endianism.
- *
- * \return Value resulting from \a u16 with toggled endianism.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\
- ((U16)(u16) << 8)))
-
-/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
- *
- * \param u32 U32 of which to toggle the endianism.
- *
- * \return Value resulting from \a u32 with toggled endianism.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\
- ((U32)Swap16((U32)(u32)) << 16)))
-
-/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
- *
- * \param u64 U64 of which to toggle the endianism.
- *
- * \return Value resulting from \a u64 with toggled endianism.
- *
- * \note More optimized if only used with values known at compile time.
- */
-#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\
- ((U64)Swap32((U64)(u64)) << 32)))
-
-/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
- *
- * \param u16 U16 of which to toggle the endianism.
- *
- * \return Value resulting from \a u16 with toggled endianism.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#define swap16(u16) Swap16(u16)
-
-/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
- *
- * \param u32 U32 of which to toggle the endianism.
- *
- * \return Value resulting from \a u32 with toggled endianism.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#if (defined __GNUC__)
-# define swap32(u32) ((U32)__builtin_bswap32((U32)(u32)))
-#else
-# define swap32(u32) Swap32(u32)
-#endif
-
-/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
- *
- * \param u64 U64 of which to toggle the endianism.
- *
- * \return Value resulting from \a u64 with toggled endianism.
- *
- * \note More optimized if only used with values unknown at compile time.
- */
-#if (defined __GNUC__)
-# define swap64(u64) ((U64)__builtin_bswap64((U64)(u64)))
-#else
-# define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\
- ((U64)swap32((U64)(u64)) << 32)))
-#endif
-
-//! @}
-
-
-/*! \name Target Abstraction
- */
-//! @{
-
-#define _GLOBEXT_ extern //!< extern storage-class specifier.
-#define _CONST_TYPE_ const //!< const type qualifier.
-#define _MEM_TYPE_SLOW_ //!< Slow memory type.
-#define _MEM_TYPE_MEDFAST_ //!< Fairly fast memory type.
-#define _MEM_TYPE_FAST_ //!< Fast memory type.
-
-typedef U8 Byte; //!< 8-bit unsigned integer.
-
-#define memcmp_ram2ram memcmp //!< Target-specific memcmp of RAM to RAM.
-#define memcmp_code2ram memcmp //!< Target-specific memcmp of RAM to NVRAM.
-#define memcpy_ram2ram memcpy //!< Target-specific memcpy from RAM to RAM.
-#define memcpy_code2ram memcpy //!< Target-specific memcpy from NVRAM to RAM.
-
-#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32.
-#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32.
-#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32.
-#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32.
-#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32.
-#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32.
-#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32.
-#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32.
-
-//! @}
-
-/**
- * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using
- * integer arithmetic.
- *
- * \param a An integer
- * \param b Another integer
- *
- * \return (\a a / \a b) rounded up to the nearest integer.
- */
-#define div_ceil(a, b) (((a) + (b) - 1) / (b))
-
-#endif // #ifndef __ASSEMBLY__
-
-
-#if defined(__ICCARM__)
-#define SHORTENUM __packed
-#elif defined(__GNUC__)
-#define SHORTENUM __attribute__((packed))
-#endif
-
-/* No operation */
-#if defined(__ICCARM__)
-#define nop() __no_operation()
-#elif defined(__GNUC__)
-#define nop() (__NOP())
-#endif
-
-#define FLASH_DECLARE(x) const x
-#define FLASH_EXTERN(x) extern const x
-#define PGM_READ_BYTE(x) *(x)
-#define PGM_READ_WORD(x) *(x)
-#define PGM_READ_DWORD(x) *(x)
-#define MEMCPY_ENDIAN memcpy
-#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len))
-
-/*Defines the Flash Storage for the request and response of MAC*/
-#define CMD_ID_OCTET (0)
-
-/* Converting of values from CPU endian to little endian. */
-#define CPU_ENDIAN_TO_LE16(x) (x)
-#define CPU_ENDIAN_TO_LE32(x) (x)
-#define CPU_ENDIAN_TO_LE64(x) (x)
-
-/* Converting of values from little endian to CPU endian. */
-#define LE16_TO_CPU_ENDIAN(x) (x)
-#define LE32_TO_CPU_ENDIAN(x) (x)
-#define LE64_TO_CPU_ENDIAN(x) (x)
-
-/* Converting of constants from little endian to CPU endian. */
-#define CLE16_TO_CPU_ENDIAN(x) (x)
-#define CLE32_TO_CPU_ENDIAN(x) (x)
-#define CLE64_TO_CPU_ENDIAN(x) (x)
-
-/* Converting of constants from CPU endian to little endian. */
-#define CCPU_ENDIAN_TO_LE16(x) (x)
-#define CCPU_ENDIAN_TO_LE32(x) (x)
-#define CCPU_ENDIAN_TO_LE64(x) (x)
-
-#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src))
-#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src))
-
-/**
- * @brief Converts a 64-Bit value into a 8 Byte array
- *
- * @param[in] value 64-Bit value
- * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value
- * @ingroup apiPalApi
- */
-static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data)
-{
- uint8_t val_index = 0;
-
- while (val_index < 8)
- {
- data[val_index++] = value & 0xFF;
- value = value >> 8;
- }
-}
-
-/**
- * @brief Converts a 16-Bit value into a 2 Byte array
- *
- * @param[in] value 16-Bit value
- * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value
- * @ingroup apiPalApi
- */
-static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data)
-{
- data[0] = value & 0xFF;
- data[1] = (value >> 8) & 0xFF;
-}
-
-/* Converts a 16-Bit value into a 2 Byte array */
-static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data)
-{
- data[0] = value & 0xFF;
- data[1] = (value >> 8) & 0xFF;
-}
-
-/* Converts a 16-Bit value into a 2 Byte array */
-static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data)
-{
- data[0] = value & 0xFF;
- data[1] = (value >> 8) & 0xFF;
-}
-
-/*
- * @brief Converts a 2 Byte array into a 16-Bit value
- *
- * @param data Specifies the pointer to the 2 Byte array
- *
- * @return 16-Bit value
- * @ingroup apiPalApi
- */
-static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data)
-{
- return (data[0] | ((uint16_t)data[1] << 8));
-}
-
-/* Converts a 8 Byte array into a 32-Bit value */
-static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data)
-{
- union
- {
- uint32_t u32;
- uint8_t u8[8];
- }long_addr;
- uint8_t index;
- for (index = 0; index < 4; index++)
- {
- long_addr.u8[index] = *data++;
- }
- return long_addr.u32;
-}
-
-/**
- * @brief Converts a 8 Byte array into a 64-Bit value
- *
- * @param data Specifies the pointer to the 8 Byte array
- *
- * @return 64-Bit value
- * @ingroup apiPalApi
- */
-static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data)
-{
- union
- {
- uint64_t u64;
- uint8_t u8[8];
- } long_addr;
-
- uint8_t val_index;
-
- for (val_index = 0; val_index < 8; val_index++)
- {
- long_addr.u8[val_index] = *data++;
- }
-
- return long_addr.u64;
-}
-/**
- * \}
- */
-
-#endif /* UTILS_COMPILER_H */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/fpu/fpu.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/fpu/fpu.h
deleted file mode 100644
index 763089d..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/fpu/fpu.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/**
- * \file
- *
- * \brief FPU support for SAM.
- *
- * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _FPU_H_INCLUDED_
-#define _FPU_H_INCLUDED_
-
-#include <compiler.h>
-
-/** Address for ARM CPACR */
-#define ADDR_CPACR 0xE000ED88
-
-/** CPACR Register */
-#define REG_CPACR (*((volatile uint32_t *)ADDR_CPACR))
-
-/**
- * \brief Enable FPU
- */
-__always_inline static void fpu_enable(void)
-{
- irqflags_t flags;
- flags = cpu_irq_save();
- REG_CPACR |= (0xFu << 20);
- __DSB();
- __ISB();
- cpu_irq_restore(flags);
-}
-
-/**
- * \brief Disable FPU
- */
-__always_inline static void fpu_disable(void)
-{
- irqflags_t flags;
- flags = cpu_irq_save();
- REG_CPACR &= ~(0xFu << 20);
- __DSB();
- __ISB();
- cpu_irq_restore(flags);
-}
-
-/**
- * \brief Check if FPU is enabled
- *
- * \return Return ture if FPU is enabled, otherwise return false.
- */
-__always_inline static bool fpu_is_enabled(void)
-{
- return (REG_CPACR & (0xFu << 20));
-}
-
-#endif /* _FPU_H_INCLUDED_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/header_files/io.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/header_files/io.h
deleted file mode 100644
index a79c646..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/header_files/io.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/**
- * \file
- *
- * \brief Arch file for SAM.
- *
- * This file defines common SAM series.
- *
- * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _SAM_IO_
-#define _SAM_IO_
-
-/* SAM3 family */
-
-/* SAM3S series */
-#if (SAM3S)
-# if (SAM3S8 || SAM3SD8)
-# include "sam3s8.h"
-# else
-# include "sam3s.h"
-# endif
-#endif
-
-/* SAM3U series */
-#if (SAM3U)
-# include "sam3u.h"
-#endif
-
-/* SAM3N series */
-#if (SAM3N)
-# include "sam3n.h"
-#endif
-
-/* SAM3XA series */
-#if (SAM3XA)
-# include "sam3xa.h"
-#endif
-
-/* SAM4S series */
-#if (SAM4S)
-# include "sam4s.h"
-#endif
-
-/* SAM4L series */
-#if (SAM4L)
-# include "sam4l.h"
-#endif
-
-/* SAM4E series */
-#if (SAM4E)
-# include "sam4e.h"
-#endif
-
-/* SAM4N series */
-#if (SAM4N)
-# include "sam4n.h"
-#endif
-
-/* SAM4C series */
-#if (SAM4C)
-# include "sam4c.h"
-#endif
-
-/* SAM4CM series */
-#if (SAM4CM)
-# if (SAM4CMP32 || SAM4CMS32)
-# include "sam4cm32.h"
-# else
-# include "sam4cm.h"
-# endif
-#endif
-
-/* SAM4CP series */
-#if (SAM4CP)
-# include "sam4cp.h"
-#endif
-
-/* SAMG51 series */
-#if (SAMG51)
-# include "samg51.h"
-#endif
-
-/* SAMG53 series */
-#if (SAMG53)
-# include "samg53.h"
-#endif
-
-/* SAMG54 series */
-#if (SAMG54)
-# include "samg54.h"
-#endif
-
-/* SAMG55 series */
-#if (SAMG55)
-# include "samg55.h"
-#endif
-
-/* SAMV71 series */
-#if (SAMV71)
-# include "samv71.h"
-#endif
-
-/* SAMV70 series */
-#if (SAMV70)
-# include "samv70.h"
-#endif
-
-/* SAME70 series */
-#if (SAME70)
-# include "same70.h"
-#endif
-
-/* SAMS70 series */
-#if (SAMS70)
-# include "sams70.h"
-#endif
-
-#endif /* _SAM_IO_ */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/linker_scripts/sams70/sams70n20/gcc/flash.ld b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/linker_scripts/sams70/sams70n20/gcc/flash.ld
deleted file mode 100644
index cb4537d..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/linker_scripts/sams70/sams70n20/gcc/flash.ld
+++ /dev/null
@@ -1,174 +0,0 @@
-/**
- * \file
- *
- * Copyright (c) 2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-
-/*------------------------------------------------------------------------------
- * Linker script for running in internal FLASH on the ATSAMS70N20
- *----------------------------------------------------------------------------*/
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-SEARCH_DIR(.)
-
-/* Memory Spaces Definitions */
-MEMORY
-{
- rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000
- ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000
-}
-
-/* The stack size used by the application. NOTE: you need to adjust according to your application. */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000;
-__ram_end__ = ORIGIN(ram) + LENGTH(ram) - 4;
-
-/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
-HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200;
-
-/* Section Definitions */
-SECTIONS
-{
- .text :
- {
- . = ALIGN(4);
- _sfixed = .;
- KEEP(*(.vectors .vectors.*))
- *(.text .text.* .gnu.linkonce.t.*)
- *(.glue_7t) *(.glue_7)
- *(.rodata .rodata* .gnu.linkonce.r.*)
- *(.ARM.extab* .gnu.linkonce.armextab.*)
-
- /* Support C constructors, and C destructors in both user code
- and the C library. This also provides support for C++ code. */
- . = ALIGN(4);
- KEEP(*(.init))
- . = ALIGN(4);
- __preinit_array_start = .;
- KEEP (*(.preinit_array))
- __preinit_array_end = .;
-
- . = ALIGN(4);
- __init_array_start = .;
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array))
- __init_array_end = .;
-
- . = ALIGN(0x4);
- KEEP (*crtbegin.o(.ctors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*crtend.o(.ctors))
-
- . = ALIGN(4);
- KEEP(*(.fini))
-
- . = ALIGN(4);
- __fini_array_start = .;
- KEEP (*(.fini_array))
- KEEP (*(SORT(.fini_array.*)))
- __fini_array_end = .;
-
- KEEP (*crtbegin.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*crtend.o(.dtors))
-
- . = ALIGN(4);
- _efixed = .; /* End of text section */
- } > rom
-
- /* .ARM.exidx is sorted, so has to go in its own output section. */
- PROVIDE_HIDDEN (__exidx_start = .);
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > rom
- PROVIDE_HIDDEN (__exidx_end = .);
-
- . = ALIGN(4);
- _etext = .;
-
- .relocate : AT (_etext)
- {
- . = ALIGN(4);
- _srelocate = .;
- *(.ramfunc .ramfunc.*);
- *(.data .data.*);
- . = ALIGN(4);
- _erelocate = .;
- } > ram
-
- /* .bss section which is used for uninitialized data */
- .bss (NOLOAD) :
- {
- . = ALIGN(4);
- _sbss = . ;
- _szero = .;
- *(.bss .bss.*)
- *(COMMON)
- . = ALIGN(4);
- _ebss = . ;
- _ezero = .;
- } > ram
-
- /* stack section */
- .stack (NOLOAD):
- {
- . = ALIGN(8);
- _sstack = .;
- . = . + STACK_SIZE;
- . = ALIGN(8);
- _estack = .;
- } > ram
-
- /* heap section */
- .heap (NOLOAD):
- {
- . = ALIGN(8);
- _sheap = .;
- . = . + HEAP_SIZE;
- . = ALIGN(8);
- _eheap = .;
- } > ram
-
- . = ALIGN(4);
- _end = . ;
- _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ;
-}
-
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/make/Makefile.sam.in b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/make/Makefile.sam.in
deleted file mode 100644
index 23c6697..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/make/Makefile.sam.in
+++ /dev/null
@@ -1,496 +0,0 @@
-# List of available make goals:
-#
-# all Default target, builds the project
-# clean Clean up the project
-# rebuild Rebuild the project
-# debug_flash Builds the project and debug in flash
-# debug_sram Builds the project and debug in sram
-#
-# doc Build the documentation
-# cleandoc Clean up the documentation
-# rebuilddoc Rebuild the documentation
-#
-# \file
-#
-# Copyright (c) 2011 - 2013 Atmel Corporation. All rights reserved.
-#
-# \asf_license_start
-#
-# \page License
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#
-# 1. Redistributions of source code must retain the above copyright notice,
-# this list of conditions and the following disclaimer.
-#
-# 2. Redistributions in binary form must reproduce the above copyright notice,
-# this list of conditions and the following disclaimer in the documentation
-# and/or other materials provided with the distribution.
-#
-# 3. The name of Atmel may not be used to endorse or promote products derived
-# from this software without specific prior written permission.
-#
-# 4. This software may only be redistributed and used in connection with an
-# Atmel microcontroller product.
-#
-# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
-# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
-# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-# \asf_license_stop
-#
-
-# Include the config.mk file from the current working path, e.g., where the
-# user called make.
-include config.mk
-
-# Tool to use to generate documentation from the source code
-DOCGEN ?= doxygen
-
-# Look for source files relative to the top-level source directory
-VPATH := $(PRJ_PATH)
-
-# Output target file
-project_type := $(PROJECT_TYPE)
-
-# Output target file
-ifeq ($(project_type),flash)
-target := $(TARGET_FLASH)
-linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH)
-debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)
-else
-target := $(TARGET_SRAM)
-linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM)
-debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)
-endif
-
-# Output project name (target name minus suffix)
-project := $(basename $(target))
-
-# Output target file (typically ELF or static library)
-ifeq ($(suffix $(target)),.a)
-target_type := lib
-else
-ifeq ($(suffix $(target)),.elf)
-target_type := elf
-else
-$(error "Target type $(target_type) is not supported")
-endif
-endif
-
-# Allow override of operating system detection. The user can add OS=Linux or
-# OS=Windows on the command line to explicit set the host OS.
-#
-# This allows to work around broken uname utility on certain systems.
-ifdef OS
- ifeq ($(strip $(OS)), Linux)
- os_type := Linux
- endif
- ifeq ($(strip $(OS)), Windows)
- os_type := windows32_64
- endif
-endif
-
-os_type ?= $(strip $(shell uname))
-
-ifeq ($(os_type),windows32)
-os := Windows
-else
-ifeq ($(os_type),windows64)
-os := Windows
-else
-ifeq ($(os_type),windows32_64)
-os ?= Windows
-else
-ifeq ($(os_type),)
-os := Windows
-else
-# Default to Linux style operating system. Both Cygwin and mingw are fully
-# compatible (for this Makefile) with Linux.
-os := Linux
-endif
-endif
-endif
-endif
-
-# Output documentation directory and configuration file.
-docdir := ../doxygen/html
-doccfg := ../doxygen/doxyfile.doxygen
-
-CROSS ?= arm-none-eabi-
-AR := $(CROSS)ar
-AS := $(CROSS)as
-CC := $(CROSS)gcc
-CPP := $(CROSS)gcc -E
-CXX := $(CROSS)g++
-LD := $(CROSS)g++
-NM := $(CROSS)nm
-OBJCOPY := $(CROSS)objcopy
-OBJDUMP := $(CROSS)objdump
-SIZE := $(CROSS)size
-GDB := $(CROSS)gdb
-
-RM := rm
-ifeq ($(os),Windows)
-RMDIR := rmdir /S /Q
-else
-RMDIR := rmdir -p --ignore-fail-on-non-empty
-endif
-
-# On Windows, we need to override the shell to force the use of cmd.exe
-ifeq ($(os),Windows)
-SHELL := cmd
-endif
-
-# Strings for beautifying output
-MSG_CLEAN_FILES = "RM *.o *.d"
-MSG_CLEAN_DIRS = "RMDIR $(strip $(clean-dirs))"
-MSG_CLEAN_DOC = "RMDIR $(docdir)"
-MSG_MKDIR = "MKDIR $(dir $@)"
-
-MSG_INFO = "INFO "
-MSG_PREBUILD = "PREBUILD $(PREBUILD_CMD)"
-MSG_POSTBUILD = "POSTBUILD $(POSTBUILD_CMD)"
-
-MSG_ARCHIVING = "AR $@"
-MSG_ASSEMBLING = "AS $@"
-MSG_BINARY_IMAGE = "OBJCOPY $@"
-MSG_COMPILING = "CC $@"
-MSG_COMPILING_CXX = "CXX $@"
-MSG_EXTENDED_LISTING = "OBJDUMP $@"
-MSG_IHEX_IMAGE = "OBJCOPY $@"
-MSG_LINKING = "LN $@"
-MSG_PREPROCESSING = "CPP $@"
-MSG_SIZE = "SIZE $@"
-MSG_SYMBOL_TABLE = "NM $@"
-
-MSG_GENERATING_DOC = "DOXYGEN $(docdir)"
-
-# Don't use make's built-in rules and variables
-MAKEFLAGS += -rR
-
-# Don't print 'Entering directory ...'
-MAKEFLAGS += --no-print-directory
-
-# Function for reversing the order of a list
-reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1))
-
-# Hide command output by default, but allow the user to override this
-# by adding V=1 on the command line.
-#
-# This is inspired by the Kbuild system used by the Linux kernel.
-ifdef V
- ifeq ("$(origin V)", "command line")
- VERBOSE = $(V)
- endif
-endif
-ifndef VERBOSE
- VERBOSE = 0
-endif
-
-ifeq ($(VERBOSE), 1)
- Q =
-else
- Q = @
-endif
-
-arflags-gnu-y := $(ARFLAGS)
-asflags-gnu-y := $(ASFLAGS)
-cflags-gnu-y := $(CFLAGS)
-cxxflags-gnu-y := $(CXXFLAGS)
-cppflags-gnu-y := $(CPPFLAGS)
-cpuflags-gnu-y :=
-dbgflags-gnu-y := $(DBGFLAGS)
-libflags-gnu-y := $(foreach LIB,$(LIBS),-l$(LIB))
-ldflags-gnu-y := $(LDFLAGS)
-flashflags-gnu-y :=
-clean-files :=
-clean-dirs :=
-
-clean-files += $(wildcard $(target) $(project).map)
-clean-files += $(wildcard $(project).hex $(project).bin)
-clean-files += $(wildcard $(project).lss $(project).sym)
-clean-files += $(wildcard $(build))
-
-# Use pipes instead of temporary files for communication between processes
-cflags-gnu-y += -pipe
-asflags-gnu-y += -pipe
-ldflags-gnu-y += -pipe
-
-# Archiver flags.
-arflags-gnu-y += rcs
-
-# Always enable warnings. And be very careful about implicit
-# declarations.
-cflags-gnu-y += -Wall -Wstrict-prototypes -Wmissing-prototypes
-cflags-gnu-y += -Werror-implicit-function-declaration
-cxxflags-gnu-y += -Wall
-# IAR doesn't allow arithmetic on void pointers, so warn about that.
-cflags-gnu-y += -Wpointer-arith
-cxxflags-gnu-y += -Wpointer-arith
-
-# Preprocessor flags.
-cppflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC))
-asflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)')
-
-# CPU specific flags.
-cpuflags-gnu-y += -mcpu=$(ARCH) -mthumb -D=__$(PART)__
-
-# Dependency file flags.
-depflags = -MD -MP -MQ $@
-
-# Debug specific flags.
-ifdef BUILD_DEBUG_LEVEL
-dbgflags-gnu-y += -g$(BUILD_DEBUG_LEVEL)
-else
-dbgflags-gnu-y += -g3
-endif
-
-# Optimization specific flags.
-ifdef BUILD_OPTIMIZATION
-optflags-gnu-y = -O$(BUILD_OPTIMIZATION)
-else
-optflags-gnu-y = $(OPTIMIZATION)
-endif
-
-# Always preprocess assembler files.
-asflags-gnu-y += -x assembler-with-cpp
-# Compile C files using the GNU99 standard.
-cflags-gnu-y += -std=gnu99
-# Compile C++ files using the GNU++98 standard.
-cxxflags-gnu-y += -std=gnu++98
-
-# Don't use strict aliasing (very common in embedded applications).
-cflags-gnu-y += -fno-strict-aliasing
-cxxflags-gnu-y += -fno-strict-aliasing
-
-# Separate each function and data into its own separate section to allow
-# garbage collection of unused sections.
-cflags-gnu-y += -ffunction-sections -fdata-sections
-cxxflags-gnu-y += -ffunction-sections -fdata-sections
-
-# Various cflags.
-cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
-cflags-gnu-y += -Wmain -Wparentheses
-cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
-cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
-cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings
-cflags-gnu-y += -Wsign-compare -Waggregate-return
-cflags-gnu-y += -Wmissing-declarations
-cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
-cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long
-cflags-gnu-y += -Wunreachable-code
-cflags-gnu-y += -Wcast-align
-cflags-gnu-y += --param max-inline-insns-single=500
-
-# Garbage collect unreferred sections when linking.
-ldflags-gnu-y += -Wl,--gc-sections
-
-# Use the linker script if provided by the project.
-ifneq ($(strip $(linker_script)),)
-ldflags-gnu-y += -Wl,-T $(linker_script)
-endif
-
-# Output a link map file and a cross reference table
-ldflags-gnu-y += -Wl,-Map=$(project).map,--cref
-
-# Add library search paths relative to the top level directory.
-ldflags-gnu-y += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH))
-
-a_flags = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__
-c_flags = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y)
-cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y)
-l_flags = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y)
-ar_flags = $(arflags-gnu-y)
-
-# Source files list and part informations must already be included before
-# running this makefile
-
-# If a custom build directory is specified, use it -- force trailing / in directory name.
-ifdef BUILD_DIR
- build-dir := $(dir $(BUILD_DIR))$(if $(notdir $(BUILD_DIR)),$(notdir $(BUILD_DIR))/)
-else
- build-dir =
-endif
-
-# Create object files list from source files list.
-obj-y := $(addprefix $(build-dir), $(addsuffix .o,$(basename $(CSRCS) $(ASSRCS))))
-# Create dependency files list from source files list.
-dep-files := $(wildcard $(foreach f,$(obj-y),$(basename $(f)).d))
-
-clean-files += $(wildcard $(obj-y))
-clean-files += $(dep-files)
-
-clean-dirs += $(call reverse,$(sort $(wildcard $(dir $(obj-y)))))
-
-# Default target.
-.PHONY: all
-ifeq ($(project_type),all)
-all:
- $(MAKE) all PROJECT_TYPE=flash
- $(MAKE) all PROJECT_TYPE=sram
-else
-ifeq ($(target_type),lib)
-all: $(target) $(project).lss $(project).sym
-else
-ifeq ($(target_type),elf)
-all: prebuild $(target) $(project).lss $(project).sym $(project).hex $(project).bin postbuild
-endif
-endif
-endif
-
-prebuild:
-ifneq ($(strip $(PREBUILD_CMD)),)
- @echo $(MSG_PREBUILD)
- $(Q)$(PREBUILD_CMD)
-endif
-
-postbuild:
-ifneq ($(strip $(POSTBUILD_CMD)),)
- @echo $(MSG_POSTBUILD)
- $(Q)$(POSTBUILD_CMD)
-endif
-
-# Clean up the project.
-.PHONY: clean
-clean:
- @$(if $(strip $(clean-files)),echo $(MSG_CLEAN_FILES))
- $(if $(strip $(clean-files)),$(Q)$(RM) $(clean-files),)
- @$(if $(strip $(clean-dirs)),echo $(MSG_CLEAN_DIRS))
-# Remove created directories, and make sure we only remove existing
-# directories, since recursive rmdir might help us a bit on the way.
-ifeq ($(os),Windows)
- $(Q)$(if $(strip $(clean-dirs)), \
- $(RMDIR) $(strip $(subst /,\,$(clean-dirs))))
-else
- $(Q)$(if $(strip $(clean-dirs)), \
- for directory in $(strip $(clean-dirs)); do \
- if [ -d "$$directory" ]; then \
- $(RMDIR) $$directory; \
- fi \
- done \
- )
-endif
-
-# Rebuild the project.
-.PHONY: rebuild
-rebuild: clean all
-
-# Debug the project in flash.
-.PHONY: debug_flash
-debug_flash: all
- $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH)" -ex "reset" -readnow -se $(TARGET_FLASH)
-
-# Debug the project in sram.
-.PHONY: debug_sram
-debug_sram: all
- $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM)
-
-.PHONY: objfiles
-objfiles: $(obj-y)
-
-# Create object files from C source files.
-$(build-dir)%.o: %.c $(MAKEFILE_PATH) config.mk
- $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
-ifeq ($(os),Windows)
- $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
-else
- $(Q)test -d $(dir $@) || mkdir -p $(dir $@)
-endif
- @echo $(MSG_COMPILING)
- $(Q)$(CC) $(c_flags) -c $< -o $@
-
-# Create object files from C++ source files.
-$(build-dir)%.o: %.cpp $(MAKEFILE_PATH) config.mk
- $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
-ifeq ($(os),Windows)
- $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
-else
- $(Q)test -d $(dir $@) || mkdir -p $(dir $@)
-endif
- @echo $(MSG_COMPILING_CXX)
- $(Q)$(CXX) $(cxx_flags) -c $< -o $@
-
-# Preprocess and assemble: create object files from assembler source files.
-$(build-dir)%.o: %.S $(MAKEFILE_PATH) config.mk
- $(Q)test -d $(dir $@) || echo $(MSG_MKDIR)
-ifeq ($(os),Windows)
- $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@))
-else
- $(Q)test -d $(dir $@) || mkdir -p $(dir $@)
-endif
- @echo $(MSG_ASSEMBLING)
- $(Q)$(CC) $(a_flags) -c $< -o $@
-
-# Include all dependency files to add depedency to all header files in use.
-include $(dep-files)
-
-ifeq ($(target_type),lib)
-# Archive object files into an archive
-$(target): $(MAKEFILE_PATH) config.mk $(obj-y)
- @echo $(MSG_ARCHIVING)
- $(Q)$(AR) $(ar_flags) $@ $(obj-y)
- @echo $(MSG_SIZE)
- $(Q)$(SIZE) -Bxt $@
-else
-ifeq ($(target_type),elf)
-# Link the object files into an ELF file. Also make sure the target is rebuilt
-# if the common Makefile.sam.in or project config.mk is changed.
-$(target): $(linker_script) $(MAKEFILE_PATH) config.mk $(obj-y)
- @echo $(MSG_LINKING)
- $(Q)$(LD) $(l_flags) $(obj-y) $(libflags-gnu-y) -o $@
- @echo $(MSG_SIZE)
- $(Q)$(SIZE) -Ax $@
- $(Q)$(SIZE) -Bx $@
-endif
-endif
-
-# Create extended function listing from target output file.
-%.lss: $(target)
- @echo $(MSG_EXTENDED_LISTING)
- $(Q)$(OBJDUMP) -h -S $< > $@
-
-# Create symbol table from target output file.
-%.sym: $(target)
- @echo $(MSG_SYMBOL_TABLE)
- $(Q)$(NM) -n $< > $@
-
-# Create Intel HEX image from ELF output file.
-%.hex: $(target)
- @echo $(MSG_IHEX_IMAGE)
- $(Q)$(OBJCOPY) -O ihex $(flashflags-gnu-y) $< $@
-
-# Create binary image from ELF output file.
-%.bin: $(target)
- @echo $(MSG_BINARY_IMAGE)
- $(Q)$(OBJCOPY) -O binary $< $@
-
-# Provide information about the detected host operating system.
-.SECONDARY: info-os
-info-os:
- @echo $(MSG_INFO)$(os) build host detected
-
-# Build Doxygen generated documentation.
-.PHONY: doc
-doc:
- @echo $(MSG_GENERATING_DOC)
- $(Q)cd $(dir $(doccfg)) && $(DOCGEN) $(notdir $(doccfg))
-
-# Clean Doxygen generated documentation.
-.PHONY: cleandoc
-cleandoc:
- @$(if $(wildcard $(docdir)),echo $(MSG_CLEAN_DOC))
- $(Q)$(if $(wildcard $(docdir)),$(RM) --recursive $(docdir))
-
-# Rebuild the Doxygen generated documentation.
-.PHONY: rebuilddoc
-rebuilddoc: cleandoc doc
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/preprocessor/mrepeat.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/preprocessor/mrepeat.h
deleted file mode 100644
index 5a2017b..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/preprocessor/mrepeat.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/**
- * \file
- *
- * \brief Preprocessor macro repeating utils.
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _MREPEAT_H_
-#define _MREPEAT_H_
-
-/**
- * \defgroup group_sam_utils_mrepeat Preprocessor - Macro Repeat
- *
- * \ingroup group_sam_utils
- *
- * \{
- */
-
-#include "preprocessor.h"
-
-
-//! Maximal number of repetitions supported by MREPEAT.
-#define MREPEAT_LIMIT 256
-
-/*! \brief Macro repeat.
- *
- * This macro represents a horizontal repetition construct.
- *
- * \param count The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT.
- * \param macro A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with
- * the current repetition number and the auxiliary data argument.
- * \param data Auxiliary data passed to macro.
- *
- * \return <tt>macro(0, data) macro(1, data) ... macro(count - 1, data)</tt>
- */
-#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count)(macro, data)
-
-#define MREPEAT0( macro, data)
-#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data)
-#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data)
-#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data)
-#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data)
-#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data)
-#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data)
-#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data)
-#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data)
-#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data)
-#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data)
-#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data)
-#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data)
-#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data)
-#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data)
-#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data)
-#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data)
-#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data)
-#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data)
-#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data)
-#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data)
-#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data)
-#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data)
-#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data)
-#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data)
-#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data)
-#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data)
-#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data)
-#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data)
-#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data)
-#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data)
-#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data)
-#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data)
-#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data)
-#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data)
-#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data)
-#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data)
-#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data)
-#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data)
-#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data)
-#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data)
-#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data)
-#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data)
-#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data)
-#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data)
-#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data)
-#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data)
-#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data)
-#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data)
-#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data)
-#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data)
-#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data)
-#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data)
-#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data)
-#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data)
-#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data)
-#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data)
-#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data)
-#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data)
-#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data)
-#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data)
-#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data)
-#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data)
-#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data)
-#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data)
-#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data)
-#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data)
-#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data)
-#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data)
-#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data)
-#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data)
-#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data)
-#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data)
-#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data)
-#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data)
-#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data)
-#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data)
-#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data)
-#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data)
-#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data)
-#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data)
-#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data)
-#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data)
-#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data)
-#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data)
-#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data)
-#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data)
-#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data)
-#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data)
-#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data)
-#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data)
-#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data)
-#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data)
-#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data)
-#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data)
-#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data)
-#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data)
-#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data)
-#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data)
-#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data)
-#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data)
-#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data)
-#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data)
-#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data)
-#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data)
-#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data)
-#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data)
-#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data)
-#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data)
-#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data)
-#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data)
-#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data)
-#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data)
-#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data)
-#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data)
-#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data)
-#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data)
-#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data)
-#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data)
-#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data)
-#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data)
-#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data)
-#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data)
-#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data)
-#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data)
-#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data)
-#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data)
-#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data)
-#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data)
-#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data)
-#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data)
-#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data)
-#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data)
-#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data)
-#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data)
-#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data)
-#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data)
-#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data)
-#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data)
-#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data)
-#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data)
-#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data)
-#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data)
-#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data)
-#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data)
-#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data)
-#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data)
-#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data)
-#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data)
-#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data)
-#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data)
-#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data)
-#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data)
-#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data)
-#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data)
-#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data)
-#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data)
-#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data)
-#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data)
-#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data)
-#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data)
-#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data)
-#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data)
-#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data)
-#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data)
-#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data)
-#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data)
-#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data)
-#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data)
-#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data)
-#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data)
-#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data)
-#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data)
-#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data)
-#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data)
-#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data)
-#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data)
-#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data)
-#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data)
-#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data)
-#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data)
-#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data)
-#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data)
-#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data)
-#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data)
-#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data)
-#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data)
-#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data)
-#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data)
-#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data)
-#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data)
-#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data)
-#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data)
-#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data)
-#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data)
-#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data)
-#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data)
-#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data)
-#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data)
-#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data)
-#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data)
-#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data)
-#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data)
-#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data)
-#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data)
-#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data)
-#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data)
-#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data)
-#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data)
-#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data)
-#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data)
-#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data)
-#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data)
-#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data)
-#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data)
-#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data)
-#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data)
-#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data)
-#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data)
-#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data)
-#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data)
-#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data)
-#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data)
-#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data)
-#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data)
-#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data)
-#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data)
-#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data)
-#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data)
-#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data)
-#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data)
-#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data)
-#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data)
-#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data)
-#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data)
-#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data)
-#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data)
-#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data)
-#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data)
-#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data)
-#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data)
-#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data)
-#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data)
-#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data)
-#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data)
-#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data)
-#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data)
-#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data)
-#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data)
-#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data)
-#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data)
-#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data)
-#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data)
-#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data)
-#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data)
-#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)
-#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)
-
-/**
- * \}
- */
-
-#endif // _MREPEAT_H_
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/preprocessor/preprocessor.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/preprocessor/preprocessor.h
deleted file mode 100644
index 184c03a..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/preprocessor/preprocessor.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- * \file
- *
- * \brief Preprocessor utils.
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _PREPROCESSOR_H_
-#define _PREPROCESSOR_H_
-
-#include "tpaste.h"
-#include "stringz.h"
-#include "mrepeat.h"
-
-
-#endif // _PREPROCESSOR_H_
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/preprocessor/stringz.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/preprocessor/stringz.h
deleted file mode 100644
index b914b73..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/preprocessor/stringz.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**
- * \file
- *
- * \brief Preprocessor stringizing utils.
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _STRINGZ_H_
-#define _STRINGZ_H_
-
-/**
- * \defgroup group_sam_utils_stringz Preprocessor - Stringize
- *
- * \ingroup group_sam_utils
- *
- * \{
- */
-
-/*! \brief Stringize.
- *
- * Stringize a preprocessing token, this token being allowed to be \#defined.
- *
- * May be used only within macros with the token passed as an argument if the token is \#defined.
- *
- * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
- * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
- * writing "A0".
- */
-#define STRINGZ(x) #x
-
-/*! \brief Absolute stringize.
- *
- * Stringize a preprocessing token, this token being allowed to be \#defined.
- *
- * No restriction of use if the token is \#defined.
- *
- * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
- * equivalent to writing "A0".
- */
-#define ASTRINGZ(x) STRINGZ(x)
-
-/**
- * \}
- */
-
-#endif // _STRINGZ_H_
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/preprocessor/tpaste.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/preprocessor/tpaste.h
deleted file mode 100644
index f8ec44a..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/preprocessor/tpaste.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/**
- * \file
- *
- * \brief Preprocessor token pasting utils.
- *
- * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef _TPASTE_H_
-#define _TPASTE_H_
-
-/**
- * \defgroup group_sam_utils_tpaste Preprocessor - Token Paste
- *
- * \ingroup group_sam_utils
- *
- * \{
- */
-
-/*! \name Token Paste
- *
- * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
- *
- * May be used only within macros with the tokens passed as arguments if the tokens are \#defined.
- *
- * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by
- * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is
- * equivalent to writing U32.
- */
-//! @{
-#define TPASTE2( a, b) a##b
-#define TPASTE3( a, b, c) a##b##c
-#define TPASTE4( a, b, c, d) a##b##c##d
-#define TPASTE5( a, b, c, d, e) a##b##c##d##e
-#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f
-#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g
-#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h
-#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i
-#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j
-//! @}
-
-/*! \name Absolute Token Paste
- *
- * Paste N preprocessing tokens together, these tokens being allowed to be \#defined.
- *
- * No restriction of use if the tokens are \#defined.
- *
- * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined
- * as 32 is equivalent to writing U32.
- */
-//! @{
-#define ATPASTE2( a, b) TPASTE2( a, b)
-#define ATPASTE3( a, b, c) TPASTE3( a, b, c)
-#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d)
-#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e)
-#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f)
-#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g)
-#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h)
-#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i)
-#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)
-//! @}
-
-/**
- * \}
- */
-
-#endif // _TPASTE_H_
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/status_codes.h b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/status_codes.h
deleted file mode 100644
index d5e6dd6..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/status_codes.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/**
- * \file
- *
- * \brief Status code definitions.
- *
- * This file defines various status codes returned by functions,
- * indicating success or failure as well as what kind of failure.
- *
- * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#ifndef STATUS_CODES_H_INCLUDED
-#define STATUS_CODES_H_INCLUDED
-
-/* Note: this is a local workaround to avoid a pre-processor clash due to the
- * lwIP macro ERR_TIMEOUT. */
-#if defined(__LWIP_ERR_H__) && defined(ERR_TIMEOUT)
-#if (ERR_TIMEOUT != -3)
-
-/* Internal check to make sure that the later restore of lwIP's ERR_TIMEOUT
- * macro is set to the correct value. Note that it is highly improbable that
- * this value ever changes in lwIP. */
-#error ASF developers: check lwip err.h new value for ERR_TIMEOUT
-#endif
-#undef ERR_TIMEOUT
-#endif
-
-/**
- * Status code that may be returned by shell commands and protocol
- * implementations.
- *
- * \note Any change to these status codes and the corresponding
- * message strings is strictly forbidden. New codes can be added,
- * however, but make sure that any message string tables are updated
- * at the same time.
- */
-enum status_code {
- STATUS_OK = 0, //!< Success
- STATUS_ERR_BUSY = 0x19,
- STATUS_ERR_DENIED = 0x1C,
- STATUS_ERR_TIMEOUT = 0x12,
- ERR_IO_ERROR = -1, //!< I/O error
- ERR_FLUSHED = -2, //!< Request flushed from queue
- ERR_TIMEOUT = -3, //!< Operation timed out
- ERR_BAD_DATA = -4, //!< Data integrity check failed
- ERR_PROTOCOL = -5, //!< Protocol error
- ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device
- ERR_NO_MEMORY = -7, //!< Insufficient memory
- ERR_INVALID_ARG = -8, //!< Invalid argument
- ERR_BAD_ADDRESS = -9, //!< Bad address
- ERR_BUSY = -10, //!< Resource is busy
- ERR_BAD_FORMAT = -11, //!< Data format not recognized
- ERR_NO_TIMER = -12, //!< No timer available
- ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running
- ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running
- ERR_ABORTED = -15, //!< Operation aborted by user
- /**
- * \brief Operation in progress
- *
- * This status code is for driver-internal use when an operation
- * is currently being performed.
- *
- * \note Drivers should never return this status code to any
- * callers. It is strictly for internal use.
- */
- OPERATION_IN_PROGRESS = -128,
-};
-
-typedef enum status_code status_code_t;
-
-#if defined(__LWIP_ERR_H__)
-#define ERR_TIMEOUT -3
-#endif
-
-#endif /* STATUS_CODES_H_INCLUDED */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/syscalls/gcc/syscalls.c b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/syscalls/gcc/syscalls.c
deleted file mode 100644
index 9ec9d7e..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/sam/utils/syscalls/gcc/syscalls.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/**
- * \file
- *
- * \brief Syscalls for SAM (GCC).
- *
- * Copyright (c) 2011-2016 Atmel Corporation. All rights reserved.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of Atmel may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * 4. This software may only be redistributed and used in connection with an
- * Atmel microcontroller product.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
- * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
- * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * \asf_license_stop
- *
- */
-/*
- * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
- */
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-extern "C" {
-#endif
-/**INDENT-ON**/
-/// @endcond
-
-#undef errno
-extern int errno;
-extern int _end;
-extern int __ram_end__;
-
-extern caddr_t _sbrk(int incr);
-extern int link(char *old, char *new);
-extern int _close(int file);
-extern int _fstat(int file, struct stat *st);
-extern int _isatty(int file);
-extern int _lseek(int file, int ptr, int dir);
-extern void _exit(int status);
-extern void _kill(int pid, int sig);
-extern int _getpid(void);
-
-extern caddr_t _sbrk(int incr)
-{
- static unsigned char *heap = NULL;
- unsigned char *prev_heap;
- int ramend = (int)&__ram_end__;
-
- if (heap == NULL) {
- heap = (unsigned char *)&_end;
- }
- prev_heap = heap;
-
- if (((int)prev_heap + incr) > ramend) {
- return (caddr_t) -1;
- }
-
- heap += incr;
-
- return (caddr_t) prev_heap;
-}
-
-extern int link(char *old, char *new)
-{
- return -1;
-}
-
-extern int _close(int file)
-{
- return -1;
-}
-
-extern int _fstat(int file, struct stat *st)
-{
- st->st_mode = S_IFCHR;
-
- return 0;
-}
-
-extern int _isatty(int file)
-{
- return 1;
-}
-
-extern int _lseek(int file, int ptr, int dir)
-{
- return 0;
-}
-
-extern void _exit(int status)
-{
- asm("BKPT #0");
- for (;;);
-}
-
-extern void _kill(int pid, int sig)
-{
- return;
-}
-
-extern int _getpid(void)
-{
- return -1;
-}
-
-/// @cond 0
-/**INDENT-OFF**/
-#ifdef __cplusplus
-}
-#endif
-/**INDENT-ON**/
-/// @endcond
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt
deleted file mode 100644
index 422f7fe..0000000
--- a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/thirdparty/CMSIS/ATMEL-disclaimer.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Only the CMSIS required parts for ASF are included here, go to the below
- * address for the full package:
- * http://www.arm.com/products/processors/cortex-m/cortex-microcontroller-software-interface-standard.php
- *
- * The library file thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math_softfp.a was generated by ATMEL, which
- * is support -mfloat-abi=softfp compiler flag, and this is also the default selection for device that
- * have FPU module and enabled.
- * If customer want to use -mfloat-abi=hard compiler flag, the project compile/link flag and link library
- * should be manual modified. The library thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a is used for
- * -mfloat-abi=hard configration.
- *
- * __CORTEX_SC is not defined for cortex-m0+, and may cause compiler warning, so the include file
- * thirdparty/CMSIS/Include/core_cmInstr.h was modified to void such warning.
- * Modified from:
- * #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
- * to:
- * #if (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300))
- *
- */
diff --git a/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf b/embedded/atsams70-tinyrouter/atsams70-tinyrouter/src/ASF/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf
deleted file mode 100644
index b374366930b2d1b5689ff5044caba49eace6aa68..0000000000000000000000000000000000000000
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