diff --git a/circuit/atsams70n-switch/README.md b/circuit/README.md similarity index 73% rename from circuit/atsams70n-switch/README.md rename to circuit/README.md index fe16d0dafd75f0aa6ce81e581c1ce1a757a7ced2..bd486016c9aa20d85f7876e99f7847946d73eef3 100644 --- a/circuit/atsams70n-switch/README.md +++ b/circuit/README.md @@ -1,36 +1,40 @@ -# Ethernet Killer Switch +# A Router for TinyNet ## Why -This board is for switching UART signals in tinynet. I wanted to keep some track of what I was doing, while I was doing it. So here it is. +This is board for switching UART signals in TinyNet. I wanted to keep some track of what I was doing, while I was doing it. So here it is. -Originally, I had developed a switch on the XMEGA platform. I wanted to get into something a bit heavier duty, as I thought a really neat trick would be to out-perform switched ethernet, outright (for embedded systems, not for datacenters). I think that in ARM chips there was enough speed to do this. As max. UART bitrate is a function, I went straight to the 300MHz ATSAMx70 chips (M7 cores). Now, being more prudent I would do some tests with these chips first, but I'm not going to. This is foolish, I know that. Max UART on the ATSAMS70 is clk/16, so 18.75Mbps. It's not huge, but it's fast enough for realtime small messages on small systems. In any case, I think the question is about system architecture more than it is about outright performance at this point. +Originally, I had developed a switch on the XMEGA platform. I wanted to get into something a bit heavier duty, as I thought a really neat trick would be to out-perform switched ethernet, outright (for network control systems, not for datacenters). I think that in ARM chips there was enough speed to do this. Maximum UART bitrate is a function of the core clock speed (and in this case, the peripheral clock speed). I went straight to the 300MHz ATSAMx70 chips (M7 cores). -I also think that, for pure switching, an FPGA or PSOC would be a better answer. It probably is. I also want my network switches to double-duty as motor controllers, sensor interfaces, etc - do general embedded-stuff. In another world, where infinite time exists, I would put FPGAs on board with a processor. With the FPGA comes a chance to invent a whole new PHY - w/ 'co-clocking' and auto-maxing bitrates, which is something I am still really interested in implementing, but there are also machines to build. I leave that experiment for another bench. +Now, being more prudent I would do some tests with these chips first, but I'm not going to. This is foolish, I know that. Max UART on the ATSAMS70 is clk/16, so 18.75Mbps. It's not huge (relative ethernet), but it's fast enough for realtime small messages on small systems. In any case, I think the question is about system architecture more than it is about outright performance at this point. -## The Chip +I also think that, for pure switching, an FPGA or PSOC would be a better answer. It probably is. I want to experiment with those during Networks week in [how to make](http://fab.cba.mit.edu/classes/863.17/CBA/people/jakeread/). + +However, I also want my network switches to double-duty as motor controllers, sensor interfaces, etc - do general embedded-stuff. In another world, where infinite time exists, I would put FPGAs on board with a processor. With the FPGA comes a chance to invent a whole new PHY - w/ 'co-clocking' and auto-maxing bitrates, which is something I am still really interested in implementing, but there are also machines to build. I leave that experiment for another bench. -Here are my notes from selecting a chip for the getting-down: +## The Chip -# SAM Selection +First order was picking the right Microcontroller for the job. I want a lot of things, and I expect this chip to become the heart of *much* of the work I'll do during the next two years, so the datasheet stakes have never been so high. -- Want a chip with: +**I want a chip with: ** - 5+ uarts - Big Clock Speed - - tite DMA - - prgmemable - - probably M4 + - DMA (direct memory access - peripherals write right into memory) + - PWM's + - ADC's + - I2C + - SPI + - PIO (parallel input / output) is really exciting for communication -# M7's +##### M7's -## SAM E +I ended up looking through Atmel's M4 and M7 Series of chips. These seem reasonably priced (actually cheap relative STM's). They're ARM, so the toolchain should be friendly to others. The M7's have a 300MHz clock that I'm getting childishly excited about. -## SAM S +My one issue is that they are a bit too fancy, and don't have exactly the peripherals I want. The XMEGAs have like 12 UARTS etc, the M7's max out at 5, even with 144 pins. -## SAM V71 - - mega, ultra, $10 +I can also tell that programming these is going to be ... well ... less straightforward. -## GO FOR +##### GO FOR - ATSAME70 - series - or ATSAMS70 - E70 is 'industrial' - and S70 lacks an Ethernet Phy, but seems like it's way more popular... - oodles of peripherals @@ -39,13 +43,13 @@ Here are my notes from selecting a chip for the getting-down: - did I mention peripherals? - $8 ... a good middle ground -## ATSAMS70N20 +#### ATSAMS70N20 - Exact PN ATSAMS70N20A-AN - N19: 512kb Flash, N20: 1024, N21: 2048 - 300MHz - OOF: Need S70N-series for USART / SPI (has 100 pins :|) - Do LQFP for 14.5x14.5mm IC: TFBGA available, is 9x9mm - + - **Reads the datasheet** - print p. 1 -> 31 pins - print p. 77 -> 84 debug - p. 279 -> 346 clock / pmic @@ -60,9 +64,12 @@ Here are my notes from selecting a chip for the getting-down: - p. 1554 -> 1574 Schematics - UART max clock is the Peripheral Clock or the PMC PCK - divided by 16. PMC PCK is an external clock, so UART clock can remain independent of processor clock. - - + - So we can have (as measured) 22.8Mbps UART - into high-speed bouncy signal land. Exciting. + +## Bonus Breakout + +I want the following (or similar) pinouts coming off of the network node - to do *other stuff* with - i.e. motor control, sensing etc. Particularely, in a first rev of this board I am designing alongside my [bldc motor driver](https://gitlab.cba.mit.edu/jakeread/mkbldcdriver) project. -## Want coming off-board - 1x UART - 1x SPI w/ 4 cs, 1 for slave select - 1-2x i2c @@ -70,19 +77,23 @@ Here are my notes from selecting a chip for the getting-down: - all dac - 8-12 adc +In the end, at this iteration, I have -## USART - - http://asf.atmel.com/docs/latest/sam.drivers.usart.usart_synchronous_example.sam3u_ek/html/index.html + - 1 UART + - 1 I2C (I2C and UART share one pin, so cannot be used at the same time) + - 1 SPI w/ 2 Chip Selects + - 1 USART w/ 2 Chip Selects (USART can be configured to do UART, or SPI, or a Clocked Serial line of your design) + - 8 PWM's on 4 channels (hi/lo - this is designed for driving half bridges for motor control) + - 4 Analog to Digital Converters (I am less pleased with this and want more...) + - 3 Spare GPIO -## OK +Notes on this so far + - More ADC's please + - Pin headers could be split - to be breadboard friendly, and to offer some stability between layers -The first thing I did was to get into the datasheet. You can see that in the notes above. I am doing pinouts, figuring what I want on board. I am going to set this up as a kind of modular getdown, where the switch has a board interconnect, and I can build other PCBs w/ different hardwares to ride below. I.E motor controllers, sensor interfaces, human interfaces (yeeees). Picking the set of pins I wanted to pull out of the chip was actually a bit painful. I'm sure I'll go through this more than once. +# Board Design - - -Now I'm going to connect this to a footprint (TQFP 100) in eagle, - - +The first thing I did was to get into the datasheet. You can see that in the notes above. I am doing pinouts, figuring what I want on board. I am going to set this up as a kind of modular getdown, where the switch has a board interconnect, and I can build other PCBs w/ different hardwares to ride below. I.E motor controllers, sensor interfaces, human interfaces (!). Picking the set of pins I wanted to pull out of the chip was actually a bit painful. I'm sure I'll go through this more than once. For JTAG Pinouts, I referenced the Tag-Connect footprint (available for download from Tag-Connect) and the ATSAM note here - http://www.atmel.com/webdoc/atmelice/atmelice.using_ocd_physical_jtag.html see Fig. 18. They match, so I don't have to do any footwork here. Nice. @@ -99,18 +110,17 @@ I'm going to look at the board interconnect - to decide how many pins I want, I I have been tempted to buy some fancy 'mezannine' connectors - but I ended up (after a few cycles) deciding to stick with a 2x20 2.54mm pitch connector. This way just about everyone will have access to the hardware, and I like that! It's also the same pitch as most IDC connectors, breadboards, etc - so hopping around between systems should be easy. I am almost tempted to split the pins a bit so that it could get right into a breadboard - or do an edge-style bb, but this seems like too much give in that direction. -I also need to jot down my notes, here, so that I can put this project on pause: +OK, Here's my schematic + + -I'm also interested in adding some memory to the chips... I want to be able to store data in longer terms - mostly routing tables, also eventually configurations. I am going down the rabbit hole, I know. But in debugging, etc, it would be cool if I didn't have to go through large startup sequences. I'll spec it out, I won't write software for it until that's necessary... Here's an SD Holder -- WM12834CT-ND -and -https://learn.adafruit.com/adafruit-micro-sd-breakout-board-card-tutorial/download +And the board -I think there's probably a better in-between - and besides, the point is a little bit to take state out of the controller, not put more in. I need to rethink this, I think. Just write good network schematics that converge quickly, right? This is more overhead than I want. + -# THE GITDOWN +Fabricated -## Need to Spec / Footprint + ## Incremental @@ -127,6 +137,10 @@ I think there's probably a better in-between - and besides, the point is a littl # Programming +It turns out this chip defaults to SWD, not JTAG. Should have read the datasheet more carefully. Also, I forgot to order the tag-connect for this number of pins... + + + ### PIO Here I am using the PIO peripheral (which also handles multiplexing for other peripherals) to turn one of my LED's on and off diff --git a/circuit/atsams70n-switch/atsams70n-switch/atsams70n-switch-v0-2-fab.zip b/circuit/atsams70n-switch/atsams70n-switch-v0-2-fab.zip similarity index 100% rename from circuit/atsams70n-switch/atsams70n-switch/atsams70n-switch-v0-2-fab.zip rename to circuit/atsams70n-switch/atsams70n-switch-v0-2-fab.zip diff --git a/circuit/atsams70n-switch/atsams70n-switch/atsams70n-switch.brd b/circuit/atsams70n-switch/atsams70n-switch.brd similarity index 100% rename from circuit/atsams70n-switch/atsams70n-switch/atsams70n-switch.brd rename to circuit/atsams70n-switch/atsams70n-switch.brd diff --git a/circuit/atsams70n-switch/atsams70n-switch/atsams70n-switch.sch b/circuit/atsams70n-switch/atsams70n-switch.sch similarity index 100% rename from circuit/atsams70n-switch/atsams70n-switch/atsams70n-switch.sch rename to circuit/atsams70n-switch/atsams70n-switch.sch diff --git a/circuit/atsams70n-switch/atsams70n-switch/atsams70n-switch.b#1 b/circuit/atsams70n-switch/atsams70n-switch/atsams70n-switch.b#1 deleted file mode 100644 index 91668064b9a6a979532043588f2e176c26b71e06..0000000000000000000000000000000000000000 --- a/circuit/atsams70n-switch/atsams70n-switch/atsams70n-switch.b#1 +++ /dev/null @@ -1,3468 +0,0 @@ -<?xml version="1.0" encoding="utf-8"?> -<!DOCTYPE eagle SYSTEM "eagle.dtd"> -<eagle version="8.3.2"> -<drawing> -<settings> -<setting alwaysvectorfont="no"/> -<setting verticaltext="up"/> -</settings> -<grid distance="10" unitdist="mil" unit="mil" style="dots" multiple="1" display="yes" altdistance="5" altunitdist="mil" altunit="mil"/> -<layers> -<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/> -<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/> -<layer 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x2="-1.973" y2="0.983" width="0.0508" layer="39"/> -<rectangle x1="0.4064" y1="-0.6985" x2="1.0564" y2="0.7015" layer="51"/> -<rectangle x1="-1.0668" y1="-0.6985" x2="-0.4168" y2="0.7015" layer="51"/> -<rectangle x1="-0.1999" y1="-0.5001" x2="0.1999" y2="0.5001" layer="35"/> -<smd name="1" x="-0.95" y="0" dx="1.3" dy="1.5" layer="1"/> -<smd name="2" x="0.95" y="0" dx="1.3" dy="1.5" layer="1"/> -<text x="-0.635" y="1.27" size="1.27" layer="25">>NAME</text> -<text x="-0.635" y="-2.54" size="1.27" layer="27">>VALUE</text> -</package> -<package name="L1812" urn="urn:adsk.eagle:footprint:13218/1" library_version="1"> -<description><b>INDUCTOR</b><p> -chip</description> -<wire x1="-1.4732" y1="1.6002" x2="1.4732" y2="1.6002" width="0.1016" layer="51"/> -<wire x1="-1.4478" y1="-1.6002" x2="1.4732" y2="-1.6002" width="0.1016" layer="51"/> -<rectangle x1="-2.3876" y1="-1.651" x2="-1.4376" y2="1.649" layer="51"/> -<rectangle x1="1.4478" y1="-1.651" x2="2.3978" y2="1.649" layer="51"/> -<smd name="1" x="-1.95" y="0" dx="1.9" dy="3.4" layer="1"/> -<smd name="2" x="1.95" y="0" dx="1.9" dy="3.4" layer="1"/> -<text x="-1.905" y="1.905" size="1.27" layer="25">>NAME</text> -<text x="-1.905" y="-3.175" size="1.27" layer="27">>VALUE</text> -</package> -</packages> -<packages3d> -<package3d name="C0805" urn="urn:adsk.eagle:package:13265/1" type="box" library_version="1"> -<description>CAPACITOR</description> -</package3d> -<package3d name="R0805" urn="urn:adsk.eagle:package:13300/1" type="box" library_version="1"> -<description>RESISTOR</description> -</package3d> -<package3d name="L1812" urn="urn:adsk.eagle:package:13290/1" type="box" library_version="1"> -<description>INDUCTOR -chip</description> -</package3d> -<package3d name="C0603" urn="urn:adsk.eagle:package:13262/1" type="box" library_version="1"> -<description>CAPACITOR</description> -</package3d> -</packages3d> -</library> -<library name="SparkFun-Connectors"> -<description><h3>SparkFun Connectors</h3> -This library contains electrically-functional connectors. -<br> -<br> -We've spent an enormous amount of time creating and checking these footprints and parts, but it is <b> the end user's responsibility</b> to ensure correctness and suitablity for a given componet or application. -<br> -<br>If you enjoy using this library, please buy one of our products at <a href=" www.sparkfun.com">SparkFun.com</a>. -<br> -<br> -<b>Licensing:</b> Creative Commons ShareAlike 4.0 International - https://creativecommons.org/licenses/by-sa/4.0/ -<br> -<br> -You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. 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Designed for Standard JTAG 10 Pin, suitable for many others.<BR> -<BR>Footprint for TC2050 NL <BR> - -<TABLE cellspacing=0 cellpadding=0 border=0> -<TR><TD width=20></TD><TD> -<TABLE cellspacing=0 cellpadding=1 border=1> -<TR bgcolor=silver><TD align=center>PAD</TD><TD align=center>Description</TD></TR> -<TR><TD align=center>1</TD><TD>VTREF</TD></TR> -<TR><TD align=center>2</TD><TD>nTRST</TD></TR> -<TR><TD align=center>3</TD><TD>TDI</TD></TR> -<TR><TD align=center>4</TD><TD>TMS</TD></TR> -<TR><TD align=center>5</TD><TD>TCK</TD></TR> -<TR><TD align=center>6</TD><TD>RTCK</TD></TR> -<TR><TD align=center>7</TD><TD>TDO</TD></TR> -<TR><TD align=center>8</TD><TD>RESET</TD></TR> -<TR><TD align=center>9</TD><TD>GND</TD></TR> -<TR><TD align=center>10</TD><TD>NC</TD></TR> -</TABLE> -</TD></TR></TABLE><BR><BR> -©2009 ROFA.cz -Modified 7/2011 by Tim McCarthy-Smith -VIDA Products INC</description> -<wire x1="0" y1="-2.54" x2="7.62" y2="-2.54" width="0.127" layer="21"/> -<smd name="10" x="1.27" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100" cream="no"/> -<smd name="9" x="2.54" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/> -<smd name="8" x="3.81" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/> -<smd name="3" x="3.81" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/> -<smd name="2" x="2.54" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/> -<smd name="1" x="1.27" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/> -<smd name="7" x="5.08" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/> -<smd name="6" x="6.35" y="0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/> -<smd name="4" x="5.08" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/> -<smd name="5" x="6.35" y="-0.635" dx="0.7874" dy="0.7874" layer="1" roundness="100"/> -<text x="-0.635" y="1.27" size="1.27" layer="25">>name</text> -<hole x="0" y="0" drill="1"/> -<hole x="7.62" y="-1.016" drill="1"/> -<hole x="7.62" y="1.016" drill="1"/> -</package> -</packages> -</library> -</libraries> -<attributes> -</attributes> -<variantdefs> -</variantdefs> -<classes> -<class number="0" name="default" width="0" drill="0"> -</class> -</classes> -<designrules name="default *"> -<description language="de"><b>EAGLE Design Rules</b> -<p> -Die Standard-Design-Rules sind so gewählt, dass sie für -die meisten Anwendungen passen. Sollte ihre Platine -besondere Anforderungen haben, treffen Sie die erforderlichen -Einstellungen hier und speichern die Design Rules unter -einem neuen Namen ab.</description> -<description language="en"><b>EAGLE Design Rules</b> -<p> -The default Design Rules have been set to cover -a wide range of applications. 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width="0.1524" layer="16"/> -<wire x1="39.3954" y1="26.4922" x2="39.7256" y2="26.162" width="0.1524" layer="16"/> -<wire x1="33.27474375" y1="26.4922" x2="39.3954" y2="26.4922" width="0.1524" layer="16"/> -<wire x1="39.7256" y1="26.162" x2="39.7296" y2="26.162" width="0.1524" layer="16"/> -<wire x1="39.7296" y1="26.162" x2="39.878" y2="26.0136" width="0.1524" layer="16"/> -<via x="39.878" y="26.0136" extent="1-16" drill="0.25"/> -<wire x1="39.878" y1="26.0136" x2="42.0765875" y2="26.0136" width="0.1524" layer="1"/> -<wire x1="42.0765875" y1="26.0136" x2="42.24568125" y2="26.18269375" width="0.1524" layer="1"/> -<wire x1="31.5856625" y1="28.18128125" x2="33.27474375" y2="26.4922" width="0.1524" layer="16"/> -<wire x1="30.704959375" y1="29.588971875" x2="30.704959375" y2="31.2762" width="0.1524" layer="1"/> -</signal> -</signals> -</board> -</drawing> -<compatibility> -<note version="6.3" minversion="6.2.2" severity="warning"> -Since Version 6.2.2 text objects can contain more than one line, -which will not be processed correctly with this version. -</note> -<note version="8.2" severity="warning"> -Since Version 8.2, EAGLE supports online libraries. The ids -of those online libraries will not be understood (or retained) -with this version. -</note> -<note version="8.3" severity="warning"> -Since Version 8.3, EAGLE supports URNs for individual library -assets (packages, symbols, and devices). The URNs of those assets -will not be understood (or retained) with this version. -</note> -<note version="8.3" severity="warning"> -Since Version 8.3, EAGLE supports the association of 3D packages -with devices in libraries, schematics, and board files. Those 3D -packages will not be understood (or retained) with this version. -</note> -</compatibility> -</eagle> diff --git a/circuit/atsams70n-switch/atsams70n-switch/eagle.epf b/circuit/atsams70n-switch/eagle.epf similarity index 100% rename from circuit/atsams70n-switch/atsams70n-switch/eagle.epf rename to circuit/atsams70n-switch/eagle.epf diff --git a/circuit/atsams70n-switch/images/swd-not-jtag.jpg b/circuit/images/swd-not-jtag.jpg similarity index 100% rename from circuit/atsams70n-switch/images/swd-not-jtag.jpg rename to circuit/images/swd-not-jtag.jpg