From 29bf37e576a65915b88f194c9d8eaa466da0c4a8 Mon Sep 17 00:00:00 2001
From: Neil Gershenfeld <gersh@cba.mit.edu>
Date: Mon, 30 Aug 2021 17:45:04 -0400
Subject: [PATCH] wip
---
python/pcb.py | 14 +++-----------
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/python/pcb.py b/python/pcb.py
index c3a003f..9e7608e 100755
--- a/python/pcb.py
+++ b/python/pcb.py
@@ -22,10 +22,10 @@
#output = "top, labels, and exterior"
#output = "top, labels, holes, and exterior"
#output = "top, bottom, labels, and exterior"
-#output = "top, bottom, labels, holes, and exterior"
-output = "top traces"
+output = "top, bottom, labels, holes, and exterior"
+#output = "top traces"
#output = "top traces and exterior"
-output = "bottom traces reversed"
+#output = "bottom traces reversed"
#output = "bottom traces reversed and exterior"
#output = "holes"
#output = "interior"
@@ -7958,12 +7958,6 @@ mask = .004 # solder mask size
pcb = PCB(x,y,width,height,mask)
-pcb = wire(pcb,w,
- point(x,y,zb),
- point(x,y+height,zb))
-
-'''
-
IC1 = ATtiny44_SOICN('IC1\nt44')
pcb = IC1.add(pcb,x+.49,y+.56)
@@ -8115,8 +8109,6 @@ pcb = wire(pcb,w,
point(V7.x,V6.y,zb),
V7.pad[2])
-'''
-
############################################################
# select output
############################################################
--
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