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atkbldcdriver

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void setuppwm(void){
	PMC->PMC_PCER1 = 1 << 28; // turn on peripheral clock for PWM 1
	// these are pins for channels 1, 2, 3 in lo / hi pairs
	PIOD->PIO_PDR = PIO_PER_P2 | PIO_PER_P3 | PIO_PER_P4 | PIO_PER_P5 | PIO_PER_P6 | PIO_PER_P7; // disable PIO
	PIOD->PIO_ABCDSR[0] = PIO_PER_P2 | PIO_PER_P3 | PIO_PER_P4 | PIO_PER_P5 | PIO_PER_P6 | PIO_PER_P7; // enable peripheral B
	//PIOD->PIO_ABCDSR[1] // already these are 0s, we want that [01] is peripheral B

	// PREA Clock is Peripheral Clock / 64
	// PREA Clock supplies Clock A, Clock A is PREA / 24
	// Clock B is off
	PWM1->PWM_CLK = PWM_CLK_PREA(2) | PWM_CLK_DIVA(7) | PWM_CLK_DIVB_CLKB_POFF;
	// Channel 0 uses CLCKA, uses Center Aligned, has dead time, is waveform aligned (with others?)
	PWM1->PWM_CH_NUM[1].PWM_CMR  = PWM_CMR_CPRE_CLKA | PWM_CMR_CES | PWM_CMR_DTE | PWM_CMR_CALG;
	// Channel 0 uses this period
	// (2 * 2^PREA * DIVA * CPRD) / f_peripheralClock
	// so for 10kHz target frequency, we want 1 / 10000,
	// have (2 * 64 * 12 * x )/ 150000000
	// ~ spreadsheets are your friends ~
	PWM1->PWM_CH_NUM[1].PWM_CPRD = PWM_CPRD_CPRD(255);
	// set duty cycle, initially, to low
	// this is between 0 and CPRD, so it looks like shooting for a big CPRD is (y)
	PWM1->PWM_CH_NUM[1].PWM_CDTY = PWM_CDTY_CDTY(1);
	// configure deadtime generator, between 0 and CPRD - CDTY
	PWM1->PWM_CH_NUM[1].PWM_DT = PWM_DT_DTH(2) | PWM_DT_DTL(2);
	// configure update mode
	// mode 1 is 'manual write of double buffer registers and automatic update of synchronous channels'
	// other modes are for manual write / manual  update and DMA mode
	// also add sync. channels - spec that 0, 1, 2 are ~ on the same wavelength, man ~
	PWM1->PWM_SCM = PWM_SCM_UPDM_MODE1 | PWM_SCM_SYNC0;

	// now, boot it up
	PWM1->PWM_ENA = PWM_ENA_CHID1; // just channel 0 for now

	// understand: compare? clock? update? duty cycle register? period register?
}

int main (void)
{
	board_init();
	sysclk_init();
	wdt_disable(WDT);

	setuppwm();

	PMC->PMC_PCER0 = 1 << ID_PIOA;

	PIOA->PIO_PER |= PIO_PER_P27;
	PIOA->PIO_OER = PIO_PER_P27;

	startupflash();

	while(1){
		// to update, must use duty update register, not just 'duty'
		PWM1->PWM_CH_NUM[1].PWM_CDTYUPD = PWM_CDTY_CDTY(20);
		delay_ms(100);
		PWM1->PWM_CH_NUM[1].PWM_CDTYUPD = PWM_CDTY_CDTY(155);
		delay_ms(50);
	}
}
	NVIC_DisableIRQ(UART1_IRQn);
	NVIC_ClearPendingIRQ(UART1_IRQn);
	NVIC_SetPriority(UART1_IRQn, 9);
	NVIC_EnableIRQ(UART1_IRQn);
void UART1_Handler(){
	if(UART1->UART_SR & UART_SR_RXRDY){
		uint8_t data = UART1->UART_RHR; // read the incoming data
		while(!(UART1->UART_SR & UART_SR_TXRDY)); // hang-10 to make sure the UART is ready to send
		UART1->UART_THR = data;
	} else {
		//
	}
}
void setupspi(void){
	// using SPI0, PID 21
	// MISO, PD20, Peripheral B
	// MOSI, PD21, Peripheral B
	// SPCK, PD22, Peripheral B
	// NPCS, PA31, Peripheral A

	PMC->PMC_PCER0 = 1 << ID_SPI0;

	PIOD->PIO_PDR |= PIO_PER_P20 | PIO_PER_P21 | PIO_PER_P22;
	PIOA->PIO_PDR |= PIO_PER_P31;

	SPI0->SPI_CR |= SPI_CR_SPIEN;

	SPI0->SPI_MR |= SPI_MR_MSTR | SPI_MR_PCS(1);

	SPI0->SPI_CSR[1] |= SPI_CSR_BITS_16_BIT | SPI_CSR_NCPHA | SPI_CSR_SCBR(200);
}
void readencoder(uint16_t *data){

	while(!(SPI0->SPI_SR & SPI_SR_TXEMPTY)); // wait 4 ready
	SPI0->SPI_TDR = SPI_TDR_TD(0xFFFF);// | SPI_TDR_PCS(1);
	while(!(SPI0->SPI_SR & SPI_SR_TXEMPTY)); // wait 4 ready
	SPI0->SPI_TDR = SPI_TDR_TD(0x0000);// | SPI_TDR_PCS(1);
	*data = SPI0->SPI_RDR & SPI_RDR_RD_Msk;

	//uint16_t pard = data >> 15;
	*data = *data << 2; // shift parity and error bit out
	*data /= 4;
}

		uint16_t encoder;

		readencoder(&encoder);

		if(reverse){
			encoder = resolution - encoder;
		}
		uint16_t elecpos = (encoder + offset) % modulo; // 0 -> 2*PI in rads

		// to update, must use duty update register, not just 'duty'
		if(dir){
			phaseu = elecpos/(modulo / 1024);
			phasev = elecpos/(modulo / 1024) + 341;
			phasew = elecpos/(modulo / 1024) + 682;
		} else {
			phaseu = elecpos/(modulo / 1024) + 682;
			phasev = elecpos/(modulo / 1024) + 341;
			phasew = elecpos/(modulo / 1024);
		}

		if (phaseu > 1023){
			phaseu -= 1023;
		}
		if(phasev > 1023){
			phasev -= 1023;
		}
		if(phasew > 1023){
			phasew -= 1023;
		}

int main(void)
{
    /* Initialize the SAM system */
    SystemInit();

	PORT->Group[1].DIRSET.reg |= (uint32_t)(1 << 9);
	PORT->Group[0].DIRSET.reg |= (uint32_t)(1 << 23);

	SysTick_Config(5000000);

	/* TCC SETUP */
	// from 49.6.2.1
	// a few registers are protected - and can only be updated when
	// TCCn.CTRLA.ENABLE = 0
	// FCTRLA and FCTRLB, WEXCTRL, DRVCTRL, and EVCTRL

	// (4) Configure Output Pin with PORT->Group[n].DIRSET.reg
	// PA8 PA9 PA10 PA12, PB10 PB11
	// 32.9.13
	PORT->Group[0].DIRSET.reg |= (uint32_t)(1 << 8) | (uint32_t)(1 << 9) | (uint32_t)(1 << 10) | (uint32_t)(1 << 12);
	PORT->Group[1].DIRSET.reg |= (uint32_t)(1 << 10) | (uint32_t)(1 << 11);

	// 1 lo / hi
	PORT->Group[0].PINCFG[10].bit.PMUXEN = 1;
	PORT->Group[0].PMUX[10>>1].reg |= PORT_PMUX_PMUXE(0x5);  // on peripheral F
	PORT->Group[0].PINCFG[12].bit.PMUXEN = 1;
	PORT->Group[0].PMUX[12>>1].reg |= PORT_PMUX_PMUXE(0x5);

	// 2 lo / hi
	PORT->Group[0].PINCFG[9].bit.PMUXEN = 1;
	PORT->Group[0].PMUX[9>>1].reg |= PORT_PMUX_PMUXO(0x5);  // on peripheral F
	PORT->Group[1].PINCFG[11].bit.PMUXEN = 1;
	PORT->Group[1].PMUX[11>>1].reg |= PORT_PMUX_PMUXO(0x5);

	// 3 lo / hi
	PORT->Group[0].PINCFG[8].bit.PMUXEN = 1;
	PORT->Group[0].PMUX[8>>1].reg |= PORT_PMUX_PMUXE(0x5);  // on peripheral F
	PORT->Group[1].PINCFG[10].bit.PMUXEN = 1;
	PORT->Group[1].PMUX[10>>1].reg |= PORT_PMUX_PMUXE(0x5);

	// (1) enable the TCC Bus Clock - CLK_TCCn_APB
	// https://www.eevblog.com/forum/microcontrollers/atmel-sam-d-tc-and-tcc-(no-asf)/

	TCC0->CTRLA.bit.ENABLE = 0;

	MCLK->APBBMASK.reg |= MCLK_APBBMASK_TCC0; // at 15.8.9

	GCLK->GENCTRL[5].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL) | GCLK_GENCTRL_GENEN;
	while(GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5);

	GCLK->PCHCTRL[TCC0_GCLK_ID].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK5;

	TCC0->CTRLA.reg |= TCC_CTRLA_PRESCALER_DIV8 | TCC_CTRLA_PRESCSYNC_PRESC |TCC_CTRLA_RESOLUTION(0);

	// (2) Select Waveform Generation operation in the WAVE register WAVE.WAVEGEN
	// we want dual slope pwm

	TCC0->WAVE.reg = TCC_WAVE_WAVEGEN_DSBOTH; // 'dual slope both' - updates on both hi and lo of slope ?

	// (3) We want OTMX - Output Matrix Channel Pin Routing Configuration - at 0x0

	TCC0->WEXCTRL.reg = TCC_WEXCTRL_DTHS(1) | TCC_WEXCTRL_DTLS(1) |
						TCC_WEXCTRL_DTIEN1 | TCC_WEXCTRL_DTIEN2 | TCC_WEXCTRL_DTIEN3 | TCC_WEXCTRL_DTIEN0 |
						TCC_WEXCTRL_OTMX(0);

	TCC0->PER.reg = TCC_PER_PER(256); // 18 bit

	TCC0->COUNT.reg = 0;

	TCC0->CC[0].reg = 12; // '3'
	TCC0->CC[1].reg = 24; // '2'
	TCC0->CC[2].reg = 48; // '1'
	TCC0->CC[3].reg = 0;

	// (4) Enable with CTRLA.ENABLE

	TCC0->CTRLA.bit.ENABLE = 1;
	while(TCC0->SYNCBUSY.bit.ENABLE);

    while (1)
    {
		PORT->Group[1].OUTTGL.reg = (uint32_t)(1 << 9);
    }
}
int main(void)
{
    /* Initialize the SAM system */
    SystemInit();

	PORT->Group[1].DIRSET.reg |= (uint32_t)(1 << 9);
	PORT->Group[0].DIRSET.reg |= (uint32_t)(1 << 23);

	SysTick_Config(5000000);

	/* BEGIN SPI SETUP */

	// PA04, SER0-0, SPI_MISO
	// PA05, SER0-1, SPI_SCK
	// PA06, SER0-2, SPI_CSN
	// PA07, SER0-3, SPI_MOSI
	PORT->Group[0].DIRCLR.reg |= (uint32_t)(1 << 4);
	PORT->Group[0].DIRSET.reg |= (uint32_t)(1 << 5) | (uint32_t)(1 << 6) | (uint32_t)(1 << 7);

	PORT->Group[0].PINCFG[4].bit.PMUXEN = 1;
	PORT->Group[0].PMUX[4>>1].reg |= PORT_PMUX_PMUXE(0x3);  // on peripheral D
	PORT->Group[0].PINCFG[5].bit.PMUXEN = 1;
	PORT->Group[0].PMUX[5>>1].reg |= PORT_PMUX_PMUXO(0x3);  // on peripheral D
	PORT->Group[0].PINCFG[6].bit.PMUXEN = 1;
	PORT->Group[0].PMUX[6>>1].reg |= PORT_PMUX_PMUXE(0x3);  // on peripheral D
	PORT->Group[0].PINCFG[7].bit.PMUXEN = 1;
	PORT->Group[0].PMUX[7>>1].reg |= PORT_PMUX_PMUXO(0x3);  // on peripheral D

	// setup clocks to sercom

	MCLK->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0; // at 15.8.9

	GCLK->GENCTRL[6].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL) | GCLK_GENCTRL_GENEN;
	while(GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6);

	GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK6;

	// TCC0_GCLK_ID

	// Some registers can't be written unless CTRL.ENABLE = 0:
	// CTRLA, CTRLB, BAD and ADDR

	// (1) set to master

	SERCOM0->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x3); // 0x2 or 0x3, slave or master

	// SERCOM0->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA | SERCOM_SPI_CTRLA_CPOL; // clock phase and polarity

	// (2) set pin configurations

	SERCOM0->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(0x0) | SERCOM_SPI_CTRLA_DOPO(0x2); // pin selections, see 35.8.1 bits 21:20 and 17:16, pg. 910

	// (3) set character size, data direction

	//SERCOM0->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; // 0 MSB, 1 LSB
	//SERCOM0->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(0x0); // 8 bits character - 0x0, so no need to set

	// (4) setup baud rate
	// f_baud = f_ref / (2 * (BAUD +1)) so BAUD = f_ref / (2 * f_baud) - 1

	SERCOM0->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(126);
	SERCOM0->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_RXEN; // slave select hardware yes

	SERCOM0->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;

    while (1)
    {
		while(!(SERCOM0->SPI.INTFLAG.bit.DRE));
		SERCOM0->SPI.DATA.reg = SERCOM_SPI_DATA_DATA(80);
		PORT->Group[1].OUTTGL.reg = (uint32_t)(1 << 9); // i-v, to check we made it thru setup
    }
}