xmega eventsys clock propagation

README.md

@@ -8,6 +8,8 @@ This is a message passing device and USB link for the [automatakit](https://gitl
 
 ![board](/images/fab-back.jpg)
 
+The board includes one USB-to-UART Bridge, a CP2102n, *which is treated as the router's 6th port*. 
+
 ## Development Notes
 
 See [circuit chatter](/circuit) and [firmware chatter](/embedded).

circuit/README.md

@@ -9,3 +9,5 @@ The circuit uses an ATxmega256A3U microcontroller and it's UART modules to chatt
 # Notes
 
  - 0.1uF cap near CP2102n is too close, can't place
+ - silk port labels are under ports 
+ - clkout has to be pin7 on C, E or D 
\ No newline at end of file

circuit/atkrouter-v01/eagle.epf

@@ -40,7 +40,7 @@ UsedLibrary="C:/EAGLE 8.3.2/lbr/ltspice/sym.lbr"
 Type="Board Editor"
 Number=3
 File="atkrouter-v01.brd"
-View="-5.94496 21.7574 107.847 82.1959"
+View="34.5202 60.3024 52.8983 70.0636"
 WireWidths=" 0.0762 0.1016 0.127 0.15 0.2 0.2032 0.4064 0.6096 0.8128 1.27 2.54 0.508 0.254 0.3048 1.016 0.1524"
 PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
 PadDrills=" 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6"
@@ -78,13 +78,13 @@ SwapLevel=0
 ArcDirection=0
 AddLevel=2
 PadsSameType=0
-Layer=48
+Layer=47
 
 [Win_2]
 Type="Schematic Editor"
 Number=1
 File="atkrouter-v01.sch"
-View="-58.1526 -5.84485 208.12 165.332"
+View="13.2075 13.1224 141.618 95.6731"
 WireWidths=" 0.0762 0.1016 0.127 0.15 0.2 0.2032 0.254 0.3048 0.4064 0.508 0.6096 0.8128 1.016 1.27 2.54 0.1524"
 PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
 PadDrills=" 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.65 0.7 0.75 0.8 0.85 0.9 1 0.6"
@@ -123,7 +123,7 @@ ArcDirection=0
 AddLevel=2
 PadsSameType=0
 Layer=91
-Views=" 1: -58.1526 -5.84485 208.12 165.332"
+Views=" 1: 13.2075 13.1224 141.618 95.6731"
 Sheet="1"
 
 [Win_3]

embedded/README.md

@@ -4,4 +4,9 @@ Firmware for the board follows the [automatakit](https://gitlab.cba.mit.edu/jake
 
 Communication is handled asynchronously: bytes received on the UART are loaded into a ringbuffer, where they are later parsed in to packets. Parsing happens as oven as possible. 
 
-... 
\ No newline at end of file
+Now, to start with clocking. 
+
+## 0th port:
+
+This is kind of confusing, and I think it's worthwhile to re-write this so that the router is actually the head. 
+

embedded/atkrouter/atkrouter/atkrouter.cproj

@@ -41,7 +41,7 @@
       </framework-data>
     </AsfFrameworkConfig>
     <avrtool>com.atmel.avrdbg.tool.atmelice</avrtool>
-    <avrtoolserialnumber>J41800087098</avrtoolserialnumber>
+    <avrtoolserialnumber>J41800086407</avrtoolserialnumber>
     <avrdeviceexpectedsignature>0x1E9842</avrdeviceexpectedsignature>
     <com_atmel_avrdbg_tool_atmelice>
       <ToolOptions>
@@ -51,7 +51,7 @@
         <InterfaceName>PDI</InterfaceName>
       </ToolOptions>
       <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
-      <ToolNumber>J41800087098</ToolNumber>
+      <ToolNumber>J41800086407</ToolNumber>
       <ToolName>Atmel-ICE</ToolName>
     </com_atmel_avrdbg_tool_atmelice>
     <avrtoolinterface>PDI</avrtoolinterface>

embedded/atkrouter/atkrouter/main.c

@@ -18,14 +18,69 @@
 // do cp2102n
 
 void clock_init(void){
+	
 	OSC.XOSCCTRL = OSC_XOSCSEL_XTAL_256CLK_gc | OSC_FRQRANGE_12TO16_gc; // select external source
 	OSC.CTRL = OSC_XOSCEN_bm; // enable external source
 	while(!(OSC.STATUS & OSC_XOSCRDY_bm)); // wait for external
-	OSC.PLLCTRL =  OSC_PLLSRC_XOSC_gc | OSC_PLLFAC0_bm | OSC_PLLFAC1_bm; // select external osc for pll, do pll = source * 3
+	OSC.PLLCTRL =  OSC_PLLSRC_XOSC_gc | 3; // select external osc for pll, do pll = source * 3
 	OSC.CTRL |= OSC_PLLEN_bm; // enable PLL
 	while (!(OSC.STATUS & OSC_PLLRDY_bm)); // wait for PLL to be ready
 	CCP = CCP_IOREG_gc; // enable protected register change
 	CLK.CTRL = CLK_SCLKSEL_PLL_gc; // switch to PLL for main clock
+	/*
+	OSC.PLLCTRL = OSC_PLLFAC4_bm | OSC_PLLFAC3_bm; // 2 MHz * 24 = 48 MHz
+	OSC.CTRL = OSC_PLLEN_bm; // enable PLL
+	while (!(OSC.STATUS & OSC_PLLRDY_bm)); // wait for PLL to be ready
+	CCP = CCP_IOREG_gc; // enable protected register change
+	CLK.CTRL = CLK_SCLKSEL_PLL_gc; // switch to PLL
+	*/
+}
+
+#define ATKTIMER_MODE_MASTER 1
+#define ATKTIMER_MODE_SLAVE 0 
+#define ATKTIMER_MODE_RING 2
+
+void atktimer_init(uint8_t mode){
+	/*
+	in this test, 
+	tx: pin F0 outputs a 1MHz clock on all output lines
+	rx: pin F4 (atk1-clkin) listens to both edges, outputs that event to PE7 (ATK1-tx)
+	*/
+	PORTF.DIRSET = PIN0_bm; // this is our clk output pin
+	PORTF.PIN0CTRL = PORT_SRLEN_bm; // slew rate limit to decrease noise (a little bit)
+	
+	if(mode == ATKTIMER_MODE_MASTER){
+		// put a 1MHz timer on the clock out lines
+		// clkout pin is PF0, TCF0.CCA
+		TCF0.CTRLA = TC_CLKSEL_DIV1_gc; // one tick is 48MHz
+		
+		uint16_t pera = 47; // going for 1MHz
+		uint8_t peral = (uint8_t) pera;
+		uint8_t perah = (uint8_t)(pera >> 8);
+		
+		TCF0.CTRLB = TC_WGMODE_FRQ_gc | (1 << 4); // frequency wave mode, and enable CCA channel output
+		// need to set CCA, 
+		TCF0.CCABUFL = peral;
+		TCF0.CCABUFH = perah;
+	} else if(mode == ATKTIMER_MODE_SLAVE) {
+		// listen for clock on a port, let's say ATK1 for now, and mirror that on our clock outputs
+		PORTF.DIRCLR = PIN4_bm; // this is ATK1-CLKIN
+		PORTF.PIN4CTRL = PORT_ISC_BOTHEDGES_gc; // sense when falling
+		
+		// setup event channel 0 to have EVSYS_CHMUX_PORTD_PIN4_gc as input
+		EVSYS_CH0MUX = EVSYS_CHMUX_PORTF_PIN4_gc;
+		// it seems we can only output events directly on pin7 of ports c, d or e :| (or pin 4 on the same ports)
+		// so output event 0 on port E, pin 7
+		// this will put event channel 0 on a pin, directly - only for as many clock cycles as the event is active. i.e. one
+		//PORTCFG_CLKEVOUT = PORTCFG_EVOUT_PE7_gc;
+		
+		TCF0.CTRLA = TC_CLKSEL_EVCH0_gc;
+		
+		TCF0.CTRLB = TC_WGMODE_FRQ_gc | (1 << 4); // frequency wave mode, and enable CCA channel output
+		// need to set CCA,
+		TCF0.CCABUFL = 0;
+		TCF0.CCABUFH = 0;
+	}
 }
 
 void uarts_init(void){
@@ -98,6 +153,7 @@ void atkps_init(void){
 int main(void)
 {
 	clock_init();
+	atktimer_init(ATKTIMER_MODE_MASTER);
 	uarts_init();
 	atkps_init();